1. MCCDrivers.zip Driver
2. FIFOS.TXT File Contents

FIFOS.TXT Driver File Contents (MCCDrivers.zip)

A WORD CONCERNING FIFO USAGE WITH THE GPIB LIBRARY
--------------------------------------------------

The GPIB cards are equipped with FIFOs in order to allow
for buffering between the various GPIB devices and the
user program. They also provide the speed advantages of
DMA without the required bus contention or DMA controller
setup.

The following models of GPIB interface cards have FIFOs:
   ISA_GPIB
   PCI_GPIB
   CPCI_GPIB
   PCM_GPIB
   PC104_GPIB

These boards each contain two FIFOs where each FIFO is
1024 bytes deep, for a total of 2048 bytes. The boards
may be used with or without the FIFOs, depending on whether
their usage is enabled via the configuration program. If
the FIFOs are disabled then the boards use simple programmed
I/O. There is no DMA capability on these boards.

HARDWARE STRUCTURE
------------------
The FIFOs on these boards sit between the GPIB bus controller
(CB7210) and the ISA (or PCI) bus. Whereas the GPIB bus
controller is a byte oriented animal (as is the IEEE-488 bus
itself), the FIFOs are treated on a word (two bytes) basis.
I.e., I/O transfers to/from the board
are in two byte chunks if the FIFOs are enabled. This provides
for some of the speed advantage inherent in the FIFO logic. Of
course this also results in some additional complexity in both
the hardware and the GPIB library.

I/O CONSIDERATIONS
------------------
GPIB operation with the FIFOs - as with programmed I/O - may
be in either synchronous (non-interrupt driven) or
asynchronous (interrupt driven) mode. However there is some
additional flexibility with the FIFOs as a result of their
ability to buffer the data stream. In particular, the library
software related to the FIFOs is capable of operating in
three different modes as follows:

1. Synchronous mode without interrupts:
This mode is used if you call ibrd or ibwrt and do not have
an interrupt level specified in your configuration file. In
this mode the status of the FIFOs is "polled" and they are
emptied (or filled, depending on whether you are doing input
or output) based on half-full and empty flags read from the
GPIB board. (Note: This mode is not available with the
PCI and PCMCIA cards since the interrupt level is
automatically assigned by the operating system.)

2. Synchronous mode with interrupts:
This mode is used if you call ibrd or ibwrt and do have
an interrupt level specified in your configuration file. In
this mode the FIFOs are emptied (or filled, depending on
whether you are doing input or output) based on the
incidence of half-full or empty (or EOI) interrupts which
are generated by the board. This is essentially the same as
asynchronous mode except that there is no return to your
main program until the operation is completed.

3. Asynchronous mode:
In asynchronous mode - as obtained by calls to either ibrda
or ibwrta - the I/O operation is initiated and then return
is immediately made to your program. In this mode the
library relies on the board-generated interrupts to
indicate when the FIFOs should be emptied or filled. In
terms of total CPU overhead this is generally the most
efficient mode since your program is free to do other
operations while the I/O operation is in progress.

On top of these basic modes are several other cosiderations:
First, for very short transfers (less than six bytes) the
FIFOs are not used. The reason for this has to do with some
tricky timing requirements associated with FIFO setup.
Secondly, you may specify "AS APPROPRIATE" in your
configuration file under the "USE FIFOs?" item. If this is
specified then only transfers greater than 256 bytes use
the FIFOs. All of these issues apply to both read and
write - there is no capability to specify different
criteria for input and output. Also, note that the FIFOs
are only used for data transfer, they are never used for
transmitting or receiving command bytes.

FIFO USAGE RECOMMENDATIONS
--------------------------
Due to the additional complexity inherent in operation with
the FIFOs, it is recommended that you first get your
application running with simple programmed I/O. Once you
are satisfied that everything is functioning correctly you
can then enable the FIFOs and realize the speed advantage.

OTHER ISSUES
------------
1. End-of-String modes
The FIFOs cannot be reliably employed if you require message
termination via an EOS byte. The FIFOs require EOI for
ending an input transfer.
2. Read Buffers
For input transfers, most applications specify a read buffer
size somewhat larger than the actual number of bytes
expected. The library then relies on the EOI flag to
indicate the end of the input message. This is good. However
be aware that the Win-95 and Win-NT drivers assume that
the specified buffer actually exists - to the full length
you have indicated. Hence, it is not (in general) valid to
pass a buffer pointer to the read routine and specify a
length greater than the true size of the allocated space.
3. The above discussion generally applies to both our 16 and
32-bit libraries. However the implementation as regards
various lower-level details is different between the two
packages.
4. We sometimes refer to usage of the GPIB interface FIFOs
as "High Speed" mode. This is not to be confused with the
ongoing industry initiative to develop an "HS488" spec
which intends to augment the existing IEEE-488 protocol
to include higher speed operating modes.