1. 570249.exe Driver
2. release.txt File Contents

release.txt Driver File Contents (570249.exe)

                     Release Note for BCM5705 BOOT Code Firmware
                    ==================================================
Version 3.14:

  1. Changed SEEPROM clock speed from 148 Khz to 374 Khz.

      Problem: The SEEPROM clock speed was set to 148KHz, in which, resulted
               in longer 2nd phase bootcode loading time. 
      Cause:   The specification did not indicate the source frequency to be 
               used to generate SEEPROM clock. The bootcode was using core 
               clock, same as 5702/3/4, for the calculation of the frequency.
      Fix:     The bootcode bypassed the initialization and using hardware
               default speed of 374 Khz. 

Version 3.13: 

  1. Changed default VPD data string from "5782" to "5705"

      Problem: The VPD data default seting was set to 5782 instead of 5705
      Cause:   The file gen_nic_mfg3.c was shared by 5782 project. When 
               the string was Changed in 5782 project, the string also got 
               changed in 5705 project. 
      Fix:     The file is separated between projects. Now each project has
               it's own copy of gen_ic_mfg3.c.
   
Version 3.12:

  1. Use default setting as 1.2V voltage for A1 and later.
  
      Problem: The core 1.2V voltage was set to 1.38V.
      Cause:   The chip revision A0 had a bug that the core voltage was too
               low, to workaround this problem, the bootcode was programming
               the core voltage higher.
               In A1 revsion, the problem is fixed in hardware; however, the
               bootcode was still programming the higher voltage. As result,
               the voltage was set to 1.38V, higher than legal voltage.
      Fix:     Bootcode will program higher voltage for revision A0 chip only.
               For A1 and later, it will use hardware default value. 

  2. Fixed PXE ROM size bug

      Problem: The secfg option 29, expansion ROM size was not taking effect.
      Cause:   Bootcode did not program the correct value in the register.
      Fix:     Bootcode is changed to program correct expansion ROM size
               setting in NVRAM configuration into register.

  3. Moved ClockRun enable code to the beginning of config access

      Problem: The PCI config space register cannot be access correctly when
               ClockRun is disabled and the BIOS had ClockRun feature 
               turned on.
      Cause:   When BIOS enables ClockRun feature, the miniPCI bus clock
               stops until ClockRun signals is asserted by device. Without
               enabling ClockRun in device, there is no PCI clock and
               bootcode has no access to PCI config space. 
      Fix:     The problem cannot be fixed in bootcode because the ClockRun
               enable bit itself is in PCI config. space.
               The change here is to move the enabling ClockRun at earlier
               time, before any config space access, and hoping (by luck) 
               there is an activities on the bus to trigger the bootcode 
               write successfully to reduce the chance of subsequence 
               incorrect access.

Version 3.11:
    1. Turned off Instruction Cache. (fixed ASF problem, CQ#6516)

Version 3.10:
    1. Fixed LED problem for WoL

Version 3.09:
    1. Supports Shared Memory data structure version 1
    2. Removed phase 2 image loading failure LED blink feature (to save space)
    3. Enabled RX CPU Instruction/data cache (to improve perfomance)
	4. Use 16 word NVRAM access for PXE

Version 3.08:
    1. Added PXE loading fix.
    2. Added Workaround for Errat#19. (DAC trim default values need to increase 4%)
    3. Fixed phy power down problem (ClearQuest 6001)
    4. Supports A1 revision silicon

Version 3.07:
    1. Support WoL Limit 10 speed
    2. Added second phase signature to fix WoL that stuck in 1G problem
    3. Fixes various ASF problems (flooding the network, not able to send PET).
       - add code to clear TxMbuf content
       - add code to enable mbuf manager

Version 3.06:
    1. Added CardBus support.
    2. Fixed stack overflow problem when ASF is enabled.

Version 3.05:
    1. Changed to force CLKRUN to maintain PCI clock for Mini-PCI mode.

Version 3.04:
    1. Fixed a problem where system can be waken up with a broadcast 
       packets with zero data content.
    2. Programed internal voltage regulator to raise voltage from 1.23V to 
       1.24V.

Version 3.03:
    1. Changed to disable Auto powerdown feature by default.

Version 3.02:
    1. Changed to allow user to enable/disable Auto powerdown GPHY.

Version 3.01:
    1. Changed to program optimum value for voltage regulator.

Version 3.00:
    1. Changed to enable CLKRUN output when it's in Mini-PCI mode.

Version 2.27:
    1. Fixed a problem where OOB WOL doesn't work.

Version 2.26:
    1. Implemented a new WOL scheme that requires drivers released
       after 07/17/02. Legacy drivers will continue to behave according 
       to the old scheme.
    2. Added power saving mode support.
    3. Fixed State Reg. 2nd stage boodcode override bug.
    4. Fixed WOL when power down from PXE or DOS driver.
    5. Fixed the timing on the ASF enable information propagation.
    6. Added workaround for ATMEL flash corruption problem.
    7. Fixed driver/bootcode race condition on MII register read problem.
    8. Turned VAUX off when WoL is disabled at standby power.
    9. Turn on GPHY.
   10. Changed to reserve memory for ASF firmware when it's enabled.

Version 2.25:
    1. Fixed PXE speed bug
    2. Added PCIX State Reg. RETRY_SAME_DMA workaround
    3. Fixed a problem where it doesn't load ASF.

Version 2.24  :
    1. Fixed a problem where system is locked if PXE is enabled.

Version 2.23  :
    1. Initial release for BCM5705.