/****************************************************************************
** Copyright (c) 2001 by Wipro Technologies Ltd.
** This module is a confidential and proprietary property of Wipro Technologies
** Ltd. and possession or use of this module requires written permission from
** Wipro Technologies.
** File Name : readme.txt
** Author : Poonam Singh
** Project : DDR CONTROLLER
** Created on : 08th April 2005
** Last modified on :
** Last modified By :
** Description : This is the readme file for running DDR CONTROLLER
*****************************************************************************/
// IDEA of the final directory structure of DDR CONTROLLER.
+------------------+
| DP MEMORY MODEL |
|__________________|
|
|
|
+-----------------------+
| ** DDR CONTROLLER ** |
|_______________________|
|
|
|
+----------------------------------------+
| GENERIC BACKEND INTERFACE (TEST BENCH) |
|________________________________________|
**** DDR CONTROLLER
|
|
+---- tb :- Contains all the GENERIC BACKEND INTERFACE Files
|
|
+---- doc :- Contains User manual, DDR Controller Architecture doc, TestBench doc.
|
|
+---- memory :- Contains all the FLEX72S18 DP MEMORY MODEL Files
|
|
+---- functional_rtl :- Contains all the RTL files required for the functional simulation on | Altera tool
|
|
+---- netlist_rtl :- Contains all the RTL files required for the netlist simulation on | Altera tool
|
|
+---- xilinx_functional_rtl :- Contains all the RTL files required for the functional
| simulation on Xilinx tool
|
|
+---- xilinx_netlist_rtl_datawidth72 :- Contains all the RTL files required for the
| netlist simulation on Xilinx tool for Datawidth 72
|
|
|
+---- xilinx_netlist_rtl_datawidth36 :- Contains all the RTL files required for the
netlist simulation on Xilinx tool for Datawidth 36
**************
tb directory
**************
***** GENERIC BACKEND INTERFACE (TEST BENCH) *****
**Contents of tb directory
**1. tb_top.v :- Main Top file having instantisation of Memory, Backend interface, DDR Controller
**2. tb.v :- Contains all the TestCases
**3. ddr_controller_task.v :- Contains all the tasks required for test bench
**4. timing.v :- Contains all the timing required for test bench
**5. defines.v :- Contains all the defines required for test bench
**************
doc directory
**************
** Contents of doc directory
** 1. User manual doc
** 2. RTL architectural doc
** 3. TestBench doc
**************
memory directory
***************
** Contents of memory directory
** All the FLEX72S18 Memory Model files.
**********************
Altera functional_rtl directory
**********************
** Contents of Altera functional_rtl directory
1. DdrCntrlTop.v
2. fifoCntrl.v
3. config_ddr.v
4. portCntrlRead.v
5. portCntrlWrite.v
6. cycleCntrl.v
7. bidircomp_add.v
8. bidircomp.v
9. fifo.v
10. pll.v
11. pll_read.v
**********************
Altera netlist_rtl directory
***********************
** Contents of Altera netlist_rtl directory
1. DdrCntrlTop.v
2. fifoCntrl.v
3. config_ddr.v
4. portCntrlRead.v
5. portCntrlWrite.v
6. cycleCntrl.v
7. bidircomp_add.v
8. bidircomp.v
9. pll.v
10. pll_read.v
11. fifo.v
12. runme
**********************
Xilinx functional_rtl directory
**********************
** Contents of Xilinx functional_rtl directory
1. DdrCntrlTop.v
2. bidircomp.
3. bidircomp_add.v
4. BUFG.v
5. config_ddr.v
6. cycleCntrl.v
7. DCM.v
8. dcm_inst.v
9. FDDRRSE.v
10. fifo.edn
11. fifo.v
12. fifo.veo
13. fifo.xco
14. fifo.xcp
15. fifo_fifo_generator_v1_1_as_1.ngc
16. fifo_flist.txt
17. FIFO_GENERATOR_V1_1.v
18. fifoCntrl.v
19. glbl.v
20. portCntrlRead.v
21. portCntrlWrite.v
**********************
Xilinx netlist_rtl directory
***********************
** Contains four directories
1. pandr
2. rtl
3. rev_1
4. syn
** Contents of Xilinx Netlist RTL Directory
1. DdrCntrlTop.v
2. fifoCntrl.v
3. config_ddr.v
4. portCntrlRead.v
5. portCntrlWrite.v
6. cycleCntrl.v
7. bidircomp_add.v
8. bidircomp.v
9. DCM
10. fifo.v
11. runme
****************************
Steps to run the Simulation
****************************
Refer to User Manual
1. Go to the directory ./tb/
2. Run command :
For Altera
==========
For 72 Datawidth
----------------
VERILOG-XL
For netlist simulation
----------------------
% verilog +transport_int_delays +transport_path_delays +pulse_r/10 +pulse_int_r/10 +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTIONCYD18S72V18_200+NETLIST_SIMULATION+NO_PLI+PASS_MSG+GENRSP+DDRBUS36+ADDBUS18+DUMP_GENERATION /h/altera/quartusII/4.2/eda/sim_lib/stratixii_atoms.v ./tb_top.v +incdir+../memory +incdir+../netlist_rtl/simulation/verilogxl +licq_vxl
For functional simulation
-------------------------
% verilog +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTION+NO_PLI+CYD18S72V18_200+FUNCTIONAL_SIMULATION+PASS_MSG+GENRSP+DDRBUS36+ADDBUS18 /h/altera/quartusII/4.2/eda/sim_lib/stratixii_atoms.v /h/altera/quartusII/4.2/eda/sim_lib/altera_mf.v ./tb_top.v +incdir+../memory +incdir+../functional_rtl +licq_vxl
MODELSIM
For netlist simulation
----------------------
% vlog +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTIONCYD18S72V18_200+NETLIST_SIMULATION+NO_PLI+PASS_MSG+GENRSP+DDRBUS36+ADDBUS18+DUMP_GENERATION+VSIM /h/altera/quartusII/4.2/eda/sim_lib/stratixii_atoms.v ./tb_top.v +incdir+../memory +incdir+../netlist_rtl/simulation/modelsim
% vsim +transport_int_delays +transport_path_delays +pulse_r/10 +pulse_int_r/10 Testbench_Top -do "run -all"
For functional simulation
-------------------------
% vlog +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTION+NO_PLI+CYD18S72V18_200+FUNCTIONAL_SIMULATION+PASS_MSG+GENRSP+DDRBUS36+ADDBUS18+VSIM+DUMP_GENERATION /h/altera/quartusII/4.2/eda/sim_lib/stratixii_atoms.v /h/altera/quartusII/4.2/eda/sim_lib/altera_mf.v ./tb_top.v +incdir+../memory +incdir+../functional_rtl
% vsim +transport_int_delays +transport_path_delays +pulse_r/10 +pulse_int_r/10 Testbench_Top -do "run -all"
For Xilinx
==========
For 72 Datawidth
----------------
VERILOG-XL
For netlist simulation
----------------------
% verilog +transport_int_delays +transport_path_delays +pulse_r/10 +pulse_int_r/10 +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTIONCYD18S72V18_200+FUNCTIONAL_SIMULATION+NO_PLI+PASS_MSG+GENRSP+ADDBUS18+DDRBUS36+DUMP_GENERATION ../xilinx_netlist_rtl_datawidth72/rtl/glbl.v ./tb_top.v +incdir+../memory +incdir+../xilinx_netlist_rtl_datawidth72/pandr/PAR/ +licq_vxl
For functional simulation
-------------------------
% verilog +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTION+NO_PLI+CYD18S72V18_200+FUNCTIONAL_SIMULATION+PASS_MSG+GENRSP+DDRBUS36+ADDBUS18 ./tb_top.v +incdir+../memory +incdir+../xilinx_functional_rtl +licq_vxl
MODELSIM
For netlist simulation
----------------------
% vlog +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTIONCYD18S72V18_200+FUNCTIONAL_SIMULATION+NO_PLI+PASS_MSG+GENRSP+ADDBUS18+DDRBUS36+DUMP_GENERATION ../xilinx_netlist_rtl_datawidth72/rtl/glbl.v ./tb_top.v +incdir+../memory +incdir+../xilinx_netlist_rtl_datawidth72/pandr/PAR/ +licq_vxl
% vsim +transport_int_delays +transport_path_delays +pulse_r/10 +pulse_int_r/10 Testbench_Top glbl -do "run -all"
For functional simulation
-------------------------
% vlog +define+BURST_WRITE_READ+SINGLE_WRITE_READ+BYTE_ENABLE_TEST+COMBINATION_READ_WRITE+COUNTER_TEST_OPERATION+RIGHT_MAILBOX_OPERATION+LEFT_MAILBOX_OPERATION+ARBITRATION_OPERATION+HOLD_BURST_WRITE_READ_OPERATION+ALTERNATE_HOLD_ASSERTION+NO_PLI+CYD18S72V18_200+FUNCTIONAL_SIMULATION+PASS_MSG+GENRSP+DDRBUS36+ADDBUS18+VSIM+DUMP_GENERATION ./tb_top.v +incdir+../memory +incdir+../xilinx_functional_rtl
% vsim +transport_int_delays +transport_path_delays +pulse_r/10 +pulse_int_r/10 Testbench_Top -do "run -all"
3. If Options +define+GENRSP is given during compilation, Check the file
a> ModelRes.rsp :- Monitor List of the pins between TestBench & DDR Controller
b> ModelRes_memory.rsp :- Monitor List of the pins between DDR Controller & memory
4. If Options +define+DUMP_GENARATION is given during compilation, Check the file
A> ddr_controller.vcd
5. On the transcript Fail/error messages apppear by default.To get the pass messages provide +define+PASS_MSG
6. Following are the defines to run respective testcase
a> SINGLE_WRITE_READ :- Single Write & Read Operation
b> BURST_WRITE_READ :- Burst Write & Read Operation
c> BYTE_ENABLE_TEST :- Byte Enable controlled Write & Read Operation+
d> COMBINATION_READ_WRITE :- All the various combination of Single Write, Single Read, Burst Write, Burst Read.
e> COUNTER_TEST_OPERATION :- All the Mask/Counter reset, loading, address readback related Operations
f> RIGHT_MAILBOX_OPERATION :- Right Mailbox Operation
g> LEFT_MAILBOX_OPERATION :- Left Mailbox Operation
h> ARBITRATION_OPERATION :- Arbitration Operation(Busy address readback).
i> HOLD_BURST_WRITE_READ_OPERATION :- Hold Burst Write Read Operation
j> ALTERNATE_HOLD_ASSERTION :- Alternate Assertion of Hold pin during Burst Write Read Operation.
7. Below defparam explanation is applicable for both DDR Controller & Backend Interface.
a> If Option +define+DDRBUS36 is given during compilation(Command Line), Datawidth 36 is selected for memory & Datawidth 72 is selected for backend.
If Option +define+DDRBUS36 is not given during compilation(Command Line), Datawidth 18 is selected for memory & Datawidth 36 is selected for backend.
b> If Option ADDBUS17 is given during compilation(Command Line), Addrwidth 17 is selected.
If Option ADDBUS18 is given during compilation(Command Line), Addrwidth 18 is selected.
If Option ADDBUS19 is given during compilation(Command Line), Addrwidth 19 is selected.
If Option ADDBUS20 is given during compilation(Command Line), Addrwidth 20 is selected.
**************
Important Note
**************
1. For Datawidth 36
User had to edit following parameter in Flex72s18v_top.v file in memory.
parameter CYP_ADDRWIDTH = 18;
parameter CYP_DATAWIDTH = 36;
parameter CYP_BYTEWIDTH = 4;
parameter CYP_LASTADDR = 262143;
User has even to edit following defines in "config_ddr.v" file for functional simulation only.
`define addwidth 18 // Address width; supported values are 17, 18, 19, 20
`define datawidth 72 // Data Width; suppported values are 36, 72
`define byteenno 8 // number of byte enable; supported values are 4, 8
2. For Altera:-
Two Library files
1. stratixii_atoms.v
2. altera_mf.v
are required for the functional & netlist simulation.
These two library files are quartus version specific and the user should refer to the files
in their own quartus software directory.
If the quartus software directory is not present then in that case user can refer to the
above two files kept in the DDR Controller database.
********************
Steps to Synthesize
********************
"./syn/." directory consist of project files, synthesis directories.
For synthesis, user has to do following :
1. Open the GUI of Synplify_pro and load the project file DdrContTop.prj available in syn directory.
Now run the tool for synthesis to generate DdrcontTop.edf. This file is generated in rev_1
directory.
2. User can also run the "runme" script provided with the DDR_Controller code to run the Synplify_pro
in command line. This script is kept in syn directory.
************************
Steps to Place and Route
************************
The user constraints file is at ./pandr/BUILD/DdrCntrlTop.ucf and user can put constraint.
Copy the files "fifo.ngo" and "fifo_fifo_generator_v1_1_as_1.ngc" from the ./rtl/ directory in the
pandr directory if they are not present in pandr directory. These files are provided in rtl directory.
Following steps need to be considered for Place and Route-
1. For place and route and finally generate the simulation netlist for the specific target simulation
tool selected, user has to run runpar script from ./syn/. This script is in syn directory. The target
simulation tool for the netlist can be selected from settings, simulation tool from GUI.
2. The output of these runs will be available as DdrContTop.v and DdrContTop.sdf in ./pandr/PAR/ for
netlist simulation.
******************************************************************************************************
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.