=============================================================================
Intel(R) Server Board SE7501WV2
=============================================================================
INTEL Enterprise Platform & Services Marketing
Intel Corporation
2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA
=============================================================================
DATE: November 7, 2003
TO: Intel server platform SE7501WV2 customers
SUBJECT: Intel SE7501WV2 BIOS Release Notes ver P16 - Release 16.00:
=============================================================================
Information in this document is provided in connection with Intel products.
No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's
Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating
to fitness for a particular purpose, merchantability, or infringement of any
patent, copyright or other intellectual property right. Intel Corporation
may have patents or pending patent applications, trademarks, copyrights, or
other intellectual property rights that relate to the presented subject matter.
The furnishing of documents and other materials and information does not
provide any license, express or implied, by estoppel or otherwise, to any such
patents, trademarks, copyrights, or other intellectual property rights.
Intel products are not intended for use in medical, life saving, or life
sustaining applications. Intel may make changes to specifications and product
descriptions at any time, without notice.
Intel is a registered trademark of Intel Corporation.
*Other names and brands are the property of their respective owners.
Copyright (C) 2003 Intel Corporation.
=============================================================================
ABOUT THIS RELEASE
=============================================================================
Build Stamp: SWV25.86B.0190.P16.0310281020
SWV2 Production Release BIOS Version 16.00
BIOS Build 0190
=============================================================================
BIOS COMPONENTS/CONTENTS
=============================================================================
Processor supported: Intel(R) Xeon(TM) Processors
Microcode update versions:
CPUID Microcode update ID
F24 1F
F25 14
F27 38
F29 18
=============================================================================
SYSTEM FIRMWARE REQUIREMENTS/REVISIONS
=============================================================================
Firmware revision:
BMC 1.19
FRU/SDR : 5.5.7 or higher
=============================================================================
INSTALLATION NOTES
=============================================================================
IMPORTANT NOTES:
1. CMOS is often recommended to be cleared after a BIOS update.
BIOS P16 does not require a CMOS clear if updating from BIOS P11 or P15
and the CMOS clear was done during those updates. If you are updating
from a BIOS version older than P11 you must clear CMOS in order
for the L3 cache option to be activated.
UPDATE INSTRUCTIONS:
1. Create a BIOS update disk; ensure to use a bootable floppy.
2. Boot the SE7501WV2 server board with floppy created in step #1.
3. At the DOS prompt type 1 (or 1.BAT) and press <Enter>. The update will
show two progress bars. After the second progress bar has reached 100
percent, the system will reboot (typically under 3 minutes).
4. Once the update is complete, proceed to clear CMOS.
CLEARING CMOS: (See "Important Notes" above)
1. Press and hold the front panel reset button for 4+ seconds.
2. Continue to hold the reset button and press the front panel power button
3. Release the reset and power button at the same time.
4. The server board will appear to boot in a normal manner but should display
a "CMOS Cleared by Jumper" message during the Power On Self Test.
=============================================================================
KNOWN ISSUES/WORKAROUNDS
=============================================================================
NONE
=============================================================================
NEW FEATURES
=============================================================================
NONE
============================================================================
ISSUES RESOLVED
============================================================================
Fixed POST hang when rebooting mutiple times.
============================================================================
PREVIOUS RELEASES
============================================================================
SE7501WV2 BIOS P15
New Features:
"M0" stepping of Intel Xeon Processors (2/2.4/2.66/2.8/3.06/3.2GHz)
is made possible in this bios.
Issues Resolved:
533 Processors Show 'Max Speed' and 'Curent Speed' Slightly Slower
Added increased processor speeds info to the BIOS ASM table.
Includes the 41003S2 Adaptec SCSI Option ROM
BIOS allows mixing of N-1 stepping processors (D1 stepping) with M0
stepping Processors without L3 cache
Includes new B0, D1 and M0 stepping CPU updates
Sony SDX-420C & SDX-520C ATAPI Tape Drives now work in U-DMA and PIO
-- SE7501WV2 BIOS P11
New Features:
Added support for M0 processors (both with and without 1M L3 cache).
Added support for mixed cpu steppings.
Issues Resolved:
Fix for failure to display Logo (Splash Screen) when booting.
Fix for MCH Errata3 -- system hung after asynchronous reset to DIMM. Fixed
issue where some DIMMS could get locked Up in a bad state, causing ECC errors
During POST. This needed a DC power cycle to get the DIMM back to normal
Working order.
Fixed issue where NIC1 can not PXE Boot if the device that is higher in boot
priority is connected
Added support for 3.06 Gig processors to SMBIOS tables.
BIOS P08 Not Allowing SMP Kernel to Load with RH AS 2.1 ES
DIMM error occurred on POST with Samsung 1GB during AC or DC cycling test.
Fix to make PCI slots on 1U systems match the value returned by PCI BIOS function
B1h, sub-function 0Eh (Get PCI IRQ routing option), previously it just returned
the # of slots in the system.
Added fix to open up more F000 space by removing code for non-Xeon processors.
This may fix the MPS table issue when certain NICs are added.
-- SE7501WV2 BIOS P09
New Features:
Added support for D1 processor.
Issues Resolved:
Fixed .ASL code so the Online update code would work, and still pass WHQL testing.
-- SE7501WV2 BIOS P06
Updated FRBDisable strings from 'Disable' to 'Disabled' per the EPS.
Changed Type 8 structure strings for Serial ports from COM A/Serial Port B
to Serial Port 1/Serial Port 2.
Add _ to the start of the OEM strings that were space characters. This is done
so the macro won't strip out the space chars. We need the padding to allow GPNV
updates of type 11 to work.
Changed default of Q_SYSMGMT_CONTINUE_SERIAL_REDIR token to 0. This prevents the
console redirection disable escape sequence from being sent to the keyboard.
Added code to populate the SSID when the Adaptec RAID option is selected.
HCT 11.x complained about I/O Apic memory assignments not being defined. Changed
code to not include these ranges when defining the PCI hole.
Fixed BIOS LED codes for 3 Memory beep codes to follow the EPS.
Add code to determine if serial ports are disabled when selecting setup items
BIOS Redirection Port and ACPI Redirection Port. If the serial port is not disabled,
don't display it and if both are disabled, gray the option.
When CMOS is cleared via the front panel switches, don't display message to power down
the system and clear the CMOS jumper when exiting setup.
Don't enable boot monitor timer on boot to floppy or CDROM drive.
Selecting Reset config data in setup doesn't generate a system re-configured
SEL event. Also, when exiting setup saving changes, system re-configured event isn't logged.
Add code to allow PXE boot from NIC 1 even if NIC 2 is connected.
Needed to describe BMC address ranges in ASL code to pass HCT 11.x tests.
Late POST Timeout: The late post timeout functionality wasn't implemented to behave
the same as the OS boot and PXE boot timeout. This functionality is required for Telco.
Fixed 32bit PCI code that returns the PCI IRQ routing information. ESI should return
the pointer to the table, but the upper 16 bits were incorrect. Changed to code to properly
compute the physicall address of the IRQ table.
Add MCA handler for processors. This is a requirement for processors with Hyperthreading Technology.
See Netburst BWG update for details.
-- SWV2 Production Release BIOS 5.00
Debugged error logging of DIMM ordering rules. Single
Row DIMMs must be populated furthest away from the MCH.
they are not, then a 3 beep POST error will occur with
POST DIAG LEDs = 08h.
Update to memory reference code revision 1.02.
SWV2 Production Release BIOS 4.00
BIOS doesn't lock down the primary flash partition, it only locks it.
Changed code to lock down the BIOS in the primary partition so it can't be
over written.
-- SWV2 Production Release BIOS 3.00
Error message not displayed during POST for different
speed processors.
FRB Policy set to "Retry 3 Times" in Setup causes
the system to not complete POST.
When CMOS jumper is set, Setup shows installed
DIMMs as "Not Installed."
Added string translations for BMC related strings in Setup.
-- SWV2 Production Release BIOS 2.00
Added a POST screen message to display FSB
speed since both 400MHz and 533MHz processors can run
in the system. This will give the end user feedback on which
processors are installed.
Update to memory reference code rev. 1.01
System ACPI Power State is not reflected
at the time of S1 and S4 Sleep. Removed the checks for
EC ASL code for board revision ID. The board revision
ID code was only needed for WV400.
Post 12 hang on power-cycle. Added code
to not access the NIC on the first boot when determining
OEM/Intel behaviour. This is causing a hang when the P64H2
PLL isn't synched.
Need to change MAX length of strings for
DMI Type1. Changed default string length from 32 chars to
40 chars.
New ATA Promise option ROM version 2.0.0140.8.
-- SWV2 Production Release BIOS 1.00
Remove SMBUS I/O ranges from motherboard
resources in the ASL code. Win2K was showing I/O conflicts
with the SMBUS device.
Remove BMC ports from the motherboard
resources ASL code. It is breaking an OEM's
IPMI driver.
WV(533) fails to boot with ATA option
selected in BIOS. Added new ATA Promise ROM that correctly
handles EBDA.
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.