840A-DM.INI Driver File Contents (dv840a03.zip)

[EEPROM]
mingnt=0x01             ;Low byte of Address 03h
maxlat=0x10             ;High byte of Address 03h
sbid=0x0840             ;Address 04h: subsystem ID
sbvid=0x1050            ;Address 05h: subsystem vendor ID
rev=0x00                ;Low byte of Address 08h
c48=0xc0                ;High byte of Address 08h

;
DefIOBase=0xd000        ;C10, free IObase assigned by user

;*** CXX R/W Test
[Cxx]
iter=4

;--- for W89C840A Chip
; <write mask> <zero bit> <one bit>
w840_00= FFFFFFFE FFCF0000 00000000
w840_04= 00000000 00000000 00000000
w840_08= 00000000 00000000 00000000
w840_0C= FFFFFFFF 00000003 00000000
w840_10= FFFFFFFF 00000003 00000000
w840_14= 00000000 00000000 00000000
w840_18= FFFFDFFD 00001105 00000000
w840_1C= FFFFFFFF FFFE5200 00000000
w840_20= 00000000 00000000 00000000
w840_24= 00000000 00000000 00000000
w840_28= FFFFFFFF FFFC0000 00000000
w840_2C= 00000000 00000000 00000000
w840_30= 00000000 00000000 00000000
w840_34= 00000000 00000000 00000000
w840_38= FFFFFFFF 00000000 00000000
w840_3C= FFFFFFFF 00000000 00000000
w840_40= FFFFFFFF 00000000 00000000
w840_44= FFFFFFFF FFFF0000 00000000
w840_48= FFFFFFFF FFFFFFF8 00000000
w840_4C= 00000000 00000000 00000000
w840_50= 00000000 00000000 00000000

[LOOPBACK]

;<testname>=<tdes> <rdes> <packet-list> <skip-length>
;           <burst-len> <cache-align> <test-count> <rand-seed>
; <skip-length>     0 .. 31
; <burst-len>       0, 1, 2, 4, 8, 16, 32
; <cache-align>     1, 2, 3
; <test-count>      1 ..
; <rand-seed>       0, 1 ..

;------ BUFFER STRUCTURE TEST ------
n_stru_00=BurstLen= 0, CacheAlign= 8
p_stru_00=BufStru BufStru cylu 4 0  1 2 0
n_stru_01=BurstLen= 0, CacheAlign=16
p_stru_01=BufStru BufStru cylu 4 0  2 2 0
n_stru_02=BurstLen= 0, CacheAlign=32
p_stru_02=BufStru BufStru cylu 4 0  3 2 0
n_stru_03=BurstLen= 1, CacheAlign= 8
p_stru_03=BufStru BufStru cylu 4 1  1 2 0
n_stru_04=BurstLen= 1, CacheAlign=16
p_stru_04=BufStru BufStru cylu 4 1  2 2 0
n_stru_05=BurstLen= 1, CacheAlign=32
p_stru_05=BufStru BufStru cylu 4 1  3 2 0
n_stru_06=BurstLen= 2, CacheAlign= 8
p_stru_06=BufStru BufStru cylu 4 2  1 2 0
n_stru_07=BurstLen= 2, CacheAlign=16
p_stru_07=BufStru BufStru cylu 4 2  2 2 0
n_stru_08=BurstLen= 2, CacheAlign=32
p_stru_08=BufStru BufStru cylu 4 2  3 2 0
n_stru_09=BurstLen= 4, CacheAlign= 8
p_stru_09=BufStru BufStru cylu 4 4  1 2 0
n_stru_10=BurstLen= 4, CacheAlign=16
p_stru_10=BufStru BufStru cylu 4 4  2 2 0
n_stru_11=BurstLen= 4, CacheAlign=32
p_stru_11=BufStru BufStru cylu 4 4  3 2 0
n_stru_12=BurstLen= 8, CacheAlign= 8
p_stru_12=BufStru BufStru cylu 4 8  1 2 0
n_stru_13=BurstLen= 8, CacheAlign=16
p_stru_13=BufStru BufStru cylu 4 8  2 2 0
n_stru_14=BurstLen= 8, CacheAlign=32
p_stru_14=BufStru BufStru cylu 4 8  3 2 0
n_stru_15=BurstLen=16, CacheAlign= 8
p_stru_15=BufStru BufStru cylu 4 16 1 2 0
n_stru_16=BurstLen=16, CacheAlign=16
p_stru_16=BufStru BufStru cylu 4 16 2 2 0
n_stru_17=BurstLen=16, CacheAlign=32
p_stru_17=BufStru BufStru cylu 4 16 3 2 0
n_stru_18=BurstLen=32, CacheAlign= 8
p_stru_18=BufStru BufStru cylu 4 32 1 2 0
n_stru_19=BurstLen=32, CacheAlign=16
p_stru_19=BufStru BufStru cylu 4 32 2 2 0
n_stru_20=BurstLen=32, CacheAlign=32
p_stru_20=BufStru BufStru cylu 4 32 3 2 0

;------ BUFFER SIZE TEST ------
n_size_00=C-C-C-C 1-1-1-1
p_size_00=Size0 Size0 cylu 4 8  2 2 0
n_size_01=C-C-C-C 1-0-0-1
p_size_01=Size1 Size1 cylu 4 8  2 2 0
n_size_02=C-C-C-C 0-1-0-1
p_size_02=Size2 Size2 cylu 4 8  2 2 0
n_size_03=C-C-C-C 0-1-1-0
p_size_03=Size3 Size3 cylu 4 8  2 2 0
n_size_04=R-R (1,1)-(1,1)
p_size_04=Size4 Size4 cylu 4 8  2 2 0
n_size_05=R-R (1,0)-(0,1)
p_size_05=Size5 Size5 cylu 4 8  2 2 0
n_size_06=R-R (0,1)-(0,1)
p_size_06=Size6 Size6 cylu 4 8  2 2 0
n_size_07=R-R (0,1)-(1,0)
p_size_07=Size7 Size7 cylu 4 8  2 2 0

;------ BUFFER EXTRA BYTES TEST ------
n_extr_00=(1,1),(1,1)-(1,2),(1,1)
p_extr_00=ExtraByte0 Extrabyte0 extr01 4 8 2 2 0
n_extr_01=(2,1),(2,1)-(2,2),(2,1)
p_extr_01=ExtraByte1 ExtraByte1 extr23 4 8 2 2 0
n_extr_02=(3,1),(3,1)-(3,2),(3,1)
p_extr_02=ExtraByte2 ExtraByte2 extr01 4 8 2 2 0
n_extr_03=(1,2),(1,2)-(1,3),(1,2)
p_extr_03=Extrabyte3 ExtraByte3 extr23 4 8 2 2 0
n_extr_04=(2,2),(2,2)-(2,3),(2,2)
p_extr_04=ExtraByte4 ExtraByte4 extr01 4 8 2 2 0
n_extr_05=(3,2),(3,2)-(3,3),(3,2)
p_extr_05=ExtraByte5 ExtraByte5 extr23 4 8 2 2 0
n_extr_06=(1,3),(1,3)-(1,1),(1,3)
p_extr_06=ExtraByte6 ExtraByte6 extr02 4 8 2 2 0
n_extr_07=(2,3),(2,3)-(2,1),(2,3)
p_extr_07=ExtraByte7 ExtraByte7 extr20 4 8 2 2 0
n_extr_08=(3,3),(3,3)-(3,1),(3,3)
p_extr_08=ExtraByte8 ExtraByte8 extr02 4 8 2 2 0

;------ BUFFER START ADDRESS TEST ------
n_addr_00=Start Address=1
p_addr_00=StartAdd1 StartAdd1 sadr02 4 8  2 2 0
n_addr_01=Start Address=2
p_addr_01=StartAdd2 StartAdd2 sadr02 4 8  2 2 0
n_addr_02=Start Address=3
p_addr_02=StartAdd3 StartAdd3 sadr02 4 8  2 2 0
n_addr_03=Start Address=4
p_addr_03=StartAdd4 StartAdd4 sadr02 4 8  2 2 0
n_addr_04=Start Address=5
p_addr_04=StartAdd5 StartAdd5 sadr02 4 8  2 2 0
n_addr_05=Start Address=6
p_addr_05=StartAdd6 StartAdd6 sadr02 4 8  2 2 0
n_addr_06=Start Address=7
p_addr_06=StartAdd7 StartAdd7 sadr02 4 8  2 2 0

;------ SKIP LENGTH TEST ------
n_skip_00=R-R-R-R-R-R, Skip Length=4
p_skip_00=Skip Skip cylu 4  0 1 2 0
n_skip_01=R-R-R-R-R-R, Skip Length=5
p_skip_01=Skip Skip cylu 5  0 1 2 0
n_skip_02=R-R-R-R-R-R, Skip Length=6
p_skip_02=Skip Skip cylu 6  0 1 2 0
n_skip_03=R-R-R-R-R-R, Skip Length=7
p_skip_03=Skip Skip cylu 7  0 1 2 0
n_skip_04=R-R-R-R-R-R, Skip Length=8
p_skip_04=Skip Skip cylu 8  0 1 2 0
n_skip_05=R-R-R-R-R-R, Skip Length=9
p_skip_05=Skip Skip cylu 9  0 1 2 0
n_skip_06=R-R-R-R-R-R, Skip Length=10
p_skip_06=Skip Skip cylu 10 0 1 2 0
n_skip_07=R-R-R-R-R-R, Skip Length=11
p_skip_07=Skip Skip cylu 11 0 1 2 0
n_skip_08=R-R-R-R-R-R, Skip Length=12
p_skip_08=Skip Skip cylu 12 0 1 2 0
n_skip_09=R-R-R-R-R-R, Skip Length=13
p_skip_09=Skip Skip cylu 13 0 1 2 0
n_skip_10=R-R-R-R-R-R, Skip Length=14
p_skip_10=Skip Skip cylu 14 0 1 2 0
n_skip_11=R-R-R-R-R-R, Skip Length=15
p_skip_11=Skip Skip cylu 15 0 1 2 0
n_skip_12=R-R-R-R-R-R, Skip Length=16
p_skip_12=Skip Skip cylu 16 0 1 2 0
n_skip_13=R-R-R-R-R-R, Skip Length=17
p_skip_13=Skip Skip cylu 17 0 1 2 0
n_skip_14=R-R-R-R-R-R, Skip Length=18
p_skip_14=Skip Skip cylu 18 0 1 2 0
n_skip_15=R-R-R-R-R-R, Skip Length=19
p_skip_15=Skip Skip cylu 19 0 1 2 0
n_skip_16=R-R-R-R-R-R, Skip Length=20
p_skip_16=Skip Skip cylu 20 0 1 2 0
n_skip_17=R-R-R-R-R-R, Skip Length=21
p_skip_17=Skip Skip cylu 21 0 1 2 0
n_skip_18=R-R-R-R-R-R, Skip Length=22
p_skip_18=Skip Skip cylu 22 0 1 2 0
n_skip_19=R-R-R-R-R-R, Skip Length=23
p_skip_19=Skip Skip cylu 23 0 1 2 0
n_skip_20=R-R-R-R-R-R, Skip Length=24
p_skip_20=Skip Skip cylu 24 0 1 2 0
n_skip_21=R-R-R-R-R-R, Skip Length=25
p_skip_21=Skip Skip cylu 25 0 1 2 0
n_skip_22=R-R-R-R-R-R, Skip Length=26
p_skip_22=Skip Skip cylu 26 0 1 2 0
n_skip_23=R-R-R-R-R-R, Skip Length=27
p_skip_23=Skip Skip cylu 27 0 1 2 0
n_skip_24=R-R-R-R-R-R, Skip Length=28
p_skip_24=Skip Skip cylu 28 0 1 2 0
n_skip_25=R-R-R-R-R-R, Skip Length=29
p_skip_25=Skip Skip cylu 29 0 1 2 0
n_skip_26=R-R-R-R-R-R, Skip Length=30
p_skip_26=Skip Skip cylu 30 0 1 2 0
n_skip_27=R-R-R-R-R-R, Skip Length=31
p_skip_27=Skip Skip cylu 31 0 1 2 0

;------ LAST PREEMPT LINK TEST ------
n_last_00=BurstLen= 0, CacheAlign= 8
p_last_00=LastLink LastLink cylu 4 0  1 2 0
n_last_01=BurstLen= 0, CacheAlign=16
p_last_01=LastLink LastLink cylu 4 0  2 2 0
n_last_02=BurstLen= 0, CacheAlign=32
p_last_02=LastLink LastLink cylu 4 0  3 2 0
n_last_03=BurstLen= 1, CacheAlign= 8
p_last_03=LastLink LastLink cylu 4 1  1 2 0
n_last_04=BurstLen= 1, CacheAlign=16
p_last_04=LastLink LastLink cylu 4 1  2 2 0
n_last_05=BurstLen= 1, CacheAlign=32
p_last_05=LastLink LastLink cylu 4 1  3 2 0
n_last_06=BurstLen= 2, CacheAlign= 8
p_last_06=LastLink LastLink cylu 4 2  1 2 0
n_last_07=BurstLen= 2, CacheAlign=16
p_last_07=LastLink LastLink cylu 4 2  2 2 0
n_last_08=BurstLen= 2, CacheAlign=32
p_last_08=LastLink LastLink cylu 4 2  3 2 0
n_last_09=BurstLen= 4, CacheAlign= 8
p_last_09=LastLink LastLink cylu 4 4  1 2 0
n_last_10=BurstLen= 4, CacheAlign=16
p_last_10=LastLink LastLink cylu 4 4  2 2 0
n_last_11=BurstLen= 4, CacheAlign=32
p_last_11=LastLink LastLink cylu 4 4  3 2 0
n_last_12=BurstLen= 8, CacheAlign= 8
p_last_12=LastLink LastLink cylu 4 8  1 2 0
n_last_13=BurstLen= 8, CacheAlign=16
p_last_13=LastLink LastLink cylu 4 8  2 2 0
n_last_14=BurstLen= 8, CacheAlign=32
p_last_14=LastLink LastLink cylu 4 8  3 2 0
n_last_15=BurstLen=16, CacheAlign= 8
p_last_15=LastLink LastLink cylu 4 16 1 2 0
n_last_16=BurstLen=16, CacheAlign=16
p_last_16=LastLink LastLink cylu 4 16 2 2 0
n_last_17=BurstLen=16, CacheAlign=32
p_last_17=LastLink LastLink cylu 4 16 3 2 0
n_last_18=BurstLen=32, CacheAlign= 8
p_last_18=LastLink LastLink cylu 4 32 1 2 0
n_last_19=BurstLen=32, CacheAlign=16
p_last_19=LastLink LastLink cylu 4 32 2 2 0
n_last_20=BurstLen=32, CacheAlign=32
p_last_20=LastLink LastLink cylu 4 32 3 2 0

;------ Multicast TEST ------
n_mult_00=BurstLen=32, CacheAlign=32
p_mult_00=BufStru BufStru mult 4 32 3 256 0

[PRACTXRX]
;<testname>=<tdes> <rdes> <packet-list> <skip-length>
;           <burst-len> <cache-align> <test-count> <rand-seed>
; <skip-length>     0 .. 31
; <burst-len>       0, 1, 2, 4, 8, 16, 32
; <cache-align>     1, 2, 3
; <test-count>      1 ..
; <rand-seed>       0, 1 ..

n_prrx_00=Rx Misc Packets Test (Ring)
p_prrx_00=maxring  maxring  misc 4 8 2 0 0
n_prrx_01=Rx Misc Packets Test (Chain)
p_prrx_01=maxchain maxchain misc 4 8 2 0 0

n_prtx_00=Tx Misc Packets Test (Ring)
p_prtx_00=maxring  maxring  misc 4 8 2 0 0
n_prtx_01=Tx Misc Packets Test (Chain)
p_prtx_01=maxchain maxchain misc 4 8 2 0 0

n_txrx_00=Tx/Rx Misc Packets Test (Ring)
p_txrx_00=maxring  maxring  misc 4 8 2 0 0
n_txrx_01=Tx/Rx Misc Packets Test (Chain)
p_txrx_01=maxchain maxchain misc 4 8 2 0 0

/* 87-09-25 add */
n_magic_00=Tx/Rx Misc Packets Test (Ring)
p_magic_00=maxring  maxring  send 4 8 2 0 0
/* 88-01-08 add */
n_frame0_00=Tx/Rx Misc Packets Test (Ring)
p_frame0_00=maxring  maxring  frame0 4 8 2 0 0
n_frame1_00=Tx/Rx Misc Packets Test (Ring)
p_frame1_00=maxring  maxring  frame1 4 8 2 0 0
n_frame2_00=Tx/Rx Misc Packets Test (Ring)
p_frame2_00=maxring  maxring  frame2 4 8 2 0 0
n_frame3_00=Tx/Rx Misc Packets Test (Ring)
p_frame3_00=maxring  maxring  frame3 4 8 2 0 0

[MAGIC]
txrx=maxring  maxring  send  4 8 2 0 0
; 88-01-08 add
[FRAME0]
txrx=maxring  maxring  frame0  4 8 2 0 0
[FRAME1]
txrx=maxring  maxring  frame1  4 8 2 0 0
[FRAME2]
txrx=maxring  maxring  frame2  4 8 2 0 0
[FRAME3]
txrx=maxring  maxring  frame3  4 8 2 0 0

[DESC]

BufStru_00=R 0 64 0 1500 C 0 1518 C 0 1518 R 0 64 0 1500
BufStru=4 6

LastLink_00=R 0 64 0 1500 C 0 1518 C 0 1518 R 0 64 0 1500 X 0 1518 0 0
LastLink=5 8

Skip_00=R 0 100 0 100 R 0 100 0 100 R 0 100 0 1100
Skip_01=R 0 100 0 100 R 0 100 0 1300 R 0 64 0 1500
Skip=6 12

Size0_00=C 0 1518 C 0 1518 C 0 1518 C 0 1518
Size0=4 4
Size1_00=C 0 1518 C 0 0 C 0 0 C 0 1518
Size1=4 4
Size2_00=C 0 0 C 0 1518 C 0 0 C 0 1518
Size2=4 4
Size3_00=C 0 0 C 0 1518 C 0 1518 C 0 0
Size3=4 4
Size4_00=R 0 1500 0 64 R 0 64 0 1500
Size4=2 4
Size5_00=R 0 1518 0 0 R 0 0 0 1518
Size5=2 4
Size6_00=R 0 0 0 1518 R 0 0 0 1518
Size6=2 4
Size7_00=R 0 0 0 1518 R 0 1518 0 0
Size7=2 4

ExtraByte0_00=R 1 642 1 900 R 1 643 1 900
ExtraByte0=2 4
ExtraByte1_00=R 2 643 2 900 R 2 644 2 900
ExtraByte1=2 4
ExtraByte2_00=R 3 644 3 900 R 3 645 3 900
ExtraByte2=2 4
ExtraByte3_00=R 1 643 1 900 R 1 644 1 900
ExtraByte3=2 4
ExtraByte4_00=R 2 644 2 900 R 2 645 2 900
ExtraByte4=2 4
ExtraByte5_00=R 3 645 3 900 R 3 646 3 900
ExtraByte5=2 4
ExtraByte6_00=R 1 644 1 900 R 1 642 1 900
ExtraByte6=2 4
ExtraByte7_00=R 2 645 2 900 R 2 643 2 900
ExtraByte7=2 4
ExtraByte8_00=R 3 646 3 900 R 3 644 3 900
ExtraByte8=2 4

StartAdd1_00=R  7 646  7 900 R  7 644  7 900
StartAdd1=2 4
StartAdd2_00=R 11 646 11 900 R 11 644 11 900
StartAdd2=2 4
StartAdd3_00=R 15 646 15 900 R 15 644 15 900
StartAdd3=2 4
StartAdd4_00=R 19 646 19 900 R 19 644 19 900
StartAdd4=2 4
StartAdd5_00=R 23 646 23 900 R 23 644 23 900
StartAdd5=2 4
StartAdd6_00=R 27 646 27 900 R 27 644 27 900
StartAdd6=2 4
StartAdd7_00=R 31 646 31 900 R 31 644 31 900
StartAdd7=2 4

minchain_00=C 0 1518 C 0 1518
minchain= 2  2

easy_00=R 0 1518 0 0  R 0 1518 0 0  R 0 1518 0 0  R 0 1518 0 0
easy_01=R 0 1518 0 0  R 0 1518 0 0  R 0 1518 0 0  R 0 1518 0 0
easy_02=R 0 1518 0 0  R 0 1518 0 0  R 0 1518 0 0  R 0 1518 0 0
easy=12 12

maxchain_00=C 0 1518 C 0 1518 C 0 1518 C 0 1518 C 0 1518 C 0 1518
maxchain_01=C 0 1518 C 0 1518 C 0 1518 C 0 1518 C 0 1518 C 0 1518
maxchain=12 12

maxring_00=R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518
maxring_01=R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518
maxring_02=R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518
maxring_03=R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518 R 0 1518 0 1518
maxring=12 24

[PKTL]
; BC=0, MC=1, XM=2, UC=3, XU=4, CE=5, XC=6, ECEP=3, ECDP=7, DCEP=8, DCDP=9
;<packet type> <packet content> <packet length (exc CRC)>
cylu=1
cylu_00=3 cylu0.pkt 1514

extr01=2
extr01_00=3 fa50.pkt 1000
extr01_01=3 fa50.pkt 1001

extr23=2
extr23_00=3 fa50.pkt 1002
extr23_01=3 fa50.pkt 1003

extr02=2
extr02_00=3 fa50.pkt 1000
extr02_01=3 fa50.pkt 1002

extr20=2
extr20_00=3 fa50.pkt 1002
extr20_01=3 fa50.pkt 1000

sadr02=2
sadr02_00=3 fa50.pkt 1000
sadr02_01=3 fa50.pkt 1002

misc= 1
misc_00= 3 digit.pkt    64

; 87-09-24 add
send= 1
send_00= 0 magic.pkt   116
; 88-01-08 add
frame0= 1
frame0_00= 3 enframe3.pkt   60
frame1= 1
frame1_00= 3 enframe4.pkt   60
frame2= 1
frame2_00= 3 enframe5.pkt   60
frame3= 1
frame3_00= 3 enframe6.pkt   60

mult= 4
mult_00= 1 digit.pkt   640
mult_01= 1 digit.pkt   640
mult_02= 1 digit.pkt   640
mult_03= 1 digit.pkt   640

[AUTO]
n_auto_00=Automatical Diagnosis 1: Loopback Test
p_auto_00=lpbk
n_auto_01=Automatical Diagnosis 2: Fxx Register Test
p_auto_01=fxxt
n_auto_02=Automatical Diagnosis 3: Cxx Register Test
p_auto_02=cxxt

[AUTON]
n_auton_00=Automatical Diagnosis 1: Loopback Test
p_auton_00=lpbk
n_auton_01=Automatical Diagnosis 2: Cxx Register Test
p_auton_01=cxxtn

[KEYL]
auto=27
auto_00=1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-
auto_01=19-20-21-22-23-24-25-26-0-
LPBK=11
LPBK_00=108-115-337-337-13-13-27-27-27-97-0-
FXXT=7
FXXT_00=112-13-27-27-97-336-0-
CXXT=8
CXXT_00=99-13-27-27-97-336-336-0-
CXXTN=7
CXXTN_00=99-13-27-27-97-336-0-

[MISC]
delay=18        ;delay of key playing
dura=819        ;duration of general timer
miimask=0x21ff  ;mask value for MII interface test
mech=-1         ;access PCI cfg space by -1:Auto, 0:Bios, 1:mech#1, 2:mech#2
amem=0xD000         ;unused memory area
; local=06 05 04 03 02 01
; FF-FF-FF-FF-FF-FF     ;0
mult=05 04 03 02 01 00  ;1
xmul=05 06 07 08 09 0A  ;2
peer=00 0A 0B 0C 0D 0E  ;3  use as DestID when transmit
; 88-88-88-88-88-88     ;4
run840a=0      ; 1: run 840a only, 0: run 840a or 840
Download Driver Pack
840A-DM.INI Driver File Contents (dv840a03.zip)

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