Release Notes for MV-2XXX Distribution Software
Ver. 1.11 February 22, 2005
What's new
----------
- Supports FPGA chip rev. 1, which is required by the following new features.
- Added support for 2 stream, 2 block data layout. See
"2 STREAM, 2 BLOCK DATA LAYOUT SUPPORT" section.
- Added the following new sections in the camera configuration file
[PLL Control]
[Sync Generator]
[Clock Generator]
The documentation on these new sections is included in this file, see
"NEW CAMERA CONFIGURATION ENTRIES" section.
- Added 16 bit TIFF file support for both the utility program and the SDK, which
can be used to save 10, 12, 16 bit image into a TIFF file.
- Added following new camera configuration files:
tm1040.ini
tm1320.ini
L301k32RGB.ini
- Fixed some minor bugs.
HISTORY (Ver 1.10)
------------------
MV-2XXX SDK becomes available with this release.
HISTORY (Ver 1.00)
------------------
This is the first release of the MV-2XXX board and software. To install the
board and the software, please refer to "MV-2500/2600 Digital Camera
Interface Boards User's Guide".
The current release of distribution software includes camera configuration
files for:
Product Camera Type File Name
_______ _______________________________________________ ________________
MV-2500 Basler A101 (Areascan, single tap) A101.ini
MV-2500 Pulnix TM-7200 (Areascan, interlaced, shifted) tm7200.ini
MV-2500 Pulnix TM-9700 (Areascan, non-interlaced) tm9700.ini
MV-2500 Uniq UP-680 (Areascan, non-interlaced, 10 bit) UP680.INI
MV-2500 Pulnix TM-1040 (Areascan, non-interlaced, shifted) tm1040.INI
MV-2500 Pulnix TM-1320 (Areascan, non-interlaced, 8 bit) tm1320.INI
MV-2600 Atmel SM2CL (Linescan, 1 or 2 taps, 8, 10, 12 bit) SM2CL4010.ini
MV-2600 Dalsa 1M150 (Areascan, 2 taps) 1M150.ini
MV-2600 Pulnix TMC-1000 (Areascan, RGB) tmc1000cl.ini
MV-2600 Uniq UP-680-12 (Areascan, 12 bit) UP680CL12.ini
MV-2600 Basler L301kc (Linescan RGB) L301k32RGB.ini
2 STREAM, 2 BLOCK DATA LAYOUT SUPPORT (since Ver. 1.11)
--------------------------------------------------------
This section is an amendment to "A.3 of Appendix A of MV-2XXX Software Development Guide".
In SDK rev. 1.11, we started supporting a 2 stream, 2 block data layout. This can be
controlled by setting the following two entries in the camera configuration file:
[Data Format]
streamLayout=2 ; must be set to 2 to use 2 stream, 2 block data layout
streamGeometry=1 ; 1 - 5, currently, 5 modes supported, see below for descriptions
streamGeometry
specifies, by means of an integer number, a pre-defined geometrical property, which is
available. Currently, the SDK supports the following modes:
1:> Two fields, interlaced. The geometry name, from the "Camera Link Tap
Configuration", is 1X_1Y2. The two fields come from 2 data streams (taps), which
are placed into two areas in the SDRAM and are de-interlaced while transferring
them into system RAM. The odd lines are from the first stream, the even lines are
from the second stream.
2:> Two half horizontal frames, top-bottom. The geometry name, from the "Camera
Link Tap Configuration", is 1X_2YE. The two half frames come from 2 data streams
(taps), which are placed into two areas in the SDRAM and are combined into a
frame while transferring them into system RAM. The top half of the frame is from
the first stream, the bottom half of the frame is from the second stream.
3:> Two half vertical frames , ->|->. The scan direction is from left to right for
both the left half and the right half. The geometry name, from the "Camera
Link Tap Configuration", is 2X_1Y. The two half horizontal frames come from 2 data
streams (taps), which are placed into two areas in the SDRAM and are combined
into a frame while transferring them into system RAM. The left half of the frame
is from the first stream, the right half of the frame is from the second stream.
4:> Two half vertical frames , ->|<-. The scan direction is from left to right for the
the left half and from right to left for the right half. The geometry name,
from the "Camera Link Tap Configuration", is 2XE_1Y. The two half horizontal
frames come from 2 data streams (taps), which are placed into two areas in the
SDRAM and are combined into a frame while transferring them into system RAM.
The left half of the frame is from the first stream, the right half of the frame is
from the second stream.
5:> Two half vertical frames , <-|->. The scan direction is from rigth to left for the
the left half and from left to right for the right half. The geometry name,
from the "Camera Link Tap Configuration", is 2XM_1Y. The two half horizontal
frames come from 2 data streams (taps), which are placed into two areas in the
SDRAM and are combined into a frame while transferring them into system RAM.
The left half of the frame is from the first stream, the right half of the frame is
from the second stream.
NEW CAMERA CONFIGURATION ENTRIES (since Ver. 1.11)
--------------------------------------------------
Phase Lock Loop (PLL) Control Section
-------------------------------------
This section controls the PLL on an MV-2XXX board. The entries in this section provide
parameters used in MV2SetPLLControl(). For more information, please see the function
description.
[PLL Control]
pll_Reference=0
pll_pFrequence=12.48
pll_Ref_Invert=0
pll_phaseAdjust=0
pll_Reference
Selects reference clock.
0:> Auto select (default). For MV-2500/2600 boards, this will select the 50 MHz LPB clock.
1:> Indicates that the reference clock is coming from internal 50MHz LPB clock.
2:> Indicates that the reference clock is coming from external clock. For MV-2500, it will
be PIXCLK. For MV-2600, it will be CLKC0.
pll_pFrequence
Specifies the pixel clock frequency. When used with camera pixel clock reference,
the parameter should be equal to pixel clock frequency. When used with internal
clock reference, this parameter sets output clock frequency, where the range is from
0.8MHz to 150 MHz.
pll_Ref_Invert
Controls the polarity of the reference clock.
0:> No inversion, so rising edge (default)
1:> Inverts the reference clock for falling edge.
pll_phaseAdjust
This parameter is used only when camera pixel clock is reference clock, which can
offset the output clock (comparing to input clock) up to 1 clock cycle. The range
or the resolution of this parameter may vary based on the pixel clock frequency:
0 - 63 when pll_pFrequence is between 0.8MHz and 12MHz
0 - 31 when pll_pFrequence is between 12MHz and 48MHz
0 - 15 when pll_pFrequence is between 48MHz and 150MHz
Sync Generator Section
----------------------
This section controls the Sync generator on a specified MV-2XXX board. The entries in this
section provide parameters used in MV2EnableSyncGenerator(). For more information,
please see the function description.
[Sync Generator]
syncGenEnable=0
syncGenType=0
syncGenHPol=0
syncGenVPol=0
syncGenHGate=0
syncGenVGate=0
syncGenHStart=0
syncGenVStart=0
syncGen_hTotal=780
syncGen_hWidth=64
syncGen_vTotal=525
syncGen_vWidth=3
syncGenEnable
Determines if MV2EnableSyncGenerator() will be called when
MV2LoadCameraConfig() is executed.
0:> Does not call MV2EnableSyncGenerator(). (default)
1:> Calls MV2EnableSyncGenerator() with parameters specified in this section.
when this entry is 0, all other entries in this section will be ignored.
syncGenType
Selects what type of sync to generate.
0:> Indicates that the output sync is separated H and V. (default)
1:> Indicates that the output sync is composite sync by ANDing H and V.
2:> Indicates that the output sync is composite sync by ORing H and V.
3:> Indicates that the output sync is composite sync by XORing H and V.
syncGenHPol
Controls the polarity of H Sync.
0:> Indicates that the output H Sync has negative pulse. (default)
1:> Indicates that the output H Sync has positive pulse.
syncGenVPol
Controls the polarity of V Sync.
0:> Indicates that the output V Sync has negative pulse. (default)
1:> Indicates that the output V Sync has positive pulse.
syncGenHGate
Controls the gate of H Sync.
0:> Indicates that the output H Sync has no gate. (default)
1:> Indicates that the output H Sync will be gated with Event0.
2:> Indicates that the output H Sync will be gated with Strobe2.
3:> Indicates that the output H Sync will be gated with Trigger0.
syncGenVGate
Controls the gate of V Sync.
0:> Indicates that the output V Sync has no gate. (default)
1:> Indicates that the output V Sync will be gated with Event0.
2:> Indicates that the output V Sync will be gated with Strobe2.
3:> Indicates that the output V Sync will be gated with Trigger0.
syncGenHStart
Controls where to start the H Sync.
0:> Indicates that the output H Sync starts immediately. (default)
1:> Indicates that the output H Sync starts when Event0 becomes active.
2:> Indicates that the output H Sync starts when Strobe2 becomes active.
3:> Indicates that the output H Sync starts when Trigger0 becomes active.
syncGenVStart
Controls the gate of V Sync.
0:> Indicates that the output V Sync starts immediately. (default)
1:> Indicates that the output V Sync starts when Event0 becomes active.
2:> Indicates that the output V Sync starts when Strobe2 becomes active.
3:> Indicates that the output V Sync starts when Trigger0 becomes active.
syncGen_hTotal
Specifies the period of the H Sync in number of pixels.
This is the distance between the front edges of two consecutive H Sync pulses.
syncGen_hWidth
Specifies the width of the H Sync pulse in number of pixels.
syncGen_vTotal
Specifies the period of the V Sync in number of lines (H Syncs).
This is the distance between the front edges of two consecutive V Sync pulses.
syncGen_vWidth
Specifies the width of the V Sync pulse in terms of number of lines (H Syncs).
Clock Generator Section
-----------------------
This section controls the clock generator on a specified MV-2XXX board. The entries in this
section provide parameters used in MV2EnableClockGenerator(). For more information,
please see the function description.
[Clock Generator]
clockGenEnable=0
clockGenSource=0
clockGenInvert=0
clockGenEnable
Determines if MV2EnableClockGenerator() will be called when
MV2LoadCameraConfig() is executed.
0:> Does not call MV2EnableClockGenerator(). (default)
1:> Calls MV2EnableClockGenerator() with parameters specified in this section.
When this entry is 0, all other entries in this section will be ignored.
clockGenSource
Selects the clock to send out.
0:> Auto select (default). For MV-2500/2600, this is the same as 1.
1:> Indicates that the output clock is from PIXCLK for MV-2500 or CLKC0 for MV-2600.
2:> Indicates that the output clock is PXCLK2 which is generated by dividing the PIXCLK or
CLKC0 by 2 and synchronizing it to H Sync.
3:> Indicates that the output clock is from MCKIN_FLD for MV-2500.
4:> Indicates that the output clock is from PLL.
5:> Indicates that the output clock is pixel clock (PIXCLK or CLKC0) divided by 512.
6:> Indicates that the output clock is pixel clock divided by 1024.
7:> Indicates that the output clock is pixel clock divided by 2048.
8:> Indicates that the output clock is pixel clock divided by 4096.
clockGenInvert
Controls the polarity of the clock.
0:> Indicates that the output clock has negative pulse. (default)
1:> Indicates that the output clock has positive pulse.
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.