Release Notes
=============
Broadcom Bootcode Firmware
For
BCM57781, BCM57785, BCM57785X,
BCM57761, BCM57765, BCM57765X,
BCM57791, BCM57795, BCM57795X
Copyright (c) 2009-2012 Broadcom Corporation
All rights reserved.
----------------------------------------
Version 1.50 January 30, 2012
---------------------------------------
Fixes:
======
1. Problem:
Aspen NIC: EEE not functioning properly after system Suspend/Resume(S3/S4).
Cause:
BC has zeroed out EEE mode control register 0x36b0 when system is resuming
from S3/S4 (with EEE disabled in nvram), this makes device is unable to
determine link partner's EEE capability anymore.
Change:
BC will clear EEE_MODE_USER_LPI_ENABLE (BIT_7) of 0x36b0 instead of zeroing
out the register when system resuming from S3/S4.
-------------------------------------------
Version 1.48 - July 08, 2011
--------------------------------------------
Fixes:
======
1. Problem: CQ 56586
Bootcode: It get EEE disabled when enter secfg and enable EEE (Option 81).
Change:
The issue is resolved by changing the EEE setup sequence between the CPMU and the GPHY.
Modified the EEE script to setup the EEE support in CPMU before setup the GPHY to
resolved the issue.
--------------------------------------------
Version 1.47 - June 23, 2011
--------------------------------------------
Enhancement:
============
1. Modified OS absent mode EEE script to improve the link stability. (17[8:0] = 1FF)
2. Modified BC to continue monitoring the link status after entering Vaux only mode.
--------------------------------------------
Version 1.46 - May 11, 2011
--------------------------------------------
Enhancement:
============
1. Update OS absent mode EEE script.
The OS absent mode EEE support is disabled by default in NVRAM.
--------------------------------------------
Version 1.44 - April 15, 2011
--------------------------------------------
Enhancement:
============
1. CQ 54515: Disable EEE by default in Boot Code.
Set the default state of the EEE_Enable bit
in NVRAM to disable.
--------------------------------------------
Version 1.43 - March 30, 2011
--------------------------------------------
Enhancement:
============
1. Updating Device ID (DID) and Subsystem ID (SSID) to 0x16A3 when
the LAN function is not used (disabled by SW).
--------------------------------------------
Version 1.42 - February 25, 2011
--------------------------------------------
Enhancement:
============
1. Reducing the link status polling frequency to every 1s when EEE is enabled.
--------------------------------------------
Version 1.41 - February 14, 2011
--------------------------------------------
Fixes:
======
1. Problem:
BC enabled LPI with non-EEE link partner.
Cause:
There is an issue in the original EEE enable script.
One of the checking conditions in this EEE enable script
will fall through even with link partner is not supporting EEE.
As a result the BC will enable LPI even with non-EEE link partners.
Change:
Modify the EEE enable logic in the script to resolve the issue.
--------------------------------------------
Version 1.40 - January 20, 2011
--------------------------------------------
Fixes:
======
1. Problem: CQ51308
Aspen-B0-57765x-Traffic broken when run 3*CC32+3*nblast with 100M speed+CLKREQ+ASPM.
Cause:
The root cause is still under investigating. It may be related to the automatic
CPMU clock switching and the handshaking logic between DMA and CPMU.
Change:
Applying CQ52071 BC workaround to monitor the LAN link speed and adjust the clock
accordingly to workaround the issue.
--------------------------------------------
Version 1.39 - January 06, 2011
--------------------------------------------
Fixes:
======
1. Problem: CQ52007
New EEE configuration in NVRAM for BC for Aspen
Change:
Using Bit 13 of HW_CONFIG instead of Bit 27 of Feature_Config to enable/disable EEE.
B57diag V14.23 or later will support this change.
2. Problem: CQ52071
10M/100M, L1 enabled, clkreq enabled, jumbo frame for both tx and rx, traffic stop.
Cause:
The root cause is still under investigating. It may be related to the automatic
CPMU clock switching and the handshaking logic between DMA and CPMU.
Change:
To work around the issue, BC will monitor the LAN link speed and adjust the clock accordingly.
Enhancements:
=============
1. Removed the enhancement which increase L1 entrance idle time from 15us to 40us.
--------------------------------------------
Version 1.38 - December 15, 2010
--------------------------------------------
Fixes:
======
1. Problem: CQ51308
Aspen-B0-57765x-Traffic broken when run 3*CC32+3*nblast with 100M speed+CLKREQ+ASPM.
Cause:
When there is packet coming from Ethernet, and PCIE is in L1 state, PCIE will be wake up.
In ASF + 100M, PCIE link will be waked up when all the data are received from Ethernet MAC,
and passes to PCIE core. Since the core clock at 62.5Mhz when ASF is enabled, it may be
too late to wake up the PCIE link.
Change:
Enabling early_L1_exit in ASF mode regardless the link speed.
Enhancements:
=============
1. Increase L1 entrance idle time from 15us to 40us. When in L0 state
and the idle time is more than 40us, PCIE will go to L1 state.
--------------------------------------------
Version 1.37 - November 26, 2010
--------------------------------------------
Fixes:
======
1. Problem: CQ51302, CQ51306
BC V1.36 does not update the BC version in shared memory correctly.
Cause:
BC version stored in the NVRAM was not update to "1.36" in BC V1.36.
Change:
Updated BC version in the NVRAM to "1.37" for BC V1.37.
--------------------------------------------
Version 1.36 - November 23, 2010
--------------------------------------------
Enhancements:
=============
1. Select 24 FTS during retrain and 64 FTS during Power up for Aspen A0.
2. Select 44 FTS during retrain and 64 FTS during Power up for Aspen B0.
3. Set Bit_18 of Reg 0x3668 to use 50MHz for PCIE Serdes lfclk_rx for
FTS in Aspen B0.
4. Enable EEE support in OS Absent Mode in Aspen B0. EEE support can
be enabled/disabled via secfg.
--------------------------------------------
Version 1.35 - November 12, 2010
--------------------------------------------
Enhancements:
=============
1. Adding MRRS Setup function for Aspen B0.
MRRS: program register B4 bits 14:12 with 0x5 for Aspen B0
--------------------------------------------
Version 1.34 - October 26, 2010
--------------------------------------------
Enhancements:
=============
1.Speed up the 10mb clock to 6.25 mhz.
To speedup 10mb core clock frequency, bootcode set bit 20:16 to 0b10011 of register 3604.
--------------------------------------------
Version 1.33 - October 21, 2010
--------------------------------------------
Enhancements:
=============
1. Select 64 FTS during retrain and 64 FTS during Power up.
2. Adding the following script to power down PLL and ref clock buffer during clock req.
mii_write(0, 0x1F,0x8010);
mii_write(0, 0x19,0x0064);
--------------------------------------------
Version 1.32 - October 12, 2010
--------------------------------------------
Enhancements:
=============
1. Enabling Card Reader 64 bit system address support in Aspen B0.
2. Switching regulator power off option: Set Bit 24 of Reg 0x3668. To use
OTP bit [130] to control for 57785(x) and 57795(x).
3. Making Card Activity LED enable bit (0x3668[25]) be programmable via
secfg command for 57765(x), 57785(x) and 57795(x).
4. Making CR_BUS_POW bit (0x3668[23]) be programmable via secfg command
for 57765x, 57785x and 57795x.
--------------------------------------------
Version 1.31 - September 30, 2010
--------------------------------------------
Enhancements:
=============
1. Disabling Card Reader 64 bit system address support in Aspen B0.
--------------------------------------------
Version 1.30 - September 24, 2010
--------------------------------------------
Fixes:
======
1. Problem:
The Card Reader clock was set to 25MHz for 57785 and 57785x.
Change:
Updating the Card Reader clock to 50MHz for 57785 and 57785x.
--------------------------------------------
Version 1.29 - September 16, 2010
--------------------------------------------
Fixes:
======
1. Problem (CQ 49863):
Non EAV Aspen sku devices should only advertise support for 5 MSI-x vector
and 6 for EAV Aspen sku devices.
Change:
Updating the number of supporting MSI-X vector in Non EAV Aspen sku devices
to 5 and 6 for EAV Aspen sku devices.
--------------------------------------------
Version 1.28 - September 2, 2010
--------------------------------------------
Fixes:
======
1. Problem:
BC 1.27 will hide all the Card Reader Functions.
Cause:
BC internal logic unexpectedly hide all the Card Reader Functions in B0.
Change:
Fixed the logic in question to prevent hiding the CR Functions unexpectedly.
--------------------------------------------
Version 1.27 - September 1, 2010
--------------------------------------------
Enhancements:
=============
1. CQ:49691 Add the ability to disable the SD and xD functions in NVRAM.
Bit 10 of offset 0x78 in NVRAM can be used to enable/disable the SD
Function while Bit 11 of offset 0x78 can be used to enable/disable
the xD Function
2. Update PCIE Reg 0x8 with ASIC Revision.
--------------------------------------------
Version 1.26 - August 16, 2010
--------------------------------------------
Fixes:
======
1. Problem CQ49238:
Aspen-B0-FPGA-MS: System will lock up for about 5 minutes when
inserting a NTFS formatted MS Card if using bc1.23/1.24a
Cause:
Removed CQ45376 workaround.
Change:
Applied CQ45376 workaround in Aspen B0 by setting register 0x6c[9:7] = 0.
--------------------------------------------
Version 1.25 - August 16, 2010
--------------------------------------------
Fixes:
======
1. Problem CQ49190:
Aspen-A0-MS: System will hang when inserting a NTFS formatted MS
Card if using bc1.23/1.24
Cause:
Removed CQ45376 workaround.
Change:
Applied CQ45376 workaround in Aspen A0 by setting register 0x6c[9:7] = 0.
Enhancements:
=============
1. Removed MRRS Setup (reg 0xb4) in Aspen B0.
2. Enable Card Reader 64 bit system address support in Aspen B0.
--------------------------------------------
Version 1.24 - August 3, 2010
--------------------------------------------
Enhancements:
=============
1. Bootcode will not speed up the 10mb clock to 6.25 mhz in B0.
The issue has been addressed in B0.
2. Bootcode will not disable Clkreq_l in low power mode improvement
in B0. The issue has been addressed in B0.
3. Bootcode will not power down PLL and ref clock buffer during clock req
in B0. The issue has been addressed in B0.
4. Bootcode will not disable clock req for L2 in B0. The issue has
been addressed in B0.
--------------------------------------------
Version 1.23 - July 26, 2010
--------------------------------------------
Enhancements:
=============
1. Bootcode will use Bit 13:11 in Reg 0x3600 to hide Function 1 to 3
in B0.
2. Skipping CQ49006 workaround. Issue has been addressed in B0.
3. Instead of selecting 24 FTS during retrain and 64FTS during Power up,
default value will be used in B0.
4. Skip CQ45376 workaround. Default value will be used in B0.
5. Instead of setting bits (1:0) of 0x3638 to 2'b11 to IDDQ the GPHY,
BC will set bit 6 of register 3600 to IDDQ the LAN in B0.
6. For B0, Bootcode will skip setting bit 12 of register 36e4 on the way down
as requested by LSI team.
7. For B0, Bootcode does not need to deposit a signature "0xA" in function 1 offset
0x198 bit [11:8] to indicate to SD card driver that the switch of functions
done by the bootcode is completed.
--------------------------------------------
Version 1.22 - May 3, 2010
--------------------------------------------
Enhancements:
=============
1. Enhance the supports for Memory Stick reader when card
reader source clock is running at 50 MHz and 200 MHz.
When the source clock is running at 50 MHz and 200 MHz,
bootcode will update the speed in Capabilities register
to 0x32 and 0xD0 respectively.
2. Bootcode will issue an extra MII write to select Serdes Register Block
to eliminate Serdes Register corruption.
--------------------------------------------
Version 1.21 - April 30, 2010
--------------------------------------------
Enhancements:
=============
1. The supports for Memory Stick reader are added to this
bootcode release.
--------------------------------------------
Version 1.20 - March 11, 2010
--------------------------------------------
Fixes:
======
1. Problem:
Fast Boot of Phase 2 bootcode failed.
Cause:
The logic to control Fast Boot of Phase 2 of bootcode
is broken.
Change:
The broken logic has been fixed.
2. Problem CQ45211:
When system enter to OOB mode, the link speed is 1G instead of
100M with ASF enabled.
Cause:
After POR, offset 0xc04 in Shared memory contains random data.
Due to the fact that the bootcode will preserve the data in offset
0xc04 in Shared memory after reset, it remains un-initialized until
system boots to the OS. If the target bit in 0xC04 is set after POR,
ASF firmware will not to reset the device when Vmain goes away,
as a result, the link state at 1G.
Change:
The new bootcode will clear offset 0xc04 if OS is absent.
Enhancements:
=============
1. Bootcode disables PERST_L 10ms delay to allow the device to resume
successfully on ICH7/ICH9. It is done by clear bit 27 of PCIE Reg 0x800.
2. Bootcode will change the VDDR BIAS to address CQ44971.
3. Bootcode clears bit 15 and bit 14 of reg 0x6280 in Function 1
to setup the card reader bridge swap control.
4. Bootcode selects 100MHz Ref Clk source for the SD Host Controller.
This is done by setting reg 0x36E4 to 0x10880819.
5. Enable SD 3.0 support to 57765, 57765x, 57795 and 57795x.
--------------------------------------------
Version 1.19 - March 11, 2010
--------------------------------------------
Fixes:
======
1. Problem (CQ46512):
K40 hung booting up while running restarts.
Cause:
There is an issue in the PCIE-IP which will cause the failure.
Change:
Bootcode will enable the new legacy way of generating reset
for unexpected shutdown based on PCIE Link not in L23 State
while Perst_L is asserting.
Enhancements:
=============
1. Bootcode will change the VDDR BIAS to address CQ44971.
Note:
1. This release is for BCM57765 only
--------------------------------------------
Version 1.18 - February 23, 2010
--------------------------------------------
Enhancements:
=============
1. Bootcode will check for PERST_L de-asserted before
accessing the Serdes Registers and PCI-E Registers.
This is done by checking Bit 2 of Register 0x2018.
2. Bootcode will disable Clkreq_l in low power mode improvement.
This is done by setting Bit 15 of Register 0x3668.
3. Bootcode will disable clock req for L2 by setting Bit 31
of pcie core reg 1814. Bootcode program Register 6800
with b31=0 , b22 = 1, and b29 = 0 to select the PCIE PL
Register at offset 1800 block. Then read/modify/write
and set bit 31 of register 7c14.
4. Bootcode will issue a write to register 6128 right after reading 6128
to determine whether or not Wake-On-Card is enabled/disabled to
workaround this issue. This is an update of the workaround implemented
in V1.17. BC V1.17 cleared Bit 11:9 of Reg 6128 as well.
In this release, Bit 11:9 will not be cleared.
--------------------------------------------
Version 1.17 - February 18, 2010
--------------------------------------------
Fixes:
======
1. Problem:
System does not wake up upon Card-Insertion and/or Card-Removal while the
system is in Sleep State.
Cause:
When the system enters sleep state, the PCIE PERST_L input signal is asserting.
This causes the rst_ahb_n signal to be asserted. It also causes the rst_sleep_n
to be asserted. This rst_sleep_n will reset the wkup_ctrl_sleep registers.
As a result, in order for the wkup_ctrl_sleep to latch the wkup_ctrl it needs
a write to the register 0x2B.
Change:
Bootcode will issue a write to register 6128 right after reading 6128
to determine whether or not Wake-On-Card is enabled/disabled to
workaround this issue.
Enhancements:
=============
1. Bootcode will disable the new legacy way of generating reset
for unexpected shutdown based on PCIE Link not in L23 State
while Perst_L is asserting to prevent unexpected strapping value
being latched in to Reg 0x7014.
--------------------------------------------
Version 1.16 - February 10, 2010
--------------------------------------------
Enhancements:
=============
1. Adding SD 3.0 support for 57765.
Bootcode will enable SD 3.0 200 MHz support for 57765
when bit 20 of NVRAM offset 0x78 is set.
SD 3.0 support is disabled by default.
--------------------------------------------
Version 1.15 - February 5, 2010
--------------------------------------------
Fixes:
======
1. Problem (CQ45376) update:
Aspen-A0-CR-Fails to copy files to SD card if b57 LAN driver v14.0.0.5
is installed.
Cause:
The root cause is still under investigation.
Change:
Set register offset 0x6C Bits [9:7] to 3'b000 as requested by LSI team.
Enhancements:
=============
1. Bootcode will switch to and set up different functions only when it
is in OS absent mode.
2. Bootcode will deposit a signature "0xA" in function 1 offset
0x198 bit [11:8] to indicate to SD card driver that the
switch of functions done by the bootcode is completed.
--------------------------------------------
Version 1.14 - February 4, 2010
--------------------------------------------
Fixes:
======
1. Problem (CQ45376):
Aspen-A0-CR-Fails to copy files to SD card if b57 LAN driver v14.0.0.5
is installed.
Cause:
The root cause is still under investigation.
Change:
Undo the Enhancement in V1.09 which will set register offset 0x6C Bits [9:7]
to 3'b101 as requested by LSI team.
Enhancements:
=============
1. Bootcode has added a function to set up MRRS for all Functions.
Driver will not program the MRRS for all Functions.
2. Bootcode will hard code data to Reg 0x36E4 instead of read/modify/write as
requested by LSI team.
3. Bootcode will disable MSIX capability for Function 1 to 3.
-----------------------------
Version 1.13 ---- 1/26/2010
-----------------------------
1. Problem:
CQ45463 CQ45377
57761 and 57781 device display card reader devices in B57diag.
Cause:
Bootcode used Bit 13:11 in Reg 0x3600 to hide Function 1 to 3.
These bits did not work and cannot hide Function 1 to 3 successfully.
Fix:
Bootcode will use BIT 13:11 in Register 0x804 to hide Function 1 to 3.
2. Enhancement:
Bootcode will set bit 12 of register 36e4 on the way down as requested by LSI team.
3. Enhancement:
Bootcode will remove the function which set up MRRS. Driver will program the MRRS.
4. Enhancement:
Hiding Function 2 is programmable via secfg for 57765.
-----------------------------
Version 1.12 ---- 1/25/2010
-----------------------------
1. Enhancement:
The default value of the polarity bit in register 6880 bit 3 of the LAN function is changed to 0 as requested by LSI team.
2. Enhancement:
The default value of the "SD Write Protect Internal Chip Pull up down Override" (bit 7:6) in register 6884 of the
LAN function is changed to "Activates Pull-up & Deactivates Pull-down" (0x01) as requested by LSI team.
3. Enhancement:
Bootcode selects the 200MHz clock from the serdes as the clk source for the clk_xin and set it run at 50MHz.
-----------------------------
Version 1.11 ---- 1/22/2010
-----------------------------
1. Enhancement:
Disabled Play Dead Mode in CPMU as requested by LSI team.
-----------------------------
Version 1.10 ---- 1/22/2010
-----------------------------
1. Enhancement:
Changing the default value of the polarity bit in register 6880 bit 3 of the LAN function to 1 as requested by LSI team.
2. Problem:
The MBUF POOL LENGTH REGISTER offset 0x440c has been programmed with incorrect value as 0x5800.
Fix:
Update The MBUF POOL LENGTH REGISTER offset 0x440c to 0xa000 as what it should be.
-----------------------------
Version 1.09 ---- 1/19/2010
-----------------------------
1. Enhancement:
Bootcode set register offset 0x6C Bits [9:7] to 3'b101 as requested by LSI team.
2. Enhancement:
Bootcode disabled Dev. serial number capability for Function 1 to 3 as requested by LSI team.
3. Enhancement:
Bootcode advertised the number of MSI message to 1 for Function 1 to 3 as requested by LSI team.
-----------------------------
Version 1.08 ---- 1/18/2010
-----------------------------
1. Enhancement:
Cleared the Card Reader Idle Enable bit, bit 8, of CPMU Control Register, offset 0x3600 as requested by LSI team.
2. Enhancement:
Initialized the TXMbuf [0] from 0x8000 to 0x D7FF.
3. Enhancement:
Speed up the Mac Clock to 62.5MHz via Reg 0x3624 as ASF is enabled.
-----------------------------
Version 1.07 ---- 1/13/2010
-----------------------------
1. Enhancement:
1. Set Fast L1,L0s exit time to 50Mhz.
2. Select 24 FTS during retrain and 64FTS during Power up.
-----------------------------
Version 1.06 ---- 1/6/2010
-----------------------------
1. Enhancement:
Instead of setting bit 6 of register 3600, the new bootcode will set bits (1:0) of 0x3638 to 2'b11 to IDDQ the GPHY only.
2. Enhancement:
Speed up the 10mb clock to 6.25 mhz.
To speedup 10mb core clock frequency, bootcode set bit 20:16 to 0b10011 of register 3604.
----------------------------
Version 1.05 ---- 12/31/2009
-----------------------------
1. Enhancement:
Adding the following script to power down PLL and ref clock buffer during clock req.
1. mii_write(0, 0x1F,0x8010);
2. mii_write(0, 0x19,0x0064);
----------------------------
Version 1.04 ---- 12/29/2009
----------------------------
1. Enhancement:
Instead of setting bit 10 (MII_CONTROL_ISOLATE) and bit 11 (MII_CONTROL_POWER_DOWN) of MII Register 0x00,
the new bootcode will set bits (1:0) of 0x3638 to 2'b11 to IDDQ the GPHY which will have better power saving.
----------------------------
Version 1.03 ---- 12/23/2009
----------------------------
1. Problem: CQ44247
The link speed stay at 10M after Windows shutdown while WOL disabled in bootcode.
Cause:
The logic to decide whether bootcode should IDDQ the device has been changed from Cilai and is broken.
As a result, bootcode failed to IDDQ the device after Windows shutdown while WOL disabled in bootcode.
Fix:
The broken logic was fixed to resolve the issue.
2. Enhancement:
Change the clk_xin source from the 200MHz clock to the Ref Clk and keep it run at 50MHz.
3. Enhancement:
Change the SD Adv clk from 25MHz to 50 MHz.
4. Problem:
Bootcode failed to detect whether Wake on Card is enabled.
Cause:
wake_on_sd_en() function failed to detect whether Wake on Card is enabled.
Fix:
The wake_on_sd_en() function was fixed to resolve the issue.
----------------------------
Version 1.02 ---- 12/11/2009
----------------------------
1. Problem:
clk_xin is not running at 50MHz with bootcode v1.01.
Cause:
Shared memory offset 0xdf4 was not initialized correctly which cause bootcode to reset CPMU base clk control bits (BIT_29 and BIT_28) to 2'b10 instead of 2'b01.
Fix:
Reinitialized shared memory offset 0xdf4 to resolve the issue.
2. Problem: CQ44833
ASPEN A0-Unable to wake up when enters to OOB mode.
Cause:
Bootcode set Bit 29 of Register 0x68a4 which prevent system to wake up by magic packet.
Fix:
Bootcode does not set Bit 29 of Register 0x68a4 and system wake up from OOB mode.
----------------------------
Version 1.01 ---- 12/10/2009
----------------------------
1. Enhancement:
Change the clk_xin run at 50MHz instead of 25MHz.
Select 50MHz for SD2.0 cards by setting cpmu base clk control bits (BIT_29 and BIT_28) to 2'b01.
----------------------------
Version 1.00 ---- 12/02/2009
----------------------------
1. Enhancement:
Removed otp read function to save code space.
2. Enhancement:
Besides checking wol_signature, bootcode will check for bit_18 & bit19 of reg 0x400 before checking
wol enable bit in nvram after Vmain goes away.
3. Enhancement:
Added MRRS setup from bootcode.
4. Enhancement:
Hide Function 1-3 for 57781, 57761 and 57791.
5. Enhancement:
Hide Function_3 if bit 16 of Reg 0x6888 is not set.
----------------------------
Version 0.09 ---- 11/04/2009
----------------------------
1. Enhancement:
Modify the bootcode to disable the VPD Capability by writing the following instructions:
Write 6800 0
Write 6440 304b
2. Enhancement:
Remove the ability to read the otp and program the L0s & L1 Exit Latency
3. Enhancement:
Use the following instruction to change the default value for L0s & L1 for ALL PCIE Functions
a. write 6800 0
b. write 64dc 0xD75E11
c. write 6800 40
d. write 64dc 0xD75E11
e. write 6800 80
f. write 64dc 0xD75E11
g. write 6800 c0
h. write 64dc 0xD75E11
i. write 6800 0
----------------------------
Version 0.08 ---- 10/22/2009
----------------------------
1. Problem:
System did not wake up in OOB case.
Cause:
Uninitialized variable cause bootcode failed to setup magic packet wol.
Fix:
Initialized the variable in question to resolved the issue.
----------------------------
Version 0.07 ---- 10/9/2009
----------------------------
1. Problem:
Bootcode failed to set the advertised speed in Function 1 to 25 MHz.
Cause:
Incorrect register offset has been used.
Fix:
Fixed the register offset error to resolve the issue.
----------------------------
Version 0.06 ---- 10/8/2009
----------------------------
1. Enhancement:
Disable Link Idle Mode in CPMU.
2. Enhancement:
Set MRRS = 5.
3. Enhancement:
Set Clk-xin for card reader to 25 MHz
4. Enhancement:
Set the advertised speed in Function 1 to 25 MHz.
5. Enhancement:
Enable ADMA2 in Function 1.
6. Enhancement:
Change Mac Clk to 1.5 MHz in Playdead Mode
7. Enhancement:
Update Aspen NVRAM pin strap table.
----------------------------
Version 0.05 ---- 10/3/2009
----------------------------
1. Enhancement:
Remove MRRS setup from bootcode.
2. Undo Enhancement 3 and Enhancement 4 for FPGA build.
----------------------------
Version 0.04 ---- 10/1/2009
----------------------------
1. Problem:
RxMbuf size is set to 0x3400 by Bootcode
Cause:
Bootcode program the RxMbuf size register to be the same as in Cilai.
Fix:
Reprogram the RxMbuf size to 0xA000.
2. Enhancement:
Bootcode must use the OTP bit 142 (6888 bit 29) how to adjust the PMU Bandgap Limit
If Bit 142 is 1, then program register 36A4 with 0x42000000 and register 36AC with 0x41
If Bit 142 is 0, then don't touch registers 36A4 and 36AC
3. Enhancement:
Hide Function 0-3 for 57781, 57761 and 57791.
4. Enhancement:
Hide Function_3 if bit 16 of Reg 0x6888 is not set.
5. Enhancement:
IDDQ Phy and program dummy device id in play dead mode.
6. Enhancement:
Set PXE BAR SIZE to zero if PXE is disabled in NVRAM.
7. Enhancement:
Remove all GPIO controls.
8. Problem:
PXE does not run.
Cause:
Exp_ROM_Addr has not been programmed.
Fix:
Reprogram Exp_ROM_Addr resolved the issue.
9. Enhancement:
Added NVRAM option to enable sd 3.0 in 57765.
The default is disable.
10. Enhancement:
Cleare bit 14 and bit 15 of offset 0x6280 for Function 1 to 3
11. Advertise ADMA2 in the SD Card-Reader Capability Register.
Read Modify Write Register 0x62A0 and set bit18
12. Enhancement:
MRRS: program register B4 bits 14:12 with 0x5 for all pcie functions
----------------------------
Version 0.03 ---- 9/18/2009
----------------------------
1. Problem: CQ 43770
Aspen- System BSOD during disabling NIC or shutting down.
Cause:
The bc v0.02 will set bit_21 of shared memory 0xb58 which incorrectly tells driver that APE is present.
Then driver will try to make some APE status update at memory mapping to device 2nd BAR
which is actually the MSI-X table, then it causes system BSOD.
Fix:
Do not set bit_21 of shared memory 0xb58
2. The root cause of V0.01 will not run is that the STACK_START_ADDRESS is not set up correctly.
After setting the STACK_START_ADDRESS to 0x8010000, the bootcode start running.
3. Added DID, SSID and SVID support for Function 1 to 3.
Bootcode will program DID, SSID and SVID for Function 1 to 3 based on IDs stored in NVRAM.
4. Added options to program secfg_configurations registers 0x6880 and 0x6884.
5. Added Media Sense support.
Set bit_20 of Reg 0x3600 if Media Sense Enable in NVRAM is set.
6. Workaround:
Issue #1: Programming SD Card-Reader PCIE Programming Interface at offset 0x9 with a value of 0x01
1. Set bits 7:6 of 6800 to 2'b01
2. Read Modify Write Register 0x43C and change bits 7:0 with 0x01
7. Workaround:
Issue #2: De-Advertise ADMA2 in the SD Card-Reader Capability Register
1. Set bits 7:6 of 6800 to 2'b01
2. Read Modify Write Register 0x62A0 and clear bit18
----------------------------
Version 0.02 ---- 9/17/2009
----------------------------
1. V0.01 is built to run with 64K scratch pad. However, FPGA does not support 64K scratch.
As a result, the bootcode will not start.
Therefore a new bootcode is built to run with a 24K byte scratch pad.
----------------------------
Version 0.01 ---- 8/31/2009
----------------------------
1. Initial engineering release
This is a branch of 57780 v3.19.
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.