1. CardReader_Broadcom_1.0.0.243_W8x64_A.zip Driver
2. release.txt File Contents

release.txt Driver File Contents (CardReader_Broadcom_1.0.0.243_W8x64_A.zip)

                              Release Notes
                              =============

                           Broadcom Selfboot OTP Patch 
                                    For 
                         BCM57781, BCM57785, BCM57785X, 
                         BCM57761, BCM57765, BCM57765X, 
                         BCM57791, BCM57795, BCM57795X
                                  Chip Rev. B0

                 Copyright (c) 2010-2012 Broadcom Corporation
                          All rights reserved.

                          
 --------------------------------------------
Version 2.10 (Format 1) - February 23, 2012
--------------------------------------------
   Enhancements:
   =============
   1.CQ 61744. Undo CQ CQ59279 workaround implemented in V2.09.
   
   Notes:
   =====
   This release is for 57785x only.
   
--------------------------------------------
Version 2.09 (Format 1) - November 16, 2011 
--------------------------------------------
   Enhancements:
   =============
   1.CQ CQ59279. Add SD3.0 card detection logic to LAN driver to accommodate 
     size limitation in 57785x OTP.
     If a SD 3.0 supported SD card is inserted, the Selfboot Patch will set 
     the Card Reader MRRS in Reg 0x6C[9:7] to 0x7,  or else, set to 0x00.  
     This will happen during PCIE is idle. This SB OTP patch image release has two parts.  
     Part 1 includes all the ICP patches and will be stored in the OTP memory.  
     Part 2 includes all the SCP patches and will be embedded in the LM_VOID LM_SD30_workaround() 
     function of the LAN driver. The SCP Patches are in the driverScritp.txt file.
 
   
   2.Undo PCIE Serdes lfclk_rx for FTS in V2.08.
   
   3.Speedup 10mb core clock frequency policy to 6.25 MHz. 
   
--------------------------------------------
Version 2.08 (Format 1) - October 07, 2011 
--------------------------------------------
   Enhancements:
   =============
   1.Set Card-Reader DMA Read MRRS in 57785/57785x to 4K.
   
   2.Use 50MHz for PCIE Serdes lfclk_rx for FTS
   
--------------------------------------------
Version 2.07 (Format 1) - July 29, 2011 
--------------------------------------------
   Enhancements:
   =============
   1.CQ57367. SD3.0 support is hard coded to be enabled in 57785/57785x B0
   
--------------------------------------------
Version 2.06 (Format 1) - April 11, 2011  
--------------------------------------------
   Fixes:
   ======
   1. Problem (CQ 54617): 
      Aspen-57781_B0-OTP PLL/refclk buffer workaround patch
      code was not being applied.

      Cause:
      ROM code was overwriting the serdes registers changes after the
      patch code was applied.
 
      Change:
      Moved the workaround code from serdes init to the post serdes
      init patch.

--------------------------------------------
Version 2.05 (Format 1) - October 20, 2010 
--------------------------------------------
   Fixes:
   ======
   1. Problem (CQ 50548): 
      Aspen-57785x_B0-OTP bootcode with the secfg WOL is 
      disabled and then system enter S5 mode observed the 
      LED still link 

      Cause:
      One of the internal flags was not setup correctly when WOL
      was disabled and cause SB ROM code not to shut down the 
      device.
 
      Change:
      Use SCP Patch 19 to correct the internal flag in question.

--------------------------------------------
Version 2.04 (Format 1) - October 16 , 2010 
--------------------------------------------
   Fixes:
   ======
   1. Problem (CQ 50400): 
      Aspen-B0-xD: Reload LAN Driver would break xD file transfer.

      Cause:
      When reloading LAN Driver, Driver will reset the LAN that cause the
      SB ROM Code to Hide the xD function again and cause the disconnect
      of the xD Function and the xD Driver.
      Change:
      Issue patch to prevent SB ROM Code Hide the xD function.


   Enhancements:
   =============
   1. Select 64 FTS during retrain and 64 FTS during Power up.

   2. Adding the following script to power down PLL and ref clock buffer during clock req. 
      mii_write(0, 0x1F,0x8010);
      mii_write(0, 0x19,0x0064);    


--------------------------------------------
Version 2.03 (Format 1) - October 12, 2010 
--------------------------------------------
   Enhancements:
   =============
   1. Set the Card Reader source clock to 50 MHz.

   2. Switching regulator power off option: Set Bit 24 of Reg 0x3668 to use  
      OTP bit [130] to control for 57785(x) and 57795(x). 

   3. Set Bit 25 (CR_ACT_LED) of Reg 0x3668 to 1 for 57765(x), 57785(x) and 57795(x). 

--------------------------------------------
Version 2.02 (Format 1) - September 15, 2010 
--------------------------------------------
   Fixes:
   ======
   1. Problem (CQ 49863): 
      Non EAV Aspen sku devices should only advertise support for 5 MSI-x vector

      Change:
      Updated the number of supporting MSI-X vector in Non EAV Aspen sku to 5.

   2. Problem (CQ 49865): 
      The xD Function is not showing up when running SB Patch and OTP SB Patch. 

      Cause:
      SB ROM Code set the Hiding xD Function bit in Reg 0x3600.

      Change:
      Patched the SB ROM code to clear the Hiding xD Function bit in Reg 0x3600.
 

---------------------------------------
Version 2.01 September 10, 2010 (Format 1)
---------------------------------------

   Fixes:
   ======
   1. Problem (CQ 49763): 
      Aspen allocates 7 MSI-X interrupts instead of 6 in Win7 OS.

      Change:
      Updated MSI-X interrupts to 6 instead of 7. 

   Enhancements:
   =============
   1. Updated PCIE Reg 0x8 with asic revision. 

   2. Set register 0x6c[9:7] = 0.


---------------------------------------
Version 2.00 August 12, 2010 (Format 1)
---------------------------------------
   Initial ASIC B0 patch release.   

   Enhancements:
   =============
   1. Set the Card Reader source clock from 50 MHz to 25 MHz.