releases.txt Driver File Contents (R243167.exe)

             Release Note for Soledad Bootcode Firmware
                          
                    5761, 5761e, 5761s, 5761se 


----------------------------
Version 3.71 ---- 5/29/09  (Do not use this bootcode for A steps devices)
----------------------------   

1. Problem: CQ41486 
   The DEADDEAD signature can't be written into the controller's shared memory in D3-hot.
 
   Workaround:
   The boot code puts the controller into Low-Power Mode only after the PCIe interface has gone down 
   (VMAINPRSNT signal is low) and the DEADDEAD signature is present in shared memory.
 
----------------------------
Version 3.70 ---- 5/18/09  (Do not use this bootcode for A steps devices)
----------------------------   

1. Enhancement: 
   Changed PCIe SerDes register values to the following to use low-power transmitter mode:
    1. Register 0x15 in block 0x8610 = 0x47b.
    2. Register 0x1A in block 0x8010 = 0x4038.

----------------------------
Version 3.69 ---- 12/30/08  (Do not use this bootcode for A steps devices)
----------------------------   

1. Enhancement: 
   Modified code to update mem->firmware_status to ~DEVICE_RESET_MAGIC after, instead of before, APE_Handshaking() to support PM offload firmware. 

2. Enhancement:
   Disable GPHY APD by the following instructions when the "enable_auto_powerdown" configuration bit is cleared in NVRAM. 
   wr 44c 0x243C941F < This disables DLL Power Down in APD by setting bit 2 in GPHY Register 1C at Shadow 0x5
   wr 44c 0x243CA801  < This disables GPHY APD
   The current code will leave the registers in their default state when the "enable_auto_powerdown" configuration bit is cleared in NVRAM. 

----------------------------
Version 3.68 ---- 10/23/08  (Do not use this bootcode for A steps devices)
----------------------------   

1. Problem:
        The SRAM starting address of Phase I bootcode in V3.67 has been changed from 0x1b000 to 0x1a800.
		This should provide more room for code size to grow.  
		However, it also causes PXE not able to run after system soft reset.

   Workaround:
        Changed the SRAM starting address for Phase I bootcode back to 0x1b000.

----------------------------
Version 3.67 ---- 10/23/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ38050 
        Some 5761 devices on some systems exhibit Mutex register access failure during system boot
   
   Cause: Boot code initialization includes accesses to the PCI Express configuration space, which accesses can coincide 
          with the PCI Express REFCLK start-up transient before the REFCLK stabilizes. 
		  In some systems the PCI Express REFCLK start-up transient generates a very high 
		  frequency clock to the PCI Express interface, and boot code PCIe register writes 
		  may corrupt these register values, such as bits that enable accessing the mutex register.

   Fix: Skip all PCI-E register access till PERESET is de-asserted.
 

----------------------------
Version 3.66 ---- 9/22/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ37451/CQ36754
          DASH: USB device pop-up error in WinXP when MGMT FW is disabled
          
   Workaround: 
          This issue is related to CQ 36754.  CQ36754 workaround is enhanced in bootcode 
		  release V3.66 by checking APE Status Register as well to detect if mgmt firmware 
		  is disabled. Once mgmt firmware is detected disable, the bootcode will enable USB Detach signal.

          
----------------------------
Version 3.65 ---- 9/15/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ37295  
          Several APE registers are read by bootcode. Due to a corner case condition the returned APE register 
          value is occasionally zero instead of the actual register value.
          
   Workaround: 
          Bootcode will read APE free run timer register and GPIO control register.  
          In case of reading the free run timer register, bootcode will only accept non-zero returned value.  
          In case of reading the GPIO control register, bootcode will read the register up to 5 times if zero value is returned.
          
2. Increased image size to 8600 bytes.
   

----------------------------
Version 3.64 ---- 9/08/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Added 5761S and 5761SE support.  Cleared Bit_7 and Bit_8 of Reg 0x3600 for 5761S and 5761SE.

----------------------------
Version 3.63 ---- 8/22/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Fix v3.62.  Bootcode will drive APE GPIO2 low when mgmt firmware is not enabled, or mgmt firmware does not support USB.
               This function remains in the mainloop to take care of APE reset scenario.

----------------------------
Version 3.62 ---- 8/15/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Fix v3.61.  Always enable USB Detach signal to reduce code size.
			Move this function to mainloop to take care of APE reset scenario.

----------------------------
Version 3.61 ---- 8/14/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ36754  
          Quicksilver NIC installed, system shows unknown USB device.
   
   Cause: USB Detach signal (APE GPIO2) was driven low.
          
   Fix: Bootcode will drive APE GPIO2 low when mgmt firmware is not enabled, or mgmt firmware does not support USB.
   
2. Bump up 5761 image size limit from 8192 to 8300 bytes.

----------------------------
Version 3.60 ---- 7/28/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ36482  
          5761E looses net work connectivity after resuming from S3 : DTM test
   
   Cause: During the debugging, we found that the core clock register was not restored to default speed of 62.5Mhz.
          This caused transmit and receive failure at 1Gb mode. 10Mb and 100Mb are not affected.
          
   Fix: Restored core clock register to default speed of 62.5Mhz.
        
----------------------------
Version 3.59 ---- 7/09/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ35982  
        BCM5761E:100Base-TX rise/fall time IEEE Compliance test fails on OEM system with manageability enabled
   
   Cause: The GPHY calibration was not performed with manageability enabled
          
   Fix: Performed the GPHY calibration when the boot code is being loaded and when detected port switching in 5761E.
   
----------------------------
Version 3.58 ---- 7/03/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ6159  
        In bootcode v3.55+, a race condition is possible where the APE would be in an infinite reset loop.
   
   Cause: The APE Heartbeat Monitoring function to monitor the heartbeat of APE was added since version V3.55.
        This function will monitor the APE heartbeat. If the heartbeat is not updating for a period of time the bootcode will 
        reset the APE. The length of the monitoring period is based on the APE heartbeat interval at offset 0x24 in APE shared memory.
        When the race condition occurred, the length of the monitoring period may be set to zero which will cause the bootcode to go into an infinite loop resetting the APE.
                     
   Fix: Disabled the APE Heartbeat Monitoring function if the APE heartbeat interval at offset 0x24 in APE shared memory is zero.
        In addition, the monitoring period will be defaulted to 6.2 sec if the APE heartbeat interval is too short. 

2. Removed the GPHY calibration from Phase II of 5761e bootcode.  The GPHY calibration is already done in Phase I of bootcode. 

----------------------------
Version 3.57 ---- 6/20/08  (Do not use this bootcode for A steps devices)
----------------------------      

1. Problem: CQ35982  
        BCM5761E:100Base-TX rise/fall time IEEE Compliance test fails on OEM system with manageability enabled
   
   Cause: The GPHY calibration was not performed with manageability enabled
          
   Fix: Performed the GPHY calibration when the boot code is being loaded.
 
----------------------------
Version 3.56 ---- 6/05/08  (Do not use this bootcode for A steps devices)
----------------------------      

1.  Modified code to perform read-modify-write operation when accessing Register 0x3624 (CPMU_Clock_Speed_Override_Policy) to 
    prevent overwriting the setting done by Dash.
    

----------------------------
Version 3.55 ---- 6/02/08  (Do not use this bootcode for A steps devices)
----------------------------      

1.  Added APE Heartbeat Monitoring function to monitor the heartbeat of APE.  
    In case the heartbeat is not updating for a few cycles, Bootcode will reset APE.
    Before APE reset, bootcode will update RxCPU_RESET_APE_COUNT and copy APE_STATE register 
    to RxCPU_LAST_APE_STAT and APE_SHMEM_APE_FW_STATUS_ADDR to APE_SHMEM_RXCPU_LAST_APE_FW_STAT in APE shared memory.  
    This function is enabled or disabled by Bit_0 of APE_FW_BEHAVIOR.

----------------------------
Version 3.54 ---- 5/29/08  (Do not use this bootcode for A steps devices)
----------------------------      
1. Problem: CQ35211 When the SUT enters S3/S4, the APE of the 5761 gets reset.
            CQ35187 5761 B0 NIC wakes up from Magic Packet even when "Allow this device to wake the computer" 
            option in the Power Management tab is unchecked.

   Cause: In BC v3.53 the BC was erroneously switching the NIC power to Vmain due to a driver issued GRC reset 
          while the system was going into a suspend state. This caused the chip to lose power when Vmain went down, and the whole chip was reset by POR.
          The power switching is due to the GPIO2 pulldown workaround added in V3.53. 
          
   Fix: Modified GPIO2 pulldown workaround for 5761 NIC such that the workaround only get enable when reset is not done by drivers.
   
        
----------------------------
Version 3.53 ---- 5/14/08  (Do not use this bootcode for A steps devices)
----------------------------      

1.  Re-built Version 3.52 and updated version to V3.53.
    Due to V3.52 may have some build issues, V3.52 has been rebuilt and updated version to V3.53.
----------------------------
Version 3.52 ---- 5/14/08  (Do not use this bootcode for A steps devices)
----------------------------      

1.  Added GPIO2 pulldown workaround for 5761 NIC.  This workaround is only applicable to 5761 NIC.
    
2.  Change the default state of Link Speed Power Mode in CPMU to disable.

----------------------------
Version 3.51 ---- 5/05/08  (Do not use this bootcode for A steps devices)
----------------------------      

1.  In order to support SW to access config space when APE is in sleep mode,
    Bit 31 of 0x3620 will be cleared to keep APE HCLK running.

----------------------------
Version 3.50 ---- 4/21/08  (Do not use this bootcode for A steps devices)
----------------------------      

1.  Removed all workaround for A steps devices.

2.  Set the default state of the Phy Auto Power Down configuration bit to be enabled.

3.  Enabled 10mb receive only mode by default when driver is absent.

4.  Updated device id and vendor id, sub system device id and sub system vendor id in APE shared memory during APD handshaking.
   
5.  Turned on the APE sleep, APE deep sleep, IPSEC idle, and IPSEC SHA-1 idle modes to save power in OOB without link.
    Set CPMU control register (0x3600) bits 4, 5, 6 and 7 in the next release of Soledad B0 boot code.  
   
6.  Changed the start address of the Phase I bootcode in SRAM
    The start address of the Phase I bootcode in SRAM has been changed from 0x1ac000 back to 0x1b000.
    Since all workaround for A steps are removed, there is more room for growing.
    
7.  Removed support for "Force PCI Mode" option in nvram configuration.

8.  Avoid Phy access corruption.
    Bootcode will read Phy ID and setup GPHY APD in Phase 2.
    The Phy access may get corrupted when Driver and Bootcode accessing PHY registers at the same time.  
    To avoid the Phy access corruption, bootcode will read the PHY ID in Phase 1 and only setup GPHTY APD when driver is not loaded.  
    When driver is loaded, driver will set up GPHY APD if it is enabled in NVRAM.
    

----------------------------
Version 3.33 ---- 4/9/08  (Obsolete)
----------------------------      

1.  Avoid Phy access corruption.
    Bootcode will read Phy ID and setup GPHY APD in Phase 2.
    The Phy access may get corrupted when Driver and Bootcode accessing PHY registers at the same time.  
    To avoid the Phy access corruption, bootcode will read the PHY ID in Phase 1 and only setup GPHTY APD when driver is not loaded.  
    When driver is loaded, driver will set up GPHY APD if it is enabled in NVRAM.
    
2.  Changed the start address of the Phase I bootcode in SRAM
    The start address of the Phase I bootcode in SRAM has been changed from 0x1b000 to 1ac00 to give 1K bytes of extra room for Phase I bootcode to grow.

3.  Turned on the APE sleep, APE deep sleep, IPSEC idle, and IPSEC SHA-1 idle modes to save power in OOB without link.
    Set CPMU control register (0x3600) bits 4, 5, 6 and 7 in the next release of Soledad B0 boot code.  

----------------------------      
Version 3.32 ---- 4/3/08  (Last version of bootcode to support A steps devices)
----------------------------      
   
1. Bootcode used BIT_15 of Reg 0x3668 to indicate APE access is enabled in Reg 0x70 for A step devices of 5761/5761e.
   Since BIT_15 was using for other function in B steps, Bootcode is going to use Bit_26 instead for all steps of 5761/5761e. 
  
----------------------------
Version 3.31 ---- 3/14/08  
----------------------------      
   
1. Problem: CQ34283 PXE failed with 3.30.
   Cause: 3.30 modification still too big.
   Fix: move 3.29 modification to phase 2
        optimize further for phase 1 and phase 2
        now phase 1 should be 32 bytes less than 3.28
        and phase 2 should be same size as 3.28

----------------------------
Version 3.30 ---- 3/10/08  
----------------------------      
   
1. Problem: CQ34163 nictest fail on A2, A7 and C2 for bootcode 3.29.
   Cause: 3.29 modification causes code size to be too big.
   Fix: Change 3.29 modification to produce smaller code.

----------------------------
Version 3.29 ---- 3/6/08  
----------------------------      
   
1. If ID6 is 1'b0 (it should be 1'b1 now) for Soledad B0, wipe out the device ID.

----------------------------
Version 3.28 ---- 2/27/08  
----------------------------      
   
1. Device get power up and down in Vaux mode.
   Boot is driving the wrong GPIO pin which cause the issue in Vaux mode.  

----------------------------
Version 3.27 ---- 2/19/08  
----------------------------      
   
1. Disable CQ27862 workaround by the following script.
   1. Write 4900 0x48401
   2. Write 4904 0xCE08
   3. Write 4910 0x18
    
2. Extended L1 ASPM Timer by writing Reg 0x7d28 with 0x182FFFA and setting bit 16 of Reg 0x7d00.

3. Copy feature_config from share memory to share memory of the APE.

4. Set all management profile APE to 60mhz, by setting bit 12-8 of Reg 0x3604- 0x361c to 00001 (60mhz).

5. Set Bit2 (Power Down) of Reg 0x3600 by read modify write to prevent clearing other bits setting of the Register.

----------------------------
Version 3.26 ---- 2/04/08  
----------------------------      
   
1. Version 3.24 should set PHY APD to be disabled, but it failed to set that. 
   This will be fixed in V3.26.
   
----------------------------
Version 3.25 ---- 1/30/08  
----------------------------      
   
1. Added function to reset the Cal Block of GPHY when detected docking/undocking event and after GPhy reset for 5761e.
   
----------------------------
Version 3.24 ---- 1/23/08  
----------------------------      
   
1. Make Phy Auto Power Down configuration controlled by the NVRAM Phy Auto Power Down configuration bit.
   Set the default state of the Phy Auto Power Down configuration bit to be disabled.
   Phy Auto Power Down configuration is done in Phase 2 of bootcode after initPhy().
   
2. Removed NVRAM configuration bits and code that allows the user to enable/disable clkreq, L0s & L1ASPM. 

----------------------------
Version 3.23 ---- 12/19/07 
----------------------------      
   
1. Problem:
     The default value of Reg 0xD8 had been changed and cause register test to fail at 0xDC.
   Cause:
     The default state of Clkreq, ASPM_L0 and ASPM_L1 setting at register 0xD8 was changed based on the NVRAM configuration bits.
   Fix:
     Modified the NVRAM configuration bits default state of Clkreq, ASPM_L0 and ASPM_L1 to preserve 
     the default state of Clkreq, ASPM_L0 and ASPM_L1 setting in Reg 0xD8.

2. Making Clkreq, ASPM_L0 and ASPM_L1 NVRAM configuration bits applicable to all steps.

----------------------------
Version 3.22 ---- 12/17/07 
----------------------------      

1. Added new configuration bits to support 5761, 5761e B0 step.
   Added Link Idle Mode, Clkreq, ASPM_L0 and ASPM_L1 configuration bits for 5761, 5761e B0.
   These new bits can be set via b57diag that support 5761, 5761e B0. 
   
2. Removed Mutex Portection when access RXCPU Event Register (0x6810).

----------------------------
Version 3.21 ---- 12/11/07 
----------------------------      

1. Problem CQ#33000:
     5761 and 5761e failed PCI SIG electrical compliance test with 50ohm termination applied.
   Cause:
     The device was using high power mode for the receiver detect.
   Workaround:
     Via MDIO write new rcvr detect threshold.
     1.  write 44c 241f8610
     2.  write 44c 24150477

----------------------------
Version 3.20 ---- 12/10/07 
----------------------------      

1. Modified code to program the replay buffer size from 64 decimal (040) to 176 decimal (0B0).

----------------------------
Version 3.19 ---- 12/07/07 
----------------------------      

1. Modified code to get the chip rev from CPMU register instead of PCI Cfg Register since there 
   will be no access to PCI CFG registers when running in Vaux Mode.

2. Modified code to setup the device to use the low power mode for the receiver detect.

3. Eliminate the mii_read() function in Phase I bootcode to save more code space.
   PHY ID in Shared Memory at offset 0xb74 will be updated in Phase II of bootcode instead of Phase I. 
   So that we can eliminate the mii_read() function in Phase I bootcode to save more code space.

----------------------------
Version 3.18 ---- 11/30/07 
----------------------------      

1. Cleaned up unused functions from source code to make room for future grow.

2. Modified code to have better handshaking with APE firmware such as not resetting 
   the PHY and not shut down the device when no VMAIN is present if APE is enabled

3. Skip APE handshaking function and workaround if AEP is disabled.

4. Added A2 step support.


----------------------------
Version 3.17 ---- 11/28/07 
----------------------------      

1. Problem:
     PXE does not work on 5761 and 5761e with bootcode version 3.16.
   Cause:
     Due to adding code to workaround the GPIO issue, the phase 1 bootcode size increase over 4k and corrupted the PXE code.
   Fix:
     Moving CQ32447, CQ31190 and CQ31680 workaound to phase 2 bootcode to resolve the issue.
     
----------------------------
Version 3.16 ---- 11/20/07 
----------------------------      

1. Problem CQ 32175:
     WOL is not working in 5761.
   Workaround:
     The workaround for this issue is to swap GPIO0 and GPIO2 for the NIC WoL function.
     This also required board level modification.
     
2. Problem CQ 32447:
      BCM5784M: Taishan-A0 Failed File-Copy-Compare with Clkreq Enabled. This can also happen to 5761 and 5761e.
    Workaround:
      Enabled CQ30808 and CQ30888 by setting bits 4:2 in Register 4910 for 5761 and 5761e A0/A1.  
      This is done by writing to register 4910 with a value of 0x1C.

----------------------------
Version 3.15 ---- 11/07/07 
----------------------------      

1. Update CQ 31190 workaround to reduce L1 Recovery Time.

2. Problem CQ 31680:
     Fails with Clock Req testing with PLLPOWER down and RefClk parked
    Workaround:
     Changing PCIE Serdes PLL Bandwidth from 9MHz to 5-6MHz to allow the PCIE 
     Serdes to tolerate noisy PCIE Reference Clock.  
     In addition, Selecting the VDDR Bias instead of the Band-Gap BIAS Circuitry

3. Problem CQ32111:
     Missing handshaking logic among the CPMU, GPHY, and GMAC_CLKGEN causing the core clock 
     to stop in D0u with Airplane power mode enabled or Link Aware Mode with 
     Link Speed Power mode disabled.
   Workaround:
     Modified 5761 and 5761e to turn off GPHY auto-powerdown mode.

4. Problem CQ31815: 
     Blue screen on boot if no network cable attached.
   Workaround:        
     Disable CPMU GPHY APD Debounce Low Logic on 5761 and 5761e.

5. Problem CQ31957: 
     PXE banner does not appear during POST on 5761e NIC
   Cause:        
     The issue is due to the first phase of the bootcode is larger then 4K and corrupted the PXE code.
   Fix:
     Reduce the code size of the bootcode resolved the issue.
     

----------------------------
Version 3.14 ---- 10/17/07 
----------------------------      
1. Due to CQ 31944, the polling of the mutex register may hang up the bootcode since there is no timeout.
   Added mutex timeout and clear for OOB WoL problem where mutex acquire hung during WoL setup. 
2. Added changes for APE handshaking signature check.

----------------------------
Version 3.13 ---- 10/11/07 
----------------------------      
1.  Set Mdio/Mdc clock speed enable bit in MII mode reg on 5761 and 5761e as per request from HW engineering.

----------------------------
Version 3.12 ---- 10/04/07 
----------------------------      
1.  Change the default state of energy detect (cable sense mode) to disable.
    Boot code enables low power mode with energy detect (cable sense mode), 
    link aware power mode and link speed power mode in 0x3600 upon power up.  
    Since there is a priority between the LPED and LA power modes, as long as LPED is enabled, 
    the CPMU will never go into the LA mode.
    
2.  APE boot rom workaround
    Initial power up, APE rom code will go into exception and deposit 0x21xx-xxxx to ape_stat reg(x4).
    Bootcode will check for ape_stat reg(x4) and apply workaround to program the initial pointer at offset 0x8
    and restart fastboot.

----------------------------
Version 3.11 ---- 10/01/07 
----------------------------      
1.  Problem CQ 31190:
      FW workaround to reduce 5761 and 5761e L1 Recovery Time.
    Workaround:
       Init patch is added to program the PCI-E Serdes to reduce 5761 and 5761e L1 recovery time.

----------------------------
 Version 3.10 ---- 9/26/07
----------------------------
1. Fixed a bug in the APE Handshaking.
  Problem: 
    Bootcode did not assert "RxCPU Firmware Initialization Complete" APE Event in handshaking.
  Cause:
	The Bvent1_0 bit in APE_EVENT1_REG not get set by bootcode. 
  Fix:
    Recode the Handshaking function to reduce the bootcode size and make sure that the APE event gets asserted.
    
2. Released 5761e bootcode along with 5761 bootcode.  There will not be any bootcode release for 5761m.
    
----------------------------
 Version 3.09 ---- 9/25/07
----------------------------
1. Added handshaking between RxCPU boot code and APE dash firmware. 

  Handshaking between RxCPU boot code and APE dash firmware is added. The handshaking has two steps.  
  First step is to update the RxCPU segment in the APE shared memory. 
  The 2nd steps is asserting "RxCPU Firmware Initialization Complete" APE Event.
  
2. Fixed a bug in releasing the APE Mutex request in Phase II bootcode.
  Problem: 
    Bootcode did not release the APE Mutex request after accessing the MII register.
  Cause:
	A bug was found in the Mutex release function in Phase II bootcode. 
  Fix:
    The Mutex release function was updated with the proper steps.
    
3. Skipped Pre-Scaler programming.
   Programming the Pre-Scaler value to offset 0x6804 is not needed since the timer is controlled by the CPMU.    

  
----------------------------
 Version 3.08 ---- 8/16/07
----------------------------
1. Added "APE Present" bit in Shared Memory. 

  Defined Bit21 in Shared Memory offset 0xb58 as "APE Present"
  
2. Added APE Mutex Support.
  Added APE Mutex Support when access MII communication register (0x44c) and RxCPU Event Register (0x6810).
  
----------------------------
 Version 3.07 ---- 6/20/07
----------------------------
1. Serial number get changed issue 

  The workaround for CQ#28997 in V3.06 only restores 0x164[31:28] and 0x168[7:0] after setting bit 23 of 0x7c04.
  In this release, the entire 32 bits of 0x164 and 0x168 will be restored.

----------------------------
 Version 3.06 ----  6/19/07
----------------------------
1. Serial number get changed issue

  Problem: CQ#28997
    The serial number in offset 0x164/168 get changed after reset. As result, OS will
    treat our device as new device in the system. 
    
  Cause:
	Under certain corner cases, the Reserved bits of  0x164[31:28] or 0x168[7:0]  may not have default value set correctly.  

  Workaround:
    Firmware will write back the hardware default value after setting bit 23 of 0x7c04. 

2. Set NO_ASF_SUPPORT flag for 5761.
   ASF code will be running on APE instead of RX-CPU and bootcode don't need to load
   the ASF firmware from NVRAM for 5761.
   
----------------------------
 Version 3.05 ----  5/23/07
----------------------------
1. Fix Expansion ROM access issue.

  Expansion ROM access has been changed for 5761/5761M.
  Modified to support new Expansion ROM access methode.

----------------------------
 Version 3.04 ----  4/25/07
----------------------------
1. Update flash pin strap value for Soledad.
  
  New supported Atmel flash devices has been added 
  to Soledad and the pin strap value has been changed.
  Updated the new pin strap value to support new added
  flash devices.

----------------------------
 Version 3.03 ----  3/29/07
----------------------------
1. Fix VPD data access issue.

  The location of VPD Data Register for Soledad has been 
  changed from 0x54 to 0x44 in PCI Config Space.
  Updated the offset of VPD Data Register.

----------------------------
 Version 3.02 ----  3/28/07
----------------------------
1. Rebuilt the bootcode.

  The initial release was built based on StanfordME. 
  The ASIC is based on Stanford instead.
  This release is based on Stanford bootcode V3.09 with the changes added
  on release Soledad bootcode V3.01 listed below.

----------------------------
 Version 3.01 ----  3/23/07
----------------------------
1. Update flash pin strap value for Soledad.

  Soledad has a different flash pin strap value than StanfordME.


----------------------------
 Version 3.00 ---- 3/6/07 
----------------------------
1. Initial engineering release

   This branch of built of StanfordME v3.09.




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