release.txt Driver File Contents (R243173.exe)

      Cilai/Caesar3/Cilai-FE Selfboot Patch For Chip Rev. A1
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            57780, 57760, 57790, 57788

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Version 2.07 (Format 1)
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1. Problem: CQ39683
    Cilai detects Receiver Error when the Link Transition between L0s/L0
   Workaround: shorten the delay of the electrical idle signal from serdes
   a. write register 0x7e70 bit [4:0] with 0x0c during device initialization or device reset
   b. write all ones to register 0x110 (correctable error status).

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Version 2.06 (Format 1)
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1. Enhancement: 
   Changed PCIe SerDes register values to the following to use low-power transmitter mode:
    1. Register 0x15 in block 0x8610 = 0x47b.
    2. Register 0x1A in block 0x8010 = 0x4038.

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Version 2.05 (Format 1)
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1. Enhancement:
    Set the default value of the lom_design option in configuration to 1 for otp patch image to provide 2 times Reprogram-ability.	

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Version 2.04 (Format 1)
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1. Enhancement:
    Set Reg 0x4400 and Reg 0x4800 to 1 to initialize BufMgr and DMAR if BufMgr is not enabled.	

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Version 2.03 (Format 1)
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1. Problem: CQ39339
    The Link drop to 10M immediately once NIC Battery Saving Mode in BACS is enabled with AC Power applied.
   
   Cause:
    The issue is due to the current default value of "DisablePowerSaving" is 0 which enabled the reverse nWay feature.
    The reverse nWay feature should not be enabled by default.
   
   Fixed:
    Changed the default value of "DisablePowerSaving" bit in NVRAM to 1 to disable the reverse nWay feature.  

2. Enhancement:
    Set Reg 0x4400 and Reg 0x4800 to 1 to initialize BufMgr and DMAR.	


3. Enhancement:
    Sets GPHY exp 75 reg vdacctrl bit 0 in GPHY initialization

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Version 2.02 (Format 1)
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1. Enhancement: CQ39027
   Added Initialization Patch to reduce the L0s Exit Latency from 1 uS down to 704 nS.
   1.  Write 7e50 with 0x2c
   2.  Write 7e14 with 0x2c
   3.  Write 44c 241f8400
   4.  Write 44c 24170083

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Version 2.01 (Format 1)
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1. Enhancement: 
   Added Initialization Patch to improve the RX performance when L0s is Enabled.
   1.  Write 7e14 with 0x2c
   2.  Write 44c 241f8400
   3.  Write 44c 24170083

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Version 2.00  (Format 0)
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Initial ASIC A1 patch release.   
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