release.txt Driver File Contents (R243173.exe)

                     Release Note for BCM5788 BOOT Code Firmware
Version 3.06: 

  1. Writes firmware id to shared memory rx_cpu_firmware_id field
      Phase1 & Phase2 code will write the firmware id to rx_cpu_firmware_id.
    Eng. Notes:
      bootcode phase1 will write value 0xfefe0008 to shared memory 0xc0c.
      bootcode phase2 will write value 0xfefe0009 to shared memory 0xc0c.
      When phase2 executes properly, the value phase1 wrote should be
      overwritten by phase2 code.  
Version 3.05:

  1. Restored phy type in manufacture data block
      PXE code needed this field to determine the phy type
      Hard coded this field to be copper type
Version 3.04:
  1. Removed TX CPU access
      There was an access to TX CPU before halt instruction.
      When there is no main power and WOL is disabled, the CPU will intend 
      to shutdown itself to save power. Before the halt instructionm, 
      there was an access to TX CPU to halt TX CPU, which does not exist 
      in 5705/Shasta family device.
      Removed the TX CPU access.
  2. Reserved more space for stack area.
      Incoming data could potentially corrupt the phase1 bootcode before 
      the phase2 bootcode loading is done. 
      After initializing mbuf address, size registers and posting the 
      signature, the phase1 bootcode is still active and busy loading 2nd 
      phase bootcode. Before the 2nd phase loading is complete, and if 
      there is data coming in, it may corrupt the phase1 bootcode since
      the phase1 bootcode was sitting at rx buffer area.
      Change phase1 code area to the protected area.
Version 3.03:

  1. Changed VPD data DEFALT_PART_NUMBER
      VPD data DEFAULT_PART_NUMBER was showing 5705 instead of 5788.

	  The source code was shared between 5705 and 5788.

	  Broke the sharing and changed the default DEFAULT_PART_NUMBER with 

  2. Fixed WOL issue
      After using restart option in Windows and restart computer to DOS. 
      Then, turn off the power, WOL will not work.

      Since there was no power lose from Windows to DOS, the signature 
      deposited by driver was not cleared. Therefore, when power lose from 
      DOS, bootcode sees the WOL signature and was bypassing the WoL 
      Changed bootcode to clear WoL signature if the startup does not have 
      driver signature.
    CQ#: 00008243

Version 3.02: 

  1. Get phy id from phy register instead of NVRAM configuration

      Get phy id from phy register instead of NVRAM configuration

      Originally, the phy id field in shared memory was read from NVRAM
      configuration. User could changed it any way they wanted and
      driver cannot rely on the content to perform as correct judgements

      The phy id in shared memory will be read from phy register instead
      of NVRAM field.

  2. Removed Phy 1.8v option
      Earlier bootcode contains 5701 product code which will
      cause a glitch in the PHY clock and could cause PHY to lock-up. 
      The code was carry over from 5701 in the old day was not needed
      in newer product.
      Removed unnecessary code that could cause Phy to lock-up.
  3. Added workaround for VPD glitch

      A false glitch can happen intermittently when host is accessing MII

      For new rev. chip, the lay out was too close between MII signals
      VPD event signal that may cause crosstalk. 

      Put a double read for VPD event. If the event self clears without
      firmware acknowledge, it is hardware glitch.

Version 3.01: 

  1. Lower voltage for 2.5v.
    Problem: the actual 2.5v regulator output is 2.66v.
    Cause:   The actual voltage level is higher than the specification
    Fix:     Changed the regulator setting to lower the voltage. 

  2. Enable phy in cold reset.

      Cannot access MAC register if phy is in powerdown state. 
      When Windows is restarting, the driver go through the shutdown 
      routine. When WoL is disabled, it turns off phy completely by 
      putting phy to powerdown mode. When it restarts, the main power,
      3.3 volt is stable. Only rely on PCI reset, the device does not
      generating power on reset; thus phy is not reset and still in 
      powerdown state. To access MAC registers, phy clock is required and
      we need to access the register for MAC address initialization.
      If it is cold reset, it will put phy to 10mbps to enable the clock 
      before accessing MAC registers. This also helps to reduce power 
      consumption by putting at lowest speed. The phy will eventually get 
      reset at phase 2 code.
Version 3.00:
    Initial version (Based on 5705 V3.14)
Download Driver Pack

How To Update Drivers Manually

After your driver has been downloaded, follow these simple steps to install it.

  • Expand the archive file (if the download file is in zip or rar format).

  • If the expanded file has an .exe extension, double click it and follow the installation instructions.

  • Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.

  • Find the device and model you want to update in the device list.

  • Double-click on it to open the Properties dialog box.

  • From the Properties dialog box, select the Driver tab.

  • Click the Update Driver button, then follow the instructions.

Very important: You must reboot your system to ensure that any driver updates have taken effect.

For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.

server: web3, load: 0.49