releases.txt Driver File Contents (R243173.exe)

           Release Note for Stanford ME Bootcode Firmware

 Version 3.11 ---- 6/20/07
1. Serial number get changed issue 

  The workaround for CQ#28997 in V3.10 only restores 0x164[31:28] and 0x168[7:0] after setting bit 23 of 0x7c04.
  In this release, the entire 32 bits of 0x164 and 0x168 will be restored.

 Version 3.10 ----  6/19/07
1. Serial number get changed issue

  Problem: CQ#28997
    The serial number in offset 0x164/168 get changed after reset. As result, OS will
    treat our device as new device in the system. 
	Under certain corner cases, the Reserved bits of  0x164[31:28] or 0x168[7:0]  may not have default value set correctly.  

    Firmware will write back the hardware default value after setting bit 23 of 0x7c04. 
 Version 3.09 ---- 02/13/07 
1. NVRAM parameters to set GPIO initial configuration for LOM designs
  Enhancement: CQ28395
    The GPIO0 and GPIO2 configuration will be based on NVRAM setting. 
    B57diag version 10.43 or later can be used to configure this setting
    on both GPIO0 and GPIO2.    
    No change for NIC designs.
    When upgrading to this version (or any future version) from any previous 
    version, "seprg" command should be used instead of "upgfrm". If "upgfrm" 
    is used, the default configuration setting will configure those GPIO pins 
    as input pins which is not compatible from the old default setting. The 
    old bootcode configure all unused GPIO pins to output and drive it to zero. 
    When "seprg" is used, the default configuration will be the same as older 
    bootcode behavior; configure to output pin and drive it zero.    
 Version 3.08 ---- 1/19/07
1. Fixed Timer Prescale value such that the timer tick will be 1us

  Problem: (CQ#27938)
    Currently, one timer tick will take 2us with the default Timer Prescale value in register 6804[7:1].  
    The default Timer Prescale value 0x7f has been used and has not been adjusted correctly.   
    Changed the Timer Prescale value to 65 in register 6804[7:1].

    5705 and newer devices.

2. Fixed STM45PE20 NVRAM write issue

   Problem: CQ#27733
     When TPM is enabled, STM45PE20 NVRAM write access intermittently fails

     When TPM is enabled (TPM_EN# tied to GND) and at the PE_RST# transition
     from low to high, the register 0x7028 may come up with a non-default value.
     This issue is seen only when WoL is enabled. WoL routine slows down
     the core clock before putting the device in WoL sleep state. 
     We don't see this issue with WoL disabled. This is because if WoL is 
     disabled, the device is put into Power Down state instead of slow core 
     clock state when the system transitions to a sleep state. 

     To workaround this, bootcode win/lock arbitration first, then reset the 
     NVRAM access block. This operation should be transparent to TPM. 

 Version 3.07 ---- 11/28/06 
1. Fixed NVRAM read bug

    Due to other project change, since version 3.06, shared_config was read
    NVRAM access FIRST/LAST bit can only be used in consecutive addresses.
    When reading configurations from offset 0xc4,0xc8 and 0xdc, 0xdc could
    not be read in one bulk read. 
    Shared_config 0xdc was read separately from previous bulk read.

 Version 3.06 ---- 11/07/06 
1. PCIE Link Polarity

  Enhancement: CQ#27039, CQ#26767, CQ#27105
    Apply PCIE Link polarity workaround only at hardware reset (POR or 

 Version 3.05 ---- 10/09/06 
1. L1 exit latency improvement
  Enhancement: CQ#27044
    Improve the L1 exit latency when Clock Request is enabled.
    No change for non-Mobile parts.

2. Enable Clock Request
  Enhancement: CQ#26951
    The clock request was disabled in version 3.04 for CQ #26629. 
    Change to use h/w default setting.

 Version 3.04 ---- 9/15/06 
1. Disable Clock Request
  Enhancement: CQ#26629
    The clock request enabled feature is not fully tested. This feature needs 
    to be disabled for RC 10.0 release.
    The ClockReq is automatically disabled by h/w on a non-Mobile parts; therefore,
    this change does not affect non-Mobile parts.
 Version 3.03 ---- 9/07/06 
1. Link speed issue

  Enhancement: CQ26652
    We have compatibility issue with Intel NIC Intel Pro/1000MT based LOM 
    (NDIS5.1 8.5.14, Auto detect for Speed/Duplex parameter, Windows XP 
    Professional SP2 O/S). The symptom shows when WoL is disabled and there
    is no management firmware loaded, after first time power up, the link 
    partner settles at speed 10H where our device settle at 1000F after the 
    link negotiation. To workaround the issue, bootcode is changed to use 
    different method to initialize the phy. 
    This issue exists not only in this device but all NetXtreme I products.  

 Version 3.02 ---- 8/18/06 
1. Corrected version number in offset

    The version in nvram offset 0x96 was showing version 3.00 for version 3.01.
    firmware Built error
    Changed the code to generate correct version number.
2. Fixed PXE does not run issue

  Problem: CQ#26399
    Cannot perform a network boot from 5756ME after a soft reboot
    Phase one bootcode was located in wrong location. Since the RxMBuff was
    increased from 48k to 56k in StanfordME. The phase one bootcode was 
    supposed to be moved up 8k also. Since it was not relocated, as result, 
    phase one bootcode was sitting at the mbuf area. When driver is loaded 
    and receiving data from the network, the bootcode was corrupted by
    incoming data. Furthermore, since the fastboot was enabled by bootcode,
    the ROM code was jumping to the corrupted area so the PXE was not
    enabled and serviced.
    Relocated phase one bootcode. 
    Since the phase one most likely to be corrupted after driver is loaded,
    any subsequent reset, the bootcode will not run due to the fastboot feature.
    Driver probably will time out waiting for the reverse of signature.      

 Version 3.01 ---- 8/15/06 
1. Initialized TxMbuf

    ASF/IPMI transmission stuck if transmit packet size larger than 440 bytes.
    TxMbuf unused bits were not initialized by ASIC. Boot code only clear range
    0x8000-0xa000 of TxMBuf after boot up. This will corrupt the TxMbuf cluster 
    if IPMI/ASF transmit bigger size (larger then 440 bytes) of packets.
    Initialize the first word of each TxMbuf cluster (range 0x8000-0xa800) 
    to zero.

2. Toggle GPIO1 for NIC configuration when shutdown

  Problem: (CQ 26346)
    5756ME/5722 NIC configuration will consume a total of 90mA when power down.
    When power down the 5756ME/5722 devices, the external logic on the NIC
    will still consumes Vaux power.
    Toggle GPIO1 when detecting Vmain is loss and WOL is disabled, so the external
    Power Switching Circuitry can shut-off the Vaux. 
    This will only apply to the NIC configuration, no change for LOM configuration.
 Version 3.00 ---- 7/17/06 
Initial Release:
  This version is a branch from 5755m bootcode v3.19. Gphy initialization 
  for BER performance workaround has been removed. 

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