releases.txt Driver File Contents (R243173.exe)

             Release Note for Baxter Bootcode Firmware
                           5752, 5752m

 Version 3.30 ---- 04/23/07 
1. NVRAM parameters to set GPIO initial configuration of Non-M device for LOM designs
  Enhancement: CQ28392
    The GPIO0 and GPIO2 configuration will be based on NVRAM setting. 
    B57diag version 10.42 can be used to configure this setting on GPIO0.
    b57diag version 10.43 or later can be used to configure this setting
    on both GPIO0 and GPIO2.    
    No change for NIC designs.
    When upgrading to this version (or any future version) from any previous 
    version, "seprg" command should be used instead of "upgfrm". If "upgfrm" 
    is used, the default configuration setting will configure those GPIO pins 
    as input pins which is not compatible from the old default setting. The 
    old bootcode configure all unused GPIO pins to output and drive it to zero. 
    When "seprg" is used, the default configuration will be the same as older 
    bootcode behavior; configure to output pin and drive it zero. 
 Version 3.29 ---- 02/13/07 
1. NVRAM parameters to set GPIO initial configuration of M device for LOM designs
  Enhancement: CQ28392
    The GPIO0 and GPIO2 configuration will be based on NVRAM setting. 
    B57diag version 10.42 can be used to configure this setting on GPIO0.
    b57diag version 10.43 or later can be used to configure this setting
    on both GPIO0 and GPIO2.    
    No change for NIC designs.
    When upgrading to this version (or any future version) from any previous 
    version, "seprg" command should be used instead of "upgfrm". If "upgfrm" 
    is used, the default configuration setting will configure those GPIO pins 
    as input pins which is not compatible from the old default setting. The 
    old bootcode configure all unused GPIO pins to output and drive it to zero. 
    When "seprg" is used, the default configuration will be the same as older 
    bootcode behavior; configure to output pin and drive it zero.    
 Version 3.28 ---- 1/19/07
1. Fixed Timer Prescale value such that the timer tick will be 1us

  Problem: (CQ#27938)
    Currently, one timer tick will take 2us with the default Timer Prescale value in register 6804[7:1].  
    The default Timer Prescale value 0x7f has been used and has not been adjusted correctly.   
    Changed the Timer Prescale value to 65 in register 6804[7:1].

    5705 and newer devices.

 Version 3.27 ---- 11/28/06 
1. Fixed NVRAM read bug

    Due to other project change, since version 3.26, shared_config was read
    NVRAM access FIRST/LAST bit can only be used in consecutive addresses.
    When reading configurations from offset 0xc4,0xc8 and 0xdc, 0xdc could
    not be read in one bulk read. 
    Shared_config 0xdc was read separately from previous bulk read.
 Version 3.26 ---- 11/13/06 
1. PCIE Link Polarity

  Enhancement: CQ#27039, CQ#26767, CQ#27105
    Apply PCIE Link polarity workaround only at hardware reset (POR or 
 Version 3.25 ---- 9/15/06 
1. Link speed issue

  Enhancement: CQ26652
    We have compatibility issue with Intel NIC Intel Pro/1000MT based LOM 
    (NDIS5.1 8.5.14, Auto detect for Speed/Duplex parameter, Windows XP 
    Professional SP2 O/S). The symptom shows when WoL is disabled and there
    is no management firmware loaded, after first time power up, the link 
    partner settles at speed 10H where our device settle at 1000F after the 
    link negotiation. To workaround the issue, bootcode is changed to use 
    different method to initialize the phy. 
    This issue exists not only in this device but all NetXtreme I products.  

2. Management firmware fails when LOM is disabled by BIOS
  Problem: CQ#25290
    The management firmware does not work when LOM is disabled by BIOS.  
    With certain platform, when the device is disabled by BIOS, PERST# is
    asserted and refclk is removed. Under this condition, the workaround 
    implemented for unstable refclk in version 3.52 logic will kick in 
    and cause bootcode to wait for stable refclk. Since the clock will 
    never be available, hence, bootcode is stuck in forever loop and cannot 
    proceed to load management firmware. 
    Added one second timeout when waiting for stable refclk. The bootcode
    will advance when the timeout expires.
    Since there is no refclk is available; furthermore, the PERST# is 
    asserted under this condition, the PCI domain registers become not 
    accessible. Since bootcode has many PCI domain register access after
    exiting the loop, all those register access become invalid and will 
    timeout causing further delay to load IPMI code. The estimated delay is
    about 3 to 4 seconds compare to normal boot under this particular 
    condition. (There is no impact and no delay under normal condition.)
3. Enabled second phase fastboot feature

    Only the first phase bootcode NVRAM loading is bypassed with the older
    bootcodes. Starting with this version, the second phase is also pre-
    reserved and NVRAM code loading is bypassed. 

    Since the bootcode is no longer reload from NVRAM, the boot time will be
    much faster. Upon reset, there will be only few words of configuration 
    NVRAM access.    
 Version 3.24 ---- 3/07/06 
1. VPD-R checksum error

  Problem: Related CQ#23565, CQ#23566
    VPD-R checksum was incorrect
    Checksum was calculated from VPD-R to the end of VPD-R region; however,
    the specification indicates that Checksum should be calculated from the
    offset zero.
    Corrected the checksum
2. Initialized Cardbus pointer register

  Enhancement: CQ#23431
    Since Cardbus support is no longer a requirement, in order to pass
    the plug-fest compliance test, we write zero to register 0x28 to disable
    cardbus feature.
 Version 3.23 ---- 2/23/06 
1. Changed L0s exit latency timer

  Enhancement: CQ#23420, CQ#23420
    Got a request from ASIC team to use hardware default for L0s exit latency
    timer. The code is changed to not to touch those registers for revision A2
    or newer.
    Since the L0s exit latency timer is changed from 1us back to hardware
    default 4us. There will be performance impact after this change. 

 Version 3.22 ---- 2/14/06 
1. Changed revision reading

    CPU reads incorrect silicon revision id in D3 power state.
    In D3 power state, except OOB, the PCI/PCIE registers are not accessible.
    All reads returns zero. Because of this, the read is not reliable.
    Instead of reading from register 0x68, the code is changed to read the
    revision id from register 0x2018. The register 0x2018 is available at all
2. PCIE link polarity workaround problem

  Problem: CQ#14612
    After Windows shutdown or DOS shutdown, the link stay at 10mb and WoL does
    not work.
    The PCIE link polarity check loop was stuck in waiting for PCIE link to
    come up while there was no VMain. Since VMain drains slowly, there was 
    a time bootcode come up seeing VMain present and apply the PCIE link 
    polarity workaround. The workaround has implemented to wait for PCIE 
    link to come up and check for the polarity. In this case, since the 
    VMain slowly goes away, PCIE link never came up and the loop was stuck 
    Put a VMain check in the workaround loop. If the VMain goes away, it will
    break out of the loop and ignore PCIE polarity workaround.
3. Fixed WoL for OS/DOS shutdown

  Problem: CQ#22944, CQ#23220
    Can't waked up by wake on lan after OS shutdown
    CPU got hang in switching to alternate clock while there is no VMain.
    When there is no VMain, bootcode cannot access PCI domain registers.
    Therefore, the code is changed to not to switch to alternate clock when
    there is no Vmain.
 Version 3.21 ---- 12/09/05 
1. Changed PLL status polling

  Problem: CQ#22283
    Bootcode version 3.16 to 3.20 did not work on some systems. 
    The device may disappear, link at 10ms, and cause b57diag CPU test to
    In 5752, depends on some systems, the PLL status returned warning
    code instead of success code for low voltage. Since the workaroud for 
    v3.16, #1 uses this code to determine good PLL status, the bootcode
    was hang waiting success code.
    Changed to poll for status bit instead of error code. 
 Version 3.20 ---- 12/06/05 
1. Force PCIE polarity

  Problem: CQ#22100,CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254
    In some platform, the PCIE link polarity comes up incorrectly. 
    ASIC could not handle all cases correctly.
    Wait until PCIE link comes up. Then based on the link polarity status
    detected by ASIC polarity auto detect, firmware will then force the 
    PCIE link to the correct polarity.
 Version 3.19 ---- 11/10/05 
1. Fixed WoL was not working issue.

  Problem: CQ#14614
    WoL was not working on OOB, DOS shutdown or Windows S5 case. 
    Version 3.16 added workaround for platforms that show an unstable 
    PCIE refclk during power up. Nevertheless, there is a limitation to 
    this workaround as to where it requires VMAIN to be present. In systems 
    where there is no VMAIN present and there is no PCI-E REFCLK at all for 
    the cases outlined above the bootcode will loop forever, therefore not 
    enabling WoL.
    Added a condition to the "unstable PCI-E Refclk" workaround to apply
    this fix only when there is VMain present.  In cases where there is no 
    VMAIN present, the boot code will no longer check/wait for a "stable 
    PCI-E Refclk" before continuing.

 Version 3.18 ---- 10/27/05 
1. Fixed data corruption issue

  Problem: CQ#14509
    Data corruption is reported by the NDIS tester while running NDIS Tests
    The stack pointer is initialized incorrectly. The file was shared by
    other project has only 48K RxMbuf. Since this device has 64K, the stack 
    pointer should be initialized to 0x20000, instead, it was initialized to
    0x1c000, the receive data buffer area. As bootcode constantly modifying
    stack content, as result, it was causing Ethernet traffic data corruption.
    Changed the stack pointer back to 0x20000.
    This issue has been intruduced in version 3.16, 3.17.      
 Version 3.17 ---- 10/18/05 
1. Fixed Cable Sense mode

    The Cable Sense mode was not enabled correctly. 
    In 5752 family devices, to enable Cable Sense mode, not only needed to
    enable SuperAirplane mode but GPHY also needed to be programmed. The 
    previous, version 3.16, was setting SuperAirplane mode without 
    configuring GPHY. Therefore, it would not function as Cable Sense mode.
    In addition to enabling SuperAirplane mode, also setting GPHY to correct

2. Move GPIO initialization to Phase1 code

    Originally, activating VAUX power was done in phase 2 bootcode.
    However, once driver waited for phase1 signature, driver may start to 
    configure GPIO for WoL setting. The 2nd phase GPIO initialization may 
    destroy driver's setting.
    This problem was worked around by driver by waiting for phase2 bootcode
    to be loaded before the GPIO initialization. This change does not 
    affect anything since driver already have the work around. 
 Version 3.16 ---- 10/7/05 
1. Worked around unstable PCIE refclk issue

    The bootcode cannot initialize PCIE registers reliablity in some

    In some particular system, the PCIE refclk was not stable for a long 
    period of time. Accessing PCI config. space registers, 0x7d00 and 
    0x7e00 block registers relying on this clock. When the clock is not
    available, all access to those registers will timeout and read will 
    return zero.
    Since all access performed to 0x7d00, 0x7e00, and
    PCI config. space is invalid until the clock is available, many 
    initialization may not be done correctly; or at least it may read
    incorrect revision ID. 
    Therefore, to ensure the code is executed properly, we need to ensure
    the clock is there first before proceeding with initialization. 
    Put a wait loop until refclk is stable before move on to initialization
2. Fixed Super Cable Sense mode

    Super Cable Sense mode was not enabled correctly.
    To enable cable sense mode, Baxter and Shasta use different registers.
    The code was using wrong register. 
    Fixed the code.    
 Version 3.15 ---- 9/7/05 
1. Removed CDR Freq value workaround for A2 or newer rev.

    The workaround for CDR (Clock & Data Recovery) "Tracking was taking much
    too long" issue has been corrected in Shasta A2 or newer revision. 
    Therefore, keep this workaround only for A1 or older revisions. 

2. Added L0s performance

    The revision A2 or newer is allowed to change PCIE serdes parameter to
    boost up the performance. The firmware will change the parameter for
    A2 or newer devices.
3. Enabled ECD12650 ASIC fix    

    ECD12650 (Low Power Mode fix) is fixed A2 or newer revision. This change 
    enables the fix if the device is A2 or newer.    
 Version 3.14 ---- 8/26/05 
1. Added Super Airplane mode

    Added Cable Sense (super-airplane mode) function
    This function is only for mobile device (5752M)
 Version 3.13 ---- 6/9/05 
1. Enabled CQ11121 ASIC fix

    There is ASIC fix for CQ11121. This version enables the fix.
  CQ11121 Problem:
    Data Link Layer Retry Logic will corrupt TLP upon receiving NAK
    The Data Link Layer's retry buffer logic will merge two TLPs, a receiving 
    TLP from the Transaction Layer with a replay TLP from the retry buffer, 
    which will generate a corrupted TLP upon receiving a NAK from the Link 
    Partner. The corner case arises whenever the rising edge of the GotNAK 
    signal occurs at the same time with the rising edge of the TransGrant 
    signal. The GotNAK signal is used by the retry logic to initiate replay 
    of a pending (unacked) TLP. The TransGrant signal is used by the Transaction 
    Layer to initiate a new TLP transfer. When the rising edge of these two 
    signals occur, a corrupted TLP is generated if the length of the replayed 
    TLP is shorter than the length of the receiving TLP from the Transaction 
    Layer. This results in system blue screened and/or Data Corruption.  

    This change is fixed in ASIC, bit 23 of 0x7d00 is a bit to enable it. 
    This version of bootcode will enable this fix by sitting bit 23 of 0x7d00 
    to 1.
 Version 3.12 ---- 5/16/05 
    LOM disappears after multiple LOW_PWR assertion/deassertion cycles

    When the PLL (Phase Lock Loop) Power Management bit is enabled 
    (register 0x7d00[4]=1), during exhausted multiple cycles of WoL testing
    (entering/resuming from D3_COLD), there is a small chance that the 
    device can lock-up.

    This is because when the 0x7d00[4] bit being set, when the PERST# is 
    asserted AND when  the chip enters PCIE L2 link state, the internal PLL 
    will be powered down. Some time later, when the PERST# is disserted, 
    the chip will try to re-establish PCIE link, at this time the PLL may 
    not able to restart because the capacitor (internal in the chip) that 
    feeding VCD is in a "intermediate charged state".

    Clear PLL power management bit, bit 4 of 0x7d00, as part of bootcode 

    This change will cause the chip to consume slightly more power during 
    D3-Cold state only. (between 55mA to 75mA, depending on whether or not 
    the "PCIE reference clock" is shut-down or not). No power consumption 
    affected in other states.

 Version 3.11 ---- 4/26/05 
1. Fixed device disappearing problem

  Problem: CQ12650
    After numerous power on/off test, in rare cases, possibly, the device
    can disappear. 
    PCIE PLL can get stuck in the powerdown state if it does not receive 
    a proper reset after exiting the IDDQ state (which can be enabled by 
    either Low Power Mode pin or the powerdown register bit)
    Not to use powerdown register bit to shutdown the device, but instead,
    the bootcode shut down individual blocks such as GPhy, PCIE Tx/Rx Serdes,
    PCI clocks, and slowing down the core clock.
    Without using shutdown register bit, and shutdown the device by each 
    individual blocks, will consume more power.
    It used to be around 10mA with shutdown bit, now the device will
    consume around 150mA at 1.2V power rail and 30mA at 2.5V.
    When deaddead feature is used to disable the device, the device will
    consume about 90mA at 1.2V and 41mA at 2.5V when VMain present. When
    VMain is turned off, it consumes around 70mA at 1.2 and 40mA at 2.5V.        

2. Fixed "deaddead" feature problem

    After depositing "deaddead" to 0xb50, the device was not shutting down.
    The data cache was turned on. When the data cache is on, the external (host)
    change of shared memory content (deaddead mark) was not able to be detected
    by internal CPU. 
    Turned off data cache before entering the service loop. 
3. Removed bootcode Power Budgeting HotPlug support

    HotPlug Power Budgeting feature was not implemented in Baxter ASIC.
    Removed bootcode HotPlug Power Budget data programming code implemented
    in bootcode version 3.06, item 3. 
 Version 3.10 ---- 3/22/05 
1. Fixed Address Lockout policy error

    Bootcode was causing policy error in bit 31:28 of register 0x7000.
    The Baxter A1 chip design is; when Address Lockout feature is enabled,
    the NVRAM Access register (0x7024) is not writable. If a write is
    attempted, a policy error 0x9 will be posted in bit 31:28 of 0x7000.
    Checks for Address Lockout feature enable status. If it is enabled,
    don't write to register 0x7024 to enable NVRAM access.
    This policy error status is originally designed for diagnostic purpose;
    however, TPM software may use this status and when there is an error, it
    shuts down the TPM software. This shutdown feature can be disabled via
    the OTP. When it is disabled, the policy error has no effect on operation of
    the device other than to make the most significant nibble of 0x7000 non-zero.
 Version 3.09 ---- 3/15/05 
1. Enabled CQ10453 fix for chip Rev. A1 or newer

    Enable CQ10453 ASIC fix for chip Rev. A1 or newer.

 Version 3.08 ---- 3/8/05 
1. Fixed the bug in v3.07

  Problem: CQ#12253
    ASF secure section was not working.    
    Revision information was not posted correctly in shared memory.
    This bug was created in v3.07 due to other project's change.
    Code was erroneously coded.
    Fixed the software bug.    

 Version 3.07 ---- 2/23/05 
1. Enabling ASIC fixes

    ASIC team has evaluated following ASIC fixes and requesting to enabling them:

      1. Enable CQ11234 Fix.       (set bit 8 of 0x7C04)
         In Shasta earlier than C0 revision of ASIC, when a PCI-E training error
         condition is detected, the link training error bit at uncorrectable 
         Error Status Register will be set. Optionally, depending on the 
         training error mask and severity setting, an uncorrectable error 
         message may be sent upstream to the root complex. This is required 
         by the PCIE v1.0a spec. 

         However, the training error has not been well defined in the spec
         v1.0a, and false triggering is highly undesirable. In the draft PCIE 
         v1.1 the link training error is removed from the specification.

         In Baxter, the ASIC added a programmable feature to support this
         change. This version of bootcode sets the bit (0x7c04[8]) which is to 
         instruct the ASIC to remove training error bits from pcie advanced 
         error reporting registers and to be PICE v1.1 compliance. 

      2. Enable CQ11386/CQ9321 fix (set bit 27 of 0x7C00)
         In Shasta earlier than C0 revision of ASIC, under some corner conditions
         (such as when the Chipset's Replay Timer parameter is programmed
         incorrectly), Shasta will send a packet on the PCI-E bus which causes 
         the chipset to viewed as an "unexpected completion".

         In Baxter, the ASIC had address this minor issue, however the h/w
         fix is by default "disabled".

         This version of bootcode enables the h/w change (sets 0x7c00[27]).
      3. Enable CQ11011 Fix        (clear bit 18 of 0x7D00 && setting bit 4 of 0x7D00)
         In Shasta earlier than C0 revision of ASIC, when the chip enters D3-Cold, 
         the chip internal PLL clock and power management can intermittently 
         become unstable for a few microseconds.

         In Baxter, this issue was fixed.  However, the firmware needs to 
         program the ASIC (clear bit 0x7d00[18] and set bit 0x7d00[4]) so
         that when the chip enters D3-cold, the PLL clock and power management
         are stable.

      4. Enable CQ11211 Fix        (set bit 24 of 0x7D00)
         In Shasta earlier than C0 revision of ASIC, if a PME_TURN_OFF message 
         is received before the device is first placed into a D3hot state 
         (and L1 link state), the device will generate an internal reset 
         because this "power-down" sequence was unexpected.  This power-
         down sequence is not legal per the PCI 1.0a spec, but is permitted 
         in the ECN 37 which is included in the draft PCI-E v1.1. spec.
         An unexpected reset could then lead to other problems. For
         instance, WoL configuration information could be lost, which could 
         cause some forms of WoL to not work.  

         In Baxter, the ASIC has been changed to support ECN 37 so an
         internal reset is not generated under this circumstance. However 
         the h/w fix is by default "disabled" (for backward compatibility).

         This version of bootcode enables the h/w fix (sets 0x7d00[24]).

      5. Enable CQ9987 Fix         (Clear bit 18 of 0x2018)      
         In Shasta earlier than C0 revision of ASIC, when ASF (or IPMI) f/w is 
         trying to enqueue an Ethernet packet into the MacTxQueue, if the 
         MacTxQueue is already full, and if there is a register access from the 
         Host, that register access may fail.

         This particular problem was avoided by older ASF and IPMI f/w.  The
         f/w would wait until the MacTxQueue is not full, and then submit the
         packet into the queue, hence avoiding the problem.

         However, in Baxter, this problem is properly fixed in the ASIC, and
         the f/w workaround is no longer needed.  However, the fix in the
         device was by default "disabled" (for backward compatibility).

         This version of bootcode enables the h/w fix (clears 0x2818[18]).

 Version 3.06 ---- 2/15/05 
1. Removed L0s performance Optimization workaround.

    After adding many feature and workarounds, the code size has reached to
    8k limit. We had to find a way to reduce the code.
    The L0s performance optimization feature implemented in Shasta bootcode v3.27,
    #2, later, found only works better in some machines and make it worse in other.
    Once there was a discussion about removing this feature. Then, decided to 
    changed it to be configurable in Shasta bootcode v3.39, #2. This code is inherited
    from Shasta and carries all the changes. Since this code is removed from Shasta in 
    order to save some code space, to keep it consistent, this feature is also removed 
    from Baxter as well.
   Removed the L0s performance optimization workaround and the configuration.

2. Enhanced CDR Freq. Value workaround performance

    With further analysis, and testing, ASIC team found with combination
    of other Rx Timer value (reg.2) and CRD_RW value (reg.7) works the
    best. Bootcode now is changed use that value.
3. Added C0 HotPlug feature

    Added HotPlug Power Budget data programming to support HotPlug feature.
4. Removed CQ#11849 workaround, version 3.02,#2

    ASIC team is still analyzing the result of workaround. This workaround may
    potentially upset Intel chipset. 
    This workaround is removed until further analysis.                 
 Version 3.05 ---- 1/27/05 
1. Disabled CQ10453 workaround

    In Baxter A1 tape-out review meeting, the decision is to go with 
    "disable the ECD 10453".
    Disabled CQ10453 workaround
    This version will be the same as version 3.03.
 Version 3.04 ---- 1/24/05 
1. Re-enabled CQ10453 workaround

    By the workaround in v3.03. CQ10453 Fix could be enabled without
    problems; Hence, the ASIC CQ10453 Fix is re-enabled. 
 Version 3.03 ---- 1/20/05 
1. Fixed PXE problem

    Using version 3.02, if PXE is enabled, the system will hang.
    The workaround applied in version 3.02 has a code will stay
    in tight loop without servicing PXE. When system BIOS try to read
    PXE without bootcode servicing the read, system will hang. 
    Changed the algorithm to service PXE while applying the workaround
    for cq#11849. 
    Version 3.02 is removed from release directory.     
 Version 3.02 ---- 1/20/05 
1. Changed CDR Frequency value

    By changing CDR (Clock & Data Recovery) Freq. value can boost
    performance. This change is recommended by ASIC team.
2. Changed Rx Error Thresholds

  Problem: CQ#11849
    Rebooting the system causes the LOM to no longer be seen by the 
    BIOS and a message is displayed on the screen which says the LOM 
    is no longer present.
    The default error threshold to cause error event was too large
    for some system, the link error was not able to be detected.
    Since the link could not be established correctly, the device
    Reduce all thresholds, frame error([8:11]), disparity error([4:7]), 
    and code error([0:3]), from default value of 0xf to 0x3. Then, have 
    bootcode to poll for any error condition. If an error is detected, 
    re-sync the link. When link is reestablished, the device will be 
    visible from the host.

3. Initialized GPIO to output

    GPIO was set to be input. When it is not connected, the signal will
    be floating.
    The hardware default for GPIO is input. Firmware needed to change it 
    to output.
    Changed bootcode to drive GPIO to output when configuration is set to LOM.
 Version 3.01 ---- 12/30/04 
1. Disabled CQ10453 workaround

    Driver load/unload will cause system to crash
    ASIC team is still evaluating this at this point
    By disabling CQ10453 ASIC hardware workaround, it made
    some system to pass overnight; however, test shows even
    with this change, it still can fail on NMI with some systems.
    ASIC team is still investigating. In the mean time, since
    this change has some improvement, this change is made.
2. Fixed Non-Atmel buffered flash problem

    Version v3.00 can only work with Atmel buffered flash. When
    other NVRAM is used, the phase 2 bootcode was not able to be
    loaded and cause LED to blink. 
    Coding problem
    Fixed the software bug.     

 Version 3.00 ---- 12/08/04 
Initial Version. This version is a branch of Shasta bootcode v3.40
with the following enhancement:

 1. Added Fastboot support
 2. Changed all unused GPIO pins to output for LOM by default.
 3. Enabled ASPM L1 Support
 4. Removed some unneeded workaround implemented for Shasta.
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