Release Note for Baxter Bootcode Firmware
============================================
5752, 5752m
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Version 3.11 ---- 4/26/05
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1. Fixed device disappearing problem
Problem: CQ12650
After numerous power on/off test, in rare cases, possibly, the device
can disappear.
Cause:
PCIE PLL can get stuck in the powerdown state if it does not receive
a proper reset after exiting the IDDQ state (which can be enabled by
either Low Power Mode pin or the powerdown register bit)
Fix:
Not to use powerdown register bit to shutdown the device, but instead,
the bootcode shut down individual blocks such as GPhy, PCIE Tx/Rx Serdes,
PCI clocks, and slowing down the core clock.
Impact:
Without using shutdown register bit, and shutdown the device by each
individual blocks, will consume more power.
It used to be around 10mA with shutdown bit, now the device will
consume around 150mA at 1.2V power rail and 30mA at 2.5V.
When deaddead feature is used to disable the device, the device will
consume about 90mA at 1.2V and 41mA at 2.5V when VMain present. When
VMain is turned off, it consumes around 70mA at 1.2 and 40mA at 2.5V.
2. Fixed "deaddead" feature problem
Problem:
After depositing "deaddead" to 0xb50, the device was not shutting down.
Cause:
The data cache was turned on. When the data cache is on, the external (host)
change of shared memory content (deaddead mark) was not able to be detected
by internal CPU.
Fix:
Turned off data cache before entering the service loop.
3. Removed bootcode Power Budgeting HotPlug support
Problem:
HotPlug Power Budgeting feature was not implemented in Baxter ASIC.
Fix:
Removed bootcode HotPlug Power Budget data programming code implemented
in bootcode version 3.06, item 3.
----------------------------
Version 3.10 ---- 3/22/05
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1. Fixed Address Lockout policy error
Problem:
Bootcode was causing policy error in bit 31:28 of register 0x7000.
Cause:
The Baxter A1 chip design is; when Address Lockout feature is enabled,
the NVRAM Access register (0x7024) is not writable. If a write is
attempted, a policy error 0x9 will be posted in bit 31:28 of 0x7000.
Fix:
Checks for Address Lockout feature enable status. If it is enabled,
don't write to register 0x7024 to enable NVRAM access.
Impact:
This policy error status is originally designed for diagnostic purpose;
however, TPM software may use this status and when there is an error, it
shuts down the TPM software. This shutdown feature can be disabled via
the OTP. When it is disabled, the policy error has no effect on operation of
the device other than to make the most significant nibble of 0x7000 non-zero.
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Version 3.09 ---- 3/15/05
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1. Enabled CQ10453 fix for chip Rev. A1 or newer
Enhancement:
Enable CQ10453 ASIC fix for chip Rev. A1 or newer.
----------------------------
Version 3.08 ---- 3/8/05
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1. Fixed the bug in v3.07
Problem: CQ#12253
ASF secure section was not working.
Cause:
Revision information was not posted correctly in shared memory.
This bug was created in v3.07 due to other project's change.
Code was erroneously coded.
Fix:
Fixed the software bug.
----------------------------
Version 3.07 ---- 2/23/05
----------------------------
1. Enabling ASIC fixes
Enhancement:
ASIC team has evaluated following ASIC fixes and requesting to enabling them:
1. Enable CQ11234 Fix. (set bit 8 of 0x7C04)
In Shasta earlier than C0 revision of ASIC, when a PCI-E training error
condition is detected, the link training error bit at uncorrectable
Error Status Register will be set. Optionally, depending on the
training error mask and severity setting, an uncorrectable error
message may be sent upstream to the root complex. This is required
by the PCIE v1.0a spec.
However, the training error has not been well defined in the spec
v1.0a, and false triggering is highly undesirable. In the draft PCIE
v1.1 the link training error is removed from the specification.
In Baxter, the ASIC added a programmable feature to support this
change. This version of bootcode sets the bit (0x7c04[8]) which is to
instruct the ASIC to remove training error bits from pcie advanced
error reporting registers and to be PICE v1.1 compliance.
2. Enable CQ11386/CQ9321 fix (set bit 27 of 0x7C00)
In Shasta earlier than C0 revision of ASIC, under some corner conditions
(such as when the Chipset's Replay Timer parameter is programmed
incorrectly), Shasta will send a packet on the PCI-E bus which causes
the chipset to viewed as an "unexpected completion".
In Baxter, the ASIC had address this minor issue, however the h/w
fix is by default "disabled".
This version of bootcode enables the h/w change (sets 0x7c00[27]).
3. Enable CQ11011 Fix (clear bit 18 of 0x7D00 && setting bit 4 of 0x7D00)
In Shasta earlier than C0 revision of ASIC, when the chip enters D3-Cold,
the chip internal PLL clock and power management can intermittently
become unstable for a few microseconds.
In Baxter, this issue was fixed. However, the firmware needs to
program the ASIC (clear bit 0x7d00[18] and set bit 0x7d00[4]) so
that when the chip enters D3-cold, the PLL clock and power management
are stable.
4. Enable CQ11211 Fix (set bit 24 of 0x7D00)
In Shasta earlier than C0 revision of ASIC, if a PME_TURN_OFF message
is received before the device is first placed into a D3hot state
(and L1 link state), the device will generate an internal reset
because this "power-down" sequence was unexpected. This power-
down sequence is not legal per the PCI 1.0a spec, but is permitted
in the ECN 37 which is included in the draft PCI-E v1.1. spec.
An unexpected reset could then lead to other problems. For
instance, WoL configuration information could be lost, which could
cause some forms of WoL to not work.
In Baxter, the ASIC has been changed to support ECN 37 so an
internal reset is not generated under this circumstance. However
the h/w fix is by default "disabled" (for backward compatibility).
This version of bootcode enables the h/w fix (sets 0x7d00[24]).
5. Enable CQ9987 Fix (Clear bit 18 of 0x2018)
In Shasta earlier than C0 revision of ASIC, when ASF (or IPMI) f/w is
trying to enqueue an Ethernet packet into the MacTxQueue, if the
MacTxQueue is already full, and if there is a register access from the
Host, that register access may fail.
This particular problem was avoided by older ASF and IPMI f/w. The
f/w would wait until the MacTxQueue is not full, and then submit the
packet into the queue, hence avoiding the problem.
However, in Baxter, this problem is properly fixed in the ASIC, and
the f/w workaround is no longer needed. However, the fix in the
device was by default "disabled" (for backward compatibility).
This version of bootcode enables the h/w fix (clears 0x2818[18]).
----------------------------
Version 3.06 ---- 2/15/05
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1. Removed L0s performance Optimization workaround.
Problem:
After adding many feature and workarounds, the code size has reached to
8k limit. We had to find a way to reduce the code.
The L0s performance optimization feature implemented in Shasta bootcode v3.27,
#2, later, found only works better in some machines and make it worse in other.
Once there was a discussion about removing this feature. Then, decided to
changed it to be configurable in Shasta bootcode v3.39, #2. This code is inherited
from Shasta and carries all the changes. Since this code is removed from Shasta in
order to save some code space, to keep it consistent, this feature is also removed
from Baxter as well.
Fix:
Removed the L0s performance optimization workaround and the configuration.
2. Enhanced CDR Freq. Value workaround performance
Enhancement:
With further analysis, and testing, ASIC team found with combination
of other Rx Timer value (reg.2) and CRD_RW value (reg.7) works the
best. Bootcode now is changed use that value.
3. Added C0 HotPlug feature
Enhancement:
Added HotPlug Power Budget data programming to support HotPlug feature.
4. Removed CQ#11849 workaround, version 3.02,#2
Problem:
ASIC team is still analyzing the result of workaround. This workaround may
potentially upset Intel chipset.
Change:
This workaround is removed until further analysis.
----------------------------
Version 3.05 ---- 1/27/05
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1. Disabled CQ10453 workaround
Problem:
In Baxter A1 tape-out review meeting, the decision is to go with
"disable the ECD 10453".
Fix:
Disabled CQ10453 workaround
This version will be the same as version 3.03.
----------------------------
Version 3.04 ---- 1/24/05
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1. Re-enabled CQ10453 workaround
Enhancement:
By the workaround in v3.03. CQ10453 Fix could be enabled without
problems; Hence, the ASIC CQ10453 Fix is re-enabled.
----------------------------
Version 3.03 ---- 1/20/05
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1. Fixed PXE problem
Problem:
Using version 3.02, if PXE is enabled, the system will hang.
Cause:
The workaround applied in version 3.02 has a code will stay
in tight loop without servicing PXE. When system BIOS try to read
PXE without bootcode servicing the read, system will hang.
Fix:
Changed the algorithm to service PXE while applying the workaround
for cq#11849.
Note:
Version 3.02 is removed from release directory.
----------------------------
Version 3.02 ---- 1/20/05
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1. Changed CDR Frequency value
Enhancement:
By changing CDR (Clock & Data Recovery) Freq. value can boost
performance. This change is recommended by ASIC team.
2. Changed Rx Error Thresholds
Problem: CQ#11849
Rebooting the system causes the LOM to no longer be seen by the
BIOS and a message is displayed on the screen which says the LOM
is no longer present.
Cause:
The default error threshold to cause error event was too large
for some system, the link error was not able to be detected.
Since the link could not be established correctly, the device
disappears.
Fix:
Reduce all thresholds, frame error([8:11]), disparity error([4:7]),
and code error([0:3]), from default value of 0xf to 0x3. Then, have
bootcode to poll for any error condition. If an error is detected,
re-sync the link. When link is reestablished, the device will be
visible from the host.
3. Initialized GPIO to output
Problem:
GPIO was set to be input. When it is not connected, the signal will
be floating.
Cause:
The hardware default for GPIO is input. Firmware needed to change it
to output.
Fix:
Changed bootcode to drive GPIO to output when configuration is set to LOM.
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Version 3.01 ---- 12/30/04
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1. Disabled CQ10453 workaround
Problem:
Driver load/unload will cause system to crash
Cause:
ASIC team is still evaluating this at this point
Fix:
By disabling CQ10453 ASIC hardware workaround, it made
some system to pass overnight; however, test shows even
with this change, it still can fail on NMI with some systems.
ASIC team is still investigating. In the mean time, since
this change has some improvement, this change is made.
2. Fixed Non-Atmel buffered flash problem
Problem:
Version v3.00 can only work with Atmel buffered flash. When
other NVRAM is used, the phase 2 bootcode was not able to be
loaded and cause LED to blink.
Cause:
Coding problem
Fix:
Fixed the software bug.
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Version 3.00 ---- 12/08/04
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Initial Version. This version is a branch of Shasta bootcode v3.40
with the following enhancement:
1. Added Fastboot support
2. Changed all unused GPIO pins to output for LOM by default.
3. Enabled ASPM L1 Support
4. Removed some unneeded workaround implemented for Shasta.
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Click the Update Driver button, then follow the instructions.
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