[INFO_FILE]
/////////////////////////////////////////////////
//
// MATROX ORION Info file
// For more informations refer to INFGUIDE.DOC
//
// REVISION HISTORY:
// 0000.0002.0000 - initial version.
// 0000.0007.0004 - CD Mil 7.00 released
// 0000.0007.1003 - CD Mil 7.10 released
// 0000.0008.0000 - Current version for Mil 7.8 (Current)
//
/////////////////////////////////////////////////
//
//***********************************************
//***********************************************
//SECTION #1: HEADER
//***********************************************
//***********************************************
// Generic product name line (ORION) = 47 caracters Max. including space for proper
// loading in Intellicam.
60BF 0008.0000.0000
ORION
"Matrox ORION"
Information file for the ORION board.
//
//
// **********************************************
// **********************************************
// SECTION #2: NEW GENERAL PARAMETERS|MEMBERS
// **********************************************
// **********************************************
//
//
[NEW_GPARAM]
//
// OPTION = ORION
// OPTION_4SIGHT_II_STD = ORION_4SIGHT_II_STD
// OPTION_4SIGHT_II_RGB = ORION_4SIGHT_II_RGB
// OPTION_4SIGHT_II_DUAL = ORION_4SIGHT_II_DUAL
// OPTION_MORPHIS = MORPHIS
//
// =============================================
//
// ******** Marc B Modification 99-12-09: Added new internal param. ********
//
GGEN_BOARD_TYPE ONE_VAL_PAR|BRD_OPT_ON|VOLATILE
//
board_specific_value
NO_STRING M_DEFAULT DUMMY_PAR OPTION no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_4SIGHT_II_STD no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_4SIGHT_II_RGB no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_4SIGHT_II_DUAL no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_MORPHIS no
eo_board_specific_value
//
eo_param
//
// --------------------------------------
//
// ******** J.McC Modification : Added new param. ********
//
GGRB_RGB_PATH MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Advanced
RGB Grab Path
eo_param_info
//
board_specific_value
no M_DEFAULT GRB_RGB_PATH_FORCED GRB_RGB_PATH_FORCED_AV yes
yes M_DEFAULT GRB_RGB_PATH_FORCED NO_BOPTION
eo_board_specific_value
//
enable = ENABLE[DAT_ENABLED & VDC_MONO & ( DEF_ORION | OPTION_4SIGHT_II_RGB )] ;
//
valid = ( ( DEF_DEC_PATH & ( VDL_PED_AMP != 50 ) & VDL_PEDEST & DEF_4SIGHT & DEF_NTSC ) ? ADDERROR[ERR_PEDESTAL_AMPL] : 0 ) ;
//
error_message
ERR_PEDESTAL_AMPL, "Use default pedestal amplitude of 50mv for NTSC or RS170."
eo_error_message
//
eo_param
//
//
//..............................
//enable = ENABLE[DAT_ENABLED & VDC_MONO ] ;
//enable = ENABLE[DAT_ENABLED & ( VDC_MONO | VDC_RGB_COL )] ;
// --------------------------------------
//
GVDT_CL_USE_CAMERA_VALID MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
GSYC_ANA_TYPE
//
valid = ( ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) & DEF_DEC_PATH & SYC_SEP ? ADDERROR[ERR_MONOSYNCSEP] ) ;
//
error_message
ERR_MONOSYNCSEP, "Separated sync not available on decoder path."
eo_error_message
//
eo_param
// --------------------------------------
//
// ******** RGB component video signal and separated SYNC. ********
// ******** The SYNC input channel is fixed. ********
//
GSYC_ANA_CHANNEL
// Sync channel other than video in monochrome via RGB
enable = ENABLE[( ! ( ( VDC_RGB_COL & SYC_SEP ) | VDC_SVID ) )] ;
//
eo_param
//
//
//..............................
// ******** Sync channel same as video in monochrome via RGB ********
//enable = ENABLE[( ! ( ( ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) & SYC_SEP ) | VDC_SVID ) )] ;
// --------------------------------------
//
GVDT_STANDARD
//
pagelinks = GVDC_VID_SIGNAL_STD.UPDATE + GVDL_PEDESTAL.UPDATE ;
//
valid = ( DEF_DEC_PATH & VDL_PEDEST & DEF_NTSC ? ADDERROR[ERR_FIXE_PEDESTAL_AMPL] :
( ( DEF_DEC_PATH & VDL_PEDEST & DEF_PAL ) ? ADDERROR[ERR_NO_PEDESTAL_AMPL] : 0 )
) ;
//
error_message
ERR_FIXE_PEDESTAL_AMPL, "Decoder automatically adjusts pedestal amplitude: Use default setting."
ERR_NO_PEDESTAL_AMPL, "Pedestal NOT present in Pal & Secam. Use default setting."
eo_error_message
//
eo_param
// --------------------------------------
//
GVDC_VID_SIGNAL_TYPE
//
pagelinks = GSYC_FORMAT ;
//
eo_param
// --------------------------------------
// ******** The following 2 equations are use to manage ********
// ******** the input channel boxes in Y/C mode. This was ********
// ******** not supported by intellicam... ********
//
GVDC_VID_SIGNAL_STD
//
pagelinks = ( GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ) ;
//
valid = ( ( DEF_MONO_VIA_RGB & VDC_IN_CH3 ) ? ADDERROR[ERR_VIDEO_NOT_AV_CH3] : 0 ) ;
//
error_message
ERR_VIDEO_NOT_AV_CH3, "Monochrome video input not available on channel 3 on RGB path: Select input 0, 1, or 2."
eo_error_message
//
eo_param
//
//
//..............................
//pagelinks = ( ( VDC_SVID & VDC_IN_CH0 ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] ) :
// ( ( VDC_SVID & VDC_IN_CH1 ) ? VDC_IN_CH0.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH2 ) ? VDC_IN_CH3.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH3 ) ? VDC_IN_CH2.SETVALUE[1] :
// 1 ) ) )
// ) + GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ;
// --------------------------------------
//
GVDC_ANA_VID_CH
//
pagelinks = (
( VDC_SVID * VDC_IN_CH0 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( VDC_SVID * VDC_IN_CH1 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( VDC_SVID * VDC_IN_CH2 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[1] ) :
( ( VDC_SVID * VDC_IN_CH3 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[1] ) : 0 ) ) )
) + GSYC_ANA_TYPE.UPDATE + GVDC_VID_SIGNAL_STD.UPDATE ;
//
valid = (
( ( VDC_MONO | VDC_C_COLOR ) *
( ( VDC_IN_CH0 & VDC_IN_CH1 ) | ( VDC_IN_CH1 & VDC_IN_CH2 ) | ( VDC_IN_CH2 & VDC_IN_CH3 ) | ( VDC_IN_CH0 & VDC_IN_CH1 & VDC_IN_CH2 ) )
) ?
( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( ( VDC_MONO | VDC_C_COLOR ) * ( VDC_IN_CH1 | VDC_IN_CH2 | VDC_IN_CH3 ) * DEF_MORPHIS ) ?
ADDERROR[ERR_MORPHIS_IN_CH_MONO_COLOR] :
( ( VDC_SVID * ( VDC_IN_CH2 | VDC_IN_CH3 ) * DEF_MORPHIS ) ?
ADDERROR[ERR_MORPHIS_IN_CH_SVID] :
( ( VDC_RGB_COL * ( VDC_IN_CH0 | VDC_IN_CH1 | VDC_IN_CH2 ) * ( ! DEF_MORPHIS ) ) ?
( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
( ( VDC_MONO * GRB_RGB_PATH_FORCED * VDC_IN_CH3 * ( ! DEF_MORPHIS ) ) ? ADDERROR[ERR_VIDEO_NOT_AV_CH3] :
0 ) ) ) )
) ;
//
error_message
ERR_VIDEO_NOT_AV_CH3, "Video NOT Available on Input Channel 3 in monochrome by RGB Path. Select Input 0-2."
ERR_MORPHIS_IN_CH_MONO_COLOR, "When dealing with monochrome or color composite, use MdigChannel() to change Input channels 1-3. Only Input channel 0 should be set in the DCF."
ERR_MORPHIS_IN_CH_SVID, "When dealing with S-Video YC, use MdigChannel() to change Input channels 2 and 3. Only Input channels 0 and 1 should be set in the DCF."
eo_error_message
//
eo_param
//
//
//
//
// .............................
//valid = ( ( VDC_SVID & VDC_IN_CH0 ) ? VDC_IN_CH1.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH1 ) ? VDC_IN_CH0.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH2 ) ? VDC_IN_CH3.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH3 ) ? VDC_IN_CH2.SETVALUE[1] :
// ( ( VDC_RGB_COL & ( VDC_IN_CH0 | VDC_IN_CH1 | VDC_IN_CH2 ) ) ?
// ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_MONO | VDC_C_COLOR ) &
// ( ( VDC_IN_CH0 & VDC_IN_CH1 ) | ( VDC_IN_CH2 & VDC_IN_CH3 ) | ( VDC_IN_CH0 & VDC_IN_CH1 & VDC_IN_CH2 ) )
// ) ?
// ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( VDC_MONO & GRB_RGB_PATH_FORCED & VDC_IN_CH3 ) ? ADDERROR[ERR_VIDEO_NOT_AV_CH3] :
// 1 ) ) ) ) ) ) & ( ( ! VDC_SVID ) & DAT_ERROR )
// ) ;
// --------------------------------------
GSYC_FORMAT
//
pagelinks = GVDC_VID_SIGNAL_TYPE ;
//
eo_param
//
//
//..............................
//valid = ( SYC_DIG & DEF_DEC_PATH ) ? ADDERROR[ERR_NO_DIGITAL_SYNC_AV] : 0 ;
//error_message
//ERR_NO_DIGITAL_SYNC_AV, "Digital synchronization not available by the Decoder path."
//eo_error_message
// --------------------------------------
//
// ******** Round the PCK_FREQ at 4 Decimals ********
//
GPCK_FREQUENCY
//
valid = (
( ( PCK_FREQ & 0xffff00 ) != 12272384 ) & ( ( PCK_FREQ & 0xffff00 ) != 14749952 ) ? ADDERROR[ERR_STD_PCK_FREQ] :
0
) ;
//
error_message
ERR_STD_PCK_FREQ, "Digitizer supports standard pixel clock frequencies only: Use 12.2726Hz (RS170/NTSC) or 14.75Hz (CCIR/PAL)."
eo_error_message
//
eo_param
//
//
//..............................
//valid = (
// ( ( ( PCK_FREQ & 0xffff00 ) != 12272384 ) & ( ( PCK_FREQ & 0xffff00 ) != 14749952 ) & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) ) ? ADDERROR[ERR_STD_PCK_FREQ] :
// ( ( ( PCK_FREQ < 1562500 ) & SYC_ANA & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_NG_PCLK_MIN] :
// ( ( ( PCK_FREQ < 87500 ) & SYC_DIG & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_SYCDIG_PCLK_MIN] : 0 ) )
// ) ;
// --------------------------------------
//
GVDT_TYPE
//
valid = ( VDT_NINTRL ? ADDERROR[ERR_NO_PROG_VID_AV] : 0 ) ;
//
error_message
ERR_NO_PROG_VID_AV, "Non-interlaced video not supported by the digitizer."
eo_error_message
//
eo_param
// --------------------------------------
//
GVDL_USE_DEFAULT
//
valid = ( ( ! ( VDL_USE_DEFVAL ) ) & DEF_MONO_VIA_DEC ) ? ADDERROR[ERR_VDL_USE_DEFVAL] : 0 ;
//
error_message
ERR_VDL_USE_DEFVAL, "Control of video voltage swing, pedestal, and references not available: Use defaults."
eo_error_message
//
eo_param
//
//
//..............................
//valid = ( ( ! ( VDL_USE_DEFVAL ) ) & DEF_DEC_PATH & ( ! VDC_C_COLOR ) ) ? ADDERROR[ERR_VDL_USE_DEFVAL] : 0 ;
// --------------------------------------
//
GVDC_ANA_VID_C_CH
//
eo_param
// --------------------------------------
//
GVDL_PEDESTAL
//
pagelinks = GVDT_STANDARD.VALID ;
//
enable = ENABLE[( DEF_RGB_PATH * ( DEF_MONO_VIA_RGB | VDC_RGB_COL ) * ( ! VDL_USE_DEFVAL ) )] ;
//
eo_param
// --------------------------------------
//
GVDL_AMPLITUDE
//
enable = ENABLE[( DEF_RGB_PATH * ( DEF_MONO_VIA_RGB | VDC_RGB_COL ) * ( ! VDL_USE_DEFVAL ) )] ;
//
valid = (
( DEF_RGB_PATH & DEF_ORION & ( VDL_AMPL < 120 ) ) ? ADDERROR[ERR_TOO_SMALL_AMPLITUDE_ORION_AV] :
( ( DEF_RGB_PATH & DEF_4SIGHT & ( VDL_AMPL < 350 ) ) ? ADDERROR[ERR_TOO_SMALL_AMPLITUDE_4SIGHT_AV] :
( ( DEF_DEC_PATH & ( VDL_AMPL != 700 ) ) ? ADDERROR[ERR_VIDEO_AMPL] : 0 ) )
) ;
//
error_message
ERR_TOO_SMALL_AMPLITUDE_ORION_AV, "Minimum video voltage swing available is 120mV."
ERR_TOO_SMALL_AMPLITUDE_4SIGHT_AV, "Minimum video voltage swing available is 350mV."
ERR_VIDEO_AMPL, "Decoder automatic gain control enabled. Use default video voltage swing of 700 mV."
eo_error_message
//
eo_param
//
//
//..............................
//valid = (
// ( DEF_RGB_PATH & ( VDL_AMPL < 120 ) ) ? ADDERROR[ERR_TOO_SMALL_AMPLITUDE_AV] :
// ( ( DEF_DEC_PATH & ( VDL_AMPL != 700 ) ) ? ADDERROR[ERR_VIDEO_AMPL] : 0 )
// ) ;
// --------------------------------------
//
GVDL_SWING
//
enable = ENABLE[( DEF_RGB_PATH * ( DEF_MONO_VIA_RGB | VDC_RGB_COL ) * ( ! VDL_USE_DEFVAL ) )] ;
//
valid = ( ( ! VDL_POS_SWG ) ? ADDERROR[ERR_FIXED_VOLTSWG] : 0 ) ;
//
error_message
ERR_FIXED_VOLTSWG,"Negative and both voltage swing not available. Use Positive voltage swing."
eo_error_message
//
eo_param
//
//
//..............................
//enable = ENABLE[0] ;
// --------------------------------------
//
GVDL_BRIGHTNESS
//
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
//
eo_param
//
//
//..............................
//enable = ENABLE[0] ;
// --------------------------------------
//
GVDL_CONTRAST
//
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
//
eo_param
//
//
//..............................
//enable = ENABLE[0] ;
// --------------------------------------
//
GVDL_SATURATION
//
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
//
eo_param
//
//
//..............................
//enable = ENABLE[0] ;
// --------------------------------------
//
GVDL_HUE
//
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
//
eo_param
//
//
//..............................
//enable = ENABLE[0] ;
// --------------------------------------
//
GEXP_GEN_MODE
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
GEXP_GEN_MODE_2
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
// ******** Si HEPVAL > HTOTAL => Erreur en cours ! ********
//
GVDT_HORIZONTAL
// Add error message for HS changed by RGB Path with Orion_4SightII_RGB Module
valid = (
DEF_HCLAMP_HBP_MIN ? ADDERROR[ERR_HCLAMP_MIN_VALUE] :
( ( OPTION_4SIGHT_II_RGB & DEF_RGB_PATH & ( VDT_HSYNC != ( 58 + ( DEF_PAL * 11 ) ) ) ) ? ADDERROR[ERR_HS_CHANGED_VALUE] :
( DEF_HCLAMP_HBP_DEF_MIN ? ADDERROR[ERR_HCLAMP_DEF_MIN_VALUE] :
( DEF_HS_HBP_HFP_ZERO ? ADDERROR[ERR_HOR_NEGATIVE_VALUE] :
( DEF_HBPORCH_MAX ? ADDERROR[ERR_HBPORCH_MAX] :
( DEF_HBPORCH_MIN ? ADDERROR[ERR_HBPORCH_MIN] :
( DEF_MORPHIS_NO_HCROP ? ADDERROR[ERR_MORPHIS_NO_H_CROP] :
( (
( ( ( VDT_HACTIVE != 640 ) * DEF_NTSC ) | ( ( VDT_HACTIVE != 768 ) & DEF_PAL ) ) *
( DEF_4SIGHT | DEF_MORPHIS )
) ? ADDERROR[ERR_HACTIVE_VALUE] :
( ( DEF_HTOTAL_IN_NOTSTD & DEF_NTSC ) ? ADDERROR[ERR_NOT_HVTOTAL_60HZ_VALUE] :
( ( DEF_HTOTAL_IN_NOTSTD & DEF_PAL ) ? ADDERROR[ERR_NOT_HVTOTAL_50HZ_VALUE] :
0 ) ) ) ) ) ) ) ) )
) ;
//
error_message
ERR_HCLAMP_MIN_VALUE, "Minimum clamping reached. Increase horizontal back porch."
ERR_HCLAMP_DEF_MIN_VALUE, "Minimum clamping reached. Decrease horizontal front porch."
ERR_HBPORCH_MAX, "Maximum horizontal sync or back porch reached. Decrease one or the other."
ERR_HBPORCH_MIN, "Minimum horizontal sync or back porch reached. Increase one or the other."
ERR_MORPHIS_NO_H_CROP, "The Horizontal Video Timing values are not available with Matrox Morphis."
ERR_HOR_NEGATIVE_VALUE, "Maximum value reached. Decrease value."
ERR_NOT_HVTOTAL_60HZ_VALUE, "Total horizontal pixels must be 780 with 640 active pixels in NTSC: Readjust total or active horizontal pixel settings."
ERR_NOT_HVTOTAL_50HZ_VALUE, "Total horizontal pixels must be 944 with 768 active pixels in PAL: Readjust total or active horizontal pixel settings."
ERR_HACTIVE_VALUE, "Active horizontal pixels must be 640 in NTSC or 768 in PAL."
ERR_HORCROPPING_VALUE, "Horizontal cropping should be in steps of 2 pixels."
ERR_HS_CHANGED_VALUE, "Horizontal synchronization must be adjusted: Set value to 58 in NTSC or 69 in PAL."
eo_error_message
//
eo_param
//
//
//..............................
//valid = (
// DEF_HCLAMP_HBP_MIN ? ADDERROR[ERR_HCLAMP_MIN_VALUE] :
// ( ( OPTION_4SIGHT_II_RGB & DEF_RGB_PATH & ( VDT_HSYNC != ( 58 + ( DEF_PAL * 11 ) ) )
// ) ? ADDERROR[ERR_HS_CHANGED_VALUE] :
// ( DEF_HCLAMP_HBP_DEF_MIN ? ADDERROR[ERR_HCLAMP_DEF_MIN_VALUE] :
// ( DEF_HS_HBP_HFP_ZERO ? ADDERROR[ERR_HOR_NEGATIVE_VALUE] :
// ( DEF_HBPORCH_MAX ? ADDERROR[ERR_HBPORCH_MAX] :
// ( (
// (
// ( ( VDT_HACTIVE != 640 ) & DEF_NTSC ) | ( ( VDT_HACTIVE != 768 ) & DEF_PAL ) ) & DEF_4SIGHT
// ) ? ADDERROR[ERR_HACTIVE_VALUE] :
// ( ( DEF_HTOTAL_IN_NOTSTD & DEF_NTSC ) ? ADDERROR[ERR_NOT_HVTOTAL_60HZ_VALUE] :
// ( ( DEF_HTOTAL_IN_NOTSTD & DEF_PAL ) ? ADDERROR[ERR_NOT_HVTOTAL_50HZ_VALUE] :
// 0 ) ) ) ) ) ) )
// ) ;
//valid = (
// DEF_HCLAMP_HBP_MIN ? ADDERROR[ERR_HCLAMP_MIN_VALUE] :
// ( DEF_HCLAMP_HBP_DEF_MIN ? ADDERROR[ERR_HCLAMP_DEF_MIN_VALUE] :
// ( DEF_HS_HBP_HFP_ZERO ? ADDERROR[ERR_HOR_NEGATIVE_VALUE] :
// ( DEF_HBPORCH_MAX ? ADDERROR[ERR_HBPORCH_MAX] :
// ( (
// (
// ( ( VDT_HACTIVE != 640 ) & DEF_NTSC ) | ( ( VDT_HACTIVE != 768 ) & DEF_PAL )
// ) & DEF_4SIGHT
// ) ? ADDERROR[ERR_HACTIVE_VALUE] :
// ( ( DEF_HTOTAL_IN_NOTSTD & DEF_NTSC ) ? ADDERROR[ERR_NOT_HVTOTAL_60HZ_VALUE] :
// ( ( DEF_HTOTAL_IN_NOTSTD & DEF_PAL ) ? ADDERROR[ERR_NOT_HVTOTAL_50HZ_VALUE] :
// 0 ) ) ) ) ) )
// ) ;
// --------------------------------------
//
GVDT_VERTICAL
//
pagelinks = GVDC_ANA_VID_CH.VALID + GSYC_ANA_TYPE.VALID + GPCK_FREQUENCY.VALID + GVDT_VERTICAL.UPDATE ;
//
// ******** Added Fixed Vertical Active for 4SightII_DUAL ONLY!!! ********
//
valid = (
( ( OPTION_4SIGHT_II_DUAL | OPTION_MORPHIS ) *
( VDT_VACTIVE != ( 480 + ( DEF_PAL * 96 ) ) )
) ? ADDERROR[ERR_VACTIVE_DUAL_NOT_STD_VALUE] :
( DEF_VACTIVE_ODD ? ADDERROR[ERR_ODD_VALUE] :
( ( ( VDT_VACTIVE > 522 ) & DEF_NTSC ) ? ADDERROR[ERR_VACTIVE_60HZ_MAX_VALUE] :
( ( ( VDT_VACTIVE > 620 ) & DEF_PAL ) ? ADDERROR[ERR_VACTIVE_50HZ_MAX_VALUE] :
( DEF_VS_VBP_MIN ? ADDERROR[ERR_VSVBP_MIN_VALUE] :
( DEF_VS_VBP_MAX ? ADDERROR[ERR_VSVBP_MAX_VALUE] :
( DEF_VS_VBP_VFP_ZERO ? ADDERROR[ERR_VERT_NEGATIVE_VALUE] :
( ( DEF_VTOTAL_IN_NOTSTD & DEF_NTSC ) ? ADDERROR[ERR_NOT_VTOTAL_60HZ_VALUE] :
( ( DEF_VTOTAL_IN_NOTSTD & DEF_PAL ) ? ADDERROR[ERR_NOT_VTOTAL_50HZ_VALUE] :
0 ) ) ) ) ) ) ) )
) ;
//
error_message
ERR_VACTIVE_DUAL_NOT_STD_VALUE, "Vertical Active value should be 480 in Ntsc and 576 in Pal."
ERR_ODD_VALUE, "Vertical active value should be EVEN."
ERR_VSVBP_MIN_VALUE, "Minimum vertical sync or back porch reached. Increase one or the other."
ERR_VSVBP_MAX_VALUE, "Maximum vertical sync or back porch reached. Decrease one or the other."
ERR_VERT_NEGATIVE_VALUE, "Maximum value reached. Decrease value."
ERR_NOT_VTOTAL_60HZ_VALUE, "Total vertical lines must be 525 in NTSC: Readjust total vertical line setting."
ERR_NOT_VTOTAL_50HZ_VALUE, "Total vertical lines must be 625 in PAL: Readjust total vertical line setting."
ERR_VACTIVE_60HZ_MAX_VALUE, "Maximum active vertical lines permitted is 522: Decrease value."
ERR_VACTIVE_50HZ_MAX_VALUE, "Maximum active vertical lines permitted is 620: Decrease value."
eo_error_message
//
eo_param
//
//
//..............................
//valid = (
// DEF_VACTIVE_ODD ? ADDERROR[ERR_ODD_VALUE] :
// ( ( ( VDT_VACTIVE > 522 ) & DEF_NTSC ) ? ADDERROR[ERR_VACTIVE_60HZ_MAX_VALUE] :
// ( ( ( VDT_VACTIVE > 620 ) & DEF_PAL ) ? ADDERROR[ERR_VACTIVE_50HZ_MAX_VALUE] :
// ( DEF_VS_VBP_MIN ? ADDERROR[ERR_VSVBP_MIN_VALUE] :
// ( DEF_VS_VBP_MAX ? ADDERROR[ERR_VSVBP_MAX_VALUE] :
// ( DEF_VS_VBP_VFP_ZERO ? ADDERROR[ERR_VERT_NEGATIVE_VALUE] :
// ( ( DEF_VTOTAL_IN_NOTSTD & DEF_NTSC ) ? ADDERROR[ERR_NOT_VTOTAL_60HZ_VALUE] :
// ( ( DEF_VTOTAL_IN_NOTSTD & DEF_PAL ) ? ADDERROR[ERR_NOT_VTOTAL_50HZ_VALUE] :
// 0 ) ) ) ) ) ) )
// ) ;
//valid = (
// DEF_DUAL_NO_VCROPPING_PAL ? ADDERROR[ERR_NO_VCROPPING_PAL_VALUE] :
// ( DEF_VACTIVE_ODD ? ADDERROR[ERR_ODD_VALUE] :
// ( ( ( VDT_VACTIVE > 522 ) & DEF_NTSC ) ? ADDERROR[ERR_VACTIVE_60HZ_MAX_VALUE] :
// ( ( ( VDT_VACTIVE > 620 ) & DEF_PAL ) ? ADDERROR[ERR_VACTIVE_50HZ_MAX_VALUE] :
// ( DEF_VS_VBP_MIN ? ADDERROR[ERR_VSVBP_MIN_VALUE] :
// ( DEF_VS_VBP_MAX ? ADDERROR[ERR_VSVBP_MAX_VALUE] :
// ( DEF_VS_VBP_VFP_ZERO ? ADDERROR[ERR_VERT_NEGATIVE_VALUE] :
// ( ( DEF_VTOTAL_IN_NOTSTD & DEF_NTSC ) ? ADDERROR[ERR_NOT_VTOTAL_60HZ_VALUE] :
// ( ( DEF_VTOTAL_IN_NOTSTD & DEF_PAL ) ? ADDERROR[ERR_NOT_VTOTAL_50HZ_VALUE] :
// 0 ) ) ) ) ) ) ) )
// ) ;
// --------------------------------------
//
GVDC_VID_WIDTH
//
eo_param
//
//
//..............................
//enable = ENABLE[( VDC_DIG )] ;
//valid = ( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) ) ? ADDERROR[ERR_BAD_BUS_WIDTH] :
// 0 ) ;
//board_specific_value
//"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV no|M_ARRAY_TWO
//"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV no|M_ARRAY_TWO
//"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV no|M_ARRAY_TWO
//"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV yes|M_ARRAY_TWO
//"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV yes|M_ARRAY_TWO
//"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV yes|M_ARRAY_TWO
//eo_board_specific_value
//error_message
//ERR_BAD_BUS_WIDTH, "8-bit bus width only with analog video signal."
//eo_error_message
// --------------------------------------
//
GGRB_TRG_SIGNAL
//
board_specific_value
"analog port trigger ( OPTO TRIG )" M_DEFAULT GRB_TRG_SIGNAL_APORT GRB_TRG_SIGNAL_APORT_AV yes
"digital port trigger ( TTL TRIG )" M_DEFAULT GRB_TRG_SIGNAL_DPORT GRB_TRG_SIGNAL_DPORT_AV yes
"external hsync of digital port" M_DEFAULT GRB_TRG_SIGNAL_HSDPORT GRB_TRG_SIGNAL_HSDPORT_AV no
"external vsync of digital port" M_DEFAULT GRB_TRG_SIGNAL_VSDPORT GRB_TRG_SIGNAL_VSDPORT_AV no
"timer 1 output" M_DEFAULT GRB_TRG_SIGNAL_TIMER1 GRB_TRG_SIGNAL_TIMER1_AV no
"timer 2 output" M_DEFAULT GRB_TRG_SIGNAL_TIMER2 GRB_TRG_SIGNAL_TIMER2_AV no
eo_board_specific_value
//
eo_param
//
//
//..............................
//pagelinks = GGRB_TRG_FORMAT + GEXP_TRG_SIGNAL ;
//valid = (
// (
// ( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & ( ! ( GRB_MD_CONT ) ) &
// ( ( ( EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 ) & GRB_TRG_SIGNAL_APORT ) |
// ( ( EXP_MD_EXT | EXP_MD_EXT_2 ) & GRB_TRG_SIGNAL_DPORT )
// )
// ) |
// ( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & GRB_MD_CONT &
// ( EXP_TRG_TTL_TIMER1 & EXP_MD_EXT_2 ) | ( EXP_TRG_TTL_TIMER2 & EXP_MD_EXT )
// )
// ) ? ADDERROR[ERR_FORMAT_TRIGGER] :
// ( ( GRB_TRG_SIGNAL_APORT & GRB_TRG_422 ) ? ADDERROR[ERR_FORMAT_OPTO] : 0 )
// ) ;
// error_message
// ERR_FORMAT_TRIGGER, "Only one Hardware Trigger Format available at once : OPTO or TTL Trigger"
// ERR_FORMAT_OPTO, "Only TTL Format available with OPTO Trigger"
// eo_error_message
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #3: COMMON BOARD LIMITATION
// **********************************************
// **********************************************
//
//
[COMMON_OPTIONS]
//
// =============================================
//
// ******** Camera type ********
//
CT_LINE_SCAN_AVAIL no
CT_FRAM_SCAN_AVAIL yes
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 1 1 1 0 0 1 1
CT_MAX_CAMERA array 1 1 1 0 0 1 1
// ana dig
CT_MAX_CONNECTORS array 3 3
//
// --------------------------------------
//
// ******** Video signal format (analog/digital) ********
//
YUVVID_AVAIL no
YUV_INPUT_AVAIL no
CHROMI_IN_AVAIL no
// ** Information on clamping position available
CLAMP_SYNC_AVAIL no
CLAMP_BPORCH_AVAIL yes
CLAMP_FPORCH_AVAIL no
//
// --------------------------------------
//
// ******** Video timing ********
//
VID_STD_RS170_PCLK 12272600
VID_STD_RS170_HORZ array 58 60 22 640
//Change for start on ODD Field (First field of Frame)
VID_STD_RS170_VERT array 6 33 6 480
VID_STD_CCIR_PCLK 14750000
VID_STD_CCIR_HORZ array 69 85 22 768
VID_STD_CCIR_VERT array 5 42 2 576
//
//VID_STD_CCIR_VERT array 5 41 3 576
//
// --------------------------------------
//
// ******** Pixel clock ********
//
//PCLK_IN_POS_POL_AV no
//PCLK_IN_NEG_POL_AV no
//PCLK_OUT_POS_POL_AV no
//PCLK_OUT_NEG_POL_AV no
//HIGH_SPEED_GRAB no
//
// --------------------------------------
//
// ******** Synchronisation signal ********
//
// ** Serration & equalization available on csync pulse
VDT_SERRATION_AVAIL no
VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_CAM_LATENCY_AV no
SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_C_IN_AV no
SYC_DIG_C_OUT_AV no
//
CSYN_IN_TTL_AV no
CSYN_IN_RS422_AV no
CSYN_OUT_TTL_AV no
CSYN_OUT_RS422_AV no
CSYN_IN_POS_POL_AV no
CSYN_IN_NEG_POL_AV no
CSYN_OUT_NEG_POL_AV no
CSYN_OUT_POS_POL_AV no
//
// ** Info about availability of analog csync separate from video signal,
// based on the video type signal. (to reflect the Bt812 limitation)
//
SYC_ASEP_O_MONO_AV equ
value = DEF_MONO_VIA_RGB ;
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//
// ** Information on sync. signal that must have the same direction **
// (both generated or both received, not one received other generated)
SYC_HVC_SAME_FORMAT yes
SYC_HS&VS_MUST_SDIR yes
SYC_HS&CS_MUST_SDIR yes
SYC_VS&CS_MUST_SDIR yes
//
// ** Information if a sync. signal may be in and out at the same time.
//
SYC_HSY_MAY_I&O no
SYC_VSY_MAY_I&O no
SYC_CSY_MAY_I&O no
SYC_ANAL_O_DIGVID_AV no
//
// --------------------------------------
//
// ******** Exposure ********
//
// ** Exposure asynchronous clock signal information **
EXP_ASY_CLK_AV no
//
// ** Asynchr. clock frequency (in Hz) ** USERCLK
EXP_ASY_CLK_FREQ 25000000
//
EXP_ASY_CLK_AV_2 no
//
// ** Asynchr. clock frequency (in Hz) ** USERCLK
EXP_ASY_CLK_FREQ_2 25000000
//
//
//EXP_CLOCK_HSYNC_AV no
//value = VDT_HSYNC_FREQ ;
//EXP_CLOCK_2_HSYNC_AV no
//value = VDT_HSYNC_FREQ ;
//EXP_CLOCK_TIMER2_AV no
//value = ( EXP_CLOCK_TIMER2 * ( 1 / ( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) * ( 1 / EXP_CLK_FREQ_2 ) ) ) ) || 1 ;
//EXP_CLOCK_2_TIMER1_AV equ
//value = ( EXP_CLOCK_2_TIMER1 * ( 1 / ( ( EXP_OUT_T0 + EXP_OUT_T1 ) * ( 1 / EXP_CLK_FREQ ) ) ) ) || 1 ;
//
//EXP_SYN_CLK_MAX_FREQ 30000000
EXP_CLK_DVED_AV no
EXP_CLK_DVED_AV_2 no
EXP_CLK_MAXDIV_FACT 1
//EXP_DELYED_FR_TRG_AV yes
//EXP_TIMER_MAX_VALUE 0xffff
//EXP_TIMER_MIN_VALUE 0
//EXP_CHK_MAXSUM_PERD no
//EXP_CHK_MAXSUM_DEL no
//EXP_CHK_MAXSUM_NDEL no
//EXP_CHK_MAXSUM_PERD yes
//EXP_CHK_MAXSUM_DEL yes
//EXP_CHK_MAXSUM_NDEL yes
//EXP_NDEL_TRG_TTL_AV yes
//EXP_NDEL_TRG_422_AV yes
//EXP_DEL_TRG_TTL_AV yes
//EXP_DEL_TRG_422_AV yes
//EXP_NDEL_OUT_TTL_AV yes
//EXP_NDEL_OUT_422_AV yes
//EXP_DEL_OUT_TTL_AV yes
//EXP_DEL_OUT_422_AV yes
//EXP_MD_PERD_AV yes
//EXP_MD_WITH_TRG_AV_2 yes
//EXP_MD_PERD_AV_2 yes
//EXP_MD_WITH_TRG_AV yes
//EXP_PERD_CLKDVED_AV no
//EXP_DEL_CLKDVED_AV no
//EXP_NDEL_CLKDVED_AV no
//EXP_TEX_CLKDVED_AV no
//EXP_THSY_CLKDVED_AV no
//EXP_TVSY_CLKDVED_AV no
//EXP_TSW_CLKDVED_AV no
//EXP_PERD_CLKDVED_AV_2 no
//EXP_DEL_CLKDVED_AV_2 no
//EXP_NDEL_CLKDVED_AV_2 no
//EXP_TEX_CLKDVED_AV_2 no
//EXP_THSY_CLKDVED_AV_2 no
//EXP_TVSY_CLKDVED_AV_2 no
//EXP_TSW_CLKDVED_AV_2 no
//
// --------------------------------------
//
// ******** none classified board options ********
//
//
SYC_ANA_IN_CH_AV array 1 1 1 1
RS_330_SUPPORTED no
VACTIVE_INTERL_EVEN no
//
// ** horizontal & vertical absolute maximum value **
// (be sure to give an absolute maximum, so keep a margin of safety
// from the maximum value found in the HW registers.)
// (Intellicam absolute maximum of 0xffffffff)
//
VDT_HORIZ_MAX_VAL 0x1000
VDT_VERT_MAX_VAL 0x1000
//
// ** Minimum timings state value (in pixel count)
// (based on HW limitation, pipeline, line buffer etc...)
//
VDT_HSY_CNT_MIN 0
VDT_HBP_CNT_MIN 0
VDT_HACT_CNT_MIN 0
VDT_HFP_CNT_MIN 0
VDT_HSY+HBP_CNT_MIN 0
VDT_VSY_CNT_MIN 0
VDT_VBP_CNT_MIN 0
VDT_VACT_CNT_MIN 0
VDT_VFP_CNT_MIN 0
VDT_VSY+VBP_CNT_MIN 0
//
// ** Vertical active value that must be a multiple value, based on
// the video type signal. analog digital
//--> Where does ON_DIG comes from????
//--> Other signal type as CCOL, RGB, SVID, YUV
VACT_MULTV_ON_DIG 1
VACT_MULTV_ON_MONO array 1 1
VACT_MULTV_ON_MONOHI array 1 1
//
// ** Horizontal active value that must be a multiple value, based on
// the video type signal.
HACT_MULTV_ON_DIG 1
HACT_MULTV_ON_MONO array 1 1
HACT_MULTV_ON_MONOHI array 1 1
//
VTOT_ARR_ON_MONO no
VTOT_ARR_ON_CCOL array 525 625
VTOT_ARR_ON_RGB no
VTOT_ARR_ON_SVID no
VTOT_ARR_ON_YUV no
VTOT_ARR_ON_MONOHI no
CLAMP_TIMING_MIN array 250 750 275
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #4: BOARD LIMITATION DESCRIPTION (A)
// **********************************************
// **********************************************
//
//
[OPTION]
ORION
//
// Board Type ORION
//
OPTION yes
OPTION_4SIGHT_II_STD no
OPTION_4SIGHT_II_RGB no
OPTION_4SIGHT_II_DUAL no
OPTION_MORPHIS no
//
// =============================================
// ORION
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
//
// RGB Path removed for Release !
//GRB_RGB_PATH_FORCED_AV no
GRB_RGB_PATH_FORCED_AV yes
//
MONO_VID_AVAIL array 1 0
//
// RGB Path removed for Release !
//RGB_COL_VID_AVAIL array 0 0
RGB_COL_VID_AVAIL array 1 1
//
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
//ANA_VID_AMPL_LIMIT array 300 1999 => 300mV for MET2/MC limit sync detect
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// ORION
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 1000 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
//PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO no
PCLK_OUT_AV_O_CCOL no
PCLK_OUT_AV_O_RGB no
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI no
//
// --------------------------------------
// ORION
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM no
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_V_OUT_AV no
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV no
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_IN_POS_POL_AV no
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
//
// --------------------------------------
// ORION
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_HSDPORT_AV no
GRB_TRG_SIGNAL_VSDPORT_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
// --------------------------------------
// ORION
// ******** Exposure control ********
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV no
//
//EXP_ASY_CLK_AV_2 no
//
//EXP_CLOCK_HSYNC_AV no
//
//EXP_CLOCK_2_HSYNC_AV no
//
//EXP_CLOCK_TIMER2_AV no
//
//EXP_CLOCK_2_TIMER1_AV no
//
//EXP_TRG_TTL_TIMER1_AV no
//EXP_TRG_TTL_TIMER2_AV no
//EXP_NDEL_TRG_422_AV no
//EXP_DEL_TRG_422_AV no
//EXP_NDEL_OUT_422_AV no
//EXP_DEL_OUT_422_AV no
//EXP_NDEL_TRG_422_AV_2 no
//EXP_DEL_TRG_422_AV_2 no
//EXP_NDEL_OUT_422_AV_2 no
//EXP_DEL_OUT_422_AV_2 no
//
//
// =============================================
//
//
[OPTION_4SIGHT_II_DUAL]
ORION_4SIGHT_II_DUAL
//
// Board Type ORION_4SIGHT_II_DUAL
//
OPTION_4SIGHT_II_DUAL yes
OPTION no
OPTION_4SIGHT_II_STD no
OPTION_4SIGHT_II_RGB no
OPTION_MORPHIS no
//
// =============================================
//
// ORION/4SIGHT/DUAL
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
//
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 0 0
//
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 350 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
//
// ORION/4SIGHT/DUAL
//
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 1000 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
//PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO no
PCLK_OUT_AV_O_CCOL no
PCLK_OUT_AV_O_RGB no
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI no
//
// --------------------------------------
//
// ORION/4SIGHT/DUAL
//
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM no
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV no
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_V_OUT_AV no
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV no
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_IN_POS_POL_AV no
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
//
// --------------------------------------
//
// ORION/4SIGHT/DUAL
//
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_HSDPORT_AV no
GRB_TRG_SIGNAL_VSDPORT_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
// --------------------------------------
//
// ORION/4SIGHT/DUAL
//
// ******** Exposure control ********
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV no
//
//EXP_ASY_CLK_AV_2 no
//
//EXP_CLOCK_HSYNC_AV no
//
//EXP_CLOCK_2_HSYNC_AV no
//
//EXP_CLOCK_TIMER2_AV no
//
//EXP_CLOCK_2_TIMER1_AV no
//
//EXP_TRG_TTL_TIMER1_AV no
//EXP_TRG_TTL_TIMER2_AV no
//EXP_NDEL_TRG_422_AV no
//EXP_DEL_TRG_422_AV no
//EXP_NDEL_OUT_422_AV no
//EXP_DEL_OUT_422_AV no
//EXP_NDEL_TRG_422_AV_2 no
//EXP_DEL_TRG_422_AV_2 no
//EXP_NDEL_OUT_422_AV_2 no
//EXP_DEL_OUT_422_AV_2 no
//
//
// =============================================
//
//
[OPTION_4SIGHT_II_RGB]
ORION_4SIGHT_II_RGB
//
// Board Type : ORION_4SIGHT_II_RGB
//
OPTION_4SIGHT_II_RGB yes
OPTION no
OPTION_4SIGHT_II_STD no
OPTION_4SIGHT_II_DUAL no
OPTION_MORPHIS no
//
// =============================================
//
// ORION_4SIGHT_II_RGB
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV yes
//
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 0
//
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 350 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
//
// ORION_4SIGHT_II_RGB
//
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 1000 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
//PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO no
PCLK_OUT_AV_O_CCOL no
PCLK_OUT_AV_O_RGB no
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI no
//
// --------------------------------------
//
// ORION_4SIGHT_II_RGB
//
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM no
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_V_OUT_AV no
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV no
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_IN_POS_POL_AV no
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
//
// --------------------------------------
//
// ORION_4SIGHT_II_RGB
//
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_HSDPORT_AV no
GRB_TRG_SIGNAL_VSDPORT_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
// --------------------------------------
//
// ORION_4SIGHT_II_RGB
//
// ******** Exposure control ********
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV no
//
//EXP_ASY_CLK_AV_2 no
//
//EXP_CLOCK_HSYNC_AV no
//
//EXP_CLOCK_2_HSYNC_AV no
//
//EXP_CLOCK_TIMER2_AV no
//
//EXP_CLOCK_2_TIMER1_AV no
//
//EXP_TRG_TTL_TIMER1_AV no
//EXP_TRG_TTL_TIMER2_AV no
//EXP_NDEL_TRG_422_AV no
//EXP_DEL_TRG_422_AV no
//EXP_NDEL_OUT_422_AV no
//EXP_DEL_OUT_422_AV no
//EXP_NDEL_TRG_422_AV_2 no
//EXP_DEL_TRG_422_AV_2 no
//EXP_NDEL_OUT_422_AV_2 no
//EXP_DEL_OUT_422_AV_2 no
//
//
// =============================================
//
//
[OPTION_4SIGHT_II_STD]
ORION_4SIGHT_II_STD
//
// Board Type : ORION_4SIGHT_II_STD
OPTION_4SIGHT_II_STD yes
OPTION no
OPTION_4SIGHT_II_RGB no
OPTION_4SIGHT_II_DUAL no
OPTION_MORPHIS no
//
// =============================================
//
// ORION_4SIGHT_II_STD
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
//
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 0 0
//
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 350 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
//
// ORION_4SIGHT_II_STD
//
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 1000 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
//PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO no
PCLK_OUT_AV_O_CCOL no
PCLK_OUT_AV_O_RGB no
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI no
//
// --------------------------------------
//
// ORION_4SIGHT_II_STD
//
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM no
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV no
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_V_OUT_AV no
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV no
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_IN_POS_POL_AV no
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
//
// --------------------------------------
//
// ORION_4SIGHT_II_STD
//
// ******** Grab Control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_HSDPORT_AV no
GRB_TRG_SIGNAL_VSDPORT_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
// --------------------------------------
//
// ORION_4SIGHT_II_STD
//
// ******** Exposure ********
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV no
//
//EXP_ASY_CLK_AV_2 no
//
//EXP_CLOCK_HSYNC_AV no
//
//EXP_CLOCK_2_HSYNC_AV no
//
//EXP_CLOCK_TIMER2_AV no
//
//EXP_CLOCK_2_TIMER1_AV no
//
//EXP_TRG_TTL_TIMER1_AV no
//EXP_TRG_TTL_TIMER2_AV no
//EXP_NDEL_TRG_422_AV no
//EXP_DEL_TRG_422_AV no
//EXP_NDEL_OUT_422_AV no
//EXP_DEL_OUT_422_AV no
//EXP_NDEL_TRG_422_AV_2 no
//EXP_DEL_TRG_422_AV_2 no
//EXP_NDEL_OUT_422_AV_2 no
//EXP_DEL_OUT_422_AV_2 no
//
// =============================================
//
//
[OPTION_MORPHIS]
MORPHIS
//
// Board Type MORPHIS
//
OPTION no
OPTION_4SIGHT_II_STD no
OPTION_4SIGHT_II_RGB no
OPTION_4SIGHT_II_DUAL no
OPTION_MORPHIS yes
//
// =============================================
// MORPHIS
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
//
// RGB Path removed for Release !
//GRB_RGB_PATH_FORCED_AV no
GRB_RGB_PATH_FORCED_AV yes
//
MONO_VID_AVAIL array 1 0
//
// RGB Path removed for Release !
RGB_COL_VID_AVAIL array 0 0
//
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
//ANA_VID_AMPL_LIMIT array 300 1999 => 300mV for MET2/MC limit sync detect
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// MORPHIS
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 1000 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
//PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO no
PCLK_OUT_AV_O_CCOL no
PCLK_OUT_AV_O_RGB no
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI no
//
// --------------------------------------
// MORPHIS
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM no
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_V_OUT_AV no
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV no
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_IN_POS_POL_AV no
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
//
// --------------------------------------
// MORPHIS
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_HSDPORT_AV no
GRB_TRG_SIGNAL_VSDPORT_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
// --------------------------------------
// MORPHIS
// ******** Exposure control ********
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV no
//
//EXP_ASY_CLK_AV_2 no
//
//EXP_CLOCK_HSYNC_AV no
//
//EXP_CLOCK_2_HSYNC_AV no
//
//EXP_CLOCK_TIMER2_AV no
//
//EXP_CLOCK_2_TIMER1_AV no
//
//EXP_TRG_TTL_TIMER1_AV no
//EXP_TRG_TTL_TIMER2_AV no
//EXP_NDEL_TRG_422_AV no
//EXP_DEL_TRG_422_AV no
//EXP_NDEL_OUT_422_AV no
//EXP_DEL_OUT_422_AV no
//EXP_NDEL_TRG_422_AV_2 no
//EXP_DEL_TRG_422_AV_2 no
//EXP_NDEL_OUT_422_AV_2 no
//EXP_DEL_OUT_422_AV_2 no
//
//
// =============================================
//
//
// ********************************************
// ********************************************
// SECTION #5: DEFINE VALUES
// ********************************************
// ********************************************
//
//
[DEFINE_VALUE]
//
// =============================================
// N.B.
// DEF utilisant un autre DEF doit etre toujours place apres ce DEF utilise dans son equation
// Raison : Valeur du DEF doit etre update
// --------------------------------------
//
// ******** Board Type group ********
//
DEF_ORION
value = OPTION ;
// --------------------------------------
DEF_4SIGHT
value = ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_RGB | OPTION_4SIGHT_II_DUAL ) ;
// --------------------------------------
DEF_MORPHIS
value = OPTION_MORPHIS ;
// --------------------------------------
// ******** Video Input Selected ********
//
DEF_INFO_INPUT
value = (
(
( ( VDC_IN_CH2 || VDC_IN_CH3 ) & SYC_COMP & VDC_SVID ) ||
( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH1 ) ||
( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 1 ) ) ||
( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 1 ) )
) ? 3 :
( (
( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH2 ) ||
( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 2 ) ) ||
( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 2 ) )
) ? 1 :
( (
( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH3 ) ||
( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 3 ) ) ||
( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 3 ) ) ||
( VDC_RGB_COL & SYC_SEP )
) ? 4 :
0 ) )
) ;
//
//
// .............................
//value = (
// ( ( ( VDC_IN_CH2 || VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ) ? 1 :
// ( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ? 2 :
// ( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
// 0 ) )
// ) ;
// --------------------------------------
// ******** Set Black Level for A/D ********
DEF_DAC3502_DEFAULT
value = ( 0x3b + ( OPTION_4SIGHT_II_RGB * 7 ) ) ;
//
//
// .............................
//value = 0x3b ;
// --------------------------------------
// ******** Video type group ********
//
DEF_NTSC
value = ( PCK_FREQ < 13511300 ) ;
// --------------------------------------
DEF_PAL
value = ( PCK_FREQ > 13511300 ) ;
// --------------------------------------
// ******** Horizontal validation error message group ********
//
DEF_HTOTAL_IN_NOTSTD
value = (
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) != 944 ) &
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) != 780 )
) ;
// --------------------------------------
DEF_HS_HBP_HFP_ZERO
value = DEF_HTOTAL_IN_NOTSTD & ( ( VDT_HSYNC == 0 ) | ( VDT_HBPORCH == 0 ) | ( VDT_HFPORCH == 0 ) ) ;
// --------------------------------------
//
// ******** Begin of specific DEF Cropping KS Registers ********
// ******** Define Horiz. clamping by RGB Path using HS2 external signal ********
//
DEF_HCLMP_BORDER
value = ( ( ( 15 / 100 ) * 2 * VDT_HBPORCH ) + 0.5 ) ;
//
//
// .............................
//value = ( ( ( 15 / 100 ) * VDT_HBPORCH ) + 0.5 ) ;
// --------------------------------------
DEF_HCLMP_WIDTH
value = ( ( ( 7 / 10 ) * 2 * VDT_HBPORCH ) + 0.5 ) ;
//
//
// .............................
//value = ( ( ( 7 / 10 ) * VDT_HBPORCH ) + 0.5 ) ;
// --------------------------------------
DEF_HBPORCH
value = ( VDT_HTOTAL - VDT_HSYNC - VDT_HACTIVE - VDT_HFPORCH ) ;
// --------------------------------------
DEF_HCLMP_WIDTH_DEF
value = ( ( ( 7 / 10 ) * 2 * DEF_HBPORCH ) + 0.5 ) ;
// --------------------------------------
DEF_HCLAMP_HBP_MIN
// ******** Removing Bug Error wrong Htotal when locked unstead Min Clamping reached. ********
// ******** HClamp Pulse width min = 2 uS ********
// ******** When use cropping by HBPORCH using VDT_HBPORCH ********
//
value = (
( DEF_HCLMP_WIDTH < ( 49 + ( DEF_PAL * 10 ) ) ) |
( DEF_4SIGHT *
( ( VDT_HSYNC + VDT_HBPORCH ) < ( 102 + ( DEF_PAL * 13 ) ) )
)
) ;
//
//
// .............................
//value = (
// ( DEF_HCLMP_WIDTH < ( 49 + ( DEF_PAL * 10 ) ) ) |
// ( DEF_4SIGHT *
// ( ( VDT_HSYNC + VDT_HBPORCH ) < ( 102 + ( DEF_PAL * 24 ) ) )
// )
// ) ;
//value = (
// ( DEF_HCLMP_WIDTH < ( 49 + ( DEF_PAL * 10 ) ) ) |
// ( DEF_4SIGHT *
// ( ( VDT_HSYNC + VDT_HBPORCH ) < ( 110 + ( DEF_PAL * 30 ) ) )
// )
// ) ;
// --------------------------------------
DEF_HBPORCH_MAX
value = (
DEF_4SIGHT *
( ( VDT_HSYNC + VDT_HBPORCH ) > ( 137 + ( DEF_PAL * 28 ) ) )
) ;
//
//
// .............................
//value = (
// DEF_4SIGHT *
// ( ( VDT_HSYNC + VDT_HBPORCH ) > ( 127 + ( DEF_PAL * 32 ) ) )
// ) ;
// --------------------------------------
DEF_HBPORCH_MIN
value = ( OPTION_4SIGHT_II_DUAL * ( VDT_HBPORCH < 53 ) ) ;
// --------------------------------------
DEF_HCLAMP_HBP_DEF_MIN
// ******** Removing Bug Error wrong Htotal when locked unstead Min Clamping reached.********
// ******** HClamp Pulse width min = 2 uS ********
// ******** When use cropping by HFPORCH using DEF_HBPORCH ********
//
value = (
( DEF_HCLMP_WIDTH_DEF < ( 49 + ( DEF_PAL * 10 ) ) ) &
( VDT_HACTIVE == ( 640 + ( DEF_PAL * 128 ) ) ) &
DEF_HTOTAL_IN_NOTSTD
) ;
//
//
// .............................
//value = (
// ( DEF_HCLMP_WIDTH_DEF < ( 49 + ( DEF_PAL * 10 ) ) ) &
// ( VDT_HACTIVE == ( 640 + ( DEF_PAL * 128 ) ) )
// ) ;
// --------------------------------------
//
// ******** Setting HW registers values group ********
//
DEF_HS1B
value = (
(
( ( VDT_HSYNC + DEF_HCLMP_BORDER ) >= ( 42 + ( 4 * DEF_PAL ) ) ) *
( ( 2 * VDT_HSYNC ) - 66 + DEF_HCLMP_BORDER )
) +
(
( ( VDT_HSYNC + DEF_HCLMP_BORDER ) < ( 42 + ( 4 * DEF_PAL ) ) ) *
( 0x1ff - ( 64 - ( ( 2 * VDT_HSYNC ) + DEF_HCLMP_BORDER ) ) )
)
) ;
//
//
// .............................
//value = (
// (
// ( ( VDT_HSYNC + DEF_HCLMP_BORDER ) >= ( 42 + ( 4 * DEF_50HZ_HV_TOTAL_STD ) ) ) *
// ( ( 2 * VDT_HSYNC ) - 66 + DEF_HCLMP_BORDER )
// ) +
// (
// ( ( VDT_HSYNC + DEF_HCLMP_BORDER ) < ( 42 + ( 4 * DEF_50HZ_HV_TOTAL_STD ) ) ) *
// ( 0x1ff - ( 64 - ( ( 2 * VDT_HSYNC ) + DEF_HCLMP_BORDER ) ) )
// )
// ) ;
// --------------------------------------
DEF_HS1E
value = (
(
( ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER ) <= ( 220 + ( 50 * DEF_PAL ) )
) *
( 0x1FF - ( 220 - ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER ) ) - ( 50 * DEF_PAL ) )
) +
(
( ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER ) > ( 222 + ( 48 * DEF_PAL ) )
) *
( ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER - ( 48 * DEF_PAL ) ) - 222 )
)
) ;
//
//
// .............................
//value = (
// (
// ( ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER ) <= ( 220 + ( 50 * DEF_50HZ_HV_TOTAL_STD ) )
// ) *
// ( 0x1FF - ( 220 - ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER ) ) - ( 50 * DEF_50HZ_HV_TOTAL_STD ) )
// ) +
// (
// ( ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER ) > ( 222 + ( 48 * DEF_50HZ_HV_TOTAL_STD ) )
// ) *
// ( ( ( 2 * ( VDT_HSYNC + VDT_HBPORCH ) ) - DEF_HCLMP_BORDER - ( 48 * DEF_50HZ_HV_TOTAL_STD ) ) - 222 )
// )
// ) ;
// --------------------------------------
//
// ******** IMPORTANT!!!! Mono Via RGB selected by External output Clock ********
// ******** until GrabPathForced done! ********
//
DEF_MONO_VIA_RGB
value = ( VDC_MONO & GRB_RGB_PATH_FORCED ) ;
//
//
// .............................
//value = ( VDC_MONO & ( ( DEF_ORION & GRB_RGB_PATH_FORCED ) | OPTION_4SIGHT_II_RGB ) ) ;
//value = ( GRB_RGB_PATH_FORCED & VDC_MONO & ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ;
// --------------------------------------
//
// ******** "DEF_RGB_PATH" = '1' when the Bt254 data is used ********
// ******** and the PSG generates the synchronization signals ********
// ******** for the VIA and the Pixel Packer. ********
// ******** Case 0 : RGB video signal ********
// ******** Case 1 : Monochrome video with non-standard video timing ********
// ******** Case 2 : Monochrome video with 2 taps camera ********
// ******** Case 3 : Monochrome video with standard video timing ********
//
DEF_RGB_PATH
value = ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) ;
//
//
// .............................
//value = ( VDC_RGB_COL | DEF_MONO_VIA_RGB | ( ! DEF_DEC_PATH ) ) ;
// --------------------------------------
DEF_MONO_VIA_DEC
value = ( ( ! GRB_RGB_PATH_FORCED ) & VDC_MONO ) ;
//
//
// .............................
//value = ( ( ! ( GRB_RGB_PATH_FORCED | OPTION_4SIGHT_II_RGB ) ) & VDC_MONO ) ;
//value = ( ( ! GRB_RGB_PATH_FORCED ) & VDC_MONO ) ;
// --------------------------------------
//
// "DEF_DEC_PATH" = '1' when the KS0127 video decoder
// is used for digitizing the video signal and generating
// the synchronization signals for the VIA and the Pixel Packer.
// Case 0 : Composite color video
// Case 1 : S-VIDEO video signal
// Case 2 : Monochrome video with standard video timing
//
DEF_DEC_PATH
value = ( DEF_MONO_VIA_DEC | VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) ;
// --------------------------------------
DEF_MONO_CAM
value = VDC_MONO ;
//
//
// .............................
//value = ( VDC_MONO | ( GRB_RGB_PATH_FORCED & VDC_MONO ) ) ;
// --------------------------------------
DEF_COLOR
value = ( VDC_C_COLOR & DEF_DEC_PATH ) ;
// --------------------------------------
DEF_COLOR_CAM
value = ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID | VDC_RGB_COL ) ;
// --------------------------------------
// Input Video Voltage Swing of 2.0 Volts Max. to A/D
// GAIN Video Swing
// 4 0 - 500 mV
// 2.8 501 - 714 mV
// 2 715 - 1000 mV
// 1.3 1001 - 1537 mV
//
DEF_VIDEO_GAIN
value = (
( ( ! VDL_USE_DEFVAL ) &
( ( 4 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 )
) ? 4000 :
( ( ( ! VDL_USE_DEFVAL ) &
( ( 2.8 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 )
) ? 2800 :
( ( ( ! VDL_USE_DEFVAL ) &
( ( 2 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 )
) ? 2000 :
( ( ( ! VDL_USE_DEFVAL ) &
( ( 1.3 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 )
) ? 1300 :
2800 ) ) )
) ;
//
//
// .............................
//value = ( ! VDL_USE_DEFVAL ) &
// ( ( 4 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 2000 :
// ( ( ! VDL_USE_DEFVAL ) &
// ( ( 2.8 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 1400 :
// ( ( ! VDL_USE_DEFVAL ) &
// ( ( 2 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 1000 :
// ( ( ! VDL_USE_DEFVAL ) &
// ( ( 1 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 500 :
// 1000 ) ) ) ) * DEF_RGB_PATH ;
// --------------------------------------
DEF_HAVB
// ******** HAVB = 0xA7 (NTSC_RGB) 0xA4 (Pal_RGB) ********
//
value = (
(
DEF_RGB_PATH *
( ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) > ( ( DEF_PAL * 75 ) + 326 ) ) *
( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 )
) +
(
DEF_RGB_PATH *
( ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) <= ( ( DEF_PAL * 75 ) + 326 ) ) *
( 0x7FF - ( ( DEF_PAL * 75 ) + 326 - ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) ) )
) +
(
DEF_DEC_PATH *
( ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) - ( 215 + ( DEF_PAL * 72 ) ) ) >= 1 ) *
( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) - ( 213 + ( DEF_PAL * 75 ) ) )
) +
(
DEF_DEC_PATH * ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) < ( 215 + ( DEF_PAL * 72 ) ) ) *
( 0x7FF - ( ( DEF_PAL * 73 ) + 214 - ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) )
)
)
) ;
//
//
// .............................
// HAVB = 0xA7 (NTSC_RGB) 0xA4 (Pal_RGB)
//value = (
// (
// DEF_RGB_PATH *
// ( ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) > ( ( DEF_50HZ_HV_TOTAL_STD * 75 ) + 326 ) ) *
// ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 )
// ) +
// (
// DEF_RGB_PATH *
// ( ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) <= ( ( DEF_50HZ_HV_TOTAL_STD * 75 ) + 326 ) ) *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 75 ) + 326 - ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) ) )
// ) +
// (
// DEF_DEC_PATH *
// ( ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) - ( 215 + ( DEF_50HZ_HV_TOTAL_STD * 72 ) ) ) >= 1 ) *
// ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) - ( 213 + ( DEF_50HZ_HV_TOTAL_STD * 75 ) ) )
// ) +
// (
// DEF_DEC_PATH * ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) < ( 215 + ( DEF_50HZ_HV_TOTAL_STD * 72 ) ) ) *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 73 ) + 214 - ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) )
// )
// )
// ) ;
// HAVB = 0xA6 (NTSC_RGB) 0xA3 (Pal_RGB)
//value = (
// (
// DEF_RGB_PATH *
// ( ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) > ( ( DEF_50HZ_HV_TOTAL_STD * 75 ) + 327 ) ) *
// ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 )
// ) +
// (
// DEF_RGB_PATH *
// ( ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) <= ( ( DEF_50HZ_HV_TOTAL_STD * 75 ) + 327 ) ) *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 75 ) + 327 - ( ( VDT_HSYNC + VDT_HBPORCH + 1 ) * 2 ) ) )
// ) +
// (
// DEF_DEC_PATH *
// ( ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) - ( 215 + ( DEF_50HZ_HV_TOTAL_STD * 72 ) ) ) >= 1 ) *
// ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) - ( 213 + ( DEF_50HZ_HV_TOTAL_STD * 75 ) ) )
// ) +
// (
// DEF_DEC_PATH * ( ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) < ( 215 + ( DEF_50HZ_HV_TOTAL_STD * 72 ) ) ) *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 73 ) + 214 - ( ( VDT_HSYNC + VDT_HBPORCH ) * 2 ) )
// )
// )
// ) ;
// --------------------------------------
DEF_HAVE
// ******** HAVE = 0xA3 (NTSC_RGB) 0xA8 (Pal_RGB) ********
//
value = (
(
DEF_RGB_PATH *
( 0x7FF - ( ( DEF_PAL * 323 ) + 1610 - ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + 1 ) * 2 ) ) )
) +
(
DEF_DEC_PATH *
( ( ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 ) -
( 1497 + ( DEF_PAL * 323 ) ) ) >= ( 1 + ( 2 * DEF_PAL ) )
) *
( ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 ) - ( 1497 + ( DEF_PAL * 323 ) ) )
) +
( DEF_DEC_PATH * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) < ( ( DEF_PAL * 164 ) + 748 ) ) *
( 0x7FF - ( ( DEF_PAL * 321 * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) < 910 ) ) +
( DEF_PAL * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) == 910 ) * 322 ) +
( DEF_PAL * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) == 911 ) * 324 ) +
1498 - ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 )
)
)
)
) ;
//
//
// .............................
// HAVE = 0xA3 (NTSC_RGB) 0xA8 (Pal_RGB)
//value = (
// (
// DEF_RGB_PATH *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 323 ) + 1610 - ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + 1 ) * 2 ) ) )
// ) +
// (
// DEF_DEC_PATH *
// ( ( ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 ) -
// ( 1497 + ( DEF_50HZ_HV_TOTAL_STD * 323 ) ) ) >= ( 1 + ( 2 * DEF_50HZ_HV_TOTAL_STD ) )
// ) *
// ( ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 ) - ( 1497 + ( DEF_50HZ_HV_TOTAL_STD * 323 ) ) )
// ) +
// ( DEF_DEC_PATH * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) < ( ( DEF_50HZ_HV_TOTAL_STD * 164 ) + 748 ) ) *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 321 * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) < 910 ) ) +
// ( DEF_50HZ_HV_TOTAL_STD * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) == 910 ) * 322 ) +
// ( DEF_50HZ_HV_TOTAL_STD * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) == 911 ) * 324 ) +
// 1498 - ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 )
// )
// )
// )
// ) ;
// HAVE = 0xA2 (NTSC_RGB) 0xA7 (Pal_RGB)
//value = (
// (
// DEF_RGB_PATH *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 323 ) + 1611 - ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + 1 ) * 2 ) ) )
// ) +
// (
// DEF_DEC_PATH *
// ( ( ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 ) -
// ( 1497 + ( DEF_50HZ_HV_TOTAL_STD * 323 ) ) ) >= ( 1 + ( 2 * DEF_50HZ_HV_TOTAL_STD ) )
// ) *
// ( ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 ) - ( 1497 + ( DEF_50HZ_HV_TOTAL_STD * 323 ) ) )
// ) +
// ( DEF_DEC_PATH * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) < ( ( DEF_50HZ_HV_TOTAL_STD * 164 ) + 748 ) ) *
// ( 0x7FF - ( ( DEF_50HZ_HV_TOTAL_STD * 321 * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) < 910 ) ) +
// ( DEF_50HZ_HV_TOTAL_STD * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) == 910 ) * 322 ) +
// ( DEF_50HZ_HV_TOTAL_STD * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) == 911 ) * 324 ) +
// 1498 - ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) * 2 )
// )
// )
// )
// ) ;
// --------------------------------------
//
// ******** Horizontal validation error message group ********
//
DEF_MORPHIS_NO_HCROP
value = (
DEF_MORPHIS * VDT_USE_HLOCK *
(
( DEF_NTSC * ( ( VDT_HSYNC != 58 ) | ( VDT_HBPORCH != 60 ) | ( VDT_HFPORCH != 22 ) ) ) |
( DEF_PAL * ( ( VDT_HSYNC != 69 ) | ( VDT_HBPORCH != 85 ) | ( VDT_HFPORCH != 22 ) ) )
)
) ;
// --------------------------------------
//
// ******** Vertical validation error message group ********
//
DEF_VACTIVE_ODD
value = ( VDT_VACTIVE % 2 ) ;
// --------------------------------------
DEF_VTOTAL_IN_NOTSTD
value = (
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 525 ) &
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 625 )
) ;
//
//
// .............................
//value = (
// ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 525 ) &
// ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 625 ) &
// ( ! DEF_VACTIVE_OVERPASS )
// ) ;
// --------------------------------------
DEF_VS_VBP_VFP_ZERO
value = DEF_VTOTAL_IN_NOTSTD & ( ( VDT_VSYNC == 0 ) | ( VDT_VBPORCH == 0 ) | ( VDT_VFPORCH == 0 ) ) ;
// --------------------------------------
DEF_VS_VBP_MIN
value = (
( DEF_ORION * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 2 + ( DEF_PAL * 2 ) ) ) ) |
( DEF_4SIGHT *
(
( VDT_VSYNC + VDT_VBPORCH ) <
(
18 + ( OPTION_4SIGHT_II_DUAL * ( 16 + ( DEF_PAL * 12 ) ) )
+ ( DEF_RGB_PATH * DEF_PAL * 2 )
)
)
) |
( DEF_MORPHIS * ( ( VDT_VSYNC + VDT_VBPORCH ) < 6 )
)
) ;
//
//
// .............................
//value = (
// ( DEF_ORION * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 2 + ( DEF_PAL * 2 ) ) ) ) |
// ( DEF_4SIGHT *
// (
// ( VDT_VSYNC + VDT_VBPORCH ) <
// (
// 18 + ( OPTION_4SIGHT_II_DUAL * ( 16 + ( DEF_PAL * 12 ) ) )
// + ( DEF_RGB_PATH * DEF_PAL * 2 )
// )
// )
// )
// ) ;
// --------------------------------------
DEF_VS_VBP_MAX
value = (
(
DEF_4SIGHT *
( ( VDT_VSYNC + VDT_VBPORCH ) > ( 39 + ( DEF_PAL * 8 ) ) )
) |
(
DEF_MORPHIS * ( ( VDT_VSYNC + VDT_VBPORCH ) > ( 41 + ( DEF_PAL * 6 ) ) )
)
) ;
//
//
// .............................
//value = (
// DEF_4SIGHT *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > ( 41 + ( DEF_PAL * ( 6 + ( DEF_RGB_PATH * 2 ) ) ) ) )
// ) ;
// --------------------------------------
DEF_ORION_VIN_HIGH
value = 0 ;
//
//
// .............................
//value = ( ( VDC_IN_CH4 | VDC_IN_CH5 | VDC_IN_CH6 | VDC_IN_CH7 ) * DEF_ORION ) ;
//value = VDC_IN_HIGH ;
// ******** Message:"Channels selected must be : 0129 or 45611 ********
// ******** DEF_INVALID_INPUT_4SIGHT ********
//value = (
// ( VDC_SVID | VDC_RGB_COL ) *
// (
// (
// OPTION_4SIGHT_LC &
// (
// (
// ( VDC_IN_CH0 | VDC_IN_CH1 | VDC_IN_CH2 | VDC_IN_CH9 ) &
// ( VDC_IN_CH4 | VDC_IN_CH5 | VDC_IN_CH6 | VDC_IN_CH11 )
// ) |
// (
// ( VDC_IN_CH3 | VDC_IN_CH7 ) &
// ( VDC_IN_CH8 | VDC_IN_CH10 )
// )
// )
// ) |
// (
// ORION_4SIGHT &
// (
// (
// (
// VDC_IN_CH0 | VDC_IN_CH1 | VDC_IN_CH2 | VDC_IN_CH9 |
// VDC_IN_CH12 | VDC_IN_CH13 | VDC_IN_CH14 | VDC_IN_CH21
// ) &
// (
// VDC_IN_CH4 | VDC_IN_CH5 | VDC_IN_CH6 | VDC_IN_CH11 |
// VDC_IN_CH16 | VDC_IN_CH17 | VDC_IN_CH18 | VDC_IN_CH23
// )
// ) |
// (
// ( VDC_IN_CH3 | VDC_IN_CH8 | VDC_IN_CH15 | VDC_IN_CH20 ) &
// ( VDC_IN_CH7 | VDC_IN_CH10 | VDC_IN_CH19 | VDC_IN_CH22 )
// )
// )
// )
// )
// ) ;
// --------------------------------------
DEF_VBI
value = (
( VDT_VSYNC + VDT_VBPORCH - 36 - ( 11 * DEF_PAL ) ) & 0x3f
) ;
//
// =============================================
//
//
// *********************************************
// *********************************************
// Section #6 : BOARD REGISTER DEFINITION
// *********************************************
// *********************************************
//
//
[PARAMETER]
// =============================================
//
INFO_XSIZE
Horizontal image size
eo_information
1
640 12 unsigned flag_overflow
value = VDT_HACTIVE ;
no_define_value
//
// =============================================
//
INFO_YSIZE
Vertical image size
eo_information
1
480 12 unsigned flag_overflow
//
value = VDT_VACTIVE ;
//
no_define_value
//
// =============================================
//
INFO_MODE
Corona DCF software specification (INFO_MODE)
eo_information
5
// --------------------------------------
MaskInterlaced regular
eo_information
0 1 unsigned flag_overflow
//
value = (
VDT_INTERL ? 0 :
( VDT_NINTRL ? 1 :
0 )
) ;
//
define_value
0 : Camera Interlaced
1 : Camera non interlaced
// --------------------------------------
MaskVideo regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
MaskColor regular
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_MONO_CAM ? 0 :
( DEF_COLOR_CAM ? 1 :
0 )
) ;
//
define_value
0 : Camera monochrome
1 : Camera color
// --------------------------------------
MaskRGB regular
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_DEC_PATH ? 0 :
( DEF_RGB_PATH ? 1 :
0 )
) ;
//
define_value
0 : Decoder path
1 : RGB path
// --------------------------------------
MaskYC regular
eo_information
0 1 unsigned flag_overflow
//
value = VDC_SVID ;
//
define_value
0 : Camera non YC
1 : Camera YC
//
// =============================================
//
INFO_TYPE
?
eo_information
1
2 8 unsigned flag_overflow
//
value = 2 ;
//
no_define_value
// 1 : Line scan
// 2 : Frame scan
// 3 : Area scan
// 4 : Others
//
// =============================================
//
INFO_DEPTH
?
eo_information
1
8 8 unsigned flag_overflow
//
value = 0x8 ;
//
no_define_value
//
//
//..............................
//value = ( VDC_WD8 ? 8 :
// ( VDC_VID_WIDTH_10 ? 10 :
// ( VDC_VID_WIDTH_12 ? 12 :
// ( VDC_VID_WIDTH_14 ? 14 :
// ( VDC_WD16 ? 16 :
// ( VDC_WD24 ? 24 :
// ( VDC_WD32 ? 32 :
// ( VDC_WD64 ? 64 :
// 8 ) ) ) ) ) ) )
// ) ;
// =============================================
//
INFO_BAND
?
eo_information
1
1 8 unsigned flag_overflow
//
value = ( VDC_MONO ? 1 :
3
) ;
//
no_define_value
//1 : Mono
//3 : Color
//
// =============================================
//
INFO_INPUT
?
eo_information
1
0 8 unsigned flag_overflow
//
value = (
( ( ( VDC_IN_CH2 || VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ) ? 1 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ? 2 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
0 ) )
) ;
//
no_define_value
//0 : Analog Channel 0
//1 : Analog Channel 1
//2 : Analog Channel 2
//3 : Analog Channel 3
//4 : Digital TTL
//5 : Digital 422
//
//
//..............................
//value = DEF_INFO_INPUT ;
//value = 0 ;
//value = (
// ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_R ) ) || DEF_MONO_VIA_DEC ||
// VDC_C_COLOR || VDC_RGB_COL || VDC_SVID ) & ( ! VDC_DIG ) & VDC_IN_CH0 & ( TAP_CONFIG == 1 ) ) ? 0 :
// ( ( ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_G ) ) || DEF_MONO_VIA_DEC ||
// VDC_C_COLOR ) & VDC_IN_CH1 & ( CT_TAPS == 0 ) & ( CT_CAMERA == 0 ) ) ||
// ( VDC_SVID & VDC_IN_CH2 ) || ( ( CT_TAPS == 0 ) & ( CT_CAMERA == 1 ) ) ) ? 1 :
// ( ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_B ) ) || DEF_MONO_VIA_DEC || VDC_C_COLOR ) &
// VDC_IN_CH2 & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) ||
// ( ( CT_TAPS == 0 ) & ( CT_CAMERA == 2 ) ) ? 2 :
// ( ( ( VDC_MONO || VDC_C_COLOR ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) &
// DEF_DEC_PATH & VDC_IN_CH3 ) ? 3 :
// ( VDC_DIG ? 5 :
// 0 ) ) ) )
// ) ;
// =============================================
//
INFO_PIXCLK
Pixel clock frequency
eo_information
1
0 32 unsigned flag_overflow
//
value = PCK_FREQ ;
//
no_define_value
//
// =============================================
//
INFO_PIPELINE
?
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_MODULE_422
Digital video and sync module
eo_information
1
0 32 unsigned flag_overflow
//
value = ( VDC_DIG ? 0x60f00 :
0 ) ;
//
no_define_value
//
// =============================================
//
INFO_CHANNEL
Corona DCF software specification (INFO_CHANNEL)
eo_information
2
// --------------------------------------
VideoSignal regular
eo_information
0 4 unsigned flag_overflow
//
// Modify also INFO_INPUT
//
value = (
( ( ( VDC_IN_CH2 | VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ) ? 1 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ? 2 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
0 ) )
) ;
//
no_define_value
//
//..............................
//value = (
// ( VDC_IN_CH1 * ( ! VDC_RGB_COL ) ) +
// ( VDC_IN_CH2 * 2 * ( ! VDC_RGB_COL ) ) +
// ( VDC_IN_CH3 * 3 * ( ! VDC_RGB_COL ) )
// ) ;
//
//
//..............................
// --------------------------------------
VideoSync regular
eo_information
0 4 unsigned flag_overflow
//
value = (
(
( ( VDC_C_COLOR || VDC_MONO ) & SYC_COMP & VDC_IN_CH1 ) ||
( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 1 ) ) ||
( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 1 ) )
) ? 1 :
(
(
( ( VDC_IN_CH2 || VDC_IN_CH3 ) & VDC_SVID ) ||
( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH2 ) ||
( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 2 ) ) ||
( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 2 ) )
) ? 2 :
(
(
( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH3 ) ||
( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 3 ) ) ||
( VDC_RGB_COL & SYC_SEP )
) ? 3 :
0 ) )
) ;
//
no_define_value
//
//
//..............................
//value = (
// (
// ( ( VDC_IN_CH2 || VDC_IN_CH3 ) & VDC_SVID ) ||
// ( ( VDC_C_COLOR || VDC_MONO ) & SYC_COMP & VDC_IN_CH1 ) ||
// ( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 1 ) ) ||
// ( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 1 ) )
// ) ? 1 :
// (
// (
// ( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH2 ) ||
// ( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 2 ) ) ||
// ( VDC_RGB_COL & SYC_COMP & ( SYC_IN_CH == 2 ) )
// ) ? 2 :
// (
// (
// ( ( VDC_MONO || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH3 ) ||
// ( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 3 ) ) ||
// ( VDC_RGB_COL & SYC_SEP )
// ) ? 3 :
// 0 ) )
// ) ;
// =============================================
//
// *********************************************
// AD5302 (begin)
// *********************************************
//
// =============================================
//
AD5302_DAC_A
AD #A (RREF-)
eo_information
1
0x3b 8 unsigned flag_overflow
//
value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
(
( ! VDL_USE_DEFVAL ) *
(
( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
/ 2618 ) + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
+ ( ( DEF_VIDEO_GAIN == 2800 ) * OPTION_4SIGHT_II_RGB )
+ ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
)
)
) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
// (
// ( ! VDL_USE_DEFVAL ) *
// (
// ( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
// / 2618 ) + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
// + ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
// )
// )
// ) ;
// =============================================
//
AD5302_DAC_B
AD #B (GREF-)
eo_information
1
0x3b 8 unsigned flag_overflow
//
value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
(
( ! VDL_USE_DEFVAL ) *
(
( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
/ 2618 ) + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
+ ( ( DEF_VIDEO_GAIN == 2800 ) * OPTION_4SIGHT_II_RGB )
+ ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
)
)
) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
// (
// ( ! VDL_USE_DEFVAL ) *
// (
// ( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
// / 2618 ) + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
// + ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
// )
// )
// ) ;
// =============================================
//
AD5302_DAC_C
AD #C (BREF-)
eo_information
1
0x3b 8 unsigned flag_overflow
//
value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
(
( ! VDL_USE_DEFVAL ) *
(
( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
/ 2618 ) + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
+ ( ( DEF_VIDEO_GAIN == 2800 ) * OPTION_4SIGHT_II_RGB )
+ ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
)
)
) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
// (
// ( ! VDL_USE_DEFVAL ) *
// (
// ( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
// / 2618 ) + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
// + ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
// )
// )
// ) ;
// =============================================
//
AD5302_DAC_E
AD #E (RLEVEL)
eo_information
1
0x3b 8 unsigned flag_overflow
//
value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
(
( ! VDL_USE_DEFVAL ) *
(
( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2618 )
+ ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
+ ( ( DEF_VIDEO_GAIN == 2800 ) * OPTION_4SIGHT_II_RGB )
+ ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
)
)
) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
// (
// ( ! VDL_USE_DEFVAL ) *
// (
// ( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2618 )
// + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
// + ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
// )
// )
// ) ;
// =============================================
//
AD5302_DAC_F
AD #F (GLEVEL)
eo_information
1
0x3b 8 unsigned flag_overflow
//
value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
(
( ! VDL_USE_DEFVAL ) *
(
( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2618 )
+ ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
+ ( ( DEF_VIDEO_GAIN == 2800 ) * OPTION_4SIGHT_II_RGB )
+ ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
)
)
) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
// (
// ( ! VDL_USE_DEFVAL ) *
// (
// ( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2618 )
// + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
// + ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
// )
// )
// ) ;
// =============================================
//
AD5302_DAC_G
AD #G (BLEVEL)
eo_information
1
0x3b 8 unsigned flag_overflow
//
value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
(
( ! VDL_USE_DEFVAL ) *
(
( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2618 )
+ ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
+ ( ( DEF_VIDEO_GAIN == 2800 ) * OPTION_4SIGHT_II_RGB )
+ ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
+ ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
)
)
) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDL_USE_DEFVAL * DEF_DAC3502_DEFAULT ) +
// (
// ( ! VDL_USE_DEFVAL ) *
// (
// ( ( ( 2618 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2618 )
// + ( ( ( DEF_VIDEO_GAIN == 1300 ) | ( DEF_VIDEO_GAIN == 2800 ) ) * 5 )
// + ( ( DEF_VIDEO_GAIN == 2000 ) * 8 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL >= 380 ) * 3 )
// + ( ( DEF_VIDEO_GAIN == 4000 ) * ( VDL_AMPL < 380 ) )
// )
// )
// ) ;
// =============================================
//
// *********************************************
// AD5302 (end)
// *********************************************
//
//
// *********************************************
// KS0127 (Begin)
// *********************************************
//
// =============================================
//
KS0127_STAT
Read Only Status Bits
eo_information
1
0 8 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
KS0127_CMDA
Control Register A
eo_information
7
// --------------------------------------
IFMT regular
eo_information
1 1 unsigned flag_overflow
//
value = DEF_NTSC ;
//
define_value
Input 50 HZ
Input 60 Hz
//
//
//..............................
//value = DEF_60HZ_HV_TOTAL_STD ;
// --------------------------------------
MNFMT regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Without IFMT Bit
With IFMT Bit
// --------------------------------------
PIXSEL regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Data Square Pixel
Output Data CCIR 601 rate
// --------------------------------------
XT24 regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Ext. CLK 26.8 Mhz
Ext. CLK 24.576 Mhz
// --------------------------------------
HFSEL regular
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Force loop to Very Fast
Force loop to Fast
Force loop to VCR Time constant
Force loop to TV Time constant
//
//
//..............................
//value = ( MEMBER_VCR_INPUT_MODE * 2 ) ;
// --------------------------------------
VSE regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Line 10/10.5
Line 9 /9.5
// --------------------------------------
POWDN regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal operation
Most Chip functions disable
//
// =============================================
//
KS0127_CMDB
Control Register B
eo_information
5
// --------------------------------------
INSEL regular
eo_information
2 4 unsigned flag_overflow
// In0,4 = AY2 | In1,5 = AC2 | In2,6 = AY0 | In3,7 = AC0
//
value = (
( VDC_IN_CH0 * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 2 ) +
( VDC_IN_CH1 * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 6 ) +
( VDC_IN_CH3 * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 4 ) +
( ( SYC_IN_CH == 0 ) * ( ( SYC_SEP * DEF_MONO_VIA_RGB ) | ( SYC_COMP * VDC_RGB_COL ) ) * 2 ) +
( ( SYC_IN_CH == 1 ) * ( ( SYC_SEP * DEF_MONO_VIA_RGB ) | ( SYC_COMP * VDC_RGB_COL ) ) * 6 ) +
( ( ( ( SYC_IN_CH == 3 ) * SYC_SEP * DEF_MONO_VIA_RGB ) | ( SYC_SEP * VDC_RGB_COL ) ) * 4 ) +
( VDC_IN_CH2 * VDC_SVID * 8 ) +
( VDC_IN_CH0 * VDC_SVID * 10 )
) ;
//
define_value
AY0=comp
AY1=comp
AY2=comp
reserved
AC0=comp
AC1=comp
AC2=comp
reserved
AY0=lum,AC0=chrom
AY1=lum,AC1=chrom
AY2=lum,AC2=chrom
reserved
reserved
reserved
reserved
AY2=lum,AC1=Cb,AC2=Cr
//
//
//..............................
//value = (
// ( VDC_IN_CH0 * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 2 ) +
// ( VDC_IN_CH1 * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 6 ) +
// ( VDC_IN_CH3 * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 4 ) +
// ( ( SYC_IN_CH == 0 ) * SYC_SEP * DEF_MONO_VIA_RGB * 2 ) +
// ( ( SYC_IN_CH == 1 ) * SYC_SEP * DEF_MONO_VIA_RGB * 6 ) +
// ( ( SYC_IN_CH == 3 ) * SYC_SEP * DEF_MONO_VIA_RGB * 4 ) +
// ( VDC_IN_CH2 * VDC_SVID * 8 ) +
// ( VDC_IN_CH0 * VDC_SVID * 10 )
// ) ;
// Include 8 Input Video Channels in Intellicam
// To be include in the Info-File when disponible in the code of Intellicam.
//value = (
// ( ( VDC_IN_CH0 | VDC_IN_CH4 ) * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 2 ) +
// ( ( VDC_IN_CH1 | VDC_IN_CH5 ) * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 6 ) +
// ( ( VDC_IN_CH3 | VDC_IN_CH6 ) * SYC_COMP * ( VDC_MONO | VDC_C_COLOR ) * 4 ) +
// ( ( ( SYC_IN_CH == 0 ) | ( SYC_IN_CH == 4 ) ) * DEF_MONO_VIA_RGB * SYC_SEP * 2 ) +
// ( ( ( SYC_IN_CH == 1 ) | ( SYC_IN_CH == 5 ) ) * DEF_MONO_VIA_RGB * SYC_SEP * 6 ) +
// ( ( ( SYC_IN_CH == 3 ) | ( SYC_IN_CH == 6 ) ) * DEF_MONO_VIA_RGB * SYC_SEP * 4 ) +
// ( VDC_IN_CH2 * VDC_SVID * 8 ) +
// ( VDC_IN_CH0 * VDC_SVID * 10 )
// ) ;
// --------------------------------------
AGCFRZ regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AGC Running
AGC Frozen
// --------------------------------------
AGCOVF regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AGC Tracks sync Tip
ADC Overflow
// --------------------------------------
VALIGN regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Serration pulses
Half or beginning line
// --------------------------------------
AGCGN regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal Mode
54 ADC Code
//
// =============================================
//
KS0127_CMDC
Control Register C
eo_information
2
// --------------------------------------
UNUSED protected
eo_information
2 7 unsigned flag_overflow
//
no_define_value
//
//
//..............................
//value = 2 ;
// --------------------------------------
VMEN regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal VS op.
VS free running
//
// =============================================
//
KS0127_CMDD
Control Register D
eo_information
7
// --------------------------------------
GPPORT regular
eo_information
0 1 unsigned flag_overflow
// Register Bit 0 : 1 = Rising Edge | 0 = Falling Edge
//
value = ( ( DEF_DEC_PATH & GRB_TRG_POS ) ? 1 : 0 ) ;
//
define_value
Low
High
//
//..............................
//value = ( ( DEF_DEC_PATH & GRB_TRG_NEG ) ? 0 : 1 ) ;
// --------------------------------------
Y1MHZ regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Luma Filters
Luma Filter 1 Mhz
// --------------------------------------
SYNDIR regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
HS1 & VS output
HS1 & VS input
// --------------------------------------
INPSL regular
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vin = analog
Vin = Dig CbYCr
reserved
Vin = Dig CVBS
// --------------------------------------
CKDIR regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Internal Clock
External CK Pin
// --------------------------------------
UNUSED6 protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
EAV regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
HS=HS1, VS=VS
HS=Code,VS=Code
//
//=============================================
//
KS0127_HAVB
HAV start control
eo_information
1
0x17 8 unsigned no_flag_overflow
//
value = ( DEF_HAVB & 0xFF ) ;
//
no_define_value
//
// =============================================
//
KS0127_HAVE
HAV end control
eo_information
1
0x13 8 unsigned no_flag_overflow
//
value = ( DEF_HAVE & 0xFF ) ;
//
no_define_value
//
// =============================================
//
KS0127_HS1B
HS1 start control
eo_information
1
0x22 8 unsigned no_flag_overflow
// HS1 for Clamping
// Both Path DEC/RGB
//
value = ( ( DEF_HS1B / 2 ) & 0xff ) ;
//
no_define_value
//
//
//..............................
// For Testing Hclmp
//value = 0xDF ;
//
// =============================================
//
KS0127_HS1E
HS1 end control
eo_information
1
0xfe 8 unsigned no_flag_overflow
// HS1 for Clamping
// Both Path DEC/RGB
//
value = ( ( DEF_HS1E / 2 ) & 0xff ) ;
//
no_define_value
//
//
//..............................
// For Testing Hclmp
//value = ( 0xCB - ( DEF_PAL * 14 ) ) ;
//
//value = ( 0xCB - ( DEF_50HZ_HV_TOTAL_STD * 14 ) ) ;
//
// =============================================
//
KS0127_HS2B
HS2 start control
eo_information
1
0 8 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( ( DEF_HS1B / 2 ) & 0xff ) ;
//
// =============================================
//
KS0127_HS2E
HS2 end control
eo_information
1
0 8 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( ( DEF_HS2E / 2 ) & 0xff ) ;
//
// =============================================
//
KS0127_AGC
AGC control
eo_information
1
0x4f 8 unsigned no_flag_overflow
//
value = 0x4F ;
//
no_define_value
//
//=============================================
//
KS0127_HXTRA
Horizontal extra
eo_information
4
// --------------------------------------
HS2B regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( DEF_HS2E & 0x1 ) ;
//value = ( DEF_HS2B & 0x1 ) ;
// --------------------------------------
HS1B regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
HAVB regular
eo_information
0 3 unsigned flag_overflow
//
value = ( DEF_HAVB >> 8 ) ;
//
no_define_value
// --------------------------------------
HAVE regular
eo_information
0 3 unsigned flag_overflow
//
value = ( DEF_HAVE >> 8 ) ;
//
no_define_value
//
// =============================================
//
KS0127_CDEM
Chroma Demodulation Control
eo_information
5
// --------------------------------------
UNUSED0 protected
eo_information
0 3 unsigned flag_overflow
//
no_define_value
// --------------------------------------
CIFCMP regular
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
No compensation
1 dB up Lsb
3 dB up Lsb
6 dB up Lsb
// --------------------------------------
UNUSED5 protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
FSEC regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
SECAM if detected
Always SECAM filter
// --------------------------------------
OUTHIZ regular
eo_information
0 1 unsigned flag_overflow
//
value = DEF_RGB_PATH ;
//
define_value
Default setting
Outputs three-stated
//
// =============================================
//
KS0127_PORTAB
Port A and B Control
eo_information
4
// --------------------------------------
DATAA regular
eo_information
7 3 unsigned flag_overflow
//
value = 7 ;
//
define_value
PortA disconnected
PortA = BPG
PortA = SYG
PortA = CBG
PortA = CBGW
PortA = SLICE
PortA = VBI
PortA = GPPORT
// --------------------------------------
DIRA regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
PortA = Input
PortA = Output
// --------------------------------------
DATAB regular
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
define_value
PortA disconnected
PortB = SCH
PortB = FH2
PortB = FS_PULSE
PortB = VBI_CVBS
PortB = VBI_PROC
PortB = NOT USED
PortB = RTCO
// --------------------------------------
DIRB regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
PortB = Input
PortB = Output
// =============================================
//
KS0127_LUMA
Luma control register
eo_information
7
// --------------------------------------
HYPK regular
eo_information
1 2 unsigned flag_overflow
//
value = ( ( VDC_C_COLOR & DEF_NTSC ) ? 0 : 1
) ;
//
define_value
Less than nominal peaking
Nominal peaking
Increased peaking
Maximum peaking
//
//
//..............................
//value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 0 : 1
// ) ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 0 : 1
// ) * DEF_DEC_PATH ;
// --------------------------------------
CTRAP regular
eo_information
1 1 unsigned flag_overflow
//
value = ( ( VDC_C_COLOR & DEF_PAL ) ? 1 : 0
) ;
//
define_value
No Chroma Trap
Chroma Trap Enabled
//
//
//..............................
//value = ( ( VDC_C_COLOR & DEF_50HZ_HV_TOTAL_STD ) ? 1 : 0
// ) ;
//value = ( ( VDC_C_COLOR & ( DEF_50HZ_H_TOTAL_ACTIVE_STD & DEF_50HZ_V_TOTAL_ACTIVE_STD ) ) ? 1 : 0
// ) * DEF_DEC_PATH ;
// --------------------------------------
HYBWR regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Full Bandwidth
Reduced Bandwidth
// --------------------------------------
PED regular
eo_information
1 1 unsigned flag_overflow
//
value = ( DEF_NTSC * ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) * DEF_DEC_PATH ) ;
//
define_value
No Pedestal
Pedestal Enabled
//
//
//..............................
//value = ( DEF_60HZ_HV_TOTAL_STD * ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) ) ;
//value = ( DEF_60HZ_H_TOTAL_ACTIVE_STD * DEF_60HZ_V_TOTAL_ACTIVE_STD * ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) ) * DEF_DEC_PATH ;
// --------------------------------------
RGBH regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Luminance = 16-235
Luminance = 0-255
// --------------------------------------
UNIT regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Luma DC Gain = PED & RGBH
Luma DC Gain = 1
// --------------------------------------
UNUSED protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
KS0127_CON
Contrast control
eo_information
1
0 8 unsigned no_flag_overflow
//
value = (
(
( VDL_CONTR < 50 ) ? ( 128 + ( VDL_CONTR * ( 127 / 49 ) ) ) :
( ( VDL_CONTR >= 50 ) ? ( ( VDL_CONTR - 50 ) * ( 127 / 50 ) ) :
0 )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// ( VDL_CONTR < 50 ) ? ( ( - 128 ) + ( VDL_CONTR * ( 128 / 50 ) ) ) :
// ( ( VDL_CONTR >= 50 ) ? ( ( VDL_CONTR - 50 ) * ( 127 / 50 ) ) :
// 0 )
// ) ;
//value = (
// ( VDL_CONTR < 50 ) ? ( ( - 128 ) + ( VDL_CONTR * ( 128 / 50 ) ) ) :
// ( ( VDL_CONTR == 50 ) ? 0 :
// ( ( VDL_CONTR > 50 ) ? ( ( VDL_CONTR - 50 ) * ( 127 / 50 ) ) :
// 0 ) )
// ) ;
//
// =============================================
//
KS0127_BRT
Brightness control
eo_information
1
0 8 unsigned no_flag_overflow
//
value = (
(
( VDL_BRGHT < 50 ) ? ( 128 + ( VDL_BRGHT * ( 127 / 49 ) ) ) :
( ( VDL_BRGHT >= 50 ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
0 )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// ( VDL_BRGHT < 50 ) ? ( VDL_BRGHT * ( 128 / 50 ) ) :
// ( ( VDL_BRGHT >= 50 ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
// 0 )
// ) ;
//value = (
// ( VDL_BRGHT < 50 ) ? ( ( - 128 ) + ( VDL_BRGHT * ( 128 / 50 ) ) ) :
// ( ( VDL_BRGHT == 50 ) ? 0 :
// ( ( VDL_BRGHT > 50 ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
// 0 ) )
// ) ;
//
// =============================================
//
KS0127_CHROMA
Chroma Control Register A
eo_information
6
// --------------------------------------
CKILL regular
eo_information
3 2 unsigned flag_overflow
//
value = ( DEF_MONO_VIA_DEC ? 3 : 0 ) ;
//
define_value
Auto Detect Mode
reserved
Color Always ON
Data Forced to Code 128
//
//
//..............................
//value = ( ( VDC_MONO & DEF_DEC_PATH ) ? 3 : 0 ) ;
//value = ( ( VDC_MONO & DEF_DEC_PATH ) ? 3 : 2 ) ;
// --------------------------------------
CORE regular
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Coring
Chroma Data 128+-1
Chroma Data 128+-3
Chroma Data 128+-7
// --------------------------------------
CBW regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Chroma Bandwidth = 850 kHz
Chroma Bandwidth = 550 kHz
// --------------------------------------
PALN regular
eo_information
0 1 unsigned flag_overflow
//
value = DEF_PAL ;
//
define_value
Select NTSC-N
Select PAL-N
//
//
//..............................
//value = DEF_50HZ_HV_TOTAL_STD ;
//value = 0 ;
// --------------------------------------
PALM regular
eo_information
0 1 unsigned flag_overflow
//
value = DEF_PAL ;
//
define_value
Select Tracking for NTSC-M
Select Tracking for PAL-M
//
//
//..............................
//value = DEF_50HZ_HV_TOTAL_STD ;
//value = 0 ;
// --------------------------------------
ACCFRZ regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Color Gain tracks the input
Color Gain freezes to sat. level
//
// =============================================
//
KS0127_CHROMB
Chroma Control Register B
eo_information
2
// --------------------------------------
SCHCMP regular
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//
//..............................
// Phase constant compare value for color burst phase.Each step = 22.5
// --------------------------------------
CDLY regular
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
No delay
Delay = -0.5
Delay = 1
Delay = 0.5
Delay = 2
Delay = 1.5
Delay = 3
Delay = 2.5
Delay = -4
Delay = -4.5
Delay = -3
Delay = -3.5
Delay = -2
Delay = -2.5
Delay = -1
Delay = -1.5
//
// =============================================
//
KS0127_DEMOD
Chroma demodulation Control & Status
eo_information
6
// --------------------------------------
MNSEC regular
eo_information
2 2 unsigned flag_overflow
//
value = 2 ;
//
define_value
Automatic SECAM detection
reserved
Chip assume Input= Not SECAM
Chip assume Input=SECAM
// --------------------------------------
MNFSC regular
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Automatic detection FSC
reserved
FSC = 4.43 or 4.286 Mhz
FSC = 3.58 Mhz
// --------------------------------------
//CTRACK regular
CFC regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Field rate & Fsc
Field rate Only
// --------------------------------------
CDMLPF regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Pass through LPF
Bypass LPF
// --------------------------------------
SECDET regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
SECAM not detected
SECAM detected
// --------------------------------------
FSCDET regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
FSC 4.43,4.286 Mhz detected
FSC 3.58 Mhz detected
//
// =============================================
//
KS0127_SAT
Color saturation control
eo_information
1
0 8 unsigned no_flag_overflow
//
value = (
(
( VDL_SATUR < 50 ) ? ( 128 + ( VDL_SATUR * ( 127 / 49 ) ) ) :
( ( VDL_SATUR >= 50 ) ? ( ( VDL_SATUR - 50 ) * ( 127 / 50 ) ) :
0 )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// ( VDL_SATUR < 50 ) ? ( VDL_SATUR * ( 128 / 50 ) ) :
// ( ( VDL_SATUR >= 50 ) ? ( ( VDL_SATUR - 50 ) * ( 127 / 50 ) ) :
// 0 )
// ) ;
//value = (
// ( VDL_SATUR < 50 ) ? ( ( - 128 ) + ( VDL_SATUR * ( 128 / 50 ) ) ) :
// ( ( VDL_SATUR == 50 ) ? 0 :
// ( ( VDL_SATUR > 50 ) ? ( ( VDL_SATUR - 50 ) * ( 127 / 50 ) ) :
// 0 ) )
// ) ;
//
// =============================================
//
KS0127_HUE
Hue control
eo_information
1
0 8 unsigned no_flag_overflow
//
value = (
(
( VDL_HUE < 50 ) ? ( 128 + ( VDL_HUE * ( 127 / 49 ) ) ) :
( ( VDL_HUE >= 50 ) ? ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) :
0 )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// ( VDL_HUE < 50 ) ? ( VDL_HUE * ( 128 / 50 ) ) :
// ( ( VDL_HUE >= 50 ) ? ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) :
// 0 )
// ) ;
//value = (
// ( VDL_HUE < 50 ) ? ( ( - 128 ) + ( VDL_HUE * ( 128 / 50 ) ) ) :
// ( ( VDL_HUE == 50 ) ? 0 :
// ( ( VDL_HUE > 50 ) ? ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) :
// 0 ) )
// ) ;
//
// =============================================
//
// Ajout de registre(s) dans les Fichiers DCF
//
// =============================================
// KS0127
//
// Scaler uses FULL bandwidth, comb is disabled
//
KS0127_VERTIA
Vertical Processing Control A
eo_information
4
// --------------------------------------
VFLTR regular
Luminance Vertical Filter
eo_information
2 3 unsigned flag_overflow
//
value = ( ( VDC_C_COLOR & DEF_NTSC ) ? 0 : 2
) ;
//
define_value
Scaler LPF path, Comb HPF
Scaler Full band, Comb Dis
Scaler Dis, Comb Full band
Scaler LPF path, Comb Dis
Scaler Disable, Comb = HPF
reserved
reserved
reserved
//
//
//..............................
//value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 0 : 2
// ) ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 0 : 2
// ) * DEF_DEC_PATH ;
// --------------------------------------
VRT2X regular
Vertical Scaler Filter Select
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
3-Tap Vertical Scaler Filter
5-Tap Vertical Scaler Filter
// --------------------------------------
YCMBCO regular
Luma Comb Filter Coefficients Selection
eo_information
3 3 unsigned flag_overflow
//
value = ( ( VDC_C_COLOR & DEF_NTSC ) ? 2 : 3 ) ;
//
define_value
[1/4 1/2 1/2]
[3/8 1/2 1/8]
[1/2 1/2 0]
[1 0 0]
[0 1 0]
[1/2 1/2 0]
[0 1/2 1/2]
[1/8 1/2 3/8]
//
//
//..............................
//value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 2 : 3 ) ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 2 : 3 ) * DEF_DEC_PATH ;
// --------------------------------------
MNYCMB regular
Luma Comb Filter Coefficients Mode
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Automatic Luma Comb Filter
Manual Luma Comb Filter
//
// Patch de Jean-Luc pour Vista Medical (SCALING)######################################
//
// ==============================================
//
KS0127_VERTIB
Vertical Processing Control B
eo_information
5
//---------------------------------------------
UNUSED protected
eo_information
0 1 unsigned no_flag_overflow
//
no_define_value
//---------------------------------------------
VSCLEN regular
eo_information
1 2 unsigned flag_overflow
//
value = 1 ;
//
define_value
Vertical scaling Enabled
Vertical scaling Disabled
V. scaling disabled 1-line delay
V. scaling disabled 2-line delay
//---------------------------------------------
HYDEC regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Luma decimation Enabled
Luma decimation Disabled
//---------------------------------------------
HYBWI regular
eo_information
1 1 unsigned flag_overflow
//
value = ( ( VDC_MONO | VDC_SVID ) ? 1 : 0 ) ;
//
define_value
Normal bandwidth
Bandwidth 1MHz Higher
//---------------------------------------------
HYLPF regular
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
define_value
Full bandwidth
4.5MHz bandwidth
3.5MHz bandwidth
2.5MHz bandwidth
1.5MHz bandwidth
reserved
reserved
reserved
//
// =============================================
//
KS0127_VERTIC
Vertical Processing Control C
eo_information
6
//---------------------------------------------
EVAVOD regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Disabled during ODD Field
Enabled during ODD Field
//
//
//..............................
//value = DEF_RGB_PATH ;
//---------------------------------------------
EVAVEV regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Disabled during EVEN Field
Enabled during EVEN Field
//
//
//..............................
//value = DEF_RGB_PATH ;
//---------------------------------------------
VYBW regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Full Bandwidth
Reduced Bandwidth
//---------------------------------------------
ACMBEN regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active comb disabled
Active comb enabled
//---------------------------------------------
CCMBCO regular
eo_information
4 3 unsigned flag_overflow
//
value = ( ( VDC_C_COLOR & DEF_NTSC ) ? 0 : 4 ) ;
//
define_value
Coeff. set [ 1/2 1/2 0 ]
Coeff. set [ 1/4 1/2 1/4 ]
Coeff. set [ 0 1/2 1/2 0 0 ]
Coeff. set [ 0 1/4 1/2 1/4 0 ]
Coeff. set [ 1 0 0 ]
Coeff. set [ 0 1 0 ]
Coeff. set [ 0 0 1 ]
No Output ( Disabled )
//
//
//..............................
//value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 0 : 4 ) ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 0 : 4 ) * DEF_DEC_PATH ;
//---------------------------------------------
MNCCMB regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Filter coeff. automatic
Filter coeff. manual
//
//==============================================
//
KS0127_HSCLL
Horizontal Scaling low byte
eo_information
2
//---------------------------------------------
CMBMOD regular
eo_information
1 1 unsigned flag_overflow
// Always 1
//
value = 1 ;
//
define_value
Comb enabled on COMB_EN
Comb enabled on VAV active
//
//
//..............................
//value = DEF_RGB_PATH ;
// --------------------------------------
//HSCL[6:0] regular
HSCL regular
eo_information
0 7 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_HSCLH
Horizontal Scaling high byte [14:7]
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_VSCLL
Vertical Scaling low byte
eo_information
3
//---------------------------------------------
ACMBRE regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
High Threshold
Low Threshold
// --------------------------------------
ACMBCO regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
100% comb
75% comb
// --------------------------------------
//VSCL[5:0] regular
VSCL regular
eo_information
0 6 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = 0x3F * DEF_RGB_PATH ;
//
//==============================================
//
KS0127_VSCLH
Vertical Scaling high byte [13:6]
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = 0xFF * DEF_RGB_PATH ;
//
//==============================================
//
KS0127_OFMTA
Output Control A
eo_information
3
// --------------------------------------
OFMT regular
eo_information
0 4 unsigned no_flag_overflow
// Always use RGB Format Output
//
value = 0 ;
//
define_value
16 Bits 4:2:2
12 Bits 4:1:1
8 Bits 4:2:2 Not Ref Code
8 Bits 4:2:2 Ref Code
24 Bits 4:4:4
16 Bits RGB 565
24 Bits RGB 888 LBO
24 Bits RGB 888 (565)
8 Bits 4:2:2 EXV
8 Bits 4:2:2 EXV,SAV,EAV
Y ADC all time
Y & C ADC all time
reserved
reserved
reserved
reserved
//
//
//..............................
//value = 9 ;
// --------------------------------------
//HAV,VAV,EVAV,EHAV,PID,ODD,HS1,HS2,VS,HSC
OENC regular
eo_information
3 2 unsigned no_flag_overflow
//
value = ( 3 * DEF_DEC_PATH ) ;
//
define_value
Video Only
(H-V)AV,E(H-V)AV,PID,ODD,HS1-2,VS,HSC
CK,CK2
reserved
// --------------------------------------
GAMEN regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
No Gamma correction
Correction to Y/G data
Correction to U/B & V/R data
Correction to Y/G & U/B & V/R
//
//==============================================
//
KS0127_OFMTB
Output Control B
eo_information
7
// --------------------------------------
EVCK2 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
EVCK regular
eo_information
0 1 unsigned no_flag_overflow
// Always 0 in both Path
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = DEF_RGB_PATH ;
// --------------------------------------
EVEHAV regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
No additionnal qualifier
HAV uses qualifier from EVAND
// --------------------------------------
EVHAV regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
No additionnal qualifier
HAV uses qualifier from EVAND
// --------------------------------------
EVHS1 regular
eo_information
1 1 unsigned no_flag_overflow
// HS1 for Clamping
// Both Path DEC/RGB
//
value = 1 ;
//
define_value
No additionnal qualifier
HS1 uses qualifier from EVAND
//
//
//..............................
//value = 0 ;
// --------------------------------------
EVAND regular
eo_information
3 2 unsigned no_flag_overflow
// HS1 for Clamping
// Both Path DEC/RGB
//
value = 3 ;
//
define_value
Qualifier is logic '0'
Qualifier is EVAV
reserved
Qualifier is VAV
//
//
//..............................
//value = 0 ;
// --------------------------------------
VSVAV regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Output normal VS
VAV is output on VS pin
//
//==============================================
//
KS0127_VBICTL
VBI Decoder Control
eo_information
6
//---------------------------------------------
ODDOS regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
//& HAV,VAV,EVAV,EHAV,PID,ODD,HS1,HS2,VS,HSC
EVENEN regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
ODDEN regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VBINSRT regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VYFMT regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VBCVBS regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_VBIL30
VBI Data Decoding [3:0]
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// 2 Bits :
// 0 = Decode normal video
// 1 = Decode Close Caption data
// 2 = Decode Teletext data
// 3 = Decode SMPTE data
//
//==============================================
//
KS0127_VBIL74
VBI Data Decoding [7:4]
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// 2 Bits :
// 0 = Decode normal video
// 1 = Decode Close Caption data
// 2 = Decode Teletext data
// 3 = Decode SMPTE data
//
//==============================================
//
KS0127_VBIL118
VBI Data Decoding [11:8]
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// 2 Bits :
// 0 = Decode normal video
// 1 = Decode Close Caption data
// 2 = Decode Teletext data
// 3 = Decode SMPTE data
//
//==============================================
//
KS0127_VBIL1512
VBI Data Decoding [15:12]
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// 2 Bits :
// 0 = Decode normal video
// 1 = Decode Close Caption data
// 2 = Decode Teletext data
// 3 = Decode SMPTE data
//
//==============================================
//
KS0127_TTFRAM
Teletext Frame Alignment Pattern
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_UVOFFL
UV Offset Adjustment Low
eo_information
2
// --------------------------------------
//VOFFST[3:0] regular
VOFFST regular
eo_information
0 4 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
//UOFFST[3:0] regular
UOFFST regular
eo_information
0 4 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_UVOFFH
UV Offset Adjustment High
eo_information
3
// --------------------------------------
//VOFFST[5:4] regular
VOFFST regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
//UOFFST[5:4] regular
UOFFST regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
UNUSED protected
eo_information
0 4 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
KS0127_UGAIN
U Component Gain Adjustment
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_VGAIN
V Component Gain Adjustment
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_VAVB
VAV Begin Value
eo_information
3
//---------------------------------------------
VAVEV0 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = DEF_PAL ;
//
no_define_value
//
//
//..............................
// ADD2-3 => Cropping 2 lines on 4 ADD2 => Cropping 1 lines on 4
// A remettre qd FPGA fonctionnera ADD 2 & 3
//value = (
// (
// ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) *
// (
// (
// ( ( VDT_VACTIVE == 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE == 576 ) & DEF_PAL )
// ) |
// (
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_PAL )
// ) * DEF_VACT_NOTSTD_ADD4
// )
// )
// ) +
// (
// ( ! DEF_VACT_NOTSTD_ADD4 ) * ( ( DEF_VAVB_ADD_LOW == 0 ) | ( DEF_VAVB_ADD_LOW == 1 ) ) *
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_PAL )
// )
// )
// ) ;
//
//value = (
// (
// ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) *
// (
// (
// ( ( VDT_VACTIVE == 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE == 576 ) & DEF_50HZ_HV_TOTAL_STD )
// ) |
// (
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_50HZ_HV_TOTAL_STD )
// ) * DEF_VACT_NOTSTD_ADD4
// )
// )
// ) +
// (
// ( ! DEF_VACT_NOTSTD_ADD4 ) * ( ( DEF_VAVB_ADD_LOW == 0 ) | ( DEF_VAVB_ADD_LOW == 1 ) ) *
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_50HZ_HV_TOTAL_STD )
// )
// )
// ) ;
//value = ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) ;
// --------------------------------------
VAVOD0 regular
eo_information
0 1 unsigned no_flag_overflow
// Line Odd Even
// Odd0 0 0 0 \
// Even0 1 1 0 | ==> not supported 1Field of 1 Frame and Second Field Next Frame !
// Odd1 2 1 1 |
// Even1 3 X 1 / ==> not supported 1Field of 1 Frame and Second Field Next Frame !
// Odd0 4 0 0 \
// Even0 5 1 0 | ==> not supported 1Field of 1 Frame and Second Field Next Frame !
// Odd1 6 1 1 |
// Even1 7 X 1 / ==> not supported 1Field of 1 Frame and Second Field Next Frame !
//
value = DEF_PAL ;
//
no_define_value
//
//
//..............................
// Cropping 3 lines on 4
// A remettre qd FPGA fonctionnera ADD 2 & 3
//value = (
// (
// ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) *
// (
// (
// ( ( VDT_VACTIVE == 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE == 576 ) & DEF_PAL )
// ) |
// (
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_PAL )
// ) * DEF_VACT_NOTSTD_ADD4
// )
// )
// ) +
// (
// ( ! DEF_VACT_NOTSTD_ADD4 ) * ( ( DEF_VAVB_ADD_LOW == 0 ) | ( DEF_VAVB_ADD_LOW == 1 ) ) *
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_PAL )
// )
// )
// ) ;
//
//value = (
// (
// ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) *
// (
// (
// ( ( VDT_VACTIVE == 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE == 576 ) & DEF_50HZ_HV_TOTAL_STD )
// ) |
// (
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_50HZ_HV_TOTAL_STD )
// ) * DEF_VACT_NOTSTD_ADD4
// )
// )
// ) +
// (
// ( ! DEF_VACT_NOTSTD_ADD4 ) * ( ( DEF_VAVB_ADD_LOW == 0 ) | ( DEF_VAVB_ADD_LOW == 1 ) ) *
// (
// ( ( VDT_VACTIVE != 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_50HZ_HV_TOTAL_STD )
// )
// )
// ) ;
//value = ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) ;
// --------------------------------------
//VAVB[6:1] regular
VAVB regular
eo_information
3 6 unsigned flag_overflow
// For cropping ONLY by Toucan
//
value = ( 2 + DEF_NTSC ) ;
//
no_define_value
//
//
//..............................
//value = (
// ( ( VDT_VBPORCH / 4 ) + DEF_NTSC ) -
// (
// ( ( ( VDT_VACTIVE != 480 ) & DEF_NTSC ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_PAL )
// ) * ( ! DEF_VACT_NOTSTD_ADD4 )
// )
// ) ;
//
//value = (
// ( ( VDT_VBPORCH / 4 ) + DEF_60HZ_HV_TOTAL_STD ) -
// (
// ( ( ( VDT_VACTIVE != 480 ) & DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE != 576 ) & DEF_50HZ_HV_TOTAL_STD )
// ) * ( ! DEF_VACT_NOTSTD_ADD4 )
// )
// ) ;
//value = ( ( VDT_VBPORCH / 4 ) + DEF_60HZ_HV_TOTAL_STD ) ;
//
//==============================================
//
KS0127_VAVE
VAV End Value [8:1]
eo_information
1
0x81 8 unsigned flag_overflow
// Maximum Vertical Active possible
//
value = (
( 0x81 * DEF_NTSC ) +
( 0x9A * DEF_PAL )
) ;
//
no_define_value
//
//
//..............................
//value = ( ( ( VDT_VBPORCH + VDT_VACTIVE ) / 4 ) + DEF_NTSC ) ;
//
//value = ( ( ( VDT_VBPORCH + VDT_VACTIVE ) / 4 ) + DEF_60HZ_HV_TOTAL_STD ) ;
//value = ( ( ( VDT_VBPORCH + VDT_VACTIVE ) / 4 ) + DEF_60HZ_HV_TOTAL_STD +
// (
// (
// ( ( VDT_VACTIVE < 480 ) * DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE < 576 ) * DEF_50HZ_HV_TOTAL_STD )
// ) &
// (
// ( ( DEF_VAVB_ADD_LOW == 0 ) | ( DEF_VAVB_ADD_LOW == 1 ) ) |
// ( DEF_VACT_NOTSTD_ADD4 & ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) )
// )
// ) -
// (
// (
// ( ( VDT_VACTIVE > 480 ) * DEF_60HZ_HV_TOTAL_STD ) |
// ( ( VDT_VACTIVE > 576 ) * DEF_50HZ_HV_TOTAL_STD )
// ) &
// (
// ( ( DEF_VAVB_ADD_LOW == 2 ) | ( DEF_VAVB_ADD_LOW == 3 ) ) |
// ( DEF_VACT_NOTSTD_ADD4 & ( ( DEF_VAVB_ADD_LOW == 0 ) | ( DEF_VAVB_ADD_LOW == 1 ) ) )
// )
// )
// ) ;
//
// =============================================
//
KS0127_CTRACK
Chroma Tracking Control Register
eo_information
4
// --------------------------------------
CFTC regular
Chroma frequency tracking time constant
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Slower
Slow
Fast
Faster
// --------------------------------------
CGTC regular
Chroma gain tracking time constant
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Slower
Slow
Fast
Faster
// --------------------------------------
DMCTL regular
Chroma demodulation bypass mode
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Chroma demodulation enabled
Bypassed for Dig YCbCr
For Analog YCbCr,Cb phased
For Analog YCbCr,Cr phased
// --------------------------------------
UNUSED protected
Bit 6,7
eo_information
0 2 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
KS0127_POLCTL
Timing signal polarity control
eo_information
8
// --------------------------------------
HS1PL regular
HS1 Polarity
eo_information
0 1 unsigned flag_overflow
// Used for CLAMPING unstead HS2
// Always 0 in both Path
//
value = 0 ;
//
define_value
Active High
Active Low
//
//
//..............................
// Always 1 in both Path
//value = 0x01 ;
// --------------------------------------
VAVPL regular
VAV Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active High
Active Low
// --------------------------------------
HS2PL regular
HS2 Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active High
Active Low
// --------------------------------------
EHAVPL regular
EHAV Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active High
Active Low
// --------------------------------------
HAVPL regular
HAV Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active High
Active Low
// --------------------------------------
ODDPL regular
ODD Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active High
Active Low
//
//
//..............................
//value = 1 ;
// Patch for FPGA => Odd ALWAYS High
// --------------------------------------
VSPL regular
VS Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active High
Active Low
// --------------------------------------
EVAVPL regular
EVAV Polarity
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Active High
Active Low
//
// =============================================
//
KS0127_REFCOD
Reference Code Insertion Control
eo_information
3
// --------------------------------------
GENLIM regular
Loop filter for Horizontal trcking loop
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
No limiter
Large range limiter
Medium range limiter
Small range limiter
// --------------------------------------
reserved protected
eo_information
9 5 unsigned flag_overflow
//
no_define_value
// --------------------------------------
YCRANG regular
Digital video output range control
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Y=(1 -254) C=(1 -254)
Y=(16-235) C=(16-240)
//
//==============================================
//
KS0127_INVALY
Invalid Y Code
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_INVALU
Invalid U Code
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_INVALV
Invalid V Code
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_UNUSEY
Unused Y Code
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_UNUSEU
Unused U Code
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
KS0127_UNUSEV
Unused V Code
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
KS0127_EXCTRL
Additional Tracking related controls
eo_information
7
// --------------------------------------
CLEVEL regular
Programmable CKILL level select but
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Chroma level is 11 IRE
Chroma level is 5.5 IRE
// --------------------------------------
BISTE regular
Test Bit for BIST Mode
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Memory fault detected
Memory correct/functional
// --------------------------------------
BISTM regular
Bist Memory Test Mode Enable
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal mode.Bist not operation
Bist En, memory test started
// --------------------------------------
AUCPWD regular
Auto Chroma ADC power down mode enabled when appropriate input format selected
eo_information
1 1 unsigned flag_overflow
// To prevent Noise Horizontal dark lines moving up in picture.
//
value = 1 ;
//
define_value
During Chip Pwr down mode
When CVBS input or case '0'
//
//
//..............................
//value = 0 ;
// --------------------------------------
ALTHAV regular
Allows HS2 to be HAV control during this VBI interval
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
HAVB/HAVE = HAV all frame
HS2B,HS2E = HAV (VAV low)
// --------------------------------------
TREE regular
Input and Bidirectional pin for test of VOH/VOL/VIH/VIL.PAL nand tree controlled by this bit
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal PAD Operation
Nand tree operation mode
// --------------------------------------
ENINCST regular
Scaler enable control bit during VBI
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Scaler ON during VBI interval
Scaler OFF during VBI interval
//
// =============================================
//
KS0127_TRACKA
Additional Tracking related controls
eo_information
7
// --------------------------------------
AGCLSB regular
AGC LSB for control of the 9 bits AGC gain value
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Write 0 if AGC_FR = 1
Write 1 if AGC_FR = 1
// --------------------------------------
VBCTRAP regular
Chroma trap enabled during the vertical blanking interval
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
CTRAP Control Only
Chroma trap En during VBLANK
// --------------------------------------
ATCTRAP regular
Auto Chroma Trap on luma path when VCR input detected
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
CTRAP Control Only
CTRAP En if VCR Detected
// --------------------------------------
VCRLEV regular
Set the Fh variation from nominal for detection of VCR type input
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
50 PPMI
100 PPM
200 PPM
400 PPM
// --------------------------------------
VCRDET regular
Detect input that is not SCH locked such as consumer type VCR
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
SCH Locked Video
Color Burst Not Locked to Fh
// --------------------------------------
MACDET regular
Macrovision Encoded Data detected as input video source
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Standard Video Decoded
Macrovision Encoded detected
// --------------------------------------
STCTRL regular
State Machine transition control
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal state machine transitions
Sync level removed for lock
//
// =============================================
//
KS0127_SHS1A
User Defined SHS1 A
eo_information
7
// --------------------------------------
COFFENB regular
Disable control for the Cpath Clamp control
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
C Chroma clamp normal
C Chroma clamp Disabled
// --------------------------------------
YOFFENB regular
Disable control for the Y path Clamp control
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Y Luma clamp normal
Y Luma clamp Disabled
// --------------------------------------
CCOVFL regular
Defines when the current CCDAT1,2 data has over written previous data that was not read
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Data valid
Data Overflow
// --------------------------------------
NEWCC regular
Defines when new Closed Caption data is ready for reading from the CCDAT1,2 bytes
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Current Data readed
Current Data new
// --------------------------------------
//Current Line enabled for Raw ADC Output
VBIMID regular
Change function of WSS enable(per line bases during VBI) to aRAW CVBS enable
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Current Line En for WSS Slicing
Enabled for Raw ADC Out
// --------------------------------------
TTSYS regular
Select Teletext input system when auto detect is not possible
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Auto Teletext Select
Teletext System B
Teletext System C
Teletext System D
// --------------------------------------
VBISWAP regular
Reversed the bit order for data output from the Closed caption or Teletext slicer
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
1st Bit Slice = MSB
1st Bit Slice = LSB
//
// =============================================
//
KS0127_TRACKB
Tracking Configuration Controls
eo_information
7
// --------------------------------------
AGCLKG regular
AGC Gain tracking Loop time constant for initial tracking mode
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Steady State time constant
2X Faster
// --------------------------------------
AGCLPG regular
AGC Gain Steady State tracking Loop time constant
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Slowest
Slow
Fast
Fastest
// --------------------------------------
//VS adjusts with all sync phase changes
VNOISCT regular
Vertical Sync noise control Enable
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
VS adjusts sync phase change
VS adjusts 4 lines phase error
// --------------------------------------
PHCTRL regular
Controls Phase detector response
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Syncs After the "0" Pt Ref
Syncs Prior the "0" Pt Ref
// --------------------------------------
VBIFR regular
Disables Frequency compensation for VCR head switch lines only.
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Frq tracking independent Ctrl
Disabled for VCR head Sw lines
// --------------------------------------
VBIPH regular
Enable Phase compensation for VCR head switch lines only
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Phase independent of Ctrl
Disabled for VCR head Sw lines
// --------------------------------------
ALT656 regular
Alternate 656 Vertical blank location for 50Hz data
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Vblank = ITU656 Spec
Vblank = 60 Hz
//
// =============================================
//
KS0127_RTC
Tracking Configuration Controls
eo_information
4
// --------------------------------------
TDMOD regular
Test Bit chroma demodulation mode
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
Test mode
// --------------------------------------
EN regular
RTC Enable Control
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Slowest
Slow
// --------------------------------------
PID regular
Polarity control for PAL ID transferred within RTC data stream
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Same Polarity as PID pin
Inverted Polarity
// --------------------------------------
DTO regular
Enables a DTO reset inside the KS0127B and send a DTO reset within the RTC data stream.
Function is activated on the rising edge of RTC_DTO
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Function Disabled
Function En 1 time when set 1
//
// =============================================
//
KS0127_CMDE
Command Register E
eo_information
4
// --------------------------------------
CHIPREVID regular
Four additionnal bits for determination of current Revision and differentiation from the KS0127
eo_information
9 4 unsigned flag_overflow
//
value = 9 ;
//
define_value
KS0127 ALL Revisions
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
KS0127S Revision A
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
HCORE regular
Luma Path Horizontal Coring.Noise Limiter for High frequency portion of Luma
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Coring function Disabled
+/- 1 Bit of Coring
+/- 2 Bit of Coring
+/- 4 Bit of Coring
// --------------------------------------
VSALG regular
Vertical Scaling line dropping algorithm
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vscaling = lines Odd and Even
Vscaling = final de-interl. video
// --------------------------------------
ODFST regular
Alternate the first scaling line between Odd and Even fields
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
First scaled field = ODD
First scaled field = EVEN
//
// =============================================
//
KS0127_VSDEL
VS Delay Control
eo_information
3
// --------------------------------------
VSDEL regular
Vertical sync delay [5:0]
eo_information
0 6 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
NOVIDC regular
Allows No Video detection bit to be output to PORTB(Pin24)
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
No Output (DATAB[2:0],DIRB=1)
// --------------------------------------
TRMS regular
Enable alternative initial tracking mode state machine
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
Varable tracking locking time
//
// =============================================
//
KS0127_CMDF
Command Register F
eo_information
8
// --------------------------------------
CBWI regular
Chroma bandwidth increase
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal Chroma Bandwidth
Increase Chroma Bandwidth
// --------------------------------------
TASKB regular
Select between task A and B as described in "VIP Specification V. 1.0".
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Select CCIR 656 Timing codes
Select between Task A and B
// --------------------------------------
REGUD regular
Control Register update control
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Updated after been writen
Only start VS after written to
// --------------------------------------
UVDLSL regular
U or V delay control when UVDLEN is set to 1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
V delayed by 1 CK period
U delayed by 1 CK period
// --------------------------------------
UVDLEN regular
Enable the function of UVDLSL
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
UVDLSL Disable
UVDLSL Enable
// --------------------------------------
EVAVY regular
Control the Output of INVALY,INVALU,INVALV codes when EVAV is inactive
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Codes not affected by EVAV
Outputed codes = EVAV inactive
// --------------------------------------
VIPMODE regular
Allows transfer of hardware sliced VBI data as ancillary data during the following lines
horizontal blanking period.
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Std KS0127 original VBI transfer
Optional Ancillary VBI transfer
// --------------------------------------
TRAPFSC regular
Enable Chroma trap location based on FSC Frequency instead of field rate
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Chroma Trap = on Field rate
Chroma Trap = Fsc Freq
//
// --------------------------------------
//
// Fin de la patch de Jean-Luc pour Vista Medical (SCALING)############################
//
//
// *********************************************
// KS0127 Chip (end)
// *********************************************
//
//
// *********************************************
// ADV7185 Chip (Begin)
// *********************************************
//
// =============================================
//
ADV7185_INPUTCTL
Input Control
eo_information
2
// --------------------------------------
INSEL regular
eo_information
0 4 unsigned flag_overflow
//INSEL[3:0]
//
value = (
( ( VDC_MONO | VDC_C_COLOR | VDC_RGB_COL ) * DEF_INFO_INPUT ) +
( VDC_SVID * ( 6 + ( DEF_INFO_INPUT / 3 ) ) )
) ;
//
define_value
CVBS = A1
CVBS = A2
CVBS = A3
CVBS = A4
CVBS = A5
CVBS = A6
S-VIDEO Y1=A1 C1=A4
S-VIDEO Y2=A2 C2=A5
S-VIDEO Y3=A3 C3=A6
YUV Y1=A1 U1=A4 V1=A5
YUV Y2=A2 U2=A3 V2=A6
reserved
reserved
reserved
reserved
reserved
//
//
//..............................
//value = (
// ( ( DEF_MONO_VIA_DEC | VDC_C_COLOR ) * DEF_INFO_INPUT ) +
// ( VDC_SVID * ( 6 + DEF_INFO_INPUT ) )
// ) ;
//value = (
// ( ( DEF_MONO_VIA_DEC | VDC_C_COLOR ) * DEF_INFO_INPUT * DEF_4SIGHT ) +
// ( VDC_SVID * DEF_4SIGHT * ( 6 + DEF_INFO_INPUT ) )
// ) ;
// --------------------------------------
VIDSEL regular
eo_information
5 4 unsigned flag_overflow
//VIDSEL[3:0]
//Auto Detect PAL_BGHID/NTSC_M Pedestal or Not
// Always Detection enable when use RGB Path because sync.'s detection.
//
value = ( ( DEF_NTSC * 5 ) + ( DEF_PAL * 8 ) ) ;
//
define_value
Auto(Pal_bghid/Ntsc_m)
Auto(Pal_bghid/Ntsc_m)Pedest
Auto(Pal_n/Ntsc_m)less Pedest.
Auto(Pal_n/Ntsc_m)Pedestal
Ntsc_m without pedestal
Ntsc_m with pedestal
Ntsc 4.43 without pedestal
Ntsc 4.43 with pedestal
Pal_bghi without pedestal
Pal_n(=bghi without pedest)
Pal_m without pedestal
Pal_m with pedestal
Pal combination N
Pal combination N pedestal
reserved
reserved
//
//
//..............................
//value = (
// ( DEF_NTSC * ( 5 - ( 4 * OPTION_4SIGHT_II_RGB ) ) ) +
// ( DEF_PAL * 8 * OPTION_4SIGHT_II_STD )
// ) ;
//value = ( DEF_NTSC ? 5 : 8 ) ;
//value = ( DEF_NTSC ? 1 : 0 ) ;
//value = ( ( DEF_NTSC & DEF_DEC_PATH ) ? 1 : 0 ) ;
//value = ( VDL_PEDEST * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_VIDEOSEL
Video Selection
eo_information
7
// --------------------------------------
VIDQUAL regular
eo_information
0 2 unsigned flag_overflow
//VIDQUAL[1:0]
// Bug by RGB Path with FPGA where first lines quit shifted in some example MIL => TV quality
//
value = DEF_RGB_PATH ;
//
define_value
Broadcast quality Std
TV quality
VCR quality
Broadcast quality
//
//
//..............................
//value = 0 ;
//value = ( 3 * DEF_DEC_PATH ) ;
// --------------------------------------
SQPE regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
STD CCIR656 27Mhz
Square Pixel ON
//
//
//..............................
//value = DEF_4SIGHT ;
//value = 0 ;
// --------------------------------------
DIFFIN regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Differential input OFF
Differential input ON
//
//
//..............................
//value = 0 ;
// --------------------------------------
4FSE regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Standard Video
4Fsc mode op.(NTSC Only)
// --------------------------------------
BETACAM regular
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
MII/SMPTE YCrCb
Betacam
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
ASE regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Re-Acquire OFF
Re-Acquire ON
//
//
//..............................
//value = 1 ;
//value = DEF_4SIGHT ;
//
// =============================================
//
ADV7185_VIDEOENCTL
Video Enhancement Control
eo_information
3
// --------------------------------------
YPM regular
eo_information
4 3 unsigned flag_overflow
//YPM[2:0]
//
value = 4 ;
//
define_value
PC1/PS1
PC1/PS1
PC1/PS2
PC2/PS3
PC3/PS4
PC4/PS5
PC5/PS6
PC6/PS6
//
//
//..............................
//value = 4 * DEF_4SIGHT ;
// --------------------------------------
COR regular
eo_information
0 2 unsigned flag_overflow
//COR[1:0]
//
value = 0 ;
//
define_value
No Coring
Truncate Y < Black +8
Truncate Y < Black +16
Truncate Y < Black +32
//
// --------------------------------------
reserved protected
eo_information
0 3 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
ADV7185_OUTPUTCTL
Output Control
eo_information
4
// --------------------------------------
OMSEL regular
eo_information
0 2 unsigned flag_overflow
//OMSEL[1:0]
//
value = 0 ;
//
define_value
HV=HVs,HVref=HVref,DV,GL
HV=HVact,HVref=HVrst,Dvalid
HV=HVact,HVref=HVrst,RD,Dvalid
reserved
// --------------------------------------
OFSEL regular
eo_information
3 4 unsigned flag_overflow
//OFSEL[3:0]
//
value = 3 ;
//
define_value
10 Bits 4:2:2
20 Bits 4:2:2
16 Bits 4:2:2
8 Bits 4:2:2
12 Bits 4:1:1
10 Bits 4:2:2/Dig. Comp.
8 Bits 4:2:2/10 Dig. Comp.
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
//
//..............................
//value = 3 * DEF_4SIGHT ;
// --------------------------------------
TOD regular
eo_information
0 1 unsigned flag_overflow
// Overwritten by Driver dependently module type
//
value = DEF_RGB_PATH ;
//
define_value
Follow OE/
Always Tri-State
//
//
//..............................
//value = 0 ;
// --------------------------------------
VBIEN regular
eo_information
0 1 unsigned flag_overflow
// VBI Lines 1_21 Enabled = 1
// When set to 1 :
// => Pal:1st Line right shifted. | Ntsc:1st Line data brighter than suppose to be.
//MUST BE ZERO
//
value = 0 ;
//
define_value
All Video lines included
No scaling/filtering lines
//
//
//..............................
//value = 1 ;
//
//=============================================
//
ADV7185_EXTOUTCTL
Extended Output Control
eo_information
3
// --------------------------------------
RANGE regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Luma(16-235)/Chroma(16-240)
Luma(1 -254)/Chroma(1 -254)
//
// --------------------------------------
reserved protected
eo_information
6 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
BT656 regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
BT656-3 V=Low (Lines 10 & 273)
BT656-4 V=Low (Lines 20 & 283)
//
//
//..............................
//value = 0 ;
//
// =============================================
//
ADV7185_GENPURPOUT
General Purpose Output
eo_information
8
// --------------------------------------
GPO0 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Low
High
// --------------------------------------
GPO1 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Low
High
// --------------------------------------
GPO2 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Low
High
// --------------------------------------
GPO3 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Low
High
// --------------------------------------
GPEL regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Outputs(1:0) Tri-State
Outputs(1:0) Enabled
//
//
//..............................
//value = 0 ;
// --------------------------------------
GPEH regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Outputs(3:2) Tri-State
Outputs(3:2) Enabled
//
//
//..............................
//value = 0 ;
// --------------------------------------
BLCVBI regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Output CrCb during VBI Lines
Blank CrCb during VBI Lines
//
//
//..............................
//value = 0 ;
// --------------------------------------
HLEN regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
GPO[0] = General purpose output
GPO[0] = HLOCK bit status
//
//
//..............................
//value = 0 ;
//
// =============================================
//
ADV7185_FIFOCTL
FIFO Control
eo_information
4
// --------------------------------------
FFM regular
eo_information
8 5 unsigned no_flag_overflow
//FFM[4:0]
//
value = 8 ;
//
no_define_value
//
//
//..............................
//value = 4 ;
//value = 4 * DEF_4SIGHT ;
// --------------------------------------
FR regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
Reset FIFO
// --------------------------------------
AFR regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
NO automatic Reset
Reset FIFO End Field
// --------------------------------------
FFST regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Not Self Timed (CLKIN)
Self Timed (27Mhz)
//
//
//..............................
//value = 1 ;
//
// =============================================
//
ADV7185_CONTCTL
Contrast control
eo_information
1
0x80 8 unsigned no_flag_overflow
//CON[7:0]
//
value = ( ( ( ( VDL_CONTR * 255 ) / 100 ) + 0.5 ) & 0xFF ) ;
//
no_define_value
//
//
//..............................
//value = ( ( ( ( VDL_CONTR * 255 ) / 100 ) + 0.5 ) * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_SATCTL
Color saturation control
eo_information
1
0x80 8 unsigned no_flag_overflow
//SAT[7:0]
//
value = ( ( ( ( VDL_SATUR * 255 ) / 100 ) + 0.5 ) & 0xFF ) ;
//
no_define_value
//
//
//..............................
//value = ( ( ( ( VDL_SATUR * 255 ) / 100 ) + 0.5 ) * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_BRIGHTCTL
Brightness control
eo_information
1
0 8 unsigned no_flag_overflow
//BRI[7:0]
//
value = (
(
( VDL_BRGHT < 50 ) ? ( 128 + ( VDL_BRGHT * ( 127 / 49 ) ) ) :
( ( VDL_BRGHT >= 50 ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
0 )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// ( ( VDL_BRGHT < 50 ) & DEF_4SIGHT ) ? ( 128 + ( VDL_BRGHT * ( 127 / 49 ) ) ) :
// ( ( ( VDL_BRGHT >= 50 ) & DEF_4SIGHT ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
// 0 )
// ) ;
//
// =============================================
//
ADV7185_HUECTL
Hue control
eo_information
1
0 8 unsigned no_flag_overflow
//HUE[7:0]
//
value = (
(
( VDL_HUE < 50 ) ? ( 128 + ( VDL_HUE * ( 127 / 49 ) ) ) :
( ( VDL_HUE >= 50 ) ? ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) :
0 )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// ( ( VDL_HUE < 50 ) & DEF_4SIGHT ) ? ( 128 + ( VDL_HUE * ( 127 / 49 ) ) ) :
// ( ( ( VDL_HUE >= 50 ) & DEF_4SIGHT ) ? ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) :
// 0 )
// ) ;
//
// =============================================
//
ADV7185_DEFVALY
Default Value Y
eo_information
3
// --------------------------------------
DEFVALEN regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Don't force Default
Use Default Y Cr Cb
// --------------------------------------
DEFAUTOEN regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Not Default /Lock lost
Default YCrCb/Lock lost
//
//
//..............................
//value = DEF_4SIGHT ;
// --------------------------------------
DEFY regular
eo_information
4 6 unsigned no_flag_overflow
//DEFY[5:0]
//
value = 4 ;
//
no_define_value
//
//
//..............................
//value = ( 4 * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_DEFVALC
Default Value C
eo_information
1
0x18 8 unsigned no_flag_overflow
//DEFC[7:0]
//
value = 0x18 ;
//
no_define_value
//
//
//..............................
//value = ( 0x88 * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_TEMPDEC
Temporal Decimation
eo_information
4
// --------------------------------------
TDE regular
eo_information
0 1 unsigned no_flag_overflow
// In Register Table BUT NOT documented !
//
value = 0 ;
//
no_define_value
// --------------------------------------
TDC regular
eo_information
0 2 unsigned no_flag_overflow
//TDC[1:0]
//
value = 0 ;
//
define_value
Suppress frames,start EVEN
Suppress frames,start ODD
Suppress EVEN Fields Only
Suppress ODD Fields Only
// --------------------------------------
TDR regular
eo_information
0 4 unsigned no_flag_overflow
//TDR[3:0]
//
value = 0 ;
//
define_value
Skip NO Fld/Frm
Skip 1 Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip ... Fld/Frm
Skip NO Fld/Frm
//
// --------------------------------------
reserved protected
eo_information
0 1 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
ADV7185_POWERMAN
Power Management
eo_information
7
// --------------------------------------
PSC regular
eo_information
0 2 unsigned no_flag_overflow
//PSC[1:0]
//
value = 0 ;
//
define_value
Normal Operation
En Pwr saving CVBS
En Power down
En Fast Power saving
// --------------------------------------
PDBP regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
PWRDN Pin
Bit 5 (POWERMAN)
// --------------------------------------
PSREF regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Voltage Reference Normal Op
Power save mode
// --------------------------------------
PSCG regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
LLC Clock Normal Operation
LLC Clock Power Save mode
// --------------------------------------
PWRDN regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
PWRDN Ultra low current
// --------------------------------------
TRAQ regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
Start re-acquire video
// --------------------------------------
RES regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Normal Operation
Reset to default values
//
// =============================================
//
ADV7185_ANACLCTL
Analog Clamp control
eo_information
5
// --------------------------------------
FICL regular
eo_information
0 2 unsigned no_flag_overflow
//FICL[1:0]
//
value = 0 ;
//
define_value
Fine current Clamp 16 Clks
Fine current Clamp 32 Clks
Fine current Clamp 64 Clks
Fine current Clamp 128 Clks
// --------------------------------------
FACL regular
eo_information
0 2 unsigned no_flag_overflow
//FACL[1:0]
//
value = 0 ;
//
define_value
Fast current Clamp 16 Clks
Fast current Clamp 32 Clks
Fast current Clamp 64 Clks
Fast current Clamp 128 Clks
//
//
//..............................
//value = ( 2 * DEF_4SIGHT ) ;
// --------------------------------------
CCLEN regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Current clamp disabled
Current clamp enabled
//
//
//..............................
//value = DEF_4SIGHT ;
// --------------------------------------
VCLEN regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Voltage clamp disabled
Voltage clamp enabled
// --------------------------------------
reserved protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
ADV7185_DIGCLCTL1
Digital Clamp control 1
eo_information
4
// --------------------------------------
// DCC0[11-8]
DCCO regular
eo_information
0 4 unsigned no_flag_overflow
//Manual Clamp OFFset
//
value = 0x0 ;
//
no_define_value
//
//
//..............................
//value = ( 0xf * DEF_4SIGHT ) ;
// --------------------------------------
DCFE regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Dig clamp loop operational
Dig clamp loop frozen
// --------------------------------------
DCT regular
eo_information
3 2 unsigned no_flag_overflow
//DCT[1:0]
//
value = 3 ;
//
define_value
Slow clamp timing ( 1Sec)
Medium clamp timing (.5Sec)
Fast clamp timing (.1Sec)
Dependent VID_QUAL Selected
//
//
//..............................
//value = ( 3 * DEF_4SIGHT ) ;
// --------------------------------------
DCCM regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Automatic Dig. clamp Enabled
Manual offset correction
//
// =============================================
//
ADV7185_DIGCLCTL2
Digital Clamp control 2
eo_information
1
0 8 unsigned no_flag_overflow
// DCCO[7-0]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_SHAPFILCTL
Shaping Filter Control
eo_information
2
// --------------------------------------
YSFM regular
eo_information
18 5 unsigned no_flag_overflow
//YSFM[4:0]
//
value = ( 18 - ( 17 * DEF_PAL * VDC_C_COLOR ) + ( 9 * DEF_NTSC * VDC_C_COLOR ) ) ;
//
no_define_value
// Maximum 16 Items ? no more ?
//Auto selection Wide Notch
//Auto selection Narrow Notch
//SVHS1
//SVHS2
//SVHS3
//SVHS4
//SVHS5
//SVHS6
//SVHS7
//SVHS8
//SVHS9
//SVHS10
//SVHS11
//SVHS12
//SVHS13
//SVHS14
//SVHS15
//SVHS16
//SVHS17
//PAL NN1
//PAL NN2
//PAL NN3
//PAL WN1
//PAL WN2
//NTSC NN1
//NTSC NN2
//NTSC NN2
//NTSC WN1
//NTSC WN2
//NTSC WN3
//reserved
//reserved
//
//
//..............................
//value = ( 18 + ( 3 * DEF_PAL * VDC_C_COLOR ) + ( 8 * DEF_NTSC * VDC_C_COLOR ) ) ;
//value = 1 ;
//value = DEF_4SIGHT ;
// --------------------------------------
CSFM regular
eo_information
2 3 unsigned no_flag_overflow
//CSFM[2:0]
//
value = ( 2 + ( 4 * DEF_NTSC * VDC_C_COLOR ) ) ;
//
define_value
Filter response 1.5 Mhz
Filter response 2.17 Mhz
SH1
SH2
SH3
SH4
SH5
reserved
//
//
//..............................
//value = 2 ;
//value = 0 ;
//
// =============================================
//
ADV7185_MISCCTL
Comb Filter control
eo_information
2
// --------------------------------------
//reserved protected
reserved regular
eo_information
4 7 unsigned no_flag_overflow
//
value = ( ( DEF_PAL & VDC_C_COLOR ) ? 8 :
( VDC_SVID ? 0 :
4 )
) ;
//
no_define_value
//
//
//..............................
//value = ( 4 + ( 4 * DEF_PAL * VDC_C_COLOR ) ) ;
//16 7 unsigned no_flag_overflow
// --------------------------------------
MVE regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
No clamp freezing
Freeze clamp in window of MacroVision
//
// =============================================
//
ADV7185_SCACROMSB
Scaling/Cropping MSB
eo_information
6
// --------------------------------------
SCE regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Scaling Disabled
Scaling Enabled
// --------------------------------------
reserved protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
//
AVDP regular
eo_information
2 2 unsigned no_flag_overflow
//AVDP[9:8]
// Hor. & Vert. Cropping by FPGA
//
value = ( ( DEF_NTSC * 2 ) + ( DEF_PAL * 3 ) ) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDT_HACTIVE >> 8 ) * ( VDT_HACTIVE <= 1023 ) ) ;
// --------------------------------------
AVHB9 regular
eo_information
0 1 unsigned no_flag_overflow
//AVHB[9]
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( ( VDT_HSYNC + VDT_HBPORCH ) >> 8 ) ;
// --------------------------------------
AVVB8 regular
eo_information
0 1 unsigned no_flag_overflow
//AVVB[8]
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( ( VDT_VSYNC + VDT_VBPORCH ) >> 8 ) ;
// --------------------------------------
AVDL8 regular
eo_information
0 1 unsigned no_flag_overflow
//AVDL[8]
// NTSC = 0xF0 PAL = 0x120
//
value = DEF_PAL ;
//
no_define_value
//
//
//..............................
//value = ( ( VDT_VACTIVE / 2 ) >> 8 ) ;
//
// =============================================
//
ADV7185_ACTVIDDESLINES
Active Video Desired Lines
eo_information
1
0xf3 8 unsigned no_flag_overflow
//AVDL[7:0]
//
value = ( ( DEF_NTSC * 0xF3 ) + ( DEF_PAL * 0x20 ) ) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDT_VACTIVE / 2 ) & 0xFF ) ;
//
// =============================================
//
ADV7185_ACTVIDVERTBEG
Active Video Vertical Begin
eo_information
1
0x1f 8 unsigned no_flag_overflow
//AVVB[7:0]
//
value = ( ( DEF_NTSC * 0x1f ) + ( DEF_PAL * 0x20 ) ) ;
//
no_define_value
//
//
//..............................
//**********************
// A VERIFIER !
//**********************
////value = ( ( VDT_VSYNC + VDT_VBPORCH - 8 - ( DEF_PAL * 7 ) ) & 0xFF ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH ) & 0xFF ) ;
//
// =============================================
//
ADV7185_VERTSCALEVAL1
Vertical Scale Value 1
eo_information
2
// --------------------------------------
VSCV regular
eo_information
1 3 unsigned no_flag_overflow
//AVDL[10:8]
// Scale = 1
//
value = 1 ;
//
no_define_value
//
//
//..............................
//value = DEF_NTSC ;
// --------------------------------------
reserved protected
eo_information
0 5 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
ADV7185_VERTSCALEVAL2
Vertical Scale Value 2
eo_information
1
0 8 unsigned no_flag_overflow
//VSCV[7:0]
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( DEF_PAL * 0xFF ) ;
//
// =============================================
//
ADV7185_ACTVIDHORBEG
Active Video Horizontal Begin
eo_information
1
0x43 8 unsigned no_flag_overflow
//AVHB[7:0]
// Horizontal cropping by 2 pix. for 4SightII by Decoder Path ONLY
//
value = (
(
(
( DEF_ORION | DEF_MORPHIS ) *
( VDT_HSYNC + VDT_HBPORCH - 51 - ( DEF_PAL * 29 ) )
) +
(
( DEF_4SIGHT * DEF_DEC_PATH ) *
( ( VDT_HSYNC + VDT_HBPORCH + 16 - ( DEF_PAL * 22 ) ) / 2 )
) +
(
DEF_4SIGHT * DEF_RGB_PATH *
( ( DEF_NTSC * 0x43 ) + ( DEF_PAL * 0x4A ) )
)
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// (
// (
// DEF_ORION *
// ( VDT_HSYNC + VDT_HBPORCH - 51 - ( DEF_PAL * 29 ) )
// ) +
// (
// ( DEF_4SIGHT * DEF_DEC_PATH ) *
// ( ( VDT_HSYNC + VDT_HBPORCH + 16 - ( DEF_PAL * 22 ) ) / 2 )
// ) +
// (
// DEF_4SIGHT * DEF_RGB_PATH *
// ( ( DEF_NTSC * 0x43 ) + ( DEF_PAL * 0x4A ) )
// )
// ) & 0xFF
// ) ;
//
// =============================================
//
ADV7185_ACTVIDDESPIX
Active Video Desired Pixel
eo_information
1
0x80 8 unsigned no_flag_overflow
//AVDP[7:0]
// NTSC=0x280 PAL=0x300
//
value = ( DEF_NTSC * 0x80 ) ;
//
no_define_value
//
//
//..............................
//value = ( ( VDT_HACTIVE & 0xFF ) * ( VDT_HACTIVE <= 1023 ) ) ;
//
// =============================================
//
ADV7185_HORSCALEVAL1
Horizontal Scale Value 1
eo_information
1
0xa 8 unsigned no_flag_overflow
//HSCV[15:8]
//Scale = 1
// Future equation
//
value = ( ( DEF_NTSC * 0xA ) + ( DEF_PAL * 0x8 ) ) ;
//
no_define_value
//
// =============================================
//
ADV7185_HORSCALEVAL2
Horizontal Scale Value 2
eo_information
1
0x81 8 unsigned no_flag_overflow
//HSCV[7:0]
//Scale = 1
// Future equation
//
value = ( ( DEF_NTSC * 0x81 ) + ( DEF_PAL * 0xAE ) ) ;
//
no_define_value
//
//
//..............................
//value = ( ( DEF_NTSC * 0x9A ) + ( DEF_PAL * 0xAA ) ) ;
//
// =============================================
//
ADV7185_COLSUBCARCTL1
Color Subcarrier Control 1
eo_information
3
// --------------------------------------
CSMF regular
eo_information
0 4 unsigned no_flag_overflow
//CSMF[27:24]
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( 0xb * DEF_4SIGHT ) ;
// --------------------------------------
CSM regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Manual FSC Disabled
FSC = CSMF(27:0)
// --------------------------------------
reserved protected
eo_information
7 3 unsigned no_flag_overflow
no_define_value
//
// =============================================
//
ADV7185_COLSUBCARCTL2
Color Subcarrier Control 2
eo_information
1
0 8 unsigned no_flag_overflow
//CSMF[23:16]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_COLSUBCARCTL3
Color Subcarrier Control 3
eo_information
1
0 8 unsigned no_flag_overflow
//CSMF[15:8]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_COLSUBCARCTL4
Color Subcarrier Control 4
eo_information
1
0 8 unsigned no_flag_overflow
//CSMF[7:0]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_PIXDELAYCTL
Pixel Delay Control
eo_information
4
// --------------------------------------
reserved protected
eo_information
0 3 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
CTA regular
eo_information
4 3 unsigned no_flag_overflow
//CTA[2:0]
//
value = 4 ;
//
define_value
reserved
Chroma 2 pix dly from Luma
Chroma 1 pix dly from Luma
No delay Chroma or Luma
Luma 1 pix dly from Chroma
Luma 2 pix dly from Chroma
Luma 3 pix dly from Chroma
reserved
//
//
//..............................
//value = 3 ;
//value = ( 3 * DEF_4SIGHT ) ;
// --------------------------------------
reserved protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
SWPC regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
No swap of Cr & Cb
Swap Cr & Cb values
//
// =============================================
//
ADV7185_MANCLKCTL1
Manual Clock Control 1
eo_information
5
// --------------------------------------
CLKVAL16 regular
eo_information
0 1 unsigned no_flag_overflow
//CLKVAL[16]
//
value = 0 ;
//
no_define_value
// --------------------------------------
CLKVAL17 regular
eo_information
0 1 unsigned no_flag_overflow
//CLKVAL[17]
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
CLKMANE regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Out Clk Freq. = Video (LLC1)
Out Clk Freq. = CLKVAL(17:0)
// --------------------------------------
FIX27E regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Output CLK = Line locked (LLC1 & LLC2)
Output CLK = 27 Mhz
//
// =============================================
//
ADV7185_MANCLKCTL2
Manual Clock Control 2
eo_information
1
0 8 unsigned no_flag_overflow
//CLKVAL[15:8]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_MANCLKCTL3
Manual Clock Control 2
eo_information
1
0 8 unsigned no_flag_overflow
//CLKVAL[7:0]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_AUTOCLKCTL
Auto Clock Control
eo_information
1
0xa0 8 unsigned no_flag_overflow
//
value = 0xA0 ;
//
no_define_value
//
// =============================================
//
ADV7185_AGCMODECTL
AGC Mode Control
eo_information
4
// --------------------------------------
CAGC regular
eo_information
2 2 unsigned no_flag_overflow
//CGAC[1:0]
//
value = 2 ;
//
define_value
Fixed Chroma Gain=CMG(11:0)
Luma gain used for Chroma
Automatic Chroma gain
Freeze Chroma gain
//
//
//..............................
//value = ( 2 * DEF_4SIGHT ) ;
// --------------------------------------
reserved protected
eo_information
3 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
LAGC regular
eo_information
5 3 unsigned no_flag_overflow
//LAGC[2:0]
// Sync. problem in monochrone for ADV7185 RS170/CCIR
//
value = 2 ;
//
define_value
Fixed Luma Gain=LMG(11:0)
No overide manual maxIRE
Auto over. manual maxIRE
No overide auto maxIRE
Auto overide auto maxIRE
Active video white peak
Active video average video
Freeze Luma gain
//
//
//..............................
//value = 4 ;
//value = ( 5 - VDC_MONO ) ;
//value = 5 ;
//value = 4 ;
//value = DEF_4SIGHT ;
// --------------------------------------
reserved protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
ADV7185_CHROGAINCTL1
Chroma Gain Control 1
eo_information
3
// --------------------------------------
GMG regular
eo_information
8 4 unsigned no_flag_overflow
//CMG[11:8] Highest 4 Bits
// Set Half gain value to correct Decoder's bug
//
value = 8 ;
//
no_define_value
//
//
//..............................
//value = 0 ;
//value = ( 0xc * DEF_4SIGHT ) ;
// --------------------------------------
reserved protected
eo_information
3 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
CAGT regular
eo_information
3 2 unsigned no_flag_overflow
//CAGT[1:0]
// BUG IN CHIP
// Changed value 3 to 1 Arril8,2004
//
value = 1 ;
//
define_value
Chroma AGC = Slow
Chroma AGC = Medium
Chroma AGC = Fast
Chroma AGC = Vid_qual Setting
//
//
//..............................
//value = 1 ;
//value = ( 3 * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_CHROGAINCTL2
Chroma Gain Control 2
eo_information
1
0 8 unsigned no_flag_overflow
// CMG[7:0]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_LUMAGAINCTL1
Luma Gain Control 1
eo_information
3
// --------------------------------------
LMG regular
eo_information
0 4 unsigned no_flag_overflow
//LMG[11:8]
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( 0xf * DEF_4SIGHT ) ;
// --------------------------------------
reserved protected
eo_information
3 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
LAGT regular
eo_information
1 2 unsigned no_flag_overflow
//LAGT[1:0]
// BUG IN CHIP
//
value = 1 ;
//
define_value
Luma AGC = Slow
Luma AGC = Medium
Luma AGC = Fast
Luma AGC = VID_QUAL Setting
//
//
//..............................
//value = 3 ;
//value = ( 3 * DEF_4SIGHT ) ;
//
// =============================================
//
ADV7185_LUMAGAINCTL2
Luma Gain Control 2
eo_information
1
0 8 unsigned no_flag_overflow
// LMG[7:0]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_MANGAINSHADCTL1
Manual Gain Shadow Control 1
eo_information
3
// --------------------------------------
LMGS regular
eo_information
0 4 unsigned no_flag_overflow
//LMGS[11:8]
//
value = 0 ;
//
no_define_value
//
//
//..............................
//value = ( 8 * DEF_4SIGHT ) ;
// --------------------------------------
reserved protected
eo_information
7 3 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
SGUE regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Disable LMGS Update
Enable LMGS Update
//
//
//..............................
//value = DEF_4SIGHT ;
//
// =============================================
//
ADV7185_MANGAINSHADCTL2
Manual Gain Shadow Control 2
eo_information
1
0 8 unsigned no_flag_overflow
// LMGS[7:0]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_MISCGAINCTL
Miscellanous Gain Control
eo_information
6
// --------------------------------------
PWUPD regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Update per video line
Update per video field
//
//
//..............................
//value = DEF_4SIGHT ;
// --------------------------------------
AVAL regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Brightness = lines 33-310
Brightness = lines 33-270
//
//
//..............................
//value = DEF_4SIGHT ;
// --------------------------------------
MIRE regular
eo_information
0 3 unsigned no_flag_overflow
//MIRE[2:0]
//
value = 0 ;
//
define_value
Pal=133 Ntsc=122
Pal=125 Ntsc=115
Pal=120 Ntsc=110
Pal=115 Ntsc=105
Pal=110 Ntsc=100
Pal=105 Ntsc=100
Pal=100 Ntsc=100
Pal=100 Ntsc=100
//
//
//..............................
//Pal/Ntsc IRE
// --------------------------------------
reserved protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
CKE regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
Color Kill Disabled
Color Kill Enabled
//
//
//..............................
//value = VDC_MONO ;
//value = ( DEF_MONO_VIA_DEC & DEF_4SIGHT ) ;
//value = 0 ;
// --------------------------------------
reserved protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
//
// =============================================
//
ADV7185_HSYNCPOSCTL1
Hsync Position Begin/End Control 1
eo_information
3
// --------------------------------------
reserved protected
eo_information
15 4 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
HSE regular
eo_information
0 2 unsigned no_flag_overflow
//HSE[9:8]
//
value = 0 ;
//
no_define_value
// --------------------------------------
HSB regular
eo_information
0 2 unsigned no_flag_overflow
//HSB[9:8]
//
value = 0 ;
//
no_define_value
//
// =============================================
//
ADV7185_HSYNCPOSCTL2
Hsync Begin Position Control 2
eo_information
1
0 8 unsigned no_flag_overflow
//HSB[7:0]
//
value = ( DEF_PAL * DEF_RGB_PATH * 0x30 ) ;
//
no_define_value
//
//
//..............................
// Bug of clamping in Palrgb & ccirrgb.
//value = 0 ;
//
// =============================================
//
ADV7185_HSYNCPOSCTL3
Hsync End Position Control 3
eo_information
1
0x3a 8 unsigned no_flag_overflow
//HSE[7:0]
//
value = ( VDT_HSYNC + ( DEF_PAL * DEF_RGB_PATH * 0x18 ) ) ;
//
no_define_value
//
//
//..............................
// Bug of clamping in Palrgb & ccirrgb.
//value = VDT_HSYNC ;
//
// =============================================
//
ADV7185_POLARITYCTL
Polarity Control Bits
eo_information
8
//
// --------------------------------------
PCLK regular
eo_information
1 1 unsigned no_flag_overflow
//
// Set to 0 unstead 1 : Orion4SightRGB bug removed.(Noisy Video)
value = 0 ;
//
define_value
LLC1,LLC2,QCLK Active High
LLC1,LLC2,QCLK Active Low
// --------------------------------------
PFF regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
HFF,AEF,AFF Active High
HFF,AEF,AFF Active Low
// --------------------------------------
PDV regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
DV (Data Valid) Active High
DV (Data Valid) Active Low
// --------------------------------------
PF regular
eo_information
0 1 unsigned no_flag_overflow
//ODD Field Orion = High
//
value = 0 ;
//
define_value
Even Field Active High
Even Field Active Low
//
//
//..............................
//value = DEF_4SIGHT ;
// --------------------------------------
PLLCREF regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
LLCREF Active High
LLCREF Active Low
// --------------------------------------
PVS regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
VS Active High
VS Active Low
// --------------------------------------
PHVR regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
HREF & VREF Active High
HREF & VREF Active Low
// --------------------------------------
PHS regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
HS Active High
HS Active Low
//
//==============================================
//
ADV7185_CHROMACOMBFILTER
Chroma Comb Filter Control
eo_information
4
//---------------------------------------------
LCM regular
Luma Comb Mode
eo_information
3 2 unsigned flag_overflow
//
value = 3 ;
//
define_value
No Comb
1H
2H
Automatic Selection Highest Comb
//---------------------------------------------
CMM regular
Chroma Comb Mode
eo_information
2 2 unsigned flag_overflow
//
value = 2 ;
//
define_value
No Comb
1H
2H
Reserved
// --------------------------------------
CCMB_AD regular
HSCL regular
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Chroma Comb NonAdaptive
Chroma Comb Adaptive
// --------------------------------------
reserved regular
eo_information
1 3 unsigned flag_overflow
//
value = ( ( DEF_PAL & VDC_C_COLOR ) ? 5 : 1 ) ;
no_define_value
//
// =============================================
//
ADV7183A_SHAPFILCTL2
Shaping Filter Control ADV7183A
eo_information
2
// --------------------------------------
YSFM regular
eo_information
18 5 unsigned no_flag_overflow
//YSFM[4:0]
//
value = 0x13 ;
//
no_define_value
// Maximum 16 Items ? no more ?
//Auto selection Wide Notch
//Auto selection Narrow Notch
//SVHS1
//SVHS2
//SVHS3
//SVHS4
//SVHS5
//SVHS6
//SVHS7
//SVHS8
//SVHS9
//SVHS10
//SVHS11
//SVHS12
//SVHS13
//SVHS14
//SVHS15
//SVHS16
//SVHS17
//PAL NN1
//PAL NN2
//PAL NN3
//PAL WN1
//PAL WN2
//NTSC NN1
//NTSC NN2
//NTSC NN2
//NTSC WN1
//NTSC WN2
//NTSC WN3
//reserved
//reserved
// --------------------------------------
CSFM regular
eo_information
2 3 unsigned no_flag_overflow
//CSFM[2:0]
//
value = 4 ;
//
define_value
Filter response 1.5 Mhz
Filter response 2.17 Mhz
SH1
SH2
SH3
SH4
SH5
reserved
//
//==============================================
//
ADV7183A_NTSCCOMBCTL
NTSC Comb Control
eo_information
1
0x80 8 unsigned no_flag_overflow
//
value = 0x80 ;
//
no_define_value
//
//==============================================
//
ADV7183A_PALCOMBCTL
PAL Comb Control
eo_information
1
0xc0 8 unsigned no_flag_overflow
//
value = 0xc0 ;
//
no_define_value
//==============================================
//
ADV7183A_MANWINDOWCTL
Manual Window Control
eo_information
1
0x43 8 unsigned no_flag_overflow
//
value = 0x43 ;
//
no_define_value
//
//==============================================
//
ADV7183A_CTIDNRCTL1
eo_information
1
0xef 8 unsigned no_flag_overflow
//
value = 0xef ;
//
no_define_value
//
//==============================================
//
ADV7183A_CTIDNRCTL2
eo_information
1
8 8 unsigned no_flag_overflow
//
value = 8 ;
//
no_define_value
//
//==============================================
//
ADV7183A_CTIDNRCTL4
eo_information
1
8 8 unsigned no_flag_overflow
//
value = ( ( DEF_NTSC * 8 ) + ( DEF_PAL * 0x14 ) ) ;
//
no_define_value
//
//==============================================
//
ADV7183A_LOCKCOUNT
eo_information
1
0x64 8 unsigned no_flag_overflow
//
value = 0x64 ;
//
no_define_value
//
// =============================================
//
// *********************************************
// ADV7185 Chip (end)
// *********************************************
//
//
// *********************************************
// Pixel Formatter Chip (Begin)
// *********************************************
//
//==============================================
PIXFORMATTER_CONFIG1
Configuration Control Reg1
eo_information
7
// --------------------------------------
NTSCPAL regular
eo_information
0 1 unsigned no_flag_overflow
//
value = DEF_PAL ;
//
define_value
NTSC
PAL
//
//
//..............................
//value = DEF_50HZ_HV_TOTAL_STD ;
//value = DEF_50HZ_HV_TOTAL_STD * DEF_RGB_PATH ;
// --------------------------------------
SQPCCIR regular
eo_information
1 1 unsigned no_flag_overflow
//
value = 1 ;
//
define_value
CCIR 601
Square Pixel
//
//
//..............................
//value = DEF_60HZ_HV_TOTAL_STD ;
// --------------------------------------
FSWHSYNC protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
//
//
//..............................
//Rename Bit field Subsampling to fswhsync
// --------------------------------------
VINMOD regular
eo_information
0 2 unsigned no_flag_overflow
// Always use RGB Input Format from DEC or RGB Path
//
value = ( DEF_RGB_PATH * 2 ) ;
//
define_value
ITU-656 YCrCb
<ORION/MORPHIS> 16 Bits 4:2:2 YCrCb / <4SIGHTII_DUAL|RGB|STD> reserved
RGB 24 Bits
reserved
//
//
//..............................
//value = (
// DEF_DEC_PATH + ( DEF_RGB_PATH * 2 )
// ) ;
//value = 2 ;
// --------------------------------------
VOUTMOD regular
eo_information
0 1 unsigned no_flag_overflow
// Always use YUV Format Output FPGA as Default for BackEnd Scaler facilities
// Overwritten by Driver. To be set to zero.
//
value = 0 ;
//
define_value
YCrCb
RGB
//
//
//..............................
//value = DEF_RGB_PATH ;
// --------------------------------------
COLOR regular
eo_information
1 1 unsigned no_flag_overflow
//
value = VDC_MONO ;
//
define_value
Color
Monochrome
//
//
//..............................
//value = VDC_MONO * DEF_RGB_PATH ;
// --------------------------------------
MONOTYP regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Normal Output Format
8 Bits Mono Output Format
//
//==============================================
//
PIXFORMATTER_CONFIG2
Configuration Control Reg2
eo_information
5
// --------------------------------------
RINSEL regular
eo_information
0 2 unsigned no_flag_overflow
//
value = (
DEF_RGB_PATH * ( VDC_MONO * ( VDC_IN_CH1 + ( 2 * VDC_IN_CH2 ) ) )
) ;
//
define_value
<ORION/4SIGHTII_RGB/MORPHIS> Red / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> Green / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> Blue / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_DUAL|RGB|STD/MORPHIS> reserved
//
//
//..............................
//value = (
// (
// ( DEF_DEC_PATH * 2 ) +
// ( DEF_RGB_PATH * ( VDC_MONO * ( VDC_IN_CH1 + ( 2 * VDC_IN_CH2 ) ) ) )
// ) * OPTION
// ) ;
// --------------------------------------
GINSEL regular
eo_information
1 2 unsigned no_flag_overflow
//
value = (
DEF_DEC_PATH +
( DEF_RGB_PATH * ( VDC_MONO * ( VDC_IN_CH1 + ( 2 * VDC_IN_CH2 ) ) ) ) +
( DEF_RGB_PATH * VDC_RGB_COL )
) ;
//
define_value
<ORION/4SIGHTII_RGB/MORPHIS> Red / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> Green / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> Blue / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_DUAL|RGB|STD/MORPHIS> reserved
//
//
//..............................
//value = (
// DEF_DEC_PATH +
// ( DEF_RGB_PATH * ( VDC_MONO * ( VDC_IN_CH1 + ( 2 * VDC_IN_CH2 ) ) ) ) +
// ( DEF_RGB_PATH * VDC_RGB_COL )
// ) ;
//value = (
// DEF_DEC_PATH + DEF_RGB_PATH
// ) ;
//value = ( ( VDC_MONO * ( VDC_IN_CH1 + ( VDC_IN_CH2 * 2 ) ) ) + VDC_RGB_COL ) * DEF_RGB_PATH ;
// --------------------------------------
BINSEL regular
eo_information
2 2 unsigned no_flag_overflow
//
value = (
( DEF_DEC_PATH * 2 ) +
( DEF_RGB_PATH * ( VDC_MONO * ( VDC_IN_CH1 + ( 2 * VDC_IN_CH2 ) ) ) ) +
( DEF_RGB_PATH * 2 * VDC_RGB_COL )
) ;
//
define_value
<ORION/4SIGHTII_RGB/MORPHIS> Red / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> Green / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> Blue / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_DUAL|RGB|STD/MORPHIS> reserved
//
//
//..............................
//value = (
// (
// ( DEF_DEC_PATH * 2 ) +
// ( DEF_RGB_PATH * ( VDC_MONO * ( VDC_IN_CH1 + ( 2 * VDC_IN_CH2 ) ) ) ) +
// ( DEF_RGB_PATH * 2 * VDC_RGB_COL )
// ) * OPTION
// ) ;
// --------------------------------------
LUTSEL regular
Lookup Table Select
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
<ORION/4SIGHTII_RGB/MORPHIS> LUT 1 / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> LUT 2 / <4SIGHTII_DUAL|STD> reserved
// --------------------------------------
CSCBYP regular
Color Space Bypass
eo_information
0 1 unsigned no_flag_overflow
// Color Space Converter used Only RGB Path because always RGB to YUV conversion used
//
value = ( DEF_RGB_PATH * ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ;
//
define_value
<ORION/4SIGHTII_RGB/MORPHIS> Bypass / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> NOT Bypass / <4SIGHTII_DUAL|STD> reserved
//
//
//..............................
//value = ( DEF_RGB_PATH * DEF_ORION ) ;
//value = DEF_RGB_PATH ;
//value = 1 ;
//
//==============================================
//
PIXFORMATTER_CONFIG3
Configuration Control Reg3
eo_information
3
// --------------------------------------
FPGABYP regular
Video Data Bypass FPGA
eo_information
1 1 unsigned no_flag_overflow
// Always use FPGA Path
//
value = 1 ;
//
define_value
<ORION|4SIGHTII_RGB/MORPHIS>Bypass / <4SIGHTII_DUAL|STD> reserved
<ORION|4SIGHTII_RGB/MORPHIS>Normal /<4SIGHTII_DUAL|STD> reserved
//Bypass Video In to Out
//Normal
//
//
//..............................
//value = 0 ;
// --------------------------------------
VSSODD regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
<ORION/MORPHIS> VS = VSYNC_OUT / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Field = VSYNC_OUT / <4SIGHTII_DUAL|RGB|STD> reserved
//
// --------------------------------------
CSC_SEL regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
<ORION/4SIGHTII_DUAL|STD/MORPHIS> reserved / <4SIGHTII_RGB> RGB To YCrCb
<ORION/4SIGHTII_DUAL|STD/MORPHIS> reserved / <4SIGHTII_RGB> YCrCb To RGB
//
//==============================================
//
PIXFORMATTER_FGCTL1
Frame Grabber Control Reg1
eo_information
7
// --------------------------------------
VIDINSEL1 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = DEF_ORION_VIN_HIGH * DEF_RGB_PATH ;
//
define_value
<ORION/MORPHIS> Vid_In1 / <4SIGHTII_DUAL|RGB|STD> Vid_In1,2,3,10
<ORION/MORPHIS> Vid_In5 / <4SIGHTII_DUAL|RGB|STD> Vid_In5,6,7,12
//
//
//..............................
// for 12 or 24 Inputs Channels with 2 or 4 Selects for Selects
//value = (
// ( DEF_4SIGHTII_VIN_HIGH * DEF_RGB_PATH ) +
// ( OPTION_4SIGHT_STD * ( VDC_IN_CH4 | VDC_IN_CH5 | VDC_IN_CH6 | VDC_IN_CH11 ) ) +
// (
// OPTION_4SIGHT *
// (
// VDC_IN_CH4 | VDC_IN_CH5 | VDC_IN_CH6 | VDC_IN_CH11 |
// VDC_IN_CH16 | VDC_IN_CH17 | VDC_IN_CH18 | VDC_IN_CH23
// )
// )
// ) ;
//value = DEF_VIN_HIGH * DEF_RGB_PATH ;
//value = ( ( VDC_MONO * VDC_IN_CH4 ) | ( VDC_RGB_COL * VDC_IN_CH4 ) ) ;
// --------------------------------------
VIDINSEL2 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = DEF_ORION_VIN_HIGH * DEF_RGB_PATH ;
//
define_value
<ORION/MORPHIS> Vid_In2 / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Vid_In6 / <4SIGHTII_DUAL|RGB|STD> reserved
//
//
//..............................
// for 12 or 24 Inputs Channels with 2 or 4 Selects for Selects
//value = (
// ( DEF_4SIGHTII_VIN_HIGH * DEF_RGB_PATH ) +
// (
// OPTION_4SIGHT *
// (
// VDC_IN_CH12 | VDC_IN_CH13 | VDC_IN_CH14 | VDC_IN_CH21 |
// VDC_IN_CH16 | VDC_IN_CH17 | VDC_IN_CH18 | VDC_IN_CH23
// ) *
// )
// ) ;
//value = ( ( VDC_MONO * VDC_IN_CH5 ) | ( VDC_RGB_COL * VDC_IN_CH4 ) ) ;
// --------------------------------------
VIDINSEL3 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = DEF_ORION_VIN_HIGH * DEF_RGB_PATH ;
//
define_value
<ORION/MORPHIS> Vid_In3 / <4SIGHTII_DUAL|RGB|STD> Vid_In4,9
<ORION/MORPHIS> Vid_In7 / <4SIGHTII_DUAL|RGB|STD> Vid_In8,11
//
//
//..............................
// for 12 or 24 Inputs Channels with 2 or 4 Selects for Selects
//value = (
// ( DEF_4SIGHTII_VIN_HIGH * DEF_RGB_PATH ) +
// ( OPTION_4SIGHT_STD * ( VDC_IN_CH8 | VDC_IN_CH10 ) ) +
// (
// OPTION_4SIGHT *
// ( ( VDC_IN_CH7 | VDC_IN_CH10 | VDC_IN_CH19 | VDC_IN_CH22 ) )
// )
// ) ;
//value = ( ( VDC_MONO * VDC_IN_CH6 ) | ( VDC_RGB_COL * VDC_IN_CH4 ) ) ;
// --------------------------------------
VIDINSEL4 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = DEF_ORION_VIN_HIGH * DEF_RGB_PATH ;
//
define_value
<ORION/MORPHIS> Vid_In4 / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Vid_In8 / <4SIGHTII_DUAL|RGB|STD> reserved
//
//
//..............................
// for 12 or 24 Inputs Channels with 2 or 4 Selects for Selects
//value = (
// ( DEF_ORION_VIN_HIGH * DEF_RGB_PATH ) +
// (
// OPTION_4SIGHT *
// ( ( VDC_IN_CH15 | VDC_IN_CH20 | VDC_IN_CH19 | VDC_IN_CH22 ) )
// )
// ) ;
//value = ( ( VDC_MONO * VDC_IN_CH7 ) | ( VDC_RGB_COL * VDC_IN_CH4 ) ) ;
// --------------------------------------
GAINSEL regular
eo_information
2 2 unsigned no_flag_overflow
//
value = ( ( DEF_VIDEO_GAIN == 1300 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 0 :
( ( ( DEF_VIDEO_GAIN == 2000 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 1 :
( ( ( DEF_VIDEO_GAIN == 2800 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 2 :
( ( ( DEF_VIDEO_GAIN == 4000 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 3 :
0 ) ) ) ;
//
define_value
Gain = 1.3
Gain = 2.0
Gain = 2.8
Gain = 4.0
//
//
//..............................
//value = ( ( DEF_VIDEO_GAIN == 1300 ) & DEF_ORION ) ? 0 :
// ( ( ( DEF_VIDEO_GAIN == 2000 ) & DEF_ORION ) ? 1 :
// ( ( ( DEF_VIDEO_GAIN == 2800 ) & DEF_ORION ) ? 2 :
// ( ( ( DEF_VIDEO_GAIN == 4000 ) & DEF_ORION ) ? 3 :
// ( DEF_4SIGHT ? 1 :
// 0 ) ) ) ) ;
//*********************************************
// To bo reinsert after while when hardware adjusted!
//value = ( ( DEF_VIDEO_GAIN == 1300 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 0 :
// ( ( ( DEF_VIDEO_GAIN == 2000 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 1 :
// ( ( ( DEF_VIDEO_GAIN == 2800 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 2 :
// ( ( ( DEF_VIDEO_GAIN == 4000 ) & ( DEF_ORION | DEF_4SIGHT ) ) ? 3 :
// 0 ) ) ) ;
//*********************************************
//
//value = ( ( DEF_VIDEO_GAIN == 1300 ) & ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ? 0 :
// ( ( ( DEF_VIDEO_GAIN == 2000 ) & ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ? 1 :
// ( ( ( DEF_VIDEO_GAIN == 2800 ) & ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ? 2 :
// ( ( ( DEF_VIDEO_GAIN == 4000 ) & ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ? 3 :
// 0 ) ) ) ;
//value = ( ( DEF_VIDEO_GAIN == 1300 ) & DEF_ORION ) ? 0 :
// ( ( ( DEF_VIDEO_GAIN == 2000 ) & DEF_ORION ) ? 1 :
// ( ( ( DEF_VIDEO_GAIN == 2800 ) & DEF_ORION ) ? 2 :
// ( ( ( DEF_VIDEO_GAIN == 4000 ) & DEF_ORION ) ? 3 :
// 0 ) ) ) ;
//value = ( DEF_VIDEO_GAIN == 1300 ) ? 0 :
// ( ( DEF_VIDEO_GAIN == 2000 ) ? 1 :
// ( ( DEF_VIDEO_GAIN == 2800 ) ? 2 :
// ( ( DEF_VIDEO_GAIN == 4000 ) ? 3 :
// 0 ) ) ) ;
//value = ( DEF_VIDEO_GAIN == 1300 ) ? 0 :
// ( ( DEF_VIDEO_GAIN == 2000 ) ? 1 :
// ( ( DEF_VIDEO_GAIN == 2800 ) ? 2 :
// ( ( DEF_VIDEO_GAIN == 4000 ) ? 3 :
// 0 ) ) ) * DEF_RGB_PATH ;
// --------------------------------------
FTRBYP regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
define_value
<ORION/MORPHIS> Input Filter Bypass / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Input Filter Used / <4SIGHTII_DUAL|RGB|STD> reserved
//
//
//..............................
//value = DEF_RGB_PATH ;
// --------------------------------------
ADCDEC regular
A/D or Decoder Selection
eo_information
0 1 unsigned no_flag_overflow
//
value = ( DEF_RGB_PATH * ( DEF_ORION | OPTION_4SIGHT_II_RGB ) ) ;
//
define_value
<ORION/4SIGHTII_RGB/MORPHIS> Decoder En / <4SIGHTII_DUAL|STD> reserved
<ORION/4SIGHTII_RGB/MORPHIS> A/D En / <4SIGHTII_DUAL|STD> reserved
//
//
//..............................
//value = ( DEF_RGB_PATH * DEF_ORION ) ;
//value = DEF_RGB_PATH ;
//
//==============================================
//
PIXFORMATTER_FGCTL2
Frame Grabber Control Reg2
eo_information
3
// --------------------------------------
DACCLK regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
DACDATA regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
DACSEL regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
<ORION/MORPHIS> No D/A Select / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Red D/A Prog. / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Green D/A Prog. / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> Blue D/A Prog. / <4SIGHTII_DUAL|RGB|STD> reserved
//
//==============================================
//
PIXFORMATTER_USEROUT
User Output Register
eo_information
2
// --------------------------------------
USEROUT1 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Low
High
// --------------------------------------
USEROUT2 regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Low
High
//
//==============================================
//
PIXFORMATTER_USERIN
Configuration Control Reg1
eo_information
4
// --------------------------------------
USERIN1 protected
eo_information
0 1 unsigned no_flag_overflow
// Read ONLY
//
no_define_value
// --------------------------------------
USERIN2 protected
eo_information
0 1 unsigned no_flag_overflow
// Read ONLY
no_define_value
// --------------------------------------
TRIGGER protected
eo_information
0 1 unsigned no_flag_overflow
// Read ONLY
no_define_value
// --------------------------------------
OPTOTRG protected
eo_information
0 1 unsigned no_flag_overflow
// Read ONLY
no_define_value
//
//==============================================
//
PIXFORMATTER_GBCTL
Grab Control Register
eo_information
6
// --------------------------------------
GBMODE regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Monoshot
Continuous
//
//
//..............................
//value = GRB_MD_CONT ;
// --------------------------------------
GBSTATE regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Grab Inactive
Grab Active
//
//
//..............................
//value = 1 * DEF_RGB_PATH ;
// --------------------------------------
GBHALT regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Normal Grab
Next Field Grab
Abort Grab Immediately
reserved
// --------------------------------------
GBSTARTMODE regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
ODD Field
EVEN Field
ANY Field
reserved
// --------------------------------------
GBFIELDNUM regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
2 Fields
1 Field ONLY
// --------------------------------------
GBGO regular
eo_information
0 1 unsigned no_flag_overflow
//
value = 0 ;
//
define_value
Stop Grab
Start Grab
//
//==============================================
//
PIXFORMATTER_TGRCTL
Trigger Control Register
eo_information
5
// --------------------------------------
TGRDETECT regular
eo_information
0 1 unsigned no_flag_overflow
//
value = ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) ;
//
define_value
Trigger detection Disable
Trigger detection Enable
//
//
//..............................
//value = ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) * DEF_RGB_PATH ;
// --------------------------------------
TGRSRC regular
eo_information
0 1 unsigned no_flag_overflow
//
value = GRB_MD_SW_TRG ;
//
define_value
Trigger Hardware
Trigger Software
//
//
//..............................
//value = GRB_MD_SW_TRG * DEF_RGB_PATH ;
// --------------------------------------
TGRHWMOD regular
eo_information
0 2 unsigned no_flag_overflow
//
value = GRB_TRG_NEG ;
//
define_value
Rising Edge
Falling Edge
High Voltage Level
Low Voltage Level
//
//
//..............................
//value = GRB_TRG_NEG * DEF_RGB_PATH ;
// --------------------------------------
TGRHWSRC regular
eo_information
1 1 unsigned no_flag_overflow
// Default = OPTO Trigger
//
value = ( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_DPORT & ( DEF_ORION | DEF_MORPHIS ) ) ? 0 : 1
) ;
//
define_value
<ORION/MORPHIS> TTL Trigger / <4SIGHTII_DUAL|RGB|STD> reserved
<ORION/MORPHIS> OPTO Trigger / <4SIGHTII_DUAL|RGB|STD> reserved
//
//
//..............................
//value = ( GRB_MD_HW_TRG * GRB_TRG_SIGNAL_APORT * DEF_ORION ) ;
//value = ( GRB_MD_HW_TRG * GRB_TRG_SIGNAL_APORT ) ;
//value = ( GRB_MD_HW_TRG * GRB_TRG_SIGNAL_APORT ) * DEF_RGB_PATH ;
// --------------------------------------
TGRSW regular
eo_information
0 1 unsigned no_flag_overflow
//
value = GRB_MD_SW_TRG ;
//
define_value
Soft Trig Disabled
Soft Trig Activated
//
//
//..............................
//value = ( GRB_MD_SW_TRG * DEF_ORION ) ;
//value = GRB_MD_SW_TRG ;
//value = GRB_MD_SW_TRG * DEF_RGB_PATH ;
//
//==============================================
//
PIXFORMATTER_INTSTAT
Interrupt Status Register
eo_information
1
0 7 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// Read ONLY
//
//==============================================
//
PIXFORMATTER_INTMASK
Interrupt Mask Register
eo_information
1
0 8 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
PIXFORMATTER_INTOEN
Interrupt Output Enable Reg
eo_information
1
0 8 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
//
//==============================================
//
PIXFORMATTER_DECCTRL
Trigger Control Register
eo_information
8
// --------------------------------------
HIGHERREG protected
eo_information
0 1 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBIEN regular
eo_information
0 1 unsigned no_flag_overflow
// To be compatible Orion-AGP & Orion-4Sight with VBICOUNT
//
value = ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) < ( 17 + ( DEF_PAL * 6 ) ) ) ;
//
define_value
<4SIGHTII_STD|DUAL> VBI Lines clipped / <4SIGHTII_RGB> reserved
<4SIGHTII_STD|DUAL> VBI Lines active / <4SIGHTII_RGB> reserved
//
//
//..............................
//value = (
// ( OPTION_4SIGHT_II_STD * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 + ( DEF_PAL * 12 ) ) ) ) |
// OPTION_4SIGHT_II_RGB
// ) ;
// --------------------------------------
HLOCKRST protected
eo_information
0 1 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
FPGABYP protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
CLIPLINE regular
eo_information
0 1 unsigned no_flag_overflow
// Decoder Rev5 Bug removed => Clipline = 0
//
value = 0 ;
//
define_value
<4SIGHTII_STD|DUAL> Normal operation / <4SIGHTII_RGB> reserved
<4SIGHTII_STD|DUAL> Clip First Line Even Field / <4SIGHTII_RGB> reserved
//
//
//..............................
//value = DEF_NTSC ;
// --------------------------------------
FSWFIELD protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
//
//
////..............................
//Add bit field fswfield
// --------------------------------------
FSWVALID protected
eo_information
1 1 unsigned no_flag_overflow
//
no_define_value
//
//
////..............................
//Add bit field fswvalid
// --------------------------------------
reserved protected
eo_information
0 1 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
PIXFORMATTER_HSTARTLOW
Horizontal Start Low Byte
eo_information
1
0x7e 8 unsigned no_flag_overflow
// DECODER = Fixe RGB = Variable for PROPER CLAMPING A/D
//
value = (
(
(
DEF_DEC_PATH *
(
126 + ( 36 * DEF_PAL )
)
) +
(
DEF_RGB_PATH *
(
VDT_HSYNC + VDT_HBPORCH - ( DEF_NTSC * 15 ) + ( DEF_PAL * 94 )
)
)
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
// Bug in PalRgb & CcirRgb in Clamping.
//value = (
// (
// (
// DEF_DEC_PATH *
// (
// 126 + ( 36 * DEF_PAL )
// )
// ) +
// (
// DEF_RGB_PATH *
// (
// VDT_HSYNC + VDT_HBPORCH - ( 15 + ( DEF_PAL * 99 ) )
// )
// )
// ) & 0xFF
// ) ;
//
//==============================================
//
PIXFORMATTER_HSTARTHIGH
Horizontal Start High Byte
eo_information
2
// --------------------------------------
HSTARTHIGH regular
eo_information
0 2 unsigned no_flag_overflow
//
value = (
(
DEF_RGB_PATH *
(
(
VDT_HSYNC + VDT_HBPORCH + ( 497 + ( DEF_PAL * 109 ) )
) >> 8
)
) & 0x03
) ;
//
no_define_value
//
//
//..............................
// Bug in PalRgb & CcirRgb in Clamping.
//value = (
// (
// (
// VDT_HSYNC + VDT_HBPORCH + ( DEF_DEC_PATH * 8 ) +
// ( DEF_RGB_PATH * ( 497 + ( DEF_PAL * 157 ) ) )
// ) >> 8
// ) & 0x03
// ) ;
// --------------------------------------
reserved protected
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
PIXFORMATTER_HSTOPLOW
Horizontal Stop Low Byte
eo_information
1
2 10 unsigned no_flag_overflow
//
value = (
(
(
DEF_DEC_PATH * ( 2 + ( 164 * DEF_PAL ) )
) +
(
DEF_RGB_PATH *
(
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE -
( 535 + ( DEF_PAL * 311 ) )
)
)
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
// Bug in PalRgb & CcirRgb in Clamping.
//value = (
// (
// (
// DEF_DEC_PATH * ( 2 + ( 164 * DEF_PAL ) )
// ) +
// (
// DEF_RGB_PATH *
// (
// VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE -
// ( 535 + ( DEF_PAL * 263 ) )
// )
// )
// ) & 0xFF
// ) ;
//
//==============================================
//
PIXFORMATTER_HSTOPHIGH
Horizontal Stop High Byte
eo_information
2
// --------------------------------------
HSTOPHIGH regular
eo_information
3 2 unsigned no_flag_overflow
//
value = (
(
( DEF_DEC_PATH * 3 ) +
(
DEF_RGB_PATH *
(
(
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - ( 279 + ( DEF_PAL * 55 ) )
) >> 8
)
)
) & 0x03
) ;
//
no_define_value
//
//
//..............................
// Bug in PalRgb & CcirRgb in Clamping.
//value = (
// (
// ( DEF_DEC_PATH * 3 ) +
// (
// DEF_RGB_PATH *
// (
// (
// VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - ( 279 + ( DEF_PAL * 7 ) )
// ) >> 8
// )
// )
// ) & 0x03
// ) ;
// --------------------------------------
reserved protected
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
PIXFORMATTER_VSTARTLOW
Vertical Start Low Byte
eo_information
1
0xc 10 unsigned no_flag_overflow
//
value = (
(
( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - ( DEF_NTSC * ( 7 + DEF_RGB_PATH ) ) -
( DEF_PAL * ( 8 + DEF_RGB_PATH ) )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// (
// 11 + ( DEF_DEC_PATH * ( 1 + ( 3 * DEF_PAL ) ) ) +
// ( DEF_PAL * DEF_RGB_PATH * 3 )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( DEF_4SIGHT * ( 27 + ( 5 * DEF_PAL ) + DEF_RGB_PATH ) )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( DEF_4SIGHT * ( 27 + ( 5 * DEF_PAL ) + DEF_RGB_PATH ) )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( OPTION_4SIGHT_II_RGB * ( 27 + ( 5 * DEF_PAL ) + DEF_RGB_PATH ) )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( OPTION_4SIGHT_II_RGB * ( 20 + ( 5 * DEF_PAL ) + DEF_RGB_PATH ) )
// ) & 0xFF
// ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH - 26 - ( DEF_PAL * 5 ) ) & 0xFF ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH - 27 - ( DEF_PAL * 5 ) ) & 0xFF ) ;
//
//==============================================
//
PIXFORMATTER_VSTARTHIGH
Vertical Start High Byte
eo_information
2
// --------------------------------------
VSTARTHIGH regular
eo_information
0 2 unsigned no_flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
PIXFORMATTER_VSTOPLOW
Vertical Stop Low Byte
eo_information
1
0xfc 10 unsigned no_flag_overflow
//
value = (
(
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE ) / 2 ) - ( DEF_NTSC * ( 7 + DEF_RGB_PATH ) ) -
( DEF_PAL * ( 264 + DEF_RGB_PATH ) )
) & 0xFF
) ;
//
no_define_value
//
//
//..............................
//value = (
// (
// ( DEF_PAL * ( 46 + DEF_DEC_PATH ) ) + ( DEF_NTSC * ( 251 + DEF_DEC_PATH ) )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( DEF_4SIGHT * ( 27 + ( DEF_PAL * 261 ) + DEF_RGB_PATH ) )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( OPTION_4SIGHT_II_RGB * ( 27 + ( DEF_PAL * 261 ) + DEF_RGB_PATH ) )
// ) & 0xFF
// ) ;
//value = (
// (
// VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( OPTION_4SIGHT_II_RGB * ( 277 + ( DEF_PAL * ( 5 + DEF_RGB_PATH ) ) ) )
// ) & 0xFF
// ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - 26 - ( DEF_PAL * 5 ) ) & 0xFF ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - 27 - ( DEF_PAL * 5 ) ) & 0xFF ) ;
//
//==============================================
//
PIXFORMATTER_VSTOPHIGH
Vertical Stop High Byte
eo_information
2
// --------------------------------------
VSTOPHIGH regular
eo_information
0 2 unsigned no_flag_overflow
//
value = DEF_PAL ;
//
no_define_value
//
//
//..............................
//value = (
// (
// (
// VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) +
// ( DEF_4SIGHT * DEF_PAL * DEF_RGB_PATH * 23 ) -
// ( DEF_4SIGHT * DEF_PAL * DEF_DEC_PATH * 32 ) -
// ( DEF_4SIGHT * DEF_NTSC * 279 )
// ) >> 8
// ) & 0x3
// ) ;
//value = (
// (
// (
// VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) +
// ( OPTION_4SIGHT_II_RGB * DEF_PAL * DEF_RGB_PATH * 23 ) -
// ( OPTION_4SIGHT_II_RGB * DEF_PAL * DEF_DEC_PATH * 32 ) -
// ( OPTION_4SIGHT_II_RGB * DEF_NTSC * 279 )
// ) >> 8
// ) & 0x3
// ) ;
//value = (
// (
// (
// VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - ( DEF_ORION * ( 26 + ( DEF_PAL * 5 ) ) ) -
// ( OPTION_4SIGHT_II_RGB * ( 21 + ( 2 * DEF_PAL ) ) )
// ) >> 8
// ) & 0x3
// ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - 27 - ( DEF_PAL * 5 ) ) >> 8 ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH + ( VDT_VACTIVE / 2 ) - 7 - ( DEF_PAL * 16 ) ) >> 8 ) ;
// --------------------------------------
reserved protected
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
// *********************************************
// Pixel Formatter Chip (end)
// *********************************************
//
// =============================================
//
//
//==============================================
//
// *********************************************
// IDRE Chip (Start)
// *********************************************
//
// =============================================
//
//
//==============================================
//
//
//==============================================
//
IDRE_VALIDGEN
Valid Patch Vertical Framing
eo_information
2
//---------------------------------------------
NbrLinpFld regular
Number of Lines per Field
eo_information
0xf0 16 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0xF0 ) + ( DEF_PAL * 0x120 ) ) ;
//
no_define_value
//---------------------------------------------
VertOff regular
Vertical Line Offset
eo_information
0x15 16 unsigned flag_overflow
//
value = (
( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + DEF_NTSC
) ;
//value = ( ( DEF_NTSC * 0x14 ) + ( DEF_PAL * 0x17 ) ) ;
//
no_define_value
//
//
//==============================================
//
// *********************************************
// IDRE Chip (End)
// *********************************************
//
// =============================================
//
//
//==============================================
//
// *********************************************
// Toucan Chip (Start)
// *********************************************
//
// =============================================
//
// Min Y Window size = 480 no manner Intellicam value Vactive ( < 480 )
//
TOUCAN_VINHEIGHT
Video Lines Active
eo_information
1
0xf0 32 unsigned no_flag_overflow
//
value = ( VDT_VACTIVE / 2 ) ;
//
no_define_value
//
//
//..............................
//value = (
// ( ( VDT_VACTIVE >= 480 ) * ( VDT_VACTIVE / 2 ) ) +
// ( ( VDT_VACTIVE < 480 ) * 480 )
// ) ;
//
//==============================================
//
TOUCAN_VBICOUNT
Video In VBI Count
eo_information
8
// --------------------------------------
VINVBCNT0 regular
VBLK field0
eo_information
0x17 6 unsigned no_flag_overflow
// Modified for G400 Vertical Cropping
//
value = ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 4 - ( DEF_PAL * 2 ) ) ;
//
no_define_value
//
//
//..............................
//value = ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 4 - ( DEF_PAL * 2 ) ) ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 4 - ( DEF_PAL * 2 ) ) ) +
// (
// ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_DUAL ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 4 - ( DEF_PAL * 2 ) ) ) +
// (
// ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_DUAL ) *
// (
// (
// ( VDT_VSYNC + VDT_VBPORCH ) == ( 47 * DEF_PAL )
// ) +
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 47 * DEF_PAL ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 1 )
// ) +
// (
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) <= ( 39 * DEF_NTSC ) ) &
// ( ( VDT_VSYNC + VDT_VBPORCH ) > ( 33 * DEF_NTSC ) )
// ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 15 )
// ) +
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// )
// )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 4 - ( DEF_PAL * 2 ) ) ) +
// ( DEF_4SIGHT * 2 )
// ) ;
// --------------------------------------
reserved0 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT0 protected
VBI count field0
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved1 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VINVBCNT1 regular
VBLK field1
eo_information
0x16 6 unsigned no_flag_overflow
// Modified for G400 Vertical Cropping
//
value = ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ;
//
no_define_value
//
//
//..............................
//value = ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) +
// (
// ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_DUAL ) *
// (
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 47 * DEF_PAL ) ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 )
// ) +
// (
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) <= ( 39 * DEF_NTSC ) ) &
// ( ( VDT_VSYNC + VDT_VBPORCH ) > ( 33 * DEF_NTSC ) )
// ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// )
// )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) +
// ( DEF_4SIGHT * DEF_NTSC * 3 )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) +
// ( DEF_4SIGHT * 2 )
// ) ;
// --------------------------------------
reserved2 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT1 protected
VBI count field1
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved3 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
TOUCAN_VBICOUNT_STD
Video In VBI Count
eo_information
8
// --------------------------------------
VINVBCNT0 regular
VBLK field0
eo_information
3 6 unsigned no_flag_overflow
// Modified for G400 Vertical Cropping
//
value = (
(
DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
) +
(
DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) >= 34 ) *
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
) +
(
DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < 34 ) *
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
)
) ;
//
no_define_value
//
//
//..............................
//value = (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) <= 39 ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > 33 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < 34 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// )
// ) ;
//value = (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) <= 39 ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > 33 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// ) ;
//value = (
// ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_DUAL ) *
// (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) <= 39 ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > 33 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// )
// ) ;
// --------------------------------------
reserved0 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT0 protected
VBI count field0
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved1 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VINVBCNT1 regular
VBLK field1
eo_information
3 6 unsigned no_flag_overflow
// Modified for G400 Vertical Cropping
//
value = (
(
DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 1 )
) +
(
DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) >= 34 ) *
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
) +
(
DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < 34 ) *
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
)
) ;
//
no_define_value
//
//
//..............................
//value = (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 1 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) <= 39 ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > 33 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < 34 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// ) ;
//value = (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 1 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) <= 39 ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > 33 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 4 )
// )
// ) ;
//value = (
// ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_DUAL ) *
// (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 1 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) <= 39 ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) > 33 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) +
// (
// ( OPTION_4SIGHT_II_STD | OPTION_4SIGHT_II_DUAL ) *
// (
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 47 * DEF_PAL ) ) *
// ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 )
// ) +
// (
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) <= ( 39 * DEF_NTSC ) ) &
// ( ( VDT_VSYNC + VDT_VBPORCH ) > ( 33 * DEF_NTSC ) )
// ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// ( ( VDT_VSYNC + VDT_VBPORCH ) < ( 34 * DEF_NTSC ) ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// )
// )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) +
// ( DEF_4SIGHT * DEF_NTSC * 3 )
// ) ;
//value = (
// ( DEF_ORION * ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 - ( DEF_PAL * 2 ) ) ) +
// ( DEF_4SIGHT * 2 )
// ) ;
// --------------------------------------
reserved2 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT1 protected
VBI count field1
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved3 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
TOUCAN_VBICOUNT_RGB
Video In VBI Count
eo_information
8
// --------------------------------------
VINVBCNT0 regular
VBLK field0
eo_information
3 6 unsigned no_flag_overflow
// Modified for G400 Vertical Cropping
//
value = 3 ;
//
no_define_value
//
//
//..............................
//value = ( 3 - ( DEF_DEC_PATH * DEF_PAL ) ) ;
// --------------------------------------
reserved0 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT0 protected
VBI count field0
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved1 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VINVBCNT1 regular
VBLK field1
eo_information
3 6 unsigned no_flag_overflow
// Modified for G400 Vertical Cropping
//
value = 3 ;
//
no_define_value
//
//
//..............................
//value = ( 3 - ( DEF_DEC_PATH * DEF_PAL ) ) ;
// --------------------------------------
reserved2 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT1 protected
VBI count field1
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved3 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
TOUCAN_VBICOUNT_DUAL
Video In VBI Count
eo_information
8
// --------------------------------------
VINVBCNT0 regular
VBLK field0
eo_information
0 6 unsigned no_flag_overflow
// No Vertical Cropping with Dual
//
value = (
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 - ( 7 * DEF_PAL ) ) & 0x3f
) ;
//
no_define_value
//
//
//..............................
//value = 0 ;
//value = (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) >= 34 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < 34 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 2 )
// )
// ) ;
// --------------------------------------
reserved0 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT0 protected
VBI count field0
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved1 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VINVBCNT1 regular
VBLK field1
eo_information
0 6 unsigned no_flag_overflow
//
value = (
( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 - ( 7 * DEF_PAL ) ) & 0x3f
) ;
//
no_define_value
//
//
//..............................
//value = 0 ;
//value = (
// (
// DEF_PAL * ( ( VDT_VSYNC + VDT_VBPORCH ) < 46 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 1 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) >= 34 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) - 16 )
// ) +
// (
// DEF_NTSC * ( ( VDT_VSYNC + VDT_VBPORCH ) < 34 ) *
// ( ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) + 3 )
// )
// ) ;
// --------------------------------------
reserved2 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
VBICNT1 protected
VBI count field1
eo_information
0 6 unsigned no_flag_overflow
//
no_define_value
// --------------------------------------
reserved3 protected
eo_information
0 2 unsigned no_flag_overflow
//
no_define_value
//
//==============================================
//
// *********************************************
// Toucan Chip (end)
// *********************************************
//
//==============================================
//
//
[EOF]
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.