[INFO_FILE]
/////////////////////////////////////////////////
//
// MATROX OASISFG Info file
// For more informations refer to INFGUIDE.DOC
//
// REVISION HISTORY:
// 0007.8000.0000 - initial version.
// 0008.0016.0000 - Current
//
/////////////////////////////////////////////////
//
// **********************************************
// **********************************************
// SECTION #1: end HEADER
// **********************************************
// **********************************************
// Generic product name line 23 = 47 characters Max. including space for proper
// loading in Intellicam.
//
//
60BF 0008.0016.0000
ODYSSEY
"Matrox OASISFG"
Information file for the OASISFG board.
// **********************************************
// **********************************************
// SECTION #2: NEW GENERAL PARAMETERS|MEMBERS
// **********************************************
// **********************************************
//
//
[NEW_GPARAM]
//
// OPTION_HELIOS_CL_DUAL = HELIOS CAMERA LINK DUAL BASE MODULE
// OPTION_HELIOS_CL_FULL = HELIOS CAMERA LINK FULL MODULE
// OPTION_HELIOS_ANA = HELIOS ANALOG MODULE
// OPTION_HELIOS_DIG = HELIOS CAMERA DIGITAL MODULE
// OPTION_ODYSSEY_CL_DUAL = ODYSSEY CAMERA LINK DUAL BASE MODULE
// OPTION_ODYSSEY_CL_FULL = ODYSSEY CAMERA LINK FULL MODULE
// OPTION_ODYSSEY_ANA = ODYSSEY ANALOG MODULE
// OPTION_ODYSSEY_DIG = ODYSSEY CAMERA DIGITAL MODULE
// OPTION_SOLIOS_CL_DUAL = SOLIOS CAMERA LINK DUAL BASE MODULE
// OPTION_SOLIOS_CL_MEDIUM = SOLIOS CAMERA LINK MEDIUM MODULE
// OPTION_SOLIOS_SINGLE_ANA = SOLIOS SINGLE ANALOG MODULE
// OPTION_SOLIOS_DUAL_ANA = SOLIOS DUAL ANALOG MODULE
// OPTION_SOLIOS_QUAD_ANA = SOLIOS QUAD ANALOG MODULE
// OPTION_SOLIOS_DIG = SOLIOS CAMERA DIGITAL MODULE
//
// =============================================
// Marc B Modification 99-12-09: Added new internal param.
//
//
GGEN_BOARD_TYPE ONE_VAL_PAR|BRD_OPT_ON|VOLATILE
//
pagelinks = (
(
CAMERA_LINK_AV * CT_FS * ( ( VDT_CL_USE_CAMERA_VALID == 1 ) | ( VDT_CL_USE_CAMERA_VALID == 4 ) )
) ?
(
VDT_NOVERT.SETVALUE[0] + VDT_INTERL.SETVALUE[0] + VDT_NINTRL.SETVALUE[1] +
VDC_DIG.SETVALUE[1] + VDC_ANA.SETVALUE[0] + VDC_TTL.SETVALUE[0] + VDC_LVDS.SETVALUE[1] +
SYC_ANA.SETVALUE[0] + SYC_DIG.SETVALUE[1] + VDT_CLP_BPO.SETVALUE[0] + SYC_COMP.SETVALUE[0] +
SYC_MD_CSYN.SETVALUE[0] + SYC_MD_HVSY.SETVALUE[1] + SYC_MD_VSYN.SETVALUE[0] + VDT_CL_USE_CAMERA_VALID.SETVALUE[1] +
SYC_MD_HSYN.SETVALUE[0] + SYC_H_IN.SETVALUE[1] + SYC_H_ILVDS.SETVALUE[1] + SYC_H_ITTL.SETVALUE[0] +
SYC_H_IPOS.SETVALUE[1] + SYC_V_IN.SETVALUE[1] + SYC_V_ILVDS.SETVALUE[1] + SYC_V_ITTL.SETVALUE[0] +
SYC_V_IPOS.SETVALUE[1] + TAP_ORDERS.SETVALUE[0x343efcea]
) :
( (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * CT_FS *
(
( VDC_ANA * VDT_STD_170 ) | ( VDC_ANA * VDT_STD_CCIR ) |
(
( PCK_FREQ == 20000000 ) * ( VDT_HSYNC == 0 ) * ( VDT_HBPORCH == 0 ) * ( VDT_HACTIVE == 1024 ) * ( VDT_HFPORCH == 0 ) *
( VDT_VSYNC == 0 ) * ( VDT_VBPORCH == 0 ) * ( VDT_VACTIVE == 1024 ) * ( VDT_VFPORCH == 0 )
)
)
) ?
(
VDT_NOVERT.SETVALUE[0] + VDT_INTERL.SETVALUE[0] + VDT_NINTRL.SETVALUE[1] +
VDC_DIG.SETVALUE[1] + VDC_ANA.SETVALUE[0] + VDC_TTL.SETVALUE[0] + VDC_LVDS.SETVALUE[1] +
SYC_ANA.SETVALUE[0] + SYC_DIG.SETVALUE[1] + VDT_CLP_BPO.SETVALUE[0] + SYC_COMP.SETVALUE[0] +
SYC_MD_CSYN.SETVALUE[0] + SYC_MD_HVSY.SETVALUE[1] +
SYC_MD_VSYN.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[0] + SYC_H_IN.SETVALUE[1] +
SYC_H_ITTL.SETVALUE[1] + SYC_H_ILVDS.SETVALUE[0] + SYC_H_IPOS.SETVALUE[1] + SYC_V_IN.SETVALUE[1] +
SYC_V_ITTL.SETVALUE[1] + SYC_V_ILVDS.SETVALUE[0] + SYC_V_IPOS.SETVALUE[1] + TAP_ORDERS.SETVALUE[0x343efcea]
) :
( (
( DEF_ODYSSEY_ANA | DEF_HELIOS_ANA | DEF_SOLIOS_ANA ) * ( TM_ENABLE == 0 ) *
(
( VDT_STD_170 * SYC_ANA ) | VDC_DIG |
( VDT_STD_170 * SYC_ANA * SYC_MD_CSYN * VDC_ANA * VDC_IN_CH0 * ( ! VDC_USE_PSG_0 ) )
)
) ?
(
VDC_DIG.SETVALUE[0] + VDC_ANA.SETVALUE[1] + VDC_TTL.SETVALUE[0] + VDC_422.SETVALUE[0] +
SYC_ANA.SETVALUE[1] + SYC_DIG.SETVALUE[0] + SYC_COMP.SETVALUE[1] +
SYC_MD_CSYN.SETVALUE[1] + SYC_MD_HVSY.SETVALUE[0] + VDT_CLP_BPO.SETVALUE[1] +
SYC_MD_VSYN.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[0] + VDC_0_AC_WITH_DC.SETVALUE[1] +
VDT_NOVERT.SETVALUE[0] + VDT_INTERL.SETVALUE[1] + VDT_NINTRL.SETVALUE[0] + SYC_H_IN.SETVALUE[0] +
SYC_H_ITTL.SETVALUE[0] + SYC_H_ILVDS.SETVALUE[0] + SYC_H_IPOS.SETVALUE[0] + SYC_V_IN.SETVALUE[0] +
SYC_V_ITTL.SETVALUE[0] + SYC_V_ILVDS.SETVALUE[0] + SYC_V_IPOS.SETVALUE[0] +
TAP_ORDERS.SETVALUE[0x343efcea] + PCK_FREQ.SETVALUE[12272700]
) :
( (
( DEF_ODYSSEY_ANA | DEF_HELIOS_ANA | DEF_SOLIOS_ANA ) * ( TM_ENABLE == 0 ) *
(
( VDT_STD_CCIR * SYC_ANA ) | VDC_DIG |
( VDT_STD_CCIR * SYC_ANA * ( SYC_DIG == 0 ) * VDC_ANA * VDC_IN_CH0 * ( ! VDC_USE_PSG_0 ) )
)
) ?
( VDC_DIG.SETVALUE[0] + VDC_ANA.SETVALUE[1] + VDC_TTL.SETVALUE[0] + VDC_422.SETVALUE[0] +
SYC_ANA.SETVALUE[1] + SYC_DIG.SETVALUE[0] + SYC_COMP.SETVALUE[1] +
SYC_MD_CSYN.SETVALUE[1] + SYC_MD_HVSY.SETVALUE[0] + VDT_CLP_BPO.SETVALUE[1] +
SYC_MD_VSYN.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[0] + VDC_0_AC_WITH_DC.SETVALUE[1] +
VDT_NOVERT.SETVALUE[0] + VDT_INTERL.SETVALUE[1] + VDT_NINTRL.SETVALUE[0] + SYC_H_IN.SETVALUE[0] +
SYC_H_ITTL.SETVALUE[0] + SYC_H_ILVDS.SETVALUE[0] + SYC_H_IPOS.SETVALUE[0] + SYC_V_IN.SETVALUE[0] +
SYC_V_ITTL.SETVALUE[0] + SYC_V_ILVDS.SETVALUE[0] + SYC_V_IPOS.SETVALUE[0] +
TAP_ORDERS.SETVALUE[0x343efcea] + PCK_FREQ.SETVALUE[14750000]
) : 1 ) ) )
) + GSYC_FORMAT.UPDATE + GSYC_TYPE.UPDATE + GSYC_DIG_V_IN.UPDATE + GSYC_DIG_H_IN.UPDATE + GVDC_VID_SIGNAL_STD.UPDATE +
GGRB_LINESCAN.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE + GVDT_TYPE.UPDATE + GCT_CAMERA_TYPE.UPDATE +
GVDT_CLAMPING.UPDATE + GCL_CONFIG_MODE.VALID ;
//
// ( VDC_DIG * ( ( VDT_VACTIVE == 480 ) | ( VDT_VACTIVE == 1024 ) ) ) |
board_specific_value
NO_STRING M_DEFAULT DUMMY_PAR OPTION_HELIOS_CL_DUAL no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_HELIOS_CL_FULL no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_HELIOS_ANA no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_HELIOS_DIG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_ODYSSEY_CL_DUAL no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_ODYSSEY_CL_FULL no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_ODYSSEY_ANA no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_ODYSSEY_DIG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_SOLIOS_CL_DUAL no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_SOLIOS_CL_MEDIUM no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_SOLIOS_SINGLE_ANA no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_SOLIOS_DUAL_ANA no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_SOLIOS_QUAD_ANA no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_SOLIOS_DIG no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDC_DIGITIZER IS_INTERACTIVE
//
param_info
Camera
Digitizer Number
eo_param_info
//
valid = (
( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 0 ) * DEF_AC1_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM0_AC1] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 0 ) * DEF_AC2_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM0_AC2] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 0 ) * DEF_AC3_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM0_AC3] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 1 ) * DEF_AC0_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM1_AC0] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 1 ) * DEF_AC2_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM1_AC2] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 1 ) * DEF_AC3_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM1_AC3] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 2 ) * DEF_AC0_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM2_AC0] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 2 ) * DEF_AC1_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM2_AC1] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 2 ) * DEF_AC3_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM2_AC3] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 3 ) * DEF_AC0_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM3_AC0] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 3 ) * DEF_AC1_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM3_AC1] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 3 ) * DEF_AC2_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM3_AC2] : 0 ) ) ) ) ) ) ) ) ) ) )
) ;
//
error_message
ERR_DIG_NUM0_AC1, "Digitizer 0 does not match with the Acquisition Path selected. Change Digitizer number to 1 or the AP1 to AP0 on the Tab Overview."
ERR_DIG_NUM0_AC2, "Digitizer 0 does not match with the Acquisition Path selected. Change Digitizer number to 2 or the AP2 to AP0 on the Tab Overview."
ERR_DIG_NUM0_AC3, "Digitizer 0 does not match with the Acquisition Path selected. Change Digitizer number to 3 or the AP3 to AP0 on the Tab Overview."
ERR_DIG_NUM1_AC0, "Digitizer 1 does not match with the Acquisition Path selected. Change Digitizer number to 0 or the AP0 to AP1 on the Tab Overview."
ERR_DIG_NUM1_AC2, "Digitizer 1 does not match with the Acquisition Path selected. Change Digitizer number to 2 or the AP2 to AP1 on the Tab Overview."
ERR_DIG_NUM1_AC3, "Digitizer 1 does not match with the Acquisition Path selected. Change Digitizer number to 3 or the AP3 to AP1 on the Tab Overview."
ERR_DIG_NUM2_AC0, "Digitizer 2 does not match with the Acquisition Path selected. Change Digitizer number to 0 or the AP0 to AP2 on the Tab Overview."
ERR_DIG_NUM2_AC1, "Digitizer 2 does not match with the Acquisition Path selected. Change Digitizer number to 1 or the AP1 to AP2 on the Tab Overview."
ERR_DIG_NUM2_AC3, "Digitizer 2 does not match with the Acquisition Path selected. Change Digitizer number to 3 or the AP3 to AP2 on the Tab Overview."
ERR_DIG_NUM3_AC0, "Digitizer 3 does not match with the Acquisition Path selected. Change Digitizer number to 0 or the AP0 to AP3 on the Tab Overview."
ERR_DIG_NUM3_AC1, "Digitizer 3 does not match with the Acquisition Path selected. Change Digitizer number to 1 or the AP1 to AP3 on the Tab Overview."
ERR_DIG_NUM3_AC2, "Digitizer 3 does not match with the Acquisition Path selected. Change Digitizer number to 2 or the AP2 to AP3 on the Tab Overview."
eo_error_message
//
eo_param
// --------------------------------------
//
// ********** Camera **********
//
GCT_CAMERA_NUMBER IS_INTERACTIVE
//
param_info
Camera
Number of Cameras
eo_param_info
//
pagelinks = ( GVDC_PSG_MODE.VALID + GTAP_REGIONSX.VALID + GVDC_PSG_0.UPDATE + GVDC_PSG_1.UPDATE +
GVDC_PSG_2.UPDATE + GVDC_PSG_3.UPDATE + GVDC_DIGITIZER.UPDATE
) ;
//
eo_param
// --------------------------------------
//
GCT_CAMERA_TAPS IS_INTERACTIVE
//
param_info
Camera
Number of Taps
eo_param_info
//
enable = ENABLE[1] ;
//
pagelinks = ( GVDC_PSG_MODE.VALID + GTAP_REGIONSX.VALID ) ;
//
valid = (
( ( CT_TAPS == 3 ) * TM_ENABLE * ( OPTION_ODYSSEY_DIG | OPTION_SOLIOS_DIG | OPTION_SOLIOS_DIG ) )
? ADDERROR[ERR_TOOMUCH_TAPS_TEST_MODE] : 0
) ;
//
error_message
ERR_TOOMUCH_TAPS_TEST_MODE, "8 Taps Not Supported in Test Mode with Digital Acquisition Board. Change the setting 1 to 4 Taps."
eo_error_message
//
eo_param
// --------------------------------------
//
GTAP_MULTIPLEX_X MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Tap Multiplexing Pixels in X
eo_param_info
//
pagelinks = ( DEF_TAPS_MULTIPLEX_X ? TAP_MULTIPLEX_X.SETVALUE[2] : TAP_MULTIPLEX_X.SETVALUE[1] ) ;
//
board_specific_value
0 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_0PCK_AV no
1 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_1PCK_AV yes 1
2 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_2PCK_AV yes
3 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_3PCK_AV yes
4 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_4PCK_AV yes
5 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_5PCK_AV yes
6 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_6PCK_AV yes
7 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_7PCK_AV yes
8 M_DEFAULT TAP_MULTIPLEX_X TAP_MTPLX_X_8PCK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GTAP_MULTIPLEX_Y MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Tap Multiplexing Pixels in Y
eo_param_info
//
pagelinks = ( DEF_TAPS_MULTIPLEX_Y ? TAP_MULTIPLEX_Y.SETVALUE[2] : TAP_MULTIPLEX_Y.SETVALUE[1] ) ;
//
board_specific_value
0 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_0PCK_AV no
1 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_1PCK_AV yes 1
2 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_2PCK_AV yes
3 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_3PCK_AV yes
4 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_4PCK_AV yes
5 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_5PCK_AV yes
6 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_6PCK_AV yes
7 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_7PCK_AV yes
8 M_DEFAULT TAP_MULTIPLEX_Y TAP_MTPLX_Y_8PCK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Tap Orders **********
//
GTAP_TAPORDERS NUM_PAR|ED_FLD_LONG|BRD_OPT_ON|IS_INTERACTIVE
//BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Tap Orders
eo_param_info
//
pagelinks = ( ( TAP_ORDERS == 0 ) ? TAP_ORDERS.SETVALUE[0x343efcea] : 0 ) ;
//
board_specific_value
NO_STRING M_DEFAULT TAP_ORDERS BOPTION_NOT_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Region Directions **********
//
GTAP_REGIONDIRECTIONS NUM_PAR|ED_FLD_LONG|BRD_OPT_ON|IS_INTERACTIVE
//BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Region Directions
eo_param_info
//
pagelinks = (
GCT_CAMERA_TAPS.UPDATE + GTAP_REGIONSX.UPDATE + GTAP_REGIONSY.UPDATE +
GTAP_PIXADJX.UPDATE + GTAP_PIXADJY.UPDATE
) ;
//
board_specific_value
NO_TRING M_DEFAULT REGION_DIRECTIONS BOPTION_NOT_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Tap configuration **********
//
GTAP_REGIONSX MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Number of regions in X
eo_param_info
//
enable = ENABLE[GTAP_AV] ;
//
pagelinks = ( GCT_CAMERA_TAPS.UPDATE + GCT_CAMERA_NUMBER.UPDATE + GTAP_REGIONSY.UPDATE +
GTAP_PIXADJX.UPDATE + GTAP_PIXADJY.UPDATE + GCT_CAMERA_TYPE.UPDATE + GTAP_MULTIPLEX_X.VALID + GVDC_PSG_MODE.VALID
) ;
//
valid = (
( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) * ( CT_CAMERA == 1 ) * ( CT_TAPS > 0 ) )
? ADDERROR[ERR_DIG_TAPS_CAMS_EXCEED] :
( ( ( TAP_REGIONSX * TAP_REGIONSY * TAP_PIXADJX * TAP_PIXADJY ) > 8 )
? ADDERROR[ERR_OVER_8TAPS] :
( ( ( TAP_REGIONSX * TAP_REGIONSY * TAP_PIXADJX * TAP_PIXADJY ) > ( 2 ^ CT_TAPS ) )
? ADDERROR[ERR_TAPS_MISSING] :
( ( ( TAP_REGIONSX * TAP_REGIONSY * TAP_PIXADJX * TAP_PIXADJY ) < ( 2 ^ CT_TAPS ) )
? ADDERROR[ERR_TAPS_TOOMANY] :
( ( CAMERA_LINK_AV * ( ( 2 ^ CT_TAPS ) != DEF_CL_NUM_TAPS ) * ( DEF_CL_NUM_TAPS == 1 ) )
? ADDERROR[ERR_TAPS_CL_1] :
( ( CAMERA_LINK_AV * ( ( 2 ^ CT_TAPS ) != DEF_CL_NUM_TAPS ) * ( DEF_CL_NUM_TAPS == 2 ) )
? ADDERROR[ERR_TAPS_CL_2] :
( ( CAMERA_LINK_AV * ( ( 2 ^ CT_TAPS ) != DEF_CL_NUM_TAPS ) * ( DEF_CL_NUM_TAPS == 4 ) )
? ADDERROR[ERR_TAPS_CL_4] :
( ( CAMERA_LINK_AV * ( ( 2 ^ CT_TAPS ) != DEF_CL_NUM_TAPS ) * ( DEF_CL_NUM_TAPS == 8 ) )
? ADDERROR[ERR_TAPS_CL_8] :
0 ) ) ) ) ) ) )
) ;
//
error_message
ERR_DIG_TAPS_CAMS_EXCEED, "Too many cameras and taps selected in RGB Color. Reduce the number of cameras or taps."
ERR_OVER_8TAPS, "Too much taps needed by digitizer. Maximum of 8 taps. Reduce number of Regions X or Y or Adjacent Pixels X or Y in Tap Configuration page."
ERR_TAPS_MISSING, "Number of taps less than Tap Configuration needed. Readjust Tap Configuration (Taps = RegionsX*Y * Adj.PixX*Y) or increase number of taps."
ERR_TAPS_TOOMANY, "Number of taps exceeded Tap Configuration needed. Readjust Tap Configuration (Taps = RegionsX*Y * Adj.PixX*Y) or decrease number of taps."
ERR_TAPS_CL_1, "Number of taps must match camera mode selected in Camera Link Configuration. Readjust number to 1 tap or camera mode selection."
ERR_TAPS_CL_2, "Number of taps must match camera mode selected in Camera Link Configuration. Readjust number to 2 taps or camera mode selection."
ERR_TAPS_CL_4, "Number of taps must match camera mode selected in Camera Link Configuration. Readjust number to 4 taps or camera mode selection."
ERR_TAPS_CL_8, "Number of taps must match camera mode selected in Camera Link Configuration. Readjust number to 8 taps or camera mode selection."
eo_error_message
//
board_specific_value
0 M_DEFAULT TAP_REGIONSX BOPTION_NOT_AV no
1 M_DEFAULT TAP_REGIONSX GTAP_AV yes 1
2 M_DEFAULT TAP_REGIONSX GTAP_AV yes
3 M_DEFAULT TAP_REGIONSX GTAP_3_TAP_AV no
4 M_DEFAULT TAP_REGIONSX GTAP_AV yes
5 M_DEFAULT TAP_REGIONSX GTAP_5_TAP_AV no
6 M_DEFAULT TAP_REGIONSX GTAP_6_TAP_AV no
7 M_DEFAULT TAP_REGIONSX BOPTION_NOT_AV no
8 M_DEFAULT TAP_REGIONSX GTAP_AV yes
9 M_DEFAULT TAP_REGIONSX GTAP_9_TAP_AV no
10 M_DEFAULT TAP_REGIONSX GTAP_10_TAP_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GTAP_REGIONSY MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Number of regions in Y
eo_param_info
//
enable = ENABLE[GTAP_AV] ;
//
pagelinks = ( GTAP_REGIONSX.VALID + GCT_CAMERA_TYPE.UPDATE + GTAP_MULTIPLEX_Y.VALID + GVDC_PSG_MODE.VALID ) ;
//
board_specific_value
0 M_DEFAULT TAP_REGIONSY BOPTION_NOT_AV no
1 M_DEFAULT TAP_REGIONSY GTAP_AV yes 1
2 M_DEFAULT TAP_REGIONSY GTAP_AV yes
3 M_DEFAULT TAP_REGIONSY GTAP_3_TAP_AV no
4 M_DEFAULT TAP_REGIONSY GTAP_AV yes
5 M_DEFAULT TAP_REGIONSY GTAP_5_TAP_AV no
6 M_DEFAULT TAP_REGIONSY GTAP_6_TAP_AV no
7 M_DEFAULT TAP_REGIONSY BOPTION_NOT_AV no
8 M_DEFAULT TAP_REGIONSY GTAP_AV yes
9 M_DEFAULT TAP_REGIONSY GTAP_9_TAP_AV no
10 M_DEFAULT TAP_REGIONSY GTAP_10_TAP_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GTAP_PIXADJX MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Number of adjacent pixels per region in X
eo_param_info
//
enable = ENABLE[GTAP_AV] ;
//
pagelinks = ( GTAP_REGIONSX.VALID + GTAP_MULTIPLEX_X.VALID + GVDC_PSG_MODE.VALID ) ;
//
board_specific_value
0 M_DEFAULT TAP_PIXADJX BOPTION_NOT_AV no
1 M_DEFAULT TAP_PIXADJX GTAP_AV yes 1
2 M_DEFAULT TAP_PIXADJX GTAP_AV yes
3 M_DEFAULT TAP_PIXADJX GTAP_3_TAP_AV no
4 M_DEFAULT TAP_PIXADJX GTAP_AV yes
5 M_DEFAULT TAP_PIXADJX GTAP_5_TAP_AV no
6 M_DEFAULT TAP_PIXADJX GTAP_6_TAP_AV no
7 M_DEFAULT TAP_PIXADJX BOPTION_NOT_AV no
8 M_DEFAULT TAP_PIXADJX GTAP_AV yes
9 M_DEFAULT TAP_PIXADJX GTAP_9_TAP_AV no
10 M_DEFAULT TAP_PIXADJX GTAP_10_TAP_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GTAP_PIXADJY MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Tap Configuration
Number of adjacent pixels per region in Y
eo_param_info
//
enable = ENABLE[GTAP_AV] ;
//
pagelinks = ( GTAP_REGIONSX.VALID + GCT_CAMERA_TYPE.UPDATE + GTAP_MULTIPLEX_Y.VALID + GVDC_PSG_MODE.VALID ) ;
//
board_specific_value
0 M_DEFAULT TAP_PIXADJY BOPTION_NOT_AV no
1 M_DEFAULT TAP_PIXADJY GTAP_AV yes 1
2 M_DEFAULT TAP_PIXADJY GTAP_AV yes
3 M_DEFAULT TAP_PIXADJY GTAP_3_TAP_AV no
4 M_DEFAULT TAP_PIXADJY GTAP_AV yes
5 M_DEFAULT TAP_PIXADJY GTAP_5_TAP_AV no
6 M_DEFAULT TAP_PIXADJY GTAP_6_TAP_AV no
7 M_DEFAULT TAP_PIXADJY BOPTION_NOT_AV no
8 M_DEFAULT TAP_PIXADJY GTAP_AV yes
9 M_DEFAULT TAP_PIXADJY GTAP_9_TAP_AV no
10 M_DEFAULT TAP_PIXADJY GTAP_10_TAP_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Camera link configuration **********
//
GCL_CONFIG_MODE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Configuration mode
eo_param_info
//
enable = ENABLE[CAMERA_LINK_AV] ;
//
pagelinks = (
( ( CLC_MODE == 0 ) & VDC_MONO & ( CLC_MODE_CH0 > 4 ) & ( CLC_MODE_CH0 != 7 ) & ( CLC_MODE_CH0 != 8 ) )
? CLC_MODE_CH0.SETVALUE[1] :
( ( ( CLC_MODE == 1 ) & VDC_MONO & ( CLC_MODE_CH0 != 9 ) & ( CLC_MODE_CH0 != 12 ) & ( CLC_MODE_CH0 != 13 ) & ( CLC_MODE_CH0 != 15 ) )
? CLC_MODE_CH0.SETVALUE[9] :
( ( ( CLC_MODE == 2 ) & ( CLC_MODE_CH0 != 16 ) & ( CLC_MODE_CH0 != 17 ) )
? CLC_MODE_CH0.SETVALUE[16] :
( ( ( CLC_MODE == 0 ) & VDC_RGB_COL & ( CLC_MODE_CH0 != 5 ) & ( CLC_MODE_CH0 != 6 ) )
? CLC_MODE_CH0.SETVALUE[5] :
( ( ( CLC_MODE == 1 ) & VDC_RGB_COL & ( CLC_MODE_CH0 != 10 ) & ( CLC_MODE_CH0 != 11 ) & ( CLC_MODE_CH0 != 14 ) )
? CLC_MODE_CH0.SETVALUE[10] :
1 ) ) ) )
) + GCL_MODE_CH0.UPDATE + GCL_MODE_CH0.VALID + GTAP_REGIONSX.VALID + GGEN_BOARD_TYPE.UPDATE +
GVDC_VID_SIGNAL_STD.UPDATE ;
//
valid = (
( ( OPTION_SOLIOS_CL_MEDIUM | OPTION_SOLIOS_CL_DUAL ) * ( CLC_MODE == 2 ) )
? ADDERROR[ERR_CL_FULL_NOT_AV] :
( ( ( DCF_IS_VIRTUAL == 0 ) * DEF_SOLIOS_CL_DUAL * ( CLC_MODE_CH0 > 8 ) )
? ADDERROR[ERR_CL_MEDIUM_FULL_NOT_AV] :
( (
( DCF_IS_VIRTUAL == 0 ) * ( DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL ) *
( CLC_MODE_CH0 > 8 )
) ? ADDERROR[ERR_CL_DUAL_NOT_BASE] :
( ( ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) * ( CLC_MODE == 2 ) )
? ADDERROR[ERR_CL_FULL_RGB_AV] : 0 ) ) )
) ;
//
error_message
ERR_CL_FULL_NOT_AV, "Camera Link Configuration FULL Not available with the SOLIOS board selected. Set the configuration to Base or Medium."
ERR_CL_MEDIUM_FULL_NOT_AV, "Camera Link Configuration MEDIUM/FULL Not available with the SOLIOS board CL/DUAL selected. Set the configuration to Base."
ERR_CL_DUAL_NOT_BASE, "Camera Link Configuration MEDIUM/FULL Not available with the ODYSSEY/HELIOS board CL/DUAL selected. Set the configuration to Base."
ERR_CL_FULL_RGB_AV, "RGB Video Not available in Camera Link Configuration FULL. Select Base or Medium configuration."
eo_error_message
//
board_specific_value
base M_DEFAULT CLC_MODE CL_CONFIG_BASE_AV yes 0
medium M_DEFAULT CLC_MODE CL_CONFIG_MEDIUM_AV yes
full M_DEFAULT CLC_MODE CL_CONFIG_FULL_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_ACTIVE_CH0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Activate Channel 0
eo_param_info
//
enable = ENABLE[CAMERA_LINK_AV] ;
//
pagelinks = ( GCL_MODE_CH0.VALID + GCL_CONFIG_MODE.VALID ) ;
//
board_specific_value
no M_DEFAULT CLC_ACTIVE_CH0 CAMERA_LINK_AV yes
yes M_DEFAULT CLC_ACTIVE_CH0 CL_CHANNEL0_AV yes 1
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDT_CL_USE_CAMERA_VALID MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
enable = ENABLE[CAMERA_LINK_AV] ;
//
pagelinks = (
( CAMERA_LINK_AV * CT_LS * ( VDT_CL_USE_CAMERA_VALID < 3 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[4] :
( ( CAMERA_LINK_AV * CT_FS * ( VDT_CL_USE_CAMERA_VALID > 2 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[1] :
( ( ( CAMERA_LINK_AV == 0 ) * CT_FS ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[1] :
( ( ( CAMERA_LINK_AV == 0 ) * CT_LS ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[4] : 0 ) ) )
) + GCT_CAMERA_TYPE.UPDATE + GVDT_HORIZONTAL.UPDATE + GVDT_VERTICAL.UPDATE +
GCL_MODE_CH0.UPDATE + GVDT_CL_USE_CAMERA_VALID.UPDATE ;
//
board_specific_value
"Use LVAL/FVAL/DVAL from Frame Grabber" M_DEFAULT VDT_CL_USE_CAMERA_VALID VDT_CL_USE_CAMERA_VALID_FS_AV yes
"Use LVAL/FVAL from Camera" M_DEFAULT VDT_CL_USE_CAMERA_VALID VDT_CL_USE_CAMERA_VALID_FS_CL_AV yes 1
"Use LVAL/FVAL/DVAL from Camera" M_DEFAULT VDT_CL_USE_CAMERA_VALID VDT_CL_USE_CAMERA_VALID_FS_CL_AV yes
"Use LVAL/DVAL from Frame Grabber" M_DEFAULT VDT_CL_USE_CAMERA_VALID VDT_CL_USE_CAMERA_VALID_LS_AV yes
"Use LVAL from Camera" M_DEFAULT VDT_CL_USE_CAMERA_VALID VDT_CL_USE_CAMERA_VALID_LS_CL_AV yes
"Use LVAL/DVAL from Camera" M_DEFAULT VDT_CL_USE_CAMERA_VALID VDT_CL_USE_CAMERA_VALID_LS_CL_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDT_CL_SIZEX MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Video Timing / Image SixeX
Image Size in X
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) )] ;
//
pagelinks = (
(
( VDT_CL_IMAGE_SIZE_X > 0 ) *
(
( ( VDT_CL_USE_CAMERA_VALID * CT_FS ) > 0 ) |
( ( VDT_CL_USE_CAMERA_VALID * CT_LS ) > 3 )
)
) ?
( VDT_HACTIVE.SETVALUE[VDT_CL_IMAGE_SIZE_X] + VDT_CL_IMAGE_SIZE_X.SETVALUE[0] ) : VDT_CL_IMAGE_SIZE_X.SETVALUE[0]
) + GVDT_CL_USE_CAMERA_VALID.UPDATE ;
//
board_specific_value
NO_STRING M_DEFAULT VDT_CL_IMAGE_SIZE_X VDT_CL_IMAGE_SIZE_X_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDT_CL_SIZEY MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Video Timing / Image SixeY
Image Size in Y
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) )] ;
//
pagelinks = (
(
( VDT_CL_IMAGE_SIZE_Y > 0 ) *
(
( ( VDT_CL_USE_CAMERA_VALID * CT_FS ) > 0 ) |
( ( VDT_CL_USE_CAMERA_VALID * CT_LS ) > 3 )
)
) ?
( VDT_VACTIVE.SETVALUE[VDT_CL_IMAGE_SIZE_Y] + VDT_CL_IMAGE_SIZE_Y.SETVALUE[0] ) : VDT_CL_IMAGE_SIZE_Y.SETVALUE[0]
) + GVDT_CL_USE_CAMERA_VALID.UPDATE ;
//
board_specific_value
NO_STRING M_DEFAULT VDT_CL_IMAGE_SIZE_Y VDT_CL_IMAGE_SIZE_Y_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDT_CL_CROPPINGX MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Video Timing / CroppingX
Image Cropping in X
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * SYC_CAM_GEN * ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) )] ;
//
pagelinks = (
(
( VDT_CL_CROPPING_X > 0 ) *
(
( ( VDT_CL_USE_CAMERA_VALID * CT_FS ) > 0 ) |
( ( VDT_CL_USE_CAMERA_VALID * CT_LS ) > 3 )
)
) ?
(
VDT_HBPORCH.SETVALUE[VDT_CL_CROPPING_X] + VDT_CL_CROPPING_X.SETVALUE[0] +
VDT_HSYNC.SETVALUE[0] + VDT_HFPORCH.SETVALUE[0]
) : VDT_CL_CROPPING_X.SETVALUE[0]
) + GVDT_CL_USE_CAMERA_VALID.UPDATE ;
//
board_specific_value
NO_STRING M_DEFAULT VDT_CL_CROPPING_X VDT_CL_CROPPING_X_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDT_CL_CROPPINGY MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Video Timing / CroppingY
Image Cropping in Y
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * SYC_CAM_GEN * ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) )] ;
//
pagelinks = (
(
( VDT_CL_CROPPING_Y > 0 ) *
(
( ( VDT_CL_USE_CAMERA_VALID * CT_FS ) > 0 ) |
( ( VDT_CL_USE_CAMERA_VALID * CT_LS ) > 3 )
)
) ?
(
VDT_VBPORCH.SETVALUE[VDT_CL_CROPPING_Y] + VDT_CL_CROPPING_Y.SETVALUE[0] +
VDT_VSYNC.SETVALUE[0] + VDT_VFPORCH.SETVALUE[0]
) : VDT_CL_CROPPING_Y.SETVALUE[0]
) + GVDT_CL_USE_CAMERA_VALID.UPDATE ;
//
board_specific_value
NO_STRING M_DEFAULT VDT_CL_CROPPING_Y VDT_CL_CROPPING_Y_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_MODE_BITMAP MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Camera Link Bitmap
eo_param_info
//
enable = ENABLE[CL_CHANNEL0_AV] ;
//
pagelinks = (
( ( CLC_MODE_CH0 == 1 ) * VDC_WD8 ) ? CL_MODE_BITMAP.SETVALUE[0] :
( ( ( CLC_MODE_CH0 == 1 ) * ( VDC_VID_WIDTH_10 | VDC_VID_WIDTH_12 ) ) ? CL_MODE_BITMAP.SETVALUE[1] :
( ( ( CLC_MODE_CH0 == 1 ) * ( VDC_VID_WIDTH_14 | VDC_VID_WIDTH_16 ) ) ? CL_MODE_BITMAP.SETVALUE[2] :
( ( CLC_MODE_CH0 == 2 ) ? CL_MODE_BITMAP.SETVALUE[3] :
( ( CLC_MODE_CH0 == 3 ) ? CL_MODE_BITMAP.SETVALUE[4] :
( ( CLC_MODE_CH0 == 4 ) ? CL_MODE_BITMAP.SETVALUE[5] :
( ( CLC_MODE_CH0 == 5 ) ? CL_MODE_BITMAP.SETVALUE[6] :
( ( CLC_MODE_CH0 == 6 ) ? CL_MODE_BITMAP.SETVALUE[7] :
( ( CLC_MODE_CH0 == 7 ) ? CL_MODE_BITMAP.SETVALUE[9] :
( ( CLC_MODE_CH0 == 8 ) ? CL_MODE_BITMAP.SETVALUE[10] :
( ( CLC_MODE_CH0 == 9 ) ? CL_MODE_BITMAP.SETVALUE[11] :
( ( CLC_MODE_CH0 == 10 ) ? CL_MODE_BITMAP.SETVALUE[12] :
( ( CLC_MODE_CH0 == 11 ) ? CL_MODE_BITMAP.SETVALUE[13] :
( ( CLC_MODE_CH0 == 12 ) ? CL_MODE_BITMAP.SETVALUE[14] :
( ( CLC_MODE_CH0 == 13 ) ? CL_MODE_BITMAP.SETVALUE[15] :
( ( CLC_MODE_CH0 == 14 ) ? CL_MODE_BITMAP.SETVALUE[16] :
( ( CLC_MODE_CH0 == 15 ) ? CL_MODE_BITMAP.SETVALUE[17] :
( ( CLC_MODE_CH0 == 16 ) ? CL_MODE_BITMAP.SETVALUE[18] :
( ( CLC_MODE_CH0 == 17 ) ? CL_MODE_BITMAP.SETVALUE[19] : 0 ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )
) + GCL_MODE_CH0.UPDATE + GVDC_VID_WIDTH.UPDATE ;
//
board_specific_value
0 M_DEFAULT CL_MODE_BITMAP 1Tap_8_Bits_AV yes
1 M_DEFAULT CL_MODE_BITMAP 1Tap_10/12_Bits_AV yes
2 M_DEFAULT CL_MODE_BITMAP 1Tap_14/16_Bits_AV yes
3 M_DEFAULT CL_MODE_BITMAP 2Taps_8_Bits_AV yes
4 M_DEFAULT CL_MODE_BITMAP 2Taps_10/12_Bits_AV yes
5 M_DEFAULT CL_MODE_BITMAP 2Taps_14/16_Bits_TimeMultiplexed_AV yes
6 M_DEFAULT CL_MODE_BITMAP 3Taps_8_Bits_RGB_AV yes
7 M_DEFAULT CL_MODE_BITMAP 6Taps_8_Bits_TimeMultiplexed_2xRGB_AV yes
8 M_DEFAULT CL_MODE_BITMAP 2Taps_8_Bits_TimeMultiplexed_AV yes
9 M_DEFAULT CL_MODE_BITMAP 4Taps_8_Bits_TimeMultiplexed_AV yes
10 M_DEFAULT CL_MODE_BITMAP 4Taps_10/12_Bits_TimeMultiplexed_AV yes
11 M_DEFAULT CL_MODE_BITMAP 2Taps_14/16_Bits_AV yes
12 M_DEFAULT CL_MODE_BITMAP 3Taps_10/12_Bits_RGB_AV yes
13 M_DEFAULT CL_MODE_BITMAP 6Taps_8_Bits_2xRGB_AV yes
14 M_DEFAULT CL_MODE_BITMAP 4Taps_8_Bits_AV yes
15 M_DEFAULT CL_MODE_BITMAP 4Taps_10/12_Bits_AV yes
16 M_DEFAULT CL_MODE_BITMAP 3Taps_14/16_Bits_RGB_AV yes
17 M_DEFAULT CL_MODE_BITMAP 8Taps_8_Bits_TimeMultiplexed_AV yes
18 M_DEFAULT CL_MODE_BITMAP 8Taps_8_Bits_AV yes
19 M_DEFAULT CL_MODE_BITMAP 4Taps_16_Bits_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_MODE_CH0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Channel 0 mode
eo_param_info
//
enable = ENABLE[CL_CHANNEL0_AV] ;
//
pagelinks = (
( CAMERA_LINK_AV * ( CLC_MODE_CH0 == 0 ) ) ? CLC_MODE_CH0.SETVALUE[1] :
( ( CAMERA_LINK_AV * VDC_RGB_COL * ( CLC_MODE == 0 ) * ( CLC_MODE_CH0 != 5 ) * ( CLC_MODE_CH0 != 6 ) )
? CLC_MODE_CH0.SETVALUE[5] :
( (
CAMERA_LINK_AV * VDC_MONO * ( CLC_MODE == 0 ) *
(
( CLC_MODE_CH0 == 5 ) | ( ( DEF_ODYSSEY_CL | DEF_HELIOS_CL | DEF_SOLIOS_CL ) * ( CLC_MODE_CH0 == 6 ) ) |
( CLC_MODE_CH0 == 9 )
)
)
? CLC_MODE_CH0.SETVALUE[1] :
( ( CAMERA_LINK_AV * VDC_RGB_COL * ( CLC_MODE == 1 ) * ( CLC_MODE_CH0 != 10 ) * ( CLC_MODE_CH0 != 11 ) * ( CLC_MODE_CH0 != 14 ) )
? CLC_MODE_CH0.SETVALUE[10] :
( ( CAMERA_LINK_AV * VDC_MONO * ( CLC_MODE == 1 ) * ( ( CLC_MODE_CH0 == 10 ) | ( CLC_MODE_CH0 == 11 ) | ( CLC_MODE_CH0 == 14 ) ) )
? CLC_MODE_CH0.SETVALUE[9] : 0 ) ) ) )
) + GVDC_VID_WIDTH.UPDATE + GCT_CAMERA_TAPS.UPDATE + GCL_MODE_BITMAP.VALID +
GVDC_PSG_MODE.VALID + GTAP_MULTIPLEX_X.VALID + GTAP_MULTIPLEX_Y.VALID ;
//
valid = (
( ( CAMERA_LINK_AV & ( DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL ) & ( ( CLC_MODE_CH0 == 6 ) | ( CLC_MODE_CH0 == 8 ) ) ) ? ADDERROR[ERR_MODE_NOT_AV] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_BUS_WIDTH == 8 ) & ( ! VDC_WD8 ) ) ? ADDERROR[ERR_8BITS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_BUS_WIDTH == 12 ) & ( ! ( VDC_VID_WIDTH_10 || VDC_VID_WIDTH_12 ) ) ) ? ADDERROR[ERR_12BITS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_BUS_WIDTH == 16 ) & ( ! ( VDC_VID_WIDTH_14 || VDC_VID_WIDTH_16 || VDC_WD16 ) ) ) ? ADDERROR[ERR_16BITS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_NUM_TAPS < ( 2 ^ CT_TAPS ) ) & ( DEF_CL_NUM_TAPS == 2 ) ) ? ADDERROR[ERR_LESS2TAPS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_NUM_TAPS < ( 2 ^ CT_TAPS ) ) & ( DEF_CL_NUM_TAPS == 4 ) ) ? ADDERROR[ERR_LESS4TAPS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_NUM_TAPS < ( 2 ^ CT_TAPS ) ) & ( DEF_CL_NUM_TAPS == 8 ) ) ? ADDERROR[ERR_LESS8TAPS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_NUM_TAPS > ( 2 ^ CT_TAPS ) ) & ( DEF_CL_NUM_TAPS == 2 ) ) ? ADDERROR[ERR_MORE2TAPS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_NUM_TAPS > ( 2 ^ CT_TAPS ) ) & ( DEF_CL_NUM_TAPS == 4 ) ) ? ADDERROR[ERR_MORE4TAPS] ) ||
( ( CAMERA_LINK_AV & ( DEF_CL_NUM_TAPS > ( 2 ^ CT_TAPS ) ) & ( DEF_CL_NUM_TAPS == 8 ) ) ? ADDERROR[ERR_MORE8TAPS] ) ||
( (
VDC_DIG * ( VDT_HACTIVE % 2 ) *
(
( CLC_MODE_CH0 == 4 ) |
( ( CLC_MODE_CH0 > 5 ) * ( CLC_MODE_CH0 < 9 ) ) |
( CLC_MODE_CH0 == 15 )
)
) ? ADDERROR[ERR_CL_TIMEMUX_HACT_ODD]
)
) ;
//
error_message
ERR_MODE_NOT_AV, "Mode selected Not available in Dual Base Configuration with 32 bits/Channel maximum. Select an other mode."
ERR_8BITS, "The data bus width must be adjusted to 8 bits as camera mode selected in Camera Link Configuration page."
ERR_12BITS, "The data bus width must be adjusted to 10 or 12 bits as camera mode selected in Camera Link Configuration page."
ERR_16BITS, "The data bus width must be adjusted to 14 or 16 bits as camera mode selected in Camera Link Configuration page."
ERR_LESS2TAPS, "The camera mode specified uses less taps than required by the data bus. Readjust number to 2 taps in Camera page."
ERR_LESS4TAPS, "The camera mode specified uses less taps than required by the data bus. Readjust number to 4 taps in Camera page."
ERR_LESS8TAPS, "The camera mode specified uses less taps than required by the data bus. Readjust number to 8 taps in Camera page."
ERR_MORE2TAPS, "The camera mode specified uses more taps than required by the data bus. Readjust number to 2 taps in Camera page."
ERR_MORE4TAPS, "The camera mode specified uses more taps than required by the data bus. Readjust number to 4 taps in Camera page."
ERR_MORE8TAPS, "The camera mode specified uses more taps than required by the data bus. Readjust number to 8 taps in Camera page."
ERR_CL_TIMEMUX_HACT_ODD, "The Horizontal Active Pixels should be Even number. Reajust Active from Video Timing Tab in Intellicam."
eo_error_message
//
board_specific_value
??? M_DEFAULT CLC_MODE_CH0 BOPTION_NOT_AV no
"1 Tap 8...16 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B1_MONO_AV yes 1
"2 Taps 8 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B2_MONO_AV yes
"2 Taps 10/12 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B3_MONO_AV yes
"2 Taps 14/16 Bits Time Multiplexed" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B4_MONO_AV yes
"3 Taps 8 Bits (RGB)" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B5_RGB_AV yes
"6 Taps 8 Bits Time Multiplexed (2xRGB)" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B6_RGB_AV yes
"4 Taps 8 Bits Time Multiplexed" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B7_MONO_AV yes
"4 Taps 10/12 Bits Time Multiplexed" M_DEFAULT CLC_MODE_CH0 CLC_MODE_B8_MONO_AV yes
"2 Taps 14/16 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M1_MONO_AV yes
"3 Taps 10/12 Bits (RGB)" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M2_RGB_AV yes
"6 Taps 8 Bits (2xRGB)" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M3_RGB_AV yes
"4 Taps 8 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M4_MONO_AV yes
"4 Taps 10/12 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M5_MONO_AV yes
"3 Taps 14/16 Bits (RGB)" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M6_RGB_AV yes
"8 Taps 8 Bits Time Multiplexed" M_DEFAULT CLC_MODE_CH0 CLC_MODE_M7_MONO_AV yes
"8 Taps 8 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_FULL_AV yes
"4 Taps 14/16 Bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_FULL_4TAPS_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_SYNC_SOURCE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Synchronization source selection
eo_param_info
//
enable = ENABLE[0] ;
//
board_specific_value
"grab channel" M_DEFAULT CLC_SYNC_SOURCE CAMERA_LINK_AV yes 0
"channel 0" M_DEFAULT CLC_SYNC_SOURCE CL_CHANNEL0_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_VSYNC_SEL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera / Camera Link Configuration
Vertical synchronization selection
eo_param_info
//
enable = ENABLE[0] ;
//
board_specific_value
"HSYNC selected (edge sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes 0
"LVDS trigger (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"Opto-coupled trigger (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"TTL trigger (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"User bit 0 (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"FVAL selected (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_VSYNC_POL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Vertical synchronization polarity
eo_param_info
//
enable = ENABLE[0] ;
//
board_specific_value
"active high" M_DEFAULT CLC_VSYNC_POL CAMERA_LINK_AV yes 0
"active low" M_DEFAULT CLC_VSYNC_POL CAMERA_LINK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_HSYNC_SEL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Horizontal synchronization selection
eo_param_info
//
enable = ENABLE[0] ;
//
board_specific_value
"HSYNC selected (edge sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes 0
"LVDS trigger (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"Opto-coupled trigger (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"TTL trigger (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"User bit 1 (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"LVAL selected (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_HSYNC_POL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera / Camera Link Configuration
Horizontal synchronization polarity
eo_param_info
//
enable = ENABLE[0] ;
//
board_specific_value
"active high" M_DEFAULT CLC_HSYNC_POL CAMERA_LINK_AV yes 0
"active low" M_DEFAULT CLC_HSYNC_POL CAMERA_LINK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Camera Link Control Bits **********
//
GCL_CC1_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Camera Link Control Bits
Control 1
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * CLB_CCOUTEN1 )] ;
//
pagelinks = ( ( CAMERA_LINK_AV & CLB_CCOUTEN1 & ( CLB_CC1 == 0 ) ) ? CLB_CC1.SETVALUE[1] : 1 ) +
GCL_CCOUT1_ENABLE.UPDATE + GCL_CC2_SRC.UPDATE + GCL_CC3_SRC.UPDATE + GCL_CC4_SRC.UPDATE ;
//
board_specific_value
disabled M_DEFAULT CLB_CC1 CL_CC1_DISABLE_AV no
"Timer 1 Output" M_DEFAULT CLB_CC1 CL_CC1_TIMER_1_AV yes 1
"Timer 2 Output" M_DEFAULT CLB_CC1 CL_CC1_TIMER_2_AV yes
"User 0 Output HIGH" M_DEFAULT CLB_CC1 CL_CC1_USROUT_0_HIGH_AV yes
"User 0 Output LOW" M_DEFAULT CLB_CC1 CL_CC1_USROUT_0_LOW_AV yes
"User 1 Output HIGH" M_DEFAULT CLB_CC1 CL_CC1_USROUT_1_HIGH_AV yes
"User 1 Output LOW" M_DEFAULT CLB_CC1 CL_CC1_USROUT_1_LOW_AV yes
"PSG VSYNC" M_DEFAULT CLB_CC1 CL_CC1_PSG_VSYNC_AV yes
"PSG HSYNC" M_DEFAULT CLB_CC1 CL_CC1_PSG_HSYNC_AV yes
"Pixel Clock" M_DEFAULT CLB_CC1 CL_CC1_PCLK_AV yes
eo_board_specific_value
//
valid = (
(
CAMERA_LINK_AV *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) ) *
( ( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 ) )
) ? ADDERROR[ERR_CC1_USER0_2_LEVELS] :
( (
CAMERA_LINK_AV *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) ) *
( ( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 ) )
) ? ADDERROR[ERR_CC1_USER1_2_LEVELS] : 0 )
) ;
//
error_message
ERR_CC1_USER0_2_LEVELS, "User Bit 0 on CC1 Conflicts with other CC Bits. User Bit 0 must be Set to the Same Level, High or Low."
ERR_CC1_USER1_2_LEVELS, "User Bit 1 on CC1 Conflicts with other CC Bits. User Bit 1 must be Set to the Same Level, High or Low."
eo_error_message
//
eo_param
// --------------------------------------
//
GCL_CC2_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Camera Link Control Bits
Control 2
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * CLB_CCOUTEN1 )] ;
//
pagelinks = ( ( CAMERA_LINK_AV & CLB_CCOUTEN1 & ( CLB_CC2 == 0 ) ) ? CLB_CC2.SETVALUE[2] : 2 ) +
GCL_CCOUT1_ENABLE.UPDATE + GCL_CC1_SRC.UPDATE + GCL_CC3_SRC.UPDATE + GCL_CC4_SRC.UPDATE ;
//
board_specific_value
disabled M_DEFAULT CLB_CC2 CL_CC2_DISABLE_AV no
"Timer 1 Output" M_DEFAULT CLB_CC2 CL_CC2_TIMER_1_AV yes
"Timer 2 Output" M_DEFAULT CLB_CC2 CL_CC2_TIMER_2_AV yes 2
"User 0 Output HIGH" M_DEFAULT CLB_CC2 CL_CC2_USROUT_0_HIGH_AV yes
"User 0 Output LOW" M_DEFAULT CLB_CC2 CL_CC2_USROUT_0_LOW_AV yes
"User 1 Output HIGH" M_DEFAULT CLB_CC2 CL_CC2_USROUT_1_HIGH_AV yes
"User 1 Output LOW" M_DEFAULT CLB_CC2 CL_CC2_USROUT_1_LOW_AV yes
"PSG VSYNC" M_DEFAULT CLB_CC2 CL_CC2_PSG_VSYNC_AV yes
"PSG HSYNC" M_DEFAULT CLB_CC2 CL_CC2_PSG_HSYNC_AV yes
"Pixel Clock" M_DEFAULT CLB_CC2 CL_CC2_PCLK_AV yes
eo_board_specific_value
//
valid = (
(
CAMERA_LINK_AV *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) ) *
( ( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 ) )
) ? ADDERROR[ERR_CC2_USER0_2_LEVELS] :
( (
CAMERA_LINK_AV *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) ) *
( ( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 ) )
) ? ADDERROR[ERR_CC2_USER1_2_LEVELS] : 0 )
) ;
//
error_message
ERR_CC2_USER0_2_LEVELS, "User Bit 0 on CC2 Conflicts with other CC Bits. User Bit 0 must be Set to the Same Level, High or Low."
ERR_CC2_USER1_2_LEVELS, "User Bit 1 on CC2 Conflicts with other CC Bits. User Bit 1 must be Set to the Same Level, High or Low."
eo_error_message
//
eo_param
// --------------------------------------
//
GCL_CC3_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Camera Link Control Bits
Control 3
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * CLB_CCOUTEN1 )] ;
//
pagelinks = ( ( CAMERA_LINK_AV & CLB_CCOUTEN1 & ( CLB_CC3 == 0 ) ) ? CLB_CC3.SETVALUE[3] : 3 ) +
GCL_CCOUT1_ENABLE.UPDATE + GCL_CC1_SRC.UPDATE + GCL_CC2_SRC.UPDATE + GCL_CC4_SRC.UPDATE ;
//
board_specific_value
disabled M_DEFAULT CLB_CC3 CL_CC3_DISABLE_AV no
"Timer 1 Output" M_DEFAULT CLB_CC3 CL_CC3_TIMER_1_AV yes
"Timer 2 Output" M_DEFAULT CLB_CC3 CL_CC3_TIMER_2_AV yes
"User 0 Output HIGH" M_DEFAULT CLB_CC3 CL_CC3_USROUT_0_HIGH_AV yes 3
"User 0 Output LOW" M_DEFAULT CLB_CC3 CL_CC3_USROUT_0_LOW_AV yes
"User 1 Output HIGH" M_DEFAULT CLB_CC3 CL_CC3_USROUT_1_HIGH_AV yes
"User 1 Output LOW" M_DEFAULT CLB_CC3 CL_CC3_USROUT_1_LOW_AV yes
"PSG VSYNC" M_DEFAULT CLB_CC3 CL_CC3_PSG_VSYNC_AV yes
"PSG HSYNC" M_DEFAULT CLB_CC3 CL_CC3_PSG_HSYNC_AV yes
"Pixel Clock" M_DEFAULT CLB_CC3 CL_CC3_PCLK_AV yes
eo_board_specific_value
//
valid = (
(
CAMERA_LINK_AV *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) ) *
( ( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 ) )
) ? ADDERROR[ERR_CC3_USER0_2_LEVELS] :
( (
CAMERA_LINK_AV *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) ) *
( ( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 ) )
) ? ADDERROR[ERR_CC3_USER1_2_LEVELS] : 0 )
) ;
//
error_message
ERR_CC3_USER0_2_LEVELS, "User Bit 0 on CC3 Conflicts with other CC Bits. User Bit 0 must be Set to the Same Level, High or Low."
ERR_CC3_USER1_2_LEVELS, "User Bit 1 on CC3 Conflicts with other CC Bits. User Bit 1 must be Set to the Same Level, High or Low."
eo_error_message
//
eo_param
// --------------------------------------
//
GCL_CC4_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Camera Link Control Bits
Control 4
eo_param_info
//
enable = ENABLE[( CAMERA_LINK_AV * CLB_CCOUTEN1 )] ;
//
pagelinks = ( ( CAMERA_LINK_AV & CLB_CCOUTEN1 & ( CLB_CC4 == 0 ) ) ? CLB_CC4.SETVALUE[5] : 5 ) +
GCL_CCOUT1_ENABLE.UPDATE + GCL_CC1_SRC.UPDATE + GCL_CC2_SRC.UPDATE + GCL_CC3_SRC.UPDATE ;
//
board_specific_value
disabled M_DEFAULT CLB_CC4 CL_CC4_DISABLE_AV no
"Timer 1 Output" M_DEFAULT CLB_CC4 CL_CC4_TIMER_1_AV yes
"Timer 2 Output" M_DEFAULT CLB_CC4 CL_CC4_TIMER_2_AV yes
"User 0 Output HIGH" M_DEFAULT CLB_CC4 CL_CC4_USROUT_0_HIGH_AV yes
"User 0 Output LOW" M_DEFAULT CLB_CC4 CL_CC4_USROUT_0_LOW_AV yes
"User 1 Output HIGH" M_DEFAULT CLB_CC4 CL_CC4_USROUT_1_HIGH_AV yes 5
"User 1 Output LOW" M_DEFAULT CLB_CC4 CL_CC4_USROUT_1_LOW_AV yes
"PSG VSYNC" M_DEFAULT CLB_CC4 CL_CC4_PSG_VSYNC_AV yes
"PSG HSYNC" M_DEFAULT CLB_CC4 CL_CC4_PSG_HSYNC_AV yes
"Pixel Clock" M_DEFAULT CLB_CC4 CL_CC4_PCLK_AV yes
eo_board_specific_value
//
valid = (
(
CAMERA_LINK_AV *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) ) *
( ( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 ) )
) ? ADDERROR[ERR_CC4_USER0_2_LEVELS] :
( (
CAMERA_LINK_AV *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) ) *
( ( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 ) )
) ? ADDERROR[ERR_CC4_USER1_2_LEVELS] : 0 )
) ;
//
error_message
ERR_CC4_USER0_2_LEVELS, "User Bit 0 on CC4 Conflicts with other CC Bits. User Bit 0 must be Set to the Same Level, High or Low."
ERR_CC4_USER1_2_LEVELS, "User Bit 1 on CC4 Conflicts with other CC Bits. User Bit 1 must be Set to the Same Level, High or Low."
eo_error_message
//
eo_param
// --------------------------------------
//
GCL_CCOUT1_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Camera Link Control Bits
Enable CC Outputs on connector 1
eo_param_info
//
enable = ENABLE[CAMERA_LINK_AV] ;
//
pagelinks = GCL_CC1_SRC.VALID + GCL_CC2_SRC.VALID + GCL_CC3_SRC.VALID + GCL_CC4_SRC.VALID ;
//
board_specific_value
no M_DEFAULT CLB_CCOUTEN1 CAMERA_LINK_AV yes
yes M_DEFAULT CLB_CCOUTEN1 CAMERA_LINK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GCL_CCOUT2_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Camera Link Control Bits
Enable CC Outputs on connector 2
eo_param_info
//
enable = ENABLE[0] ;
//
board_specific_value
no M_DEFAULT CLB_CCOUTEN2 CAMERA_LINK_AV yes
yes M_DEFAULT CLB_CCOUTEN2 CAMERA_LINK_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Camera Link 4 Users bits I/O **********
//
GUSR_IN_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
Input Enable
eo_param_info
//
enable = ENABLE[1] ;
//
board_specific_value
no M_DEFAULT USR_IENABLE M_DEFAULT yes
yes M_DEFAULT USR_IENABLE M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_IN_FORMAT ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
Input Format
eo_param_info
//
enable = ENABLE[USR_IENABLE] ;
//
board_specific_value
TTL M_DEFAULT USR_ITTL USR_ITTL_AV yes
LVDS M_DEFAULT USR_ILVDS M_DEFAULT yes
OPTO M_DEFAULT USR_IOPTO M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_OUT_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
Output Enable
eo_param_info
//
enable = ENABLE[1] ;
//
board_specific_value
no M_DEFAULT USR_OENABLE M_DEFAULT yes
yes M_DEFAULT USR_OENABLE M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_OUT_FORMAT ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
Output Format
eo_param_info
//
enable = ENABLE[USR_OENABLE] ;
//
board_specific_value
TTL M_DEFAULT USR_OTTL USR_OTTL_AV yes
LVDS M_DEFAULT USR_OLVDS M_DEFAULT yes
eo_board_specific_value
//
eo_param
//
// User bit notice: all members are bumped down 1 place compared to their
// parameters for compatibility with the PULSAR, cam ctrl bits map to dig
// mod bits on pulsar
// --------------------------------------
//
GUSR_BIT_0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 0
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_0_OTH0 USR_BIT_0_AV yes
yes M_DEFAULT USR_BIT_0_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_BIT_1 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 1
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_1_OTH0 USR_BIT_1_AV yes
yes M_DEFAULT USR_BIT_1_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_BIT_2 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 2
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_2_OTH0 USR_BIT_2_AV yes
yes M_DEFAULT USR_BIT_2_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_BIT_3 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 3
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_3_OTH0 USR_BIT_3_AV yes
yes M_DEFAULT USR_BIT_3_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_BIT_4 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 4
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_4_OTH0 USR_BIT_4_AV yes
yes M_DEFAULT USR_BIT_4_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_BIT_5 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 5
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_5_OTH0 USR_BIT_5_AV yes
yes M_DEFAULT USR_BIT_5_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GUSR_BIT_6 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Bits
User Bit 6
eo_param_info
//
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
//
board_specific_value
no M_DEFAULT USR_BIT_6_OTH0 USR_BIT_6_AV yes
yes M_DEFAULT USR_BIT_6_OTH0 NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Test module **********
//
GTM_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Advanced
Enable Test Mode
eo_param_info
//
enable = ENABLE[(
VDC_ANA | ( VDC_DIG * ( ! CAMERA_LINK_AV ) ) |
( CAMERA_LINK_AV * ( PCK_USE_OUT | ( ! SYC_CAM_GEN ) ) )
)] ;
//
pagelinks = ( GTM_PIXELMODE.VALID + GVDT_HORIZONTAL.VALID + GVDT_VERTICAL.VALID ) ;
//
board_specific_value
no M_DEFAULT TM_ENABLE TM_TESTMODE_AV yes
yes M_DEFAULT TM_ENABLE TM_TESTMODE_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GTM_LINENUMBER MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Advanced
Generate Line Numbers
eo_param_info
//
enable = ENABLE[TM_ENABLE] ;
//
board_specific_value
no M_DEFAULT TM_LINENUMBER TM_ENABLE yes
yes M_DEFAULT TM_LINENUMBER TM_ENABLE yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GTM_PIXELMODE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Advanced
Pixel Mode
eo_param_info
//
enable = ENABLE[TM_ENABLE] ;
//
board_specific_value
"Moving Pattern" M_DEFAULT TM_PIXELMODE TM_PIXELMODE_0_AV yes
"Consecutive Pixels with Horizontal Reset" M_DEFAULT TM_PIXELMODE TM_PIXELMODE_1_AV yes
"Consecutive Pixels without horizontal reset" M_DEFAULT TM_PIXELMODE TM_PIXELMODE_2_AV yes
"Byte Aligned Pixels with Horizontal Reset" M_DEFAULT TM_PIXELMODE TM_PIXELMODE_3_AV yes
"Byte Aligned Pixels without Horizontal Reset" M_DEFAULT TM_PIXELMODE TM_PIXELMODE_4_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Video Signal **********
//
GCT_CAMERA_TYPE IS_INTERACTIVE
param_info
Camera
Type
eo_param_info
//
pagelinks = (
(
( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
CT_LS * ( ! GRB_LS_FREE_RUN ) * ( ! GRB_LS_FIXED_LINE ) * ( ! GRB_LS_VARIABLE_LINE ) * ( ! GRB_LS_FRMFIX_LINEFIX ) *
( ! GRB_LS_FRMFIX_LINEVAR ) * ( ! GRB_LS_FRMVAR_LINEFIX ) * ( ! GRB_LS_FRMVAR_LINEVAR )
) ? (
VDT_NOVERT.SETVALUE[1] + VDT_INTERL.SETVALUE[0] + VDT_NINTRL.SETVALUE[1] +
VDC_DIG.SETVALUE[1] + VDC_ANA.SETVALUE[0] + VDC_TTL.SETVALUE[0] + VDC_LVDS.SETVALUE[1] +
SYC_ANA.SETVALUE[0] + SYC_DIG.SETVALUE[1] + VDT_CLP_BPO.SETVALUE[0] +
SYC_MD_CSYN.SETVALUE[0] + SYC_MD_HVSY.SETVALUE[0] + GRB_LS_FREE_RUN.SETVALUE[1] +
SYC_MD_VSYN.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[1] + GRB_START_ANY.SETVALUE[0] +
SYC_H_IN.SETVALUE[1] + SYC_H_ILVDS.SETVALUE[1] + SYC_H_IPOS.SETVALUE[1] +
SYC_V_IN.SETVALUE[0] + SYC_V_ILVDS.SETVALUE[0] + SYC_V_IPOS.SETVALUE[0] +
VDT_VSYNC.SETVALUE[0] + VDT_VBPORCH.SETVALUE[0] + VDT_VFPORCH.SETVALUE[0] +
VDT_VTOTAL.SETVALUE[VDT_VACTIVE] + VDT_VSYNC_FREQ.SETVALUE[0]
) :
( (
( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
CT_FS * VDT_NOVERT
) ? (
VDT_NOVERT.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[0] + SYC_MD_HVSY.SETVALUE[1] +
SYC_V_IN.SETVALUE[1] + SYC_V_ILVDS.SETVALUE[1] + SYC_V_IPOS.SETVALUE[1]
) : 0 )
) + GVDC_VID_SIGNAL_TYPE.UPDATE + GGEN_BOARD_TYPE.UPDATE + GCT_CAMERA_TYPE.UPDATE + GVDC_PSG_MODE.VALID +
GSYC_TYPE.UPDATE + GGRB_LINESCAN.UPDATE + GVDT_TYPE.UPDATE + GCT_CAMERA_BAYER_MODE.UPDATE ;
//
eo_param
// --------------------------------------
GCT_CAMERA_BAYER_MODE ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Camera
Bayer Mode
eo_param_info
//
enable = ENABLE[1] ;
//
pagelinks = ( GVDT_HORIZONTAL.VALID + GVDT_VERTICAL.VALID ) ;
//
eo_param
// --------------------------------------
GVDC_VID_SIGNAL_TYPE
//
pagelinks = (
(
( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
( SYC_ANA | VDC_ANA ) * CT_FS & SYC_COMP * ( VDT_STD_170 | VDT_STD_CCIR )
) ?
( VDT_STD_170.SETVALUE[1] + VDT_NOVERT.SETVALUE[0] + VDT_INTERL.SETVALUE[0] + VDT_NINTRL.SETVALUE[1] +
VDC_DIG.SETVALUE[1] + VDC_ANA.SETVALUE[0] + VDC_TTL.SETVALUE[0] + VDC_LVDS.SETVALUE[1] +
SYC_ANA.SETVALUE[0] + SYC_DIG.SETVALUE[1] + VDT_CLP_BPO.SETVALUE[0] + SYC_COMP.SETVALUE[0] +
SYC_MD_CSYN.SETVALUE[0] + SYC_MD_HVSY.SETVALUE[1] +
SYC_MD_VSYN.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[0] +
SYC_H_IN.SETVALUE[1] + SYC_H_ILVDS.SETVALUE[1] + SYC_H_IPOS.SETVALUE[1] +
SYC_V_IN.SETVALUE[1] + SYC_V_ILVDS.SETVALUE[1] + SYC_V_IPOS.SETVALUE[1]
) :
( (
( DEF_ODYSSEY_ANA | DEF_HELIOS_ANA | DEF_SOLIOS_ANA ) * ( TM_ENABLE == 0 ) *
( VDC_DIG | ( ( VDT_STD_170 | VDT_STD_CCIR ) * SYC_ANA * ( SYC_DIG == 0 ) * VDC_ANA * VDC_IN_CH0 * ( ! VDC_USE_PSG_0 ) ) )
) ?
( VDC_DIG.SETVALUE[0] + VDC_ANA.SETVALUE[1] + VDC_TTL.SETVALUE[0] + VDC_422.SETVALUE[0] +
SYC_ANA.SETVALUE[1] + SYC_DIG.SETVALUE[0] + SYC_COMP.SETVALUE[1] +
SYC_MD_CSYN.SETVALUE[1] + SYC_MD_HVSY.SETVALUE[0] +
SYC_MD_VSYN.SETVALUE[0] + SYC_MD_HSYN.SETVALUE[0] + VDC_0_AC_WITH_DC.SETVALUE[1] +
VDT_NOVERT.SETVALUE[0] + VDT_INTERL.SETVALUE[1] + VDT_NINTRL.SETVALUE[0]
) :
1 )
) + GSYC_FORMAT.UPDATE + GSYC_TYPE.UPDATE + GSYC_DIG_V_IN.UPDATE + GSYC_DIG_H_IN.UPDATE +
GGEN_BOARD_TYPE.UPDATE + GVDT_TYPE.UPDATE + GCT_CAMERA_TYPE.UPDATE + GGRB_LINESCAN.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDT_STANDARD
//
eo_param
// --------------------------------------
//
GVDC_VID_SIGNAL_STD
//
// Should be removed to prevent GPF when loading DIG DCF Async. CT_CAMERA updated without pagelink
//pagelinks = GCT_CAMERA_NUMBER.UPDATE ;
pagelinks = GVDC_PSG_MODE.VALID + GVDC_PSG_0.UPDATE + GVDC_PSG_1.UPDATE + GVDC_PSG_2.UPDATE +
GVDC_PSG_3.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDC_ANA_VID_CH
//
eo_param
// --------------------------------------
//
GVDC_VID_WIDTH
//
pagelinks = (
GCL_MODE_CH0.UPDATE + GVDC_VID_SIGNAL_STD.UPDATE + GCT_CAMERA_TAPS.UPDATE +
GCT_CAMERA_NUMBER.UPDATE + GCL_MODE_BITMAP.VALID + GCL_MODE_CH0.VALID + GVDC_PSG_MODE.VALID
) ;
//
valid = DAT_ERROR ||
(
( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * VDC_RGB_COL * ( ( ! VDC_WD8 ) | ( CT_TAPS > 1 ) ) ) ? ADDERROR[ERR_TOOMANY_WIDTH_RGB] :
( (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * VDC_MONO * ( ! VDC_WD8 ) *
(
( ( CT_TAPS == 3 ) * ( CT_CAMERA == 0 ) ) |
( ( CT_TAPS == 2 ) * ( CT_CAMERA == 1 ) ) |
( ( CT_TAPS == 1 ) * ( CT_CAMERA == 3 ) )
)
) ? ADDERROR[ERR_TOOMANY_WIDTH_8TAPS] : 0 )
) ;
//
error_message
ERR_TOOMANY_WIDTH_RGB, "Cannot have more than 8 bits Data Bus Width in RGB Color 1,2 Taps or 1,2 Cameras. Readjust Pixel Width."
ERR_TOOMANY_WIDTH_8TAPS, "Cannot have more than 8 bits Data Bus Width with number of Cameras and Taps selected."
eo_error_message
//
board_specific_value
"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV yes|M_ARRAY_TWO
"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV yes|M_ARRAY_TWO
"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV yes|M_ARRAY_TWO
"16 bits" 16 VDC_VID_WIDTH_16 VDC_VID_WIDTH_16_AV yes|M_ARRAY_TWO
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDC_MIL_CHANNEL
//
enable = ENABLE[( VDC_ANA | DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL )] ;
//
pagelinks = (
( CAMERA_LINK_AV * VDC_USE_PSG_0 ) ? VDC_MIL_CHANNEL.SETVALUE[0] :
( ( CAMERA_LINK_AV * VDC_USE_PSG_1 ) ? VDC_MIL_CHANNEL.SETVALUE[1] : 0 )
) ;
//** + GVDC_VID_SIGNAL_STD.VALID + GVDC_PSG_0.UPDATE + GVDC_PSG_1.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDC_PSG_MODE
//
pagelinks = (
(
CAMERA_LINK_AV *
(
( VDC_USE_PSG_0 * ( ! VDC_USE_PSG_1 ) ) |
( ( ! VDC_USE_PSG_0 ) * VDC_USE_PSG_1 * ( DEF_ODYSSEY_CL | DEF_HELIOS_CL | DEF_SOLIOS_CL ) )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[1] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[0] + VDC_USE_PSG_2.SETVALUE[0] + VDC_USE_PSG_3.SETVALUE[0]
) :
( ( CAMERA_LINK_AV * VDC_USE_PSG_1 ) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[1] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[0] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[0] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_ANA * VDC_MONO *
(
(
( ! CT_CAMERA ) * ( ! CT_TAPS ) * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) *
( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 )
) |
(
( ( ( CT_CAMERA != 1 ) * ( ! CT_TAPS ) ) | ( ( ! CT_CAMERA ) * ( CT_TAPS != 1 ) ) ) *
(
( VDC_USE_PSG_0 * VDC_USE_PSG_1 * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_2 * VDC_USE_PSG_3 * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) )
)
) |
(
( CT_CAMERA != 2 ) * ( ! CT_TAPS ) * VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * ( ! VDC_USE_PSG_3 )
) |
(
( ( ( CT_CAMERA != 3 ) * ( ! CT_TAPS ) ) | ( ( ! CT_CAMERA ) * ( CT_TAPS != 2 ) ) ) *
VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * VDC_USE_PSG_3
)
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[1] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[0] + VDC_USE_PSG_2.SETVALUE[0] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_ANA * VDC_MONO * (
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 0 ) ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) )
) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 )
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[1] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[0] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_ANA * (
( VDC_MONO * ( CT_CAMERA == 2 ) * ( CT_TAPS == 0 ) ) |
( ( VDC_RGB_PACK | VDC_RGB_COL ) * ( CT_CAMERA == 0 ) * ( CT_TAPS == 0 ) )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[1] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[1] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_ANA * VDC_MONO * (
( ( CT_TAPS == 0 ) * ( CT_CAMERA == 3 ) ) |
( ( CT_TAPS == 2 ) * ( CT_CAMERA == 0 ) ) |
( ( CT_TAPS == 1 ) * ( CT_CAMERA == 1 ) )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[1] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[1] + VDC_USE_PSG_3.SETVALUE[1]
) :
( (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) * VDC_MONO *
(
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 0 ) * ( VDC_WD8 | VDC_VID_WIDTH_10 | VDC_VID_WIDTH_12 |
VDC_VID_WIDTH_14 | VDC_WD16
)
) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) * VDC_WD8 )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[1] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[0] + VDC_USE_PSG_2.SETVALUE[0] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) * VDC_MONO *
( VDC_VID_WIDTH_10 | VDC_VID_WIDTH_12 | VDC_VID_WIDTH_14 | VDC_WD16 )
) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) * VDC_WD8 ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 2 ) * VDC_MONO * VDC_WD8 )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[1] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[0] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) * VDC_MONO * ( CT_CAMERA == 1 ) * ( CT_TAPS == 0 )
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[1] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[0] + VDC_USE_PSG_2.SETVALUE[1] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) * ( VDC_VID_WIDTH_12 | VDC_VID_WIDTH_14 | VDC_WD16 ) ) |
(
( CT_CAMERA == 0 ) * ( CT_TAPS == 2 ) * VDC_MONO * ( VDC_VID_WIDTH_10 | VDC_VID_WIDTH_12 )
) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) * VDC_WD8 ) |
( ( CT_CAMERA == 2 ) * ( CT_TAPS == 0 ) * VDC_MONO )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[1] + VDC_PSG_MODE_4_CHECKS.SETVALUE[0] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[1] + VDC_USE_PSG_3.SETVALUE[0]
) :
( (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( CT_CAMERA == 1 ) * ( CT_TAPS == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) * VDC_WD8
) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 2 ) * VDC_MONO * ( VDC_VID_WIDTH_14 | VDC_WD16 ) ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 3 ) * VDC_MONO * VDC_WD8 ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 1 ) * VDC_MONO * ( ! VDC_WD8 ) ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 2 ) * VDC_MONO * VDC_WD8 ) |
( ( CT_CAMERA == 3 ) * ( CT_TAPS == 0 ) * VDC_MONO )
)
) ?
(
VDC_PSG_MODE_1_CHECK.SETVALUE[0] + VDC_PSG_MODE_2_CHECKS.SETVALUE[0] + VDC_PSG_MODE_1_3_CHECKS.SETVALUE[0] +
VDC_PSG_MODE_3_CHECKS.SETVALUE[0] + VDC_PSG_MODE_4_CHECKS.SETVALUE[1] + VDC_PSG_MODE_ANY_CHECKS.SETVALUE[0] +
VDC_USE_PSG_0.SETVALUE[1] + VDC_USE_PSG_1.SETVALUE[1] + VDC_USE_PSG_2.SETVALUE[1] + VDC_USE_PSG_3.SETVALUE[1]
) : 0 ) ) ) ) ) ) ) ) ) )
) + GVDC_VID_WIDTH.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE ;
//
//** + GVDC_VID_WIDTH.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE +
//** GCT_CAMERA_NUMBER.UPDATE + GCT_CAMERA_TAPS.UPDATE ;
//
// Causing GPF when loading Dig DCFs
// ) + GCT_CAMERA_NUMBER.UPDATE + GCT_CAMERA_TAPS.UPDATE +
// GVDC_VID_SIGNAL_TYPE.UPDATE + GVDC_VID_WIDTH.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDC_PSG_0
//
enable = ENABLE[1] ;
//
pagelinks = GVDC_MIL_CHANNEL.VALID ;
//
valid = (
DEF_GRAB_PSG_CHANGE_ERROR ? ADDERROR[ERR_GRAB_SOURCE_WRONG_PSG] :
( DEF_EXP0_PSG_CHANGE_ERROR ? ADDERROR[ERR_EXP0_TRG_SOURCE_WRONG_PSG] :
( DEF_ARM_EXP0_PSG_CHANGE_ERROR ? ADDERROR[ERR_ARM_EXP0_TRG_SOURCE_WRONG_PSG] :
( DEF_EXP1_PSG_CHANGE_ERROR ? ADDERROR[ERR_EXP1_TRG_SOURCE_WRONG_PSG] :
( DEF_ARM_EXP1_PSG_CHANGE_ERROR ? ADDERROR[ERR_ARM_EXP1_TRG_SOURCE_WRONG_PSG] :
( (
( ( ( ( CT_CAMERA + 1 ) * ( 2 ^ CT_TAPS ) ) == 2 ) * ( CT_CAMERA > 0 ) * VDC_ANA ) *
( ! (
( VDC_USE_PSG_0 * VDC_USE_PSG_1 * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_2 * VDC_USE_PSG_3 * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) )
)
)
) ? ADDERROR[ERR_2CAM] :
( (
( ( CT_CAMERA == 2 ) * ( ! CT_TAPS ) * VDC_ANA ) *
( ! ( VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * ( ! VDC_USE_PSG_3 ) ) )
) ? ADDERROR[ERR_3CAM] :
( (
( ( ( ( CT_CAMERA + 1 ) * ( 2 ^ CT_TAPS ) ) == 4 ) * ( CT_CAMERA > 0 ) * VDC_ANA ) *
( ! ( VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * VDC_USE_PSG_3 ) )
) ? ADDERROR[ERR_4CAM] : 0 ) ) ) ) ) ) )
) ;
//
error_message
ERR_GRAB_SOURCE_WRONG_PSG, "Grab Trigger signal selected Not available with the Acquisition Path selected. Change Grab Trigger signal in Intellicam Grab Mode page or Acquisition Path."
ERR_EXP0_TRG_SOURCE_WRONG_PSG, "Timer 1 Trigger signal selected Not available with the Acquisition Path selected. Change Timer 1 Trigger signal in Intellicam Timer 1 page or Acquisition Path."
ERR_ARM_EXP0_TRG_SOURCE_WRONG_PSG, "Timer 1 Trigger ARM signal selected Not available with the Acquisition Path selected. Change Timer 1 Trigger ARM signal in Intellicam Timer 1 Advanced page or Acquisition Path."
ERR_EXP1_TRG_SOURCE_WRONG_PSG, "Timer 2 Trigger signal selected Not available with the Acquisition Path selected. Change Timer 2 Trigger signal in Intellicam Timer 2 page or Acquisition Path."
ERR_ARM_EXP1_TRG_SOURCE_WRONG_PSG, "Timer 2 Trigger ARM signal selected Not available with the Acquisition Path selected. Change Timer 2 Trigger ARM signal in Intellicam Timer 2 Advanced page or Acquisition Path."
ERR_2CAM, "Wrong Acquisition Path in Video Signal page with number of Cameras and Taps selected. Use AP 0 and 1 or AP 2 and 3."
ERR_3CAM, "Wrong Acquisition Path in Video Signal page with number of Cameras and Taps selected. Use AP 0 and 1 and 2."
ERR_4CAM, "Wrong Acquisition Path in Video Signal page with number of Cameras and Taps selected. Use AP 0 and 1 and 2 and 3."
eo_error_message
//
eo_param
// --------------------------------------
//
GVDC_PSG_1
//
enable = ENABLE[(
( VDC_ANA * ( ! OPTION_SOLIOS_SINGLE_ANA ) ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
VDC_RGB_COL | VDC_RGB_PACK |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) * VDC_MONO * ( ! VDC_WD8 ) ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 2 ) * VDC_MONO ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 3 ) * VDC_MONO * VDC_WD8 ) |
( ( CT_CAMERA == 1 ) * ( ( ( CT_TAPS == 1 ) * ( ! VDC_WD8 ) ) | ( CT_TAPS == 2 ) ) * VDC_MONO ) |
( ( CT_CAMERA == 2 ) * ( CT_TAPS == 0 ) * VDC_MONO ) |
( ( CT_CAMERA == 3 ) * ( CT_TAPS == 0 ) * VDC_MONO )
)
)
)] ;
//
pagelinks = GVDC_MIL_CHANNEL.VALID ;
//
eo_param
// --------------------------------------
//
GVDC_PSG_2
//
enable = ENABLE[(
( VDC_ANA * ( ! ( OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_SINGLE_ANA ) ) ) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) * VDC_WD8 ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 2 ) * VDC_MONO * ( VDC_VID_WIDTH_10 | VDC_VID_WIDTH_12 | VDC_VID_WIDTH_14 | VDC_WD16 ) ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 3 ) * VDC_MONO ) |
( ( CT_CAMERA == 1 ) * VDC_MONO ) |
( ( CT_CAMERA > 1 ) * ( CT_TAPS == 0 ) * VDC_MONO ) |
(
( CT_CAMERA == 1 ) * ( CT_TAPS == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK )
)
)
)
)] ;
// ( ( CT_CAMERA == 1 ) * ( ( CT_TAPS == 1 ) | ( CT_TAPS == 2 ) ) * VDC_MONO ) |
eo_param
// --------------------------------------
//
GVDC_PSG_3
//
enable = ENABLE[(
( VDC_ANA * ( ! ( OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_SINGLE_ANA ) ) ) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 2 ) * ( VDC_VID_WIDTH_14 | VDC_WD16 ) ) |
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 3 ) * VDC_MONO ) |
( ( CT_CAMERA == 1 ) * ( ( ( CT_TAPS == 1 ) * ( ! VDC_WD8 ) ) | ( CT_TAPS == 2 ) ) ) |
( ( CT_CAMERA == 3 ) * ( CT_TAPS == 0 ) * VDC_MONO ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK ) )
)
)
)] ;
//
eo_param
// --------------------------------------
//
GVDC_COUPLING_0
//
enable = ENABLE[(
VDC_ANA *
(
VDC_RGB_COL | VDC_RGB_PACK |
( VDC_MONO * VDC_USE_PSG_0 * ( ( ! CT_TAPS ) | CT_TAPS | ( CT_TAPS == 2 ) ) )
)
)] ;
//
board_specific_value
NO_STRING M_DEFAULT VDC_ODYSSEY_ANA_FILTER VDC_ODYSSEY_ANA_FILTER_AV yes
eo_board_specific_value
//
//
pagelinks = (
( VDC_ANA * VDC_MONO * VDC_USE_PSG_0 * ( ! VDC_0_AC_WITH_DC ) * ( ! VDC_0_DC_WITH_DC ) * ( ! VDC_0_DC_WITHOUT_DC ) ) ?
VDC_0_AC_WITH_DC.SETVALUE[1] : 0
) + GVDC_COUPLING_1.UPDATE + GVDC_COUPLING_2.UPDATE + GVDC_COUPLING_3.UPDATE +
GGEN_BOARD_TYPE.VALID ;
//
eo_param
// --------------------------------------
//
GVDC_COUPLING_1
//
enable = ENABLE[( VDC_ANA * VDC_MONO * ( ! CT_TAPS ) * ( ! CT_CAMERA ) * VDC_USE_PSG_1 )] ;
//
eo_param
// --------------------------------------
//
GVDC_COUPLING_2
//
enable = ENABLE[(
VDC_ANA * VDC_MONO * VDC_USE_PSG_2 *
( ( ( CT_TAPS < 2 ) * ( ! CT_CAMERA ) ) | ( CT_CAMERA == 1 ) )
)] ;
//
eo_param
// --------------------------------------
//
GVDC_COUPLING_3
//
enable = ENABLE[( VDC_ANA * VDC_MONO * ( ! CT_TAPS ) * ( ! CT_CAMERA ) * VDC_USE_PSG_3 )] ;
//
eo_param
// --------------------------------------
//
GVDC_FILTER_0
//
enable = ENABLE[(
VDC_ANA *
(
VDC_RGB_COL | VDC_RGB_PACK |
( VDC_MONO * VDC_USE_PSG_0 * ( ( ! CT_TAPS ) | CT_TAPS | ( CT_TAPS == 2 ) ) )
)
)] ;
//
pagelinks = (
(
OPTION_ODYSSEY_ANA *
(
( ( VDC_ODYSSEY_ANA_FILTER == 0 ) * VDC_0_FILTER_1 ) |
( ( ! VDC_0_NO_FILTER ) * ( ! VDC_0_FILTER_0 ) * VDC_0_FILTER_1 )
)
) ? (
VDC_0_FILTER_1.SETVALUE[0] + VDC_0_NO_FILTER.SETVALUE[1]
VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
OPTION_ODYSSEY_ANA *
(
( ( ! VDC_0_NO_FILTER ) * ( ! VDC_0_FILTER_0 ) * ( ! VDC_0_FILTER_1 ) ) |
( ( ! VDC_0_NO_FILTER ) * VDC_0_FILTER_0 * ( ! VDC_0_FILTER_1 ) )
)
) ? ( VDC_0_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( VDC_0_NO_FILTER * ( ! VDC_0_FILTER_0 ) * ( ! VDC_0_FILTER_1 ) ) |
( VDC_ODYSSEY_ANA_FILTER * VDC_0_NO_FILTER )
)
) ? (
VDC_0_NO_FILTER.SETVALUE[0] + VDC_0_FILTER_1.SETVALUE[1] +
VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( ( ! VDC_0_NO_FILTER ) * ( ! VDC_0_FILTER_0 ) * ( ! VDC_0_FILTER_1 ) ) |
( ( ! VDC_0_NO_FILTER ) * VDC_0_FILTER_0 * ( ! VDC_0_FILTER_1 ) )
)
) ? ( VDC_0_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) : 0 ) ) )
) + GVDC_FILTER_1.UPDATE + GVDC_FILTER_2.UPDATE + GVDC_FILTER_3.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDC_FILTER_1
//
enable = ENABLE[( VDC_ANA * VDC_MONO * ( ! CT_TAPS ) * ( ! CT_CAMERA ) * VDC_USE_PSG_1 )] ;
//
pagelinks = (
(
OPTION_ODYSSEY_ANA *
(
( ( VDC_ODYSSEY_ANA_FILTER == 0 ) * VDC_1_FILTER_1 ) |
( ( ! VDC_1_NO_FILTER ) * ( ! VDC_1_FILTER_0 ) * VDC_1_FILTER_1 )
)
) ? (
VDC_1_FILTER_1.SETVALUE[0] + VDC_1_NO_FILTER.SETVALUE[1]
VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
OPTION_ODYSSEY_ANA *
(
( ( ! VDC_1_NO_FILTER ) * ( ! VDC_1_FILTER_0 ) * ( ! VDC_1_FILTER_1 ) ) |
( ( ! VDC_1_NO_FILTER ) * VDC_1_FILTER_0 * ( ! VDC_1_FILTER_1 ) )
)
) ? ( VDC_1_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( VDC_1_NO_FILTER * ( ! VDC_1_FILTER_0 ) * ( ! VDC_1_FILTER_1 ) ) |
( VDC_ODYSSEY_ANA_FILTER * VDC_1_NO_FILTER )
)
) ? (
VDC_1_NO_FILTER.SETVALUE[0] + VDC_1_FILTER_1.SETVALUE[1] +
VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( ( ! VDC_1_NO_FILTER ) * ( ! VDC_1_FILTER_0 ) * ( ! VDC_1_FILTER_1 ) ) |
( ( ! VDC_1_NO_FILTER ) * VDC_1_FILTER_0 * ( ! VDC_1_FILTER_1 ) )
)
) ? ( VDC_1_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) : 0 ) ) )
) + GVDC_FILTER_1.UPDATE + GVDC_FILTER_2.UPDATE + GVDC_FILTER_3.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDC_FILTER_2
//
enable = ENABLE[(
VDC_ANA * VDC_MONO * VDC_USE_PSG_2 *
( ( ( CT_TAPS < 2 ) * ( ! CT_CAMERA ) ) | ( CT_CAMERA == 1 ) )
)] ;
//
pagelinks = (
(
OPTION_ODYSSEY_ANA *
(
( ( VDC_ODYSSEY_ANA_FILTER == 0 ) * VDC_2_FILTER_1 ) |
( ( ! VDC_2_NO_FILTER ) * ( ! VDC_2_FILTER_0 ) * VDC_2_FILTER_1 )
)
) ? (
VDC_2_FILTER_1.SETVALUE[0] + VDC_2_NO_FILTER.SETVALUE[1]
VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
OPTION_ODYSSEY_ANA *
(
( ( ! VDC_2_NO_FILTER ) * ( ! VDC_2_FILTER_0 ) * ( ! VDC_2_FILTER_1 ) ) |
( ( ! VDC_2_NO_FILTER ) * VDC_2_FILTER_0 * ( ! VDC_2_FILTER_1 ) )
)
) ? ( VDC_2_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( VDC_2_NO_FILTER * ( ! VDC_2_FILTER_0 ) * ( ! VDC_2_FILTER_1 ) ) |
( VDC_ODYSSEY_ANA_FILTER * VDC_2_NO_FILTER )
)
) ? (
VDC_2_NO_FILTER.SETVALUE[0] + VDC_2_FILTER_1.SETVALUE[1] +
VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( ( ! VDC_2_NO_FILTER ) * ( ! VDC_2_FILTER_0 ) * ( ! VDC_2_FILTER_1 ) ) |
( ( ! VDC_2_NO_FILTER ) * VDC_2_FILTER_0 * ( ! VDC_2_FILTER_1 ) )
)
) ? ( VDC_2_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) : 0 ) ) )
) + GVDC_FILTER_1.UPDATE + GVDC_FILTER_2.UPDATE + GVDC_FILTER_3.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDC_FILTER_3
//
enable = ENABLE[( VDC_ANA * VDC_MONO * ( ! CT_TAPS ) * ( ! CT_CAMERA ) * VDC_USE_PSG_3 )] ;
//
pagelinks = (
(
OPTION_ODYSSEY_ANA *
(
( ( VDC_ODYSSEY_ANA_FILTER == 0 ) * VDC_3_FILTER_1 ) |
( ( ! VDC_3_NO_FILTER ) * ( ! VDC_3_FILTER_0 ) * VDC_3_FILTER_1 )
)
) ? (
VDC_3_FILTER_1.SETVALUE[0] + VDC_3_NO_FILTER.SETVALUE[1]
VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
OPTION_ODYSSEY_ANA *
(
( ( ! VDC_3_NO_FILTER ) * ( ! VDC_3_FILTER_0 ) * ( ! VDC_3_FILTER_1 ) ) |
( ( ! VDC_3_NO_FILTER ) * VDC_3_FILTER_0 * ( ! VDC_3_FILTER_1 ) )
)
) ? ( VDC_3_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[1]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( VDC_3_NO_FILTER * ( ! VDC_3_FILTER_0 ) * ( ! VDC_3_FILTER_1 ) ) |
( VDC_ODYSSEY_ANA_FILTER * VDC_3_NO_FILTER )
)
) ? (
VDC_3_NO_FILTER.SETVALUE[0] + VDC_3_FILTER_1.SETVALUE[1] +
VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) :
( (
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) *
(
( ( ! VDC_3_NO_FILTER ) * ( ! VDC_3_FILTER_0 ) * ( ! VDC_3_FILTER_1 ) ) |
( ( ! VDC_3_NO_FILTER ) * VDC_3_FILTER_0 * ( ! VDC_3_FILTER_1 ) )
)
) ? ( VDC_3_FILTER_0.SETVALUE[1] + VDC_ODYSSEY_ANA_FILTER.SETVALUE[0]
) : 0 ) ) )
) + GVDC_FILTER_1.UPDATE + GVDC_FILTER_2.UPDATE + GVDC_FILTER_3.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDT_CLAMPING
//
enable = ENABLE[( VDC_ANA )] ;
//
pagelinks = GGEN_BOARD_TYPE.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE ;
//
eo_param
// --------------------------------------
//
GVDL_USE_DEFAULT
//
eo_param
// --------------------------------------
//
GVDL_PEDESTAL
//
pagelinks = ( GVDL_AMPLITUDE.UPDATE + GVDL_AMPLITUDE.VALID ) ;
//
valid = (
( VDL_PEDEST * ( VDL_PED_AMP > 999 ) ) ? ADDERROR[ERR_VID_PEDEST] :
( ( VDL_PEDEST * ( VDL_PED_AMP > VDL_AMPL ) ) ? ADDERROR[ERR_PEDEST_HIGHER_AMPL] : 0 )
) ;
//
error_message
ERR_VID_PEDEST, "Maximum Pedestal Amplitude is 999 mV. Decrease the value."
ERR_PEDEST_HIGHER_AMPL, "Pedestal Amplitude should be lower than Video Amplitude. Reduce Pedestal Amplitude."
eo_error_message
//
eo_param
// --------------------------------------
//
GVDL_SWING
//
eo_param
// --------------------------------------
//
GVDL_AMPLITUDE
//
pagelinks = GVDL_PEDESTAL.UPDATE ;
//
valid = (
( ( VDL_AMPL < 252 ) * ( ! VDL_PEDEST ) ) ? ADDERROR[ERR_VID_AMPL] :
( ( ( ( VDL_AMPL - VDL_PED_AMP ) <= 251 ) * VDL_PEDEST ) ? ADDERROR[ERR_VID_AMPL_PEDEST] :
( ( VDL_AMPL > 2400 ) ? ADDERROR[ERR_VID_AMPL_PEDEST_MAX]: 0 ) )
) ;
//
error_message
ERR_VID_AMPL, "Minimum Video Amplitude is 252 mV. Increase Video Amplitude."
ERR_VID_AMPL_PEDEST, "Maximum Video Gain reached. Increase Video Amplitude or Decrease Pedestal where Amplitude - Pedestal = 252 mV."
ERR_VID_AMPL_PEDEST_MAX, "Video Amplitude - Pedestal Amplitute should be 2400 mV Maximum. Decrease Video Amplitude or Increase Pedestal Amplitude."
eo_error_message
//
eo_param
//
// --------------------------------------
//
GVDL_BRIGHTNESS
//
eo_param
// --------------------------------------
//
GVDL_CONTRAST
//
eo_param
// --------------------------------------
//
GVDL_SATURATION
//
eo_param
// --------------------------------------
//
GVDL_HUE
//
eo_param
// --------------------------------------
//
// ********** Video Timing **********
//
// --------------------------------------
//
GVDT_TYPE
//
pagelinks = GVDC_VID_SIGNAL_TYPE.UPDATE + GGEN_BOARD_TYPE.UPDATE + GCT_CAMERA_TYPE.UPDATE ;
//
valid = (
( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 0 ) * DEF_AC1_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM0_AC1] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 0 ) * DEF_AC2_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM0_AC2] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 0 ) * DEF_AC3_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM0_AC3] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 1 ) * DEF_AC0_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM1_AC0] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 1 ) * DEF_AC2_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM1_AC2] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 1 ) * DEF_AC3_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM1_AC3] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 2 ) * DEF_AC0_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM2_AC0] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 2 ) * DEF_AC1_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM2_AC1] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 2 ) * DEF_AC3_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM2_AC3] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 3 ) * DEF_AC0_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM3_AC0] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 3 ) * DEF_AC1_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM3_AC1] :
( ( ( DCF_IS_VIRTUAL == 0 ) * ( VDC_DIGITIZER == 3 ) * DEF_AC2_PROGRAMMED * ( CT_CAMERA == 0 ) )
? ADDERROR[ERR_DIG_NUM3_AC2] : 0 ) ) ) ) ) ) ) ) ) ) )
) ;
//
error_message
ERR_DIG_NUM0_AC1, "Digitizer 0 does not match with the Acquisition Path selected. Change Digitizer number to 1 or the AP1 to AP0 on the Tab Overview."
ERR_DIG_NUM0_AC2, "Digitizer 0 does not match with the Acquisition Path selected. Change Digitizer number to 2 or the AP2 to AP0 on the Tab Overview."
ERR_DIG_NUM0_AC3, "Digitizer 0 does not match with the Acquisition Path selected. Change Digitizer number to 3 or the AP3 to AP0 on the Tab Overview."
ERR_DIG_NUM1_AC0, "Digitizer 1 does not match with the Acquisition Path selected. Change Digitizer number to 0 or the AP0 to AP1 on the Tab Overview."
ERR_DIG_NUM1_AC2, "Digitizer 1 does not match with the Acquisition Path selected. Change Digitizer number to 2 or the AP2 to AP1 on the Tab Overview."
ERR_DIG_NUM1_AC3, "Digitizer 1 does not match with the Acquisition Path selected. Change Digitizer number to 3 or the AP3 to AP1 on the Tab Overview."
ERR_DIG_NUM2_AC0, "Digitizer 2 does not match with the Acquisition Path selected. Change Digitizer number to 0 or the AP0 to AP2 on the Tab Overview."
ERR_DIG_NUM2_AC1, "Digitizer 2 does not match with the Acquisition Path selected. Change Digitizer number to 1 or the AP1 to AP2 on the Tab Overview."
ERR_DIG_NUM2_AC3, "Digitizer 2 does not match with the Acquisition Path selected. Change Digitizer number to 3 or the AP3 to AP2 on the Tab Overview."
ERR_DIG_NUM3_AC0, "Digitizer 3 does not match with the Acquisition Path selected. Change Digitizer number to 0 or the AP0 to AP3 on the Tab Overview."
ERR_DIG_NUM3_AC1, "Digitizer 3 does not match with the Acquisition Path selected. Change Digitizer number to 1 or the AP1 to AP3 on the Tab Overview."
ERR_DIG_NUM3_AC2, "Digitizer 3 does not match with the Acquisition Path selected. Change Digitizer number to 2 or the AP2 to AP3 on the Tab Overview."
eo_error_message
//
eo_param
// --------------------------------------
//
GVDT_HORIZONTAL
//
pagelinks = (
GVDT_VERTICAL.UPDATE + GVDT_STANDARD.UPDATE + GVDT_CLAMPING.UPDATE + GVDC_COUPLING_0.UPDATE +
GVDC_COUPLING_1.UPDATE + GVDC_COUPLING_2.UPDATE + GVDC_COUPLING_3.UPDATE +
GCT_CAMERA_BAYER_MODE.UPDATE + GVDT_CL_USE_CAMERA_VALID.VALID + GVDT_CL_USE_CAMERA_VALID.UPDATE +
GCL_MODE_CH0.VALID + GCT_CAMERA_TYPE.UPDATE
) ;
//
valid = (
DEF_HFPORCH_MIN_ANA ? ADDERROR[ERR_HFPORCH_MIN_ANA] :
( ( ( VDT_HSYNC > 0xFFFFFF ) | ( VDT_HBPORCH > 0xFFFFFF ) | ( VDT_HACTIVE > 0xFFFFFF ) | ( VDT_HFPORCH > 0xFFFFFF ) ) ? ADDERROR[ERR_HMAXINPUT_VALUE] :
( ( VDT_USE_HLOCK * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) > VDT_HTOTAL ) ) ? ADDERROR[ERR_HTOTAL] :
( ( DEF_ERR_HCLAMP_MIN * VDT_CLP_BPO *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
)
) ? ADDERROR[ERR_HCLAMP_HBPORCH_MIN] :
( ( DEF_ERR_HCLAMP_MIN * VDT_CLP_FPO *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
)
) ? ADDERROR[ERR_HCLAMP_HFPORCH_MIN] :
( ( DEF_ERR_HCLAMP_MIN * VDT_CLP_SYN *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
)
) ? ADDERROR[ERR_HCLAMP_HSYNC_MIN] :
( DEF_ERR_NGHECNT_HTOTAL_MIN ? ADDERROR[ERR_NGHECNT_HTOTAL_MIN] :
( (
( PCK_FREQ > 20000000 ) *
(
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) > 2500 ) |
( DEF_HTOTAL_ENTRY > 2500 )
) *
( ! DEF_DIGITIZER_MASTER ) * ( ! PCK_CAM_GEN ) * VDC_ANA
) ? ADDERROR[ERR_MAX_HTOTAL>20MHZ_2500] :
( ( ( VDT_HTOTAL > 16777215 ) | ( DEF_HTOTAL_ENTRY > 16777215 ) ) ? ADDERROR[ERR_HTOTAL_EXCEED] :
( (
( ! CT_BAYER_DISABLE ) *
( ( VDT_HACTIVE % 2 ) * ( ( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) ) )
) ? ADDERROR[ERR_HOR_ODD_BAYER] :
( DEF_TEST_MODE_HBP_MIN_ANA ? ADDERROR[ERR_TEST_MODE_HBP_MIN_ANA] :
( DEF_TEST_MODE_HSY_HBP_MIN_CL ? ADDERROR[ERR_TEST_MODE_HSY_HBP_MIN_CL] :
( DEF_TEST_MODE_HFP_MIN ? ADDERROR[ERR_TEST_MODE_HFP_MIN] :
( ( VDT_HACTIVE < 10 ) ? ADDERROR[ERR_HACTIVE_MIN] : 0 ) ) ) ) ) ) ) ) ) ) ) ) )
) ;
//
error_message
ERR_HFPORCH_MIN_ANA, "Minimum of 6 counts in Horizontal Front Porch reached. Increase HFPORCH or decrease HBPORCH or HSYNC."
ERR_HMAXINPUT_VALUE, "Maximum value to enter in the Horizontal Timing is 16777215."
ERR_HTOTAL, "Maximum Horizontal Timing programmed reached. Reduce the Horizontal values to set the sum count to HTOTAL."
ERR_HTOTAL_EXCEED, "Horizontal Total should be 16777215 counts maximum. Reduce Horizontal Total."
ERR_HCLAMP_HBPORCH_MIN, "Minimum Horizontal Back Porch Clamping Reached. Increase Horizontal Back Porch Timing or change Clamping position."
ERR_HCLAMP_HFPORCH_MIN, "Minimum Horizontal Front Porch Clamping Reached. Increase Horizontal Front Porch Timing or change Clamping position."
ERR_HCLAMP_HSYNC_MIN, "Minimum Horizontal Sync Clamping Reached. Increase Horizontal Sync Timing or change Clamping position."
ERR_NGHECNT_HTOTAL_MIN, "Minimum Horizontal Total reached for Noise Gating. Increase one of the Horizontal values."
ERR_MAX_HTOTAL>20MHZ_2500, "Maximum 2500 Horizontal Total Counts reached when using PLL. Reduce Pixel Clock or Horizontal Total."
ERR_CL_TIMEMUX_HACT_ODD, "The Horizontal Active Pixels should be Even number. Reajust Active from Video Timing Tab in Intellicam."
ERR_HOR_ODD_BAYER, "Horizontal Active should be Even number in Bayer mode. Readjust the Horizontal Active to Even value."
ERR_TEST_MODE_HBP_MIN_ANA, "Minimum Horizontal Back Porch reached in Test Mode. Increase the BPorch."
ERR_TEST_MODE_HSY_HBP_MIN_CL, "Minimum Horizontal Back Porch and Synchronization or Delay X reached in Test Mode. Increase Sync or BPorch or Delay X."
ERR_TEST_MODE_HFP_MIN, "Minimum Horizontal Front Porch reached in Test Mode. Increase FPorch to a minimum of 1."
ERR_HACTIVE_MIN, "Minimum Horizontal Active should be 9 counts. Increase the value."
eo_error_message
//
eo_param
//
//
//..............................
//Removed error for even pixel in CL Timemultiplex to put in GCL_MODE_CH0
//ERR_HBLANK_MIN, "Minimum horizontal blank reached. HSYNC + HBPORCH + HFPORCH should be 3 counts Minimum."
//valid = (
// (
// DEF_HBLANK_MIN |
// (
// ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HFPORCH ) < 3 ) * ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VFPORCH ) == 0 )
// )
// ) ? ADDERROR[ERR_HBLANK_MIN] :
// ( DEF_HFPORCH_MIN_ANA ? ADDERROR[ERR_HFPORCH_MIN_ANA] :
// ( ( ( VDT_HSYNC > 0x7FFF ) | ( VDT_HBPORCH > 0x7FFF ) | ( VDT_HACTIVE > 0x7fff ) | ( VDT_HFPORCH > 0x7FFF ) ) ? ADDERROR[ERR_HMAXINPUT_VALUE] :
// ( ( VDT_USE_HLOCK * ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) > VDT_HTOTAL ) ) ? ADDERROR[ERR_HTOTAL] :
// ( ( DEF_ERR_HCLAMP_MIN * VDT_CLP_BPO ) ? ADDERROR[ERR_HCLAMP_HBPORCH_MIN] :
// ( ( DEF_ERR_HCLAMP_MIN * VDT_CLP_FPO ) ? ADDERROR[ERR_HCLAMP_HFPORCH_MIN] :
// ( ( DEF_ERR_HCLAMP_MIN * VDT_CLP_SYN ) ? ADDERROR[ERR_HCLAMP_HSYNC_MIN] :
// ( (
// ( PCK_FREQ > 20000000 ) & ( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) > 2500 ) & ( ! DEF_DIGITIZER_MASTER ) &
// ( ! PCK_CAM_GEN ) & VDC_ANA
// ) ? ADDERROR[ERR_MAX_HTOTAL>20MHZ_2500] : 0 ) ) ) ) ) ) )
// ) ;
// --------------------------------------
//
GVDT_VERTICAL
//
pagelinks = (
GVDT_TYPE.UPDATE + GVDC_COUPLING_0.UPDATE + GVDC_COUPLING_1.UPDATE + GVDC_COUPLING_2.UPDATE +
GVDC_COUPLING_3.UPDATE + GCT_CAMERA_BAYER_MODE.UPDATE + GVDT_CL_USE_CAMERA_VALID.VALID
) ;
//
valid = (
( ( VDT_VSYNC > 0xFFFFF ) | ( VDT_VBPORCH > 0xFFFFF ) | ( VDT_VACTIVE > 0xFFfff ) | ( VDT_VFPORCH > 0xFFFFF ) ) ? ADDERROR[ERR_VMAXINPUT_VALUE] :
( ( VDT_USE_VLOCK * ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) > VDT_VTOTAL ) ) ? ADDERROR[ERR_VTOTAL] :
( ( ( ( VDT_VACTIVE % 2 ) | DEF_VACTIVE_ODD ) * VDT_INTERL * VDC_ANA ) ? ADDERROR[ERR_INTRL_VACTIVE_ODD] :
( (
(
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH + 1 ) % 2 ) |
( ( DEF_VTOTAL_ENTRY + 1 ) % 2 )
) * ( VDT_USE_VLOCK == 0 ) * VDC_ANA * VDT_INTERL
) ? ADDERROR[ERR_INTRL_VTOTAL_EVEN] :
( ( ( VDT_VTOTAL > 1048575 ) | ( DEF_VTOTAL_ENTRY > 1048575 ) ) ? ADDERROR[ERR_VTOTAL_EXCEED] :
( (
( ! CT_BAYER_DISABLE ) * ( VDT_VACTIVE % 2 )
) ? ADDERROR[ERR_VERT_ODD_BAYER] :
( DEF_TEST_MODE_VFP_MIN ? ADDERROR[ERR_TEST_MODE_VFP_MIN] :
( DEF_TEST_MODE_VBLANK_MIN_ANA ? ADDERROR[ERR_TEST_MODE_VBLANK_MIN_ANA] :
( ( DEF_TEST_MODE_VBLANK_MIN_CL * CT_FS ) ? ADDERROR[ERR_TEST_MODE_VBLANK_MIN_CL] : 0 ) ) ) ) ) ) ) )
) ;
//
error_message
ERR_VTOTAL, "Maximum Vertical timing programmed reached. Reduce the Vertical values to set the sum count to VTOTAL."
ERR_VMAXINPUT_VALUE, "Maximum value to enter in the Vertical timing is 1048575."
ERR_INTRL_VACTIVE_ODD, "Vertical Active should be Even Count in Interlaced scan. Set to Even value."
ERR_INTRL_VTOTAL_EVEN, "Vertical Total should be Odd Count in Interlaced scan. Set to Odd value."
ERR_VTOTAL_EXCEED, "Vertical Total should be 1048575 counts maximum. Reduce Vertical Total."
ERR_VERT_ODD_BAYER, "Vertical Active should be Even number in Bayer mode. Readjust the Vertical Active to Even value."
ERR_TEST_MODE_VFP_MIN, "Minimum Vertical Front Porch reached in Test Mode. Increase VPorch to a minimum of 1."
ERR_TEST_MODE_VBLANK_MIN_ANA, "Minimum Vertical Blank Should be 3 Counts in Interlaced Test Mode. Increase VSync or BPorch or FPorch."
ERR_TEST_MODE_VBLANK_MIN_CL, "Minimum Vertical Blank or Delay Y Should be 1 Count in Moving Pattern Test Mode. Increase VSync or BPorch or FPorch or Delay Y."
eo_error_message
//
eo_param
// --------------------------------------
//
// ********** Sync Signal **********
//
GSYC_ANA_TYPE
//
//enable = ENABLE[( ! CAMERA_LINK_AV )] ;
//
eo_param
// --------------------------------------
//
GSYC_LATENCY
//
// To be modified with new Intellicam member to replace "SYC_CAM_LATENCY" AND TAKE SECOND EQUATION
//
enable = ENABLE[( VDC_ANA * ( TM_ENABLE == 0 ) * ( DEF_DIGITIZER_MASTER | ( SYC_DIG * SYC_CAM_GEN ) ) )] ;
//
eo_param
// --------------------------------------
//
GSYC_FORMAT
//
pagelinks = GSYC_TYPE.VALID ;
//
valid = (
(
CT_FS *
(
VDC_ANA *
(
(
SYC_H_IN * SYC_V_IN *
( ( SYC_H_ITTL * ( ! SYC_V_ITTL ) ) | ( SYC_H_ILVDS * ( ! SYC_V_ILVDS ) ) )
) |
(
SYC_H_OUT * SYC_V_OUT *
( ( SYC_H_OTTL * ( ! SYC_V_OTTL ) ) | ( SYC_H_OLVDS * ( ! SYC_V_OLVDS ) ) )
)
)
)
) ? ADDERROR[ERR_SYNC_FORMAT] : 0
) ;
//
error_message
ERR_SYNC_FORMAT, "The Horizontal and Vertical synchronization should be the same Format: TTL or LVDS."
eo_error_message
//
eo_param
//
// --------------------------------------
//
GSYC_TYPE
//
pagelinks = (
( VDC_ANA * SYC_DIG * SYC_MD_CSYN ) ? ( SYC_MD_HVSY.SETVALUE[1] + SYC_MD_CSYN.SETVALUE[0] ) : 0
) + GGEN_BOARD_TYPE.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE + GCT_CAMERA_TYPE.UPDATE +
GSYC_FORMAT.UPDATE ;
//
eo_param
//
// --------------------------------------
//
GSYC_BLOC_SYNC
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
GSYC_ANA_CHANNEL
// Separate SYNC from VIDEO
//
//enable = ENABLE[( ! CAMERA_LINK_AV )] ;
enable = ENABLE[( ! ( ( ( VDC_RGB_COL | VDC_RGB_PACK ) * SYC_SEP ) | SYC_DIG ) )] ;
//
eo_param
// --------------------------------------
//
GSYC_EXT_VSYNC
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
// ********** Digital Synchro. **********
//
GSYC_DIG_H_OUT
//
enable = ENABLE[(
( VDC_ANA * ( ( SYC_ANA * ( SYC_CAM_GEN > 0 ) ) | DEF_DIGITIZER_MASTER ) ) |
( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( SYC_CAM_GEN == 0 ) ) | CAMERA_LINK_AV
)] ;
//
pagelinks = ( GSYC_DIG_H_OUT_FOR.UPDATE + GSYC_DIG_H_OUT_POL.UPDATE + GSYC_FORMAT.VALID ) ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_V_OUT
//
enable = ENABLE[(
( VDC_ANA * ( ( SYC_ANA * ( SYC_CAM_GEN > 0 ) ) | DEF_DIGITIZER_MASTER ) ) |
( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( SYC_CAM_GEN == 0 ) ) | CAMERA_LINK_AV
)] ;
//
pagelinks = ( GSYC_DIG_V_OUT_FOR.UPDATE + GSYC_DIG_V_OUT_POL.UPDATE + GSYC_FORMAT.VALID ) ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_H_OUT_FOR
//
pagelinks = ( GSYC_FORMAT.VALID + GEXP_OUT_FORMAT.VALID ) ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_V_OUT_FOR
//
pagelinks = ( GSYC_FORMAT.VALID + GEXP_OUT_FORMAT.VALID ) ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_H_IN
//
enable = ENABLE[( SYC_DIG * ( SYC_CAM_GEN > 0 ) * ( SYC_MD_HSYN | SYC_MD_HVSY ) )] ;
//
pagelinks = ( GGEN_BOARD_TYPE.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE + GSYC_DIG_H_IN_FOR.UPDATE +
GSYC_DIG_H_IN_POL.UPDATE + GSYC_FORMAT.VALID ) ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_H_IN_POL
//
enable = ENABLE[( SYC_DIG * SYC_H_IN )] ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_H_IN_FOR
//
pagelinks = GSYC_FORMAT.VALID ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_V_IN
//
enable = ENABLE[( CT_FS * SYC_DIG * ( SYC_CAM_GEN > 0 ) * ( SYC_MD_VSYN | SYC_MD_HVSY ) )] ;
//
pagelinks = ( GGEN_BOARD_TYPE.UPDATE + GVDC_VID_SIGNAL_TYPE.UPDATE + GSYC_DIG_V_IN_FOR.UPDATE +
GSYC_DIG_V_IN_POL.UPDATE + GSYC_FORMAT.VALID + GSYC_FORMAT.VALID ) ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_V_IN_POL
//
enable = ENABLE[( SYC_DIG * SYC_V_IN )] ;
//
eo_param
// --------------------------------------
//
GSYC_DIG_V_IN_FOR
//
pagelinks = GSYC_FORMAT.VALID ;
//
eo_param
// --------------------------------------
//
GSYC_SOURCE
//
pagelinks = ( GPCK_EXT_SIGNAL.UPDATE + GEXP_FREQUENCY_2.VALID ) ;
//
eo_param
// --------------------------------------
//
// ********** Pixel Clock **********
//
GPCK_FREQUENCY
//
pagelinks = ( GEXP_FREQUENCY.VALID + GEXP_FREQUENCY_2.VALID + GGEN_BOARD_TYPE.UPDATE ) ;
//
valid = (
( ( PCK_FREQ < 19999995 ) * CAMERA_LINK_AV * SYC_CAM_GEN ) ? ADDERROR[ERR_CL_PCK_FREQ_LOW] :
( ( ( PCK_FREQ > 66000000 ) * ( OPTION_SOLIOS_CL_MEDIUM | OPTION_SOLIOS_CL_DUAL ) )
? ADDERROR[ERR_SOLIOS_CL_PCLK_TOO_HIGH] :
( ( ( PCK_FREQ > 65000000 ) * ( OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) )
? ADDERROR[ERR_SOLIOS_ANA_PCLK_TOO_HIGH] :
( DEF_ERR_INTERNAL_TRG0_2_FORMATS_SEL ? ADDERROR[ERR_2_TRG0_SELECT] :
( DEF_ERR_INTERNAL_TRG1_2_FORMATS_SEL ? ADDERROR[ERR_2_TRG1_SELECT] :
( DEF_ERR_INTERNAL_TRG2_2_FORMATS_SEL ? ADDERROR[ERR_2_TRG2_SELECT] :
( DEF_ERR_INTERNAL_TRG3_2_FORMATS_SEL ? ADDERROR[ERR_2_TRG3_SELECT] : 0 ) ) ) ) ) )
) ;
//
error_message
ERR_CL_PCK_FREQ_LOW, "Pixel Clock Frequency is lower then 20 Mhz in Camera Link slave mode. Set the pixel clock to 20 Mhz."
ERR_SOLIOS_CL_PCLK_TOO_HIGH, "Pixel Clock Higher than 66Mhz Not Supported with Solios. Reduce PCLK to a Maximum of 66MHZ."
ERR_SOLIOS_ANA_PCLK_TOO_HIGH, "Pixel Clock Higher than 65Mhz Not Supported with Solios Analog. Reduce PCLK to a Maximum of 65MHZ."
ERR_GRBTRG_FMT, "The Grab Trigger Signal selected Not available with the Format selected. Change one of the other."
ERR_2_TRG0_SELECT, "Trigger Format conflict in TRIG0 in DIG_TRGIN register. Change Grab Trigger Signal OR Arm or Trigger Signal of Timer1 or 2."
ERR_2_TRG1_SELECT, "Trigger Format conflict in TRIG1 in DIG_TRGIN register. Change Grab Trigger Signal OR Arm or Trigger Signal of Timer1 or 2."
ERR_2_TRG2_SELECT, "Trigger Format conflict in TRIG2 in DIG_TRGIN register. Change Grab Trigger Signal OR Arm or Trigger Signal of Timer1 or 2."
ERR_2_TRG3_SELECT, "Trigger Format conflict in TRIG3 in DIG_TRGIN register. Change Grab Trigger Signal OR Arm or Trigger Signal of Timer1 or 2."
eo_error_message
//
eo_param
// --------------------------------------
//
GPCK_EXT_SIGNAL
//
enable = ENABLE[1] ;
//
pagelinks = (
( PCK_CAM_R&G * CAMERA_LINK_AV ) ?
(
PCK_ITTL.SETVALUE[0] + PCK_I422.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] +
PCK_OTTL.SETVALUE[0] + PCK_O422.SETVALUE[0] + PCK_OLVDS.SETVALUE[1]
) :
( (
PCK_CAM_R&G * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * ( ! PCK_I422 ) * ( ! PCK_ILVDS ) *
(
( ( ! PCK_O422 ) * ( ! PCK_OLVDS ) ) |
( ( ! PCK_O422 ) * PCK_OLVDS ) |
( PCK_OTTL * ( PCK_I422 | PCK_ILVDS ) )
)
) ?
(
PCK_ITTL.SETVALUE[0] + PCK_I422.SETVALUE[0] + PCK_IOPTO.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] +
PCK_OTTL.SETVALUE[0] + PCK_O422.SETVALUE[0] + PCK_OOPTO.SETVALUE[0] + PCK_OLVDS.SETVALUE[1]
) : 0 )
) + GPCK_IN_FORMAT.UPDATE + GPCK_OUT_FORMAT.UPDATE + GSYC_SOURCE.VALID + GSYC_SOURCE.UPDATE ;
//
//pagelinks = (
// (
// ( PCK_ITTL * PCK_CAM_GEN ) |
// ( PCK_OTTL * ( PCK_CAM_REC | PCK_CAM_R&G ) ) |
// ( PCK_CAM_R&G * ( VDC_ANA | CAMERA_LINK_AV ) )
// ) ?
// (
// PCK_ITTL.SETVALUE[0] + PCK_I422.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] +
// PCK_OTTL.SETVALUE[0] + PCK_O422.SETVALUE[0] + PCK_OLVDS.SETVALUE[1]
// ) :
// ( (
// PCK_CAM_R&G * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * ( ! PCK_I422 ) * ( ! PCK_ILVDS ) *
// (
// ( ( ! PCK_O422 ) * ( ! PCK_OLVDS ) ) |
// ( ( ! PCK_O422 ) * PCK_OLVDS ) |
// ( PCK_OTTL * ( PCK_I422 | PCK_ILVDS ) )
// )
// ) ?
// (
// PCK_ITTL.SETVALUE[0] + PCK_I422.SETVALUE[0] + PCK_IOPTO.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] +
// PCK_OTTL.SETVALUE[0] + PCK_O422.SETVALUE[0] + PCK_OOPTO.SETVALUE[0] + PCK_OLVDS.SETVALUE[1]
// ) : 0 )
// ) + GPCK_IN_FORMAT.UPDATE + GPCK_OUT_FORMAT.UPDATE + GSYC_SOURCE.VALID + GSYC_SOURCE.UPDATE ;
//
////
//board_specific_value
//"DVI LVDS/TTL Clock from AP0" M_DEFAULT PCK_ANA_DVI_LVDS_TTL_AC0 PCK_ANA_DVI_LVDS_TTL_AC0_AV yes
//"DVI LVDS/TTL Clock from AP1" M_DEFAULT PCK_ANA_DVI_LVDS_TTL_AC1 PCK_ANA_DVI_LVDS_TTL_AC1_AV yes
//"DVI LVDS/TTL Clock from AP2" M_DEFAULT PCK_ANA_DVI_LVDS_TTL_AC2 PCK_ANA_DVI_LVDS_TTL_AC2_AV yes
//"DVI LVDS/TTL Clock from AP3" M_DEFAULT PCK_ANA_DVI_LVDS_TTL_AC3 PCK_ANA_DVI_LVDS_TTL_AC3_AV yes
//"Internal AUX Clock from AP0" M_DEFAULT PCK_ANA_AUX_TTL_AC0 PCK_ANA_AUX_TTL_AC0_AV yes
//"Internal AUX Clock from AP1" M_DEFAULT PCK_ANA_AUX_TTL_AC1 PCK_ANA_AUX_TTL_AC1_AV yes
//"Internal AUX Clock from AP2" M_DEFAULT PCK_ANA_AUX_TTL_AC2 PCK_ANA_AUX_TTL_AC2_AV yes
//"Internal AUX Clock from AP3" M_DEFAULT PCK_ANA_AUX_TTL_AC3 PCK_ANA_AUX_TTL_AC3_AV yes
//eo_board_specific_value
////
valid = (
(
( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * ( ( PCK_I422 * PCK_OLVDS ) | ( PCK_ILVDS * PCK_O422 ) ) ) |
( VDC_ANA * PCK_CAM_R&G * ( ( PCK_ITTL * PCK_OLVDS ) | ( PCK_ILVDS * PCK_OTTL ) ) )
) ? ADDERROR[ERR_PCK_FORMAT] : 0
) ;
//
//valid = (
// (
// ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * ( ( PCK_I422 * PCK_OLVDS ) | ( PCK_ILVDS * PCK_O422 ) )
// ) ? ADDERROR[ERR_PCK_FORMAT] : 0
// ) ;
//
error_message
ERR_PCK_FORMAT, "The Input and Output Pixel Clock Format should be the same."
eo_error_message
//
eo_param
// --------------------------------------
//
GPCK_IN_FORMAT
//
enable = ENABLE[( PCK_CAM_GEN )] ;
//
pagelinks = GPCK_EXT_SIGNAL.VALID ;
//
eo_param
// --------------------------------------
//
GPCK_IN_POL
//
enable = ENABLE[( PCK_CAM_GEN )] ;
//
eo_param
// --------------------------------------
//
GPCK_IN_DELAY
//
enable = ENABLE[(
( VDC_ANA * SYC_CAM_GEN * ( PCK_CAM_GEN == 0 ) * ( PCK_CAM_REC == 0 ) ) |
( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_CAM_GEN )
)] ;
//
eo_param
// --------------------------------------
//
GPCK_SLOW_SCAN_HSYNC ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Advanced
HSync Reference Selection
eo_param_info
//
enable = ENABLE[( VDC_ANA )] ;
//
board_specific_value
"Default " M_DEFAULT SLOW_SCAN_PLL_HREFSEL_DEFAULT SLOW_SCAN_PLL_HREFSEL_DEFAULT_AV yes 1
"None " M_DEFAULT SLOW_SCAN_PLL_HREFSEL_NONE SLOW_SCAN_PLL_HREFSEL_NONE_AV yes
"DVI CHSync" M_DEFAULT SLOW_SCAN_PLL_HREFSEL_DVI SLOW_SCAN_PLL_HREFSEL_DVI_AV yes
"AUX CHSync" M_DEFAULT SLOW_SCAN_PLL_HREFSEL_AUX SLOW_SCAN_PLL_HREFSEL_AUX_AV yes
"Video CSync" M_DEFAULT SLOW_SCAN_PLL_HREFSEL_VIDEO SLOW_SCAN_PLL_HREFSEL_VIDEO_AV yes
"DVI CHSync Other AC" M_DEFAULT SLOW_SCAN_PLL_HREFSEL_DVI_OTHERAC SLOW_SCAN_PLL_HREFSEL_DVI_OTHERAC_AV yes
"DVI CHSync from AC1" M_DEFAULT SLOW_SCAN_PLL_HREFSEL_DVI_AC1 SLOW_SCAN_PLL_HREFSEL_DVI_AC1_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GPCK_SLOW_SCAN_PCK ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Other / Advanced
Pixel Clock Selection
eo_param_info
//
enable = ENABLE[( VDC_ANA )] ;
//
board_specific_value
"Default " M_DEFAULT SLOW_SCAN_PLL_PCKSEL_DEFAULT SLOW_SCAN_PLL_PCKSEL_DEFAULT_AV yes 1
"None " M_DEFAULT SLOW_SCAN_PLL_PCKSEL_NONE SLOW_SCAN_PLL_PCKSEL_NONE_AV yes
"DVI CHSync" M_DEFAULT SLOW_SCAN_PLL_PCKSEL_DVI SLOW_SCAN_PLL_PCKSEL_DVI_AV yes
"AUX CHSync" M_DEFAULT SLOW_SCAN_PLL_PCKSEL_AUX SLOW_SCAN_PLL_PCKSEL_AUX_AV yes
"Video CSync" M_DEFAULT SLOW_SCAN_PLL_PCKSEL_VIDEO SLOW_SCAN_PLL_PCKSEL_VIDEO_AV yes
"DVI CHSync Other AC" M_DEFAULT SLOW_SCAN_PLL_PCKSEL_DVI_OTHERAC SLOW_SCAN_PLL_PCKSEL_DVI_OTHERAC_AV yes
"DVI CHSync from AC1" M_DEFAULT SLOW_SCAN_PLL_PCKSEL_DVI_AC1 SLOW_SCAN_PLL_PCKSEL_DVI_AC1_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GPCK_OUT_FREQ
//
enable = ENABLE[( PCK_CAM_REC | PCK_USE_OUT )] ;
//
eo_param
// --------------------------------------
//
GPCK_OUT_FORMAT
//
enable = ENABLE[( PCK_CAM_REC | PCK_USE_OUT )] ;
//
pagelinks = GPCK_EXT_SIGNAL.VALID ;
//
eo_param
// --------------------------------------
//
GPCK_OUT_POL
//
enable = ENABLE[( PCK_CAM_REC | PCK_USE_OUT )] ;
//
eo_param
// --------------------------------------
//
GPCK_EXT_OUT
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
// ********** Grab Mode **********
//
GGRB_MODE
//
pagelinks = (
( GRB_MD_CONT & CT_LS & ( ! GRB_LS_FIXED_LINE ) & ( ! GRB_LS_VARIABLE_LINE ) & ( ! GRB_LS_FREE_RUN ) )
? (
GRB_LS_FREE_RUN.SETVALUE[1] + GRB_LS_FIXED_LINE.SETVALUE[0] + GRB_LS_FRMFIX_LINEFIX.SETVALUE[0] +
GRB_LS_FRMFIX_LINEVAR.SETVALUE[0] + GRB_LS_FRMVAR_LINEFIX.SETVALUE[0] + GRB_LS_FRMVAR_LINEVAR.SETVALUE[0]
) :
( (
CT_LS & ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) &
(
( GRB_LS_FREE_RUN | GRB_LS_FIXED_LINE | GRB_LS_VARIABLE_LINE ) &
( ! GRB_LS_FRMFIX_LINEFIX ) & ( ! GRB_LS_FRMFIX_LINEVAR ) & ( ! GRB_LS_FRMVAR_LINEFIX ) & ( ! GRB_LS_FRMVAR_LINEVAR )
)
)
? ( GRB_LS_FRMFIX_LINEFIX.SETVALUE[1] + GRB_LS_FREE_RUN.SETVALUE[0] + GRB_LS_FIXED_LINE.SETVALUE[0] +
GRB_LS_VARIABLE_LINE.SETVALUE[0]
) :
( ( CT_LS & ( ! GRB_MD_CONT ) )
? ( GRB_ACT_IMMEDIATE.SETVALUE[1] + GRB_ACT_NXT_FRM.SETVALUE[0] + GRB_ACT_IMM_SKP_NFR.SETVALUE[0] ) :
0 ) )
) + GGRB_LINESCAN.UPDATE + GEXP_GEN_MODE.VALID ;
//
eo_param
// --------------------------------------
//
GGRB_ACTIVATION
//
enable = ENABLE[( ( ! GRB_MD_CONT ) * CT_FS )] ;
//
pagelinks = GGRB_MODE.UPDATE ;
//
//board_specific_value
//"Asynchronous Reset Delayed 2 Frames" M_DEFAULT GRB_ACT_IMM_SKP_N2FR GRB_ACT_IMM_SKN2F_AV yes
//"Asynchronous Reset Delayed 3 Frames" M_DEFAULT GRB_ACT_IMM_SKP_N3FR GRB_ACT_IMM_SKN3F_AV yes
//"Asynchronous Reset Delayed 4 Frames" M_DEFAULT GRB_ACT_IMM_SKP_N4FR GRB_ACT_IMM_SKN4F_AV yes
//"Asynchronous Reset Delayed 5 Frames" M_DEFAULT GRB_ACT_IMM_SKP_N5FR GRB_ACT_IMM_SKN5F_AV yes
//"Asynchronous Reset Delayed 6 Frames" M_DEFAULT GRB_ACT_IMM_SKP_N6FR GRB_ACT_IMM_SKN6F_AV yes
//"Asynchronous Reset Delayed 7 Frames" M_DEFAULT GRB_ACT_IMM_SKP_N7FR GRB_ACT_IMM_SKN7F_AV yes
//eo_board_specific_value
//
eo_param
// --------------------------------------
//
GGRB_LINESCAN
//
enable = ENABLE[( CT_LS )] ;
//
pagelinks = GEXP_GEN_MODE.VALID + GEXP_GEN_MODE.UPDATE + GEXP_GEN_MODE_2.UPDATE + GCT_CAMERA_TYPE.UPDATE +
GVDT_TYPE.UPDATE + GSYC_TYPE.UPDATE + GGRB_MODE.VALID ;
//
eo_param
// --------------------------------------
//
GGRB_TRG_SIGNAL
//
pagelinks = ( GVDC_PSG_0.VALID + GEXP_FREQUENCY.VALID + GPCK_FREQUENCY.VALID ) ;
//
board_specific_value
"PSG HSync" M_DEFAULT GRB_TRG_HS_PSG GRB_TRG_HS_PSG_AV yes 0
"PSG VSync" M_DEFAULT GRB_TRG_VS_PSG GRB_TRG_VS_PSG_AV yes
"Timer 1 Output" M_DEFAULT GRB_TRG_TIMER0 GRB_TRG_TIMER0_AV yes
"Timer 2 Output" M_DEFAULT GRB_TRG_TIMER1 GRB_TRG_TIMER1_AV yes
"Timer 3 Output" M_DEFAULT GRB_TRG_TIMER2 GRB_TRG_TIMER2_AV no
"Timer 4 Output" M_DEFAULT GRB_TRG_TIMER3 GRB_TRG_TIMER3_AV no
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC01_OPTO_CL GRB_TRG_2_AC01_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC01_OPTO_CL GRB_TRG_3_AC01_OPTO_CL_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [AP1 ONLY Trig0]" M_DEFAULT GRB_TRG_0_AC1_OPTO_CL GRB_TRG_0_AC1_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [AP1 ONLY Trig1]" M_DEFAULT GRB_TRG_1_AC1_OPTO_CL GRB_TRG_1_AC1_OPTO_CL_AV yes
"Hardware Port2, TTL_AUX_IO_0 (HD44: pin43) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC01_TTL_CL GRB_TRG_2_AC01_TTL_CL_AV yes
"Hardware Port3, TTL_AUX_IO_1 (HD44: pin15) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC01_TTL_CL GRB_TRG_3_AC01_TTL_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC01_LVDS_CL GRB_TRG_2_AC01_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC01_LVDS_CL GRB_TRG_3_AC01_LVDS_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [AP1 ONLY Trig0]" M_DEFAULT GRB_TRG_0_AC1_LVDS_CL GRB_TRG_0_AC1_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [AP1 ONLY Trig1]" M_DEFAULT GRB_TRG_1_AC1_LVDS_CL GRB_TRG_1_AC1_LVDS_CL_AV yes
"Hardware Port6, P0_OPTO_AUX_IN0 (DB9: pin7+ and 2-)" M_DEFAULT GRB_TRG_0_AC0_OPTO_CL GRB_TRG_0_AC0_OPTO_CL_AV yes
"Hardware Port7, P0_OPTO_AUX_IN1 (DB9: pin4+ and 5-)" M_DEFAULT GRB_TRG_1_AC0_OPTO_CL GRB_TRG_1_AC0_OPTO_CL_AV yes
"Hardware Port8, P0_TTL_AUX_IO_0 (DB9: pin1)" M_DEFAULT GRB_TRG_0_AC0_TTL_CL GRB_TRG_0_AC0_TTL_CL_AV yes
"Hardware Port9, P0_TTL_AUX_IO_1 (HD44: pin13)" M_DEFAULT GRB_TRG_1_AC0_TTL_CL GRB_TRG_1_AC0_TTL_CL_AV yes
"Hardware Port8, P1_TTL_AUX_IO_0 (HD44: pin35)" M_DEFAULT GRB_TRG_0_AC1_TTL_CL GRB_TRG_0_AC1_TTL_CL_AV yes
"Hardware Port9, P1_TTL_AUX_IO_1 (HD44: pin1)" M_DEFAULT GRB_TRG_1_AC1_TTL_CL GRB_TRG_1_AC1_TTL_CL_AV yes
"Hardware Port10, P0_LVDS_AUX_IN0 (DB9: pin8+ and 3-)" M_DEFAULT GRB_TRG_0_AC0_LVDS_CL GRB_TRG_0_AC0_LVDS_CL_AV yes
"Hardware Port11, P0_LVDS_AUX_IN1 (HD44: pin37+ and 23-)" M_DEFAULT GRB_TRG_1_AC0_LVDS_CL GRB_TRG_1_AC0_LVDS_CL_AV yes
"Hardware Port0, P0_OPTO_AUX(TRIG)_IN (DB9: pin7+ and 2-)" M_DEFAULT GRB_TRG_1_AC0_OPTO_ANA GRB_TRG_1_AC0_OPTO_ANA_AV yes
"Hardware Port0, P1_OPTO_AUX(TRIG)_IN (DB9: pin4+ and 5-)" M_DEFAULT GRB_TRG_1_AC1_OPTO_ANA GRB_TRG_1_AC1_OPTO_ANA_AV yes
"Hardware Port0, P2_OPTO_AUX(TRIG)_IN (DB9: pin1+ and 6-)" M_DEFAULT GRB_TRG_1_AC2_OPTO_ANA GRB_TRG_1_AC2_OPTO_ANA_AV yes
"Hardware Port0, P3_OPTO_AUX(TRIG)_IN (DB9: pin8+ and 3-)" M_DEFAULT GRB_TRG_1_AC3_OPTO_ANA GRB_TRG_1_AC3_OPTO_ANA_AV yes
"Hardware Port1, P0_TTL_AUX(TRIG)_IN (DVI 0: pin14)" M_DEFAULT GRB_TRG_0_AC0_TTL_ANA GRB_TRG_0_AC0_TTL_ANA_AV yes
"Hardware Port1, P1_TTL_AUX(TRIG)_IN (DVI 0: pin22)" M_DEFAULT GRB_TRG_0_AC1_TTL_ANA GRB_TRG_0_AC1_TTL_ANA_AV yes
"Hardware Port1, P2_TTL_AUX(TRIG)_IN (DVI 1: pin14)" M_DEFAULT GRB_TRG_0_AC2_TTL_ANA GRB_TRG_0_AC2_TTL_ANA_AV yes
"Hardware Port1, P3_TTL_AUX(TRIG)_IN (DVI 1: pin22)" M_DEFAULT GRB_TRG_0_AC3_TTL_ANA GRB_TRG_0_AC3_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0+ (HD44: pin35) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX0_TTL_ANA GRB_TRG_2_4AC_AUX0_TTL_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1+ (HD44: pin12) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX1_TTL_ANA GRB_TRG_3_4AC_AUX1_TTL_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2+ (HD44: pin8 ) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX2_TTL_ANA GRB_TRG_2_4AC_AUX2_TTL_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3+ (HD44: pin39) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX3_TTL_ANA GRB_TRG_3_4AC_AUX3_TTL_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4+ (HD44: pin7 ) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX4_TTL_ANA GRB_TRG_2_4AC_AUX4_TTL_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5+ (HD44: pin6 ) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX5_TTL_ANA GRB_TRG_3_4AC_AUX5_TTL_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6+ (HD44: pin32) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX6_TTL_ANA GRB_TRG_2_4AC_AUX6_TTL_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7+ (HD44: pin1 ) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX7_TTL_ANA GRB_TRG_3_4AC_AUX7_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0 (HD44: pin35+ and 34-) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX0_LVDS_ANA GRB_TRG_2_4AC_AUX0_LVDS_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX1_LVDS_ANA GRB_TRG_3_4AC_AUX1_LVDS_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2 (HD44: pin8+ and 24-) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX2_LVDS_ANA GRB_TRG_2_4AC_AUX2_LVDS_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3 (HD44: pin39+ and 38- [Common Trigger])" M_DEFAULT GRB_TRG_3_4AC_AUX3_LVDS_ANA GRB_TRG_3_4AC_AUX3_LVDS_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX4_LVDS_ANA GRB_TRG_2_4AC_AUX4_LVDS_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX5_LVDS_ANA GRB_TRG_3_4AC_AUX5_LVDS_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT GRB_TRG_2_4AC_AUX6_LVDS_ANA GRB_TRG_2_4AC_AUX6_LVDS_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7 (HD44: pin1+ and 16-) [Common Trigger]" M_DEFAULT GRB_TRG_3_4AC_AUX7_LVDS_ANA GRB_TRG_3_4AC_AUX7_LVDS_ANA_AV yes
"Hardware Port2, P0_OPTO_AUX(TRIG)_IN_0 (HD44: pin2+ and 17-)" M_DEFAULT GRB_TRG_0_AC0_OPTO_DIG GRB_TRG_0_AC0_OPTO_DIG_AV yes
"Hardware Port3, P0_OPTO_AUX(TRIG)_IN_1 (DB9 : pin7+ and 2-)" M_DEFAULT GRB_TRG_1_AC0_OPTO_DIG GRB_TRG_1_AC0_OPTO_DIG_AV yes
"Hardware Port2, P1_OPTO_AUX(TRIG)_IN_0 (HD44: pin12+ and 28-) " M_DEFAULT GRB_TRG_0_AC1_OPTO_DIG GRB_TRG_0_AC1_OPTO_DIG_AV yes
"Hardware Port3, P1_OPTO_AUX(TRIG)_IN_1 (DB9 : pin4+ and 5-) " M_DEFAULT GRB_TRG_1_AC1_OPTO_DIG GRB_TRG_1_AC1_OPTO_DIG_AV yes
"Hardware Port2, P2_OPTO_AUX(TRIG)_IN_0 (HD44: pin13+ and 14-) " M_DEFAULT GRB_TRG_0_AC2_OPTO_DIG GRB_TRG_0_AC2_OPTO_DIG_AV yes
"Hardware Port3, P2_OPTO_AUX(TRIG)_IN_1 (DB9 : pin1+ and 6-) " M_DEFAULT GRB_TRG_1_AC2_OPTO_DIG GRB_TRG_1_AC2_OPTO_DIG_AV yes
"Hardware Port2, P3_OPTO_AUX(TRIG)_IN_0 (HD44: pin23+ and 37-) " M_DEFAULT GRB_TRG_0_AC3_OPTO_DIG GRB_TRG_0_AC3_OPTO_DIG_AV yes
"Hardware Port3, P3_OPTO_AUX(TRIG)_IN_1 (DB9 : pin8+ and 3-) " M_DEFAULT GRB_TRG_1_AC3_OPTO_DIG GRB_TRG_1_AC3_OPTO_DIG_AV yes
"Hardware Port0, P0_TTL_AUX(TRIG)_IO (CON0: pin49)" M_DEFAULT GRB_TRG_1_AC0_TTL_DIG GRB_TRG_1_AC0_TTL_DIG_AV yes
"Hardware Port0, P1_TTL_AUX(TRIG)_IO (CON0: pin99)" M_DEFAULT GRB_TRG_1_AC1_TTL_DIG GRB_TRG_1_AC1_TTL_DIG_AV yes
"Hardware Port0, P2_TTL_AUX(TRIG)_IO (CON1: pin49)" M_DEFAULT GRB_TRG_1_AC2_TTL_DIG GRB_TRG_1_AC2_TTL_DIG_AV yes
"Hardware Port0, P3_TTL_AUX(TRIG)_IO (CON1: pin99)" M_DEFAULT GRB_TRG_1_AC3_TTL_DIG GRB_TRG_1_AC3_TTL_DIG_AV yes
"Hardware Port1, P0_LVDS_AUX(VSYNC)_IN (CON0: pin35+ and 36-) " M_DEFAULT GRB_TRG_0_AC0_LVDS_DIG GRB_TRG_0_AC0_LVDS_DIG_AV yes
"Hardware Port1, P1_LVDS_AUX(VSYNC)_IN (CON0: pin85+ and 86-) " M_DEFAULT GRB_TRG_0_AC1_LVDS_DIG GRB_TRG_0_AC1_LVDS_DIG_AV yes
"Hardware Port1, P2_LVDS_AUX(VSYNC)_IN (CON1: pin35+ and 36-) " M_DEFAULT GRB_TRG_0_AC2_LVDS_DIG GRB_TRG_0_AC2_LVDS_DIG_AV yes
"Hardware Port1, P3_LVDS_AUX(VSYNC)_IN (CON1: pin85+ and 86-) " M_DEFAULT GRB_TRG_0_AC3_LVDS_DIG GRB_TRG_0_AC3_LVDS_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC0_AUX1_TTL_DIG GRB_TRG_2_AC0_AUX1_TTL_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC0_AUX2_TTL_DIG GRB_TRG_3_AC0_AUX2_TTL_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC1_AUX1_TTL_DIG GRB_TRG_2_AC1_AUX1_TTL_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC1_AUX2_TTL_DIG GRB_TRG_3_AC1_AUX2_TTL_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC2_AUX1_TTL_DIG GRB_TRG_2_AC2_AUX1_TTL_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC2_AUX2_TTL_DIG GRB_TRG_3_AC2_AUX2_TTL_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39) [Common Trigger]" M_DEFAULT GRB_TRG_2_AC3_AUX1_TTL_DIG GRB_TRG_2_AC3_AUX1_TTL_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC3_AUX2_TTL_DIG GRB_TRG_3_AC3_AUX2_TTL_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20+ and 4-) [Common Trigger] " M_DEFAULT GRB_TRG_2_AC0_AUX1_LVDS_DIG GRB_TRG_2_AC0_AUX1_LVDS_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT GRB_TRG_3_AC0_AUX2_LVDS_DIG GRB_TRG_3_AC0_AUX2_LVDS_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7+ and 22-) [Common Trigger] " M_DEFAULT GRB_TRG_2_AC1_AUX1_LVDS_DIG GRB_TRG_2_AC1_AUX1_LVDS_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15+ and 30-) [Common Trigger] " M_DEFAULT GRB_TRG_3_AC1_AUX2_LVDS_DIG GRB_TRG_3_AC1_AUX2_LVDS_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44+ and 29-) [Common Trigger] " M_DEFAULT GRB_TRG_2_AC2_AUX1_LVDS_DIG GRB_TRG_2_AC2_AUX1_LVDS_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32+ and 31-) [Common Trigger] " M_DEFAULT GRB_TRG_3_AC2_AUX2_LVDS_DIG GRB_TRG_3_AC2_AUX2_LVDS_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39+ and 38-) [Common Trigger] " M_DEFAULT GRB_TRG_2_AC3_AUX1_LVDS_DIG GRB_TRG_2_AC3_AUX1_LVDS_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43+ and 42-) [Common Trigger] " M_DEFAULT GRB_TRG_3_AC3_AUX2_LVDS_DIG GRB_TRG_3_AC3_AUX2_LVDS_DIG_AV yes
"Rotary Encoder Trigger, P0_LVDS_AUX_IN0-1 (DB9: pin8+ and 3-) & (HD44: pin37+ and 23-)" M_DEFAULT GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS_AUX_IN0-1 (HD44: pin32+ and 31-) & (HD44: pin12+ and 28-)" M_DEFAULT GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN0-1 (HD44: pin35+ and 34-) & (HD44: pin12+ and 28-)" M_DEFAULT GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN2-3 (HD44: pin8+ and 24-) & (HD44: pin39+ and 38-)" M_DEFAULT GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN4-5 (HD44: pin7+ and 22-) & (HD44: pin6+ and 5-)" M_DEFAULT GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN6-7 (HD44: pin32+ and 31-) & (HD44: pin1+ and 16-)" M_DEFAULT GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN0-1 (HD44: pin20+ and 4-) & (HD44: pin6+ and 5-)" M_DEFAULT GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN2-3 (HD44: pin7+ and 22-) & (HD44: pin15+ and 30-)" M_DEFAULT GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN4-5 (HD44: pin44+ and 29-) & (HD44: pin32+ and 31-)" M_DEFAULT GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN6-7 (HD44: pin39+ and 38-) & (HD44: pin43+ and 42-)" M_DEFAULT GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV yes
"OLD Rotary Encoder" M_DEFAULT GRB_TRG_LVDS_ROTARY_ENCODER GRB_TRG_LVDS_ROTARY_ENCODER_AV no
eo_board_specific_value
//
eo_param
//
// --------------------------------------
//
GGRB_TRG_FORMAT
//
enable = ENABLE[( GRB_MD_HW_TRG )] ;
//
eo_param
//
// --------------------------------------
//
GGRB_TRG_POL
//
eo_param
// --------------------------------------
//
// ********** Exposure Signal Timer1 **********
//
GEXP_GEN_MODE
//
enable = ENABLE[1] ;
//
pagelinks = ( GGRB_LINESCAN.UPDATE + GEXP_CLOCK_2.UPDATE + GEXP_GEN_MODE_2.UPDATE + GEXP_GEN_MODE_2.VALID +
GEXP_ARM_MODE.VALID + GCT_CAMERA_TYPE.UPDATE ) ;
//
valid = (
(
CT_LS * ( GRB_LS_FIXED_LINE | GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMVAR_LINEFIX ) *
( ! EXP_MD_PERD ) * ( ! EXP_MD_PERD_2 )
) ? ADDERROR[ERR_NO_TIMERS_EN_FIXED_LINE] :
( (
CT_LS * ( GRB_LS_VARIABLE_LINE | GRB_LS_FRMFIX_LINEVAR | GRB_LS_FRMVAR_LINEVAR ) *
( ! EXP_MD_W_TRG ) * ( ! EXP_MD_W_TRG_2 )
) ? ADDERROR[ERR_NO_TIMERS_EN_VARIABLE_LINE] :
( ( EXP_CLK_TIMER1 * EXP_CLK_2_TIMER0 ) ? ADDERROR[ERR_2CLKS_TIMER0_TIMER1] : 0 ) )
) ;
//
error_message
ERR_NO_TIMERS_EN_FIXED_LINE, "At least one Timer should be set in Periodic."
ERR_NO_TIMERS_EN_VARIABLE_LINE, "At least one Timer should be set on Trigger Event."
ERR_NO_PERIODIC_TIMER1, "Timer 2 should be set in Periodic."
ERR_2CLKS_TIMER0_TIMER1, "1 Timer Clock Should be selected at once. Select Timer 1 Output or Timer 2 Output as Exposure Clock."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_OUT_TIM_0
//
enable = ENABLE[( EXP_MD_PERD | EXP_MD_W_TRG )] ;
//
pagelinks = (
GEXP_GEN_MODE.UPDATE + GEXP_TRG_SIGNAL.UPDATE + GEXP_CLOCK.UPDATE + GEXP_FREQUENCY.VALID +
GEXP_FREQUENCY_2.VALID
) ;
//
valid = (
( ( DEF_TIMER0_TRIGGERS_PIPE_DELAY == 2 ) * ( EXP_OUT_T0 < 2 ) ) ? ADDERROR[ERR_TIMER0_DLY2_MIN] :
( ( ( DEF_TIMER0_TRIGGERS_PIPE_DELAY == 3 ) * ( EXP_OUT_T0 < 3 ) ) ? ADDERROR[ERR_TIMER0_DLY3_MIN] :
( ( ( DEF_TIMER0_TRIGGERS_PIPE_DELAY == 4 ) * ( EXP_OUT_T0 < 4 ) ) ? ADDERROR[ERR_TIMER0_DLY4_MIN] :
( ( ( DEF_TIMER0_TRIGGERS_PIPE_DELAY == 5 ) * ( EXP_OUT_T0 < 5 ) ) ? ADDERROR[ERR_TIMER0_DLY5_MIN] :
( DEF_TMR0_CLKFREQ<=TRGFREQ ? ADDERROR[ERR_TIMER0_CLKFREQ<=TRGFREQ] :
( ( ( EXP_OUT_T3 > 0 ) * ( EXP_OUT_T2 == 0 ) ) ? ADDERROR[ERR_TIMER0_1DLY_PULSE2] : 0 ) ) ) ) )
) ;
//
error_message
ERR_TIMER0_DLY2_MIN, "Delay of Pulse 1 from Timer 1 should be at least 2 counts minimum."
ERR_TIMER0_DLY3_MIN, "Delay of Pulse 1 from Timer 1 should be at least 3 counts minimum."
ERR_TIMER0_DLY4_MIN, "Delay of Pulse 1 from Timer 1 should be at least 4 counts minimum."
ERR_TIMER0_DLY5_MIN, "Delay of Pulse 1 from Timer 1 should be at least 5 counts minimum."
ERR_TIMER0_CLKFREQ<=TRGFREQ, "Frequency of Timer1 Clock should be at least higher than the Trigger Frequency. Set the Exposure Time Smaller or Same as the Trigger Time."
ERR_TIMER0_1DLY_PULSE2, "At least 1 count minimum should be set for Delay 2 when Pulse 2 is activated for Timer 1."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_OUT_TIM_2
//
enable = ENABLE[( ( EXP_MD_PERD * ( ! EXP_CLK_2_TIMER0 ) ) | EXP_MD_W_TRG )] ;
//
eo_param
// --------------------------------------
//
GEXP_OUT_TIM_3
//
enable = ENABLE[( ( EXP_MD_PERD * ( ! EXP_CLK_2_TIMER0 ) ) | EXP_MD_W_TRG )] ;
//
eo_param
// --------------------------------------
//
GEXP_OUT_FORMAT
//
pagelinks = GEXP_OUT_FORMAT_2.UPDATE ;
//
valid = (
(
VDC_ANA *
(
( EXP_OUT_TTL * ( ! EXP_OUT_TTL_2 ) * ( ! EXP_OUT_DEFAULT ) * ( ! EXP_OUT_DEFAULT_2 ) * DEF_TIMER1_ENABLED ) |
( EXP_OUT_LVDS * ( ! EXP_OUT_LVDS_2 ) * ( ! EXP_OUT_DEFAULT ) * ( ! EXP_OUT_DEFAULT_2 ) * DEF_TIMER1_ENABLED )
)
) ? ADDERROR[ERR_EXP01_OUT_FORMAT] :
( (
VDC_ANA *
(
( EXP_OUT_DEFAULT * SYC_H_OTTL * DEF_TIMER1_ENABLED * ( ! EXP_OUT_TTL_2 ) ) |
( EXP_OUT_DEFAULT * SYC_H_OLVDS * DEF_TIMER1_ENABLED * ( ! EXP_OUT_LVDS_2 ) )
)
) ? ADDERROR[ERR_EXP01_HSYNC_OUT_FORMAT] :
( (
VDC_ANA *
(
( EXP_OUT_DEFAULT_2 * SYC_V_OTTL * DEF_TIMER0_ENABLED * ( ! EXP_OUT_TTL ) ) |
( EXP_OUT_DEFAULT_2 * SYC_V_OLVDS * DEF_TIMER0_ENABLED * ( ! EXP_OUT_LVDS ) )
)
) ? ADDERROR[ERR_EXP01_VSYNC_OUT_FORMAT] : 0 ) )
) ;
//
error_message
ERR_EXP01_OUT_FORMAT, "The Timer1 and Timer2 should have the same Output Format: TTL or LVDS."
ERR_EXP01_HSYNC_OUT_FORMAT, "The Timer2 and Horizontal Sync. should have the same Output Format: TTL or LVDS."
ERR_EXP01_VSYNC_OUT_FORMAT, "The Timer1 and Vertical Sync. should have the same Output Format: TTL or LVDS."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_TRG_SIGNAL
//
enable = ENABLE[( EXP_MD_W_TRG )] ;
//
pagelinks = ( GEXP_CLOCK.UPDATE + GVDC_PSG_0.VALID + GPCK_FREQUENCY.VALID ) ;
//
board_specific_value
"TTL Trigger" M_DEFAULT EXP_TRG_TTL_TIMER0 EXP_TRG_TTL_TIMER0_AV no
"Timer 1 = 0" M_DEFAULT EXP_TRG_CNTEQ0_TIMER0 EXP_TRG_CNTEQ0_TIMER0_AV no
"Timer 2 Output" M_DEFAULT EXP_TRG_TIMER1 EXP_TRG_TIMER1_AV yes
"Timer 3 Output" M_DEFAULT EXP_TRG_TIMER2 EXP_TRG_TIMER2_AV no
"Timer 4 Output" M_DEFAULT EXP_TRG_TIMER3 EXP_TRG_TIMER3_AV no
"Timer 1 Output from AP0" M_DEFAULT EXP_0_TRG_TIMER0_AC0 EXP_0_TRG_TIMER0_AC0_AV yes
"Timer 1 Output from AP1" M_DEFAULT EXP_0_TRG_TIMER0_AC1 EXP_0_TRG_TIMER0_AC1_AV yes
"Timer 1 Output from AP2" M_DEFAULT EXP_0_TRG_TIMER0_AC2 EXP_0_TRG_TIMER0_AC2_AV yes
"Timer 1 Output from AP3" M_DEFAULT EXP_0_TRG_TIMER0_AC3 EXP_0_TRG_TIMER0_AC3_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC01_OPTO_CL EXP_0_TRG_2_AC01_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC01_OPTO_CL EXP_0_TRG_3_AC01_OPTO_CL_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [AP1 ONLY Trig0]" M_DEFAULT EXP_0_TRG_0_AC1_OPTO_CL EXP_0_TRG_0_AC1_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [AP1 ONLY Trig1]" M_DEFAULT EXP_0_TRG_1_AC1_OPTO_CL EXP_0_TRG_1_AC1_OPTO_CL_AV yes
"Hardware Port2, TTL_AUX_IO_0 (HD44: pin43) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC01_TTL_CL EXP_0_TRG_2_AC01_TTL_CL_AV yes
"Hardware Port3, TTL_AUX_IO_1 (HD44: pin15) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC01_TTL_CL EXP_0_TRG_3_AC01_TTL_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC01_LVDS_CL EXP_0_TRG_2_AC01_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC01_LVDS_CL EXP_0_TRG_3_AC01_LVDS_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [AP1 ONLY Trig0]" M_DEFAULT EXP_0_TRG_0_AC1_LVDS_CL EXP_0_TRG_0_AC1_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [AP1 ONLY Trig1]" M_DEFAULT EXP_0_TRG_1_AC1_LVDS_CL EXP_0_TRG_1_AC1_LVDS_CL_AV yes
"Hardware Port6, P0_OPTO_AUX_IN0 (DB9: pin7+ and 2-)" M_DEFAULT EXP_0_TRG_0_AC0_OPTO_CL EXP_0_TRG_0_AC0_OPTO_CL_AV yes
"Hardware Port7, P0_OPTO_AUX_IN1 (DB9: pin4+ and 5-)" M_DEFAULT EXP_0_TRG_1_AC0_OPTO_CL EXP_0_TRG_1_AC0_OPTO_CL_AV yes
"Hardware Port8, P0_TTL_AUX_IO_0 (DB9: pin1)" M_DEFAULT EXP_0_TRG_0_AC0_TTL_CL EXP_0_TRG_0_AC0_TTL_CL_AV yes
"Hardware Port9, P0_TTL_AUX_IO_1 (HD44: pin13)" M_DEFAULT EXP_0_TRG_1_AC0_TTL_CL EXP_0_TRG_1_AC0_TTL_CL_AV yes
"Hardware Port8, P1_TTL_AUX_IO_0 (HD44: pin35)" M_DEFAULT EXP_0_TRG_0_AC1_TTL_CL EXP_0_TRG_0_AC1_TTL_CL_AV yes
"Hardware Port9, P1_TTL_AUX_IO_1 (HD44: pin1)" M_DEFAULT EXP_0_TRG_1_AC1_TTL_CL EXP_0_TRG_1_AC1_TTL_CL_AV yes
"Hardware Port10, P0_LVDS_AUX_IN0 (DB9: pin8+ and 3-)" M_DEFAULT EXP_0_TRG_0_AC0_LVDS_CL EXP_0_TRG_0_AC0_LVDS_CL_AV yes
"Hardware Port11, P0_LVDS_AUX_IN1 (HD44: pin37+ and 23-)" M_DEFAULT EXP_0_TRG_1_AC0_LVDS_CL EXP_0_TRG_1_AC0_LVDS_CL_AV yes
"Hardware Port0, P0_OPTO_AUX(TRIG)_IN (DB9: pin7+ and 2-)" M_DEFAULT EXP_0_TRG_1_AC0_OPTO_ANA EXP_0_TRG_1_AC0_OPTO_ANA_AV yes
"Hardware Port0, P1_OPTO_AUX(TRIG)_IN (DB9: pin4+ and 5-)" M_DEFAULT EXP_0_TRG_1_AC1_OPTO_ANA EXP_0_TRG_1_AC1_OPTO_ANA_AV yes
"Hardware Port0, P2_OPTO_AUX(TRIG)_IN (DB9: pin1+ and 6-)" M_DEFAULT EXP_0_TRG_1_AC2_OPTO_ANA EXP_0_TRG_1_AC2_OPTO_ANA_AV yes
"Hardware Port0, P3_OPTO_AUX(TRIG)_IN (DB9: pin8+ and 3-)" M_DEFAULT EXP_0_TRG_1_AC3_OPTO_ANA EXP_0_TRG_1_AC3_OPTO_ANA_AV yes
"Hardware Port1, P0_TTL_AUX(TRIG)_IN (DVI 0: pin14)" M_DEFAULT EXP_0_TRG_0_AC0_TTL_ANA EXP_0_TRG_0_AC0_TTL_ANA_AV yes
"Hardware Port1, P1_TTL_AUX(TRIG)_IN (DVI 0: pin22)" M_DEFAULT EXP_0_TRG_0_AC1_TTL_ANA EXP_0_TRG_0_AC1_TTL_ANA_AV yes
"Hardware Port1, P2_TTL_AUX(TRIG)_IN (DVI 1: pin14)" M_DEFAULT EXP_0_TRG_0_AC2_TTL_ANA EXP_0_TRG_0_AC2_TTL_ANA_AV yes
"Hardware Port1, P3_TTL_AUX(TRIG)_IN (DVI 1: pin22)" M_DEFAULT EXP_0_TRG_0_AC3_TTL_ANA EXP_0_TRG_0_AC3_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0+ (HD44: pin35) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX0_TTL_ANA EXP_0_TRG_2_4AC_AUX0_TTL_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1+ (HD44: pin12) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX1_TTL_ANA EXP_0_TRG_3_4AC_AUX1_TTL_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2+ (HD44: pin8 ) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX2_TTL_ANA EXP_0_TRG_2_4AC_AUX2_TTL_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3+ (HD44: pin39) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX3_TTL_ANA EXP_0_TRG_3_4AC_AUX3_TTL_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4+ (HD44: pin7 ) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX4_TTL_ANA EXP_0_TRG_2_4AC_AUX4_TTL_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5+ (HD44: pin6 ) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX5_TTL_ANA EXP_0_TRG_3_4AC_AUX5_TTL_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6+ (HD44: pin32) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX6_TTL_ANA EXP_0_TRG_2_4AC_AUX6_TTL_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7+ (HD44: pin1 ) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX7_TTL_ANA EXP_0_TRG_3_4AC_AUX7_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0 (HD44: pin35+ and 34-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX0_LVDS_ANA EXP_0_TRG_2_4AC_AUX0_LVDS_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX1_LVDS_ANA EXP_0_TRG_3_4AC_AUX1_LVDS_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2 (HD44: pin8+ and 24-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX2_LVDS_ANA EXP_0_TRG_2_4AC_AUX2_LVDS_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX3_LVDS_ANA EXP_0_TRG_3_4AC_AUX3_LVDS_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX4_LVDS_ANA EXP_0_TRG_2_4AC_AUX4_LVDS_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX5_LVDS_ANA EXP_0_TRG_3_4AC_AUX5_LVDS_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_4AC_AUX6_LVDS_ANA EXP_0_TRG_2_4AC_AUX6_LVDS_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7 (HD44: pin1+ and 16-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_4AC_AUX7_LVDS_ANA EXP_0_TRG_3_4AC_AUX7_LVDS_ANA_AV yes
"Hardware Port2, P0_OPTO_AUX(TRIG)_IN_0 (HD44: pin2+ and 17-)" M_DEFAULT EXP_0_TRG_0_AC0_OPTO_DIG EXP_0_TRG_0_AC0_OPTO_DIG_AV yes
"Hardware Port3, P0_OPTO_AUX(TRIG)_IN_1 (DB9 : pin7+ and 2-)" M_DEFAULT EXP_0_TRG_1_AC0_OPTO_DIG EXP_0_TRG_1_AC0_OPTO_DIG_AV yes
"Hardware Port2, P1_OPTO_AUX(TRIG)_IN_0 (HD44: pin12+ and 28-) " M_DEFAULT EXP_0_TRG_0_AC1_OPTO_DIG EXP_0_TRG_0_AC1_OPTO_DIG_AV yes
"Hardware Port3, P1_OPTO_AUX(TRIG)_IN_1 (DB9 : pin4+ and 5-) " M_DEFAULT EXP_0_TRG_1_AC1_OPTO_DIG EXP_0_TRG_1_AC1_OPTO_DIG_AV yes
"Hardware Port2, P2_OPTO_AUX(TRIG)_IN_0 (HD44: pin13+ and 14-) " M_DEFAULT EXP_0_TRG_0_AC2_OPTO_DIG EXP_0_TRG_0_AC2_OPTO_DIG_AV yes
"Hardware Port3, P2_OPTO_AUX(TRIG)_IN_1 (DB9 : pin1+ and 6-) " M_DEFAULT EXP_0_TRG_1_AC2_OPTO_DIG EXP_0_TRG_1_AC2_OPTO_DIG_AV yes
"Hardware Port2, P3_OPTO_AUX(TRIG)_IN_0 (HD44: pin23+ and 37-) " M_DEFAULT EXP_0_TRG_0_AC3_OPTO_DIG EXP_0_TRG_0_AC3_OPTO_DIG_AV yes
"Hardware Port3, P3_OPTO_AUX(TRIG)_IN_1 (DB9 : pin8+ and 3-) " M_DEFAULT EXP_0_TRG_1_AC3_OPTO_DIG EXP_0_TRG_1_AC3_OPTO_DIG_AV yes
"Hardware Port0, P0_TTL_AUX(TRIG)_IO (CON0: pin49)" M_DEFAULT EXP_0_TRG_1_AC0_TTL_DIG EXP_0_TRG_1_AC0_TTL_DIG_AV yes
"Hardware Port0, P1_TTL_AUX(TRIG)_IO (CON0: pin99)" M_DEFAULT EXP_0_TRG_1_AC1_TTL_DIG EXP_0_TRG_1_AC1_TTL_DIG_AV yes
"Hardware Port0, P2_TTL_AUX(TRIG)_IO (CON1: pin49)" M_DEFAULT EXP_0_TRG_1_AC2_TTL_DIG EXP_0_TRG_1_AC2_TTL_DIG_AV yes
"Hardware Port0, P3_TTL_AUX(TRIG)_IO (CON1: pin99)" M_DEFAULT EXP_0_TRG_1_AC3_TTL_DIG EXP_0_TRG_1_AC3_TTL_DIG_AV yes
"Hardware Port1, P0_LVDS_AUX(VSYNC)_IN (CON0: pin35+ and 36-) " M_DEFAULT EXP_0_TRG_0_AC0_LVDS_DIG EXP_0_TRG_0_AC0_LVDS_DIG_AV yes
"Hardware Port1, P1_LVDS_AUX(VSYNC)_IN (CON0: pin85+ and 86-) " M_DEFAULT EXP_0_TRG_0_AC1_LVDS_DIG EXP_0_TRG_0_AC1_LVDS_DIG_AV yes
"Hardware Port1, P2_LVDS_AUX(VSYNC)_IN (CON1: pin35+ and 36-) " M_DEFAULT EXP_0_TRG_0_AC2_LVDS_DIG EXP_0_TRG_0_AC2_LVDS_DIG_AV yes
"Hardware Port1, P3_LVDS_AUX(VSYNC)_IN (CON1: pin85+ and 86-) " M_DEFAULT EXP_0_TRG_0_AC3_LVDS_DIG EXP_0_TRG_0_AC3_LVDS_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC0_AUX1_TTL_DIG EXP_0_TRG_2_AC0_AUX1_TTL_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC0_AUX2_TTL_DIG EXP_0_TRG_3_AC0_AUX2_TTL_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC1_AUX1_TTL_DIG EXP_0_TRG_2_AC1_AUX1_TTL_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC1_AUX2_TTL_DIG EXP_0_TRG_3_AC1_AUX2_TTL_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC2_AUX1_TTL_DIG EXP_0_TRG_2_AC2_AUX1_TTL_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC2_AUX2_TTL_DIG EXP_0_TRG_3_AC2_AUX2_TTL_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC3_AUX1_TTL_DIG EXP_0_TRG_2_AC3_AUX1_TTL_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC3_AUX2_TTL_DIG EXP_0_TRG_3_AC3_AUX2_TTL_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20+ and 4-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC0_AUX1_LVDS_DIG EXP_0_TRG_2_AC0_AUX1_LVDS_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC0_AUX2_LVDS_DIG EXP_0_TRG_3_AC0_AUX2_LVDS_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC1_AUX1_LVDS_DIG EXP_0_TRG_2_AC1_AUX1_LVDS_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15+ and 30-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC1_AUX2_LVDS_DIG EXP_0_TRG_3_AC1_AUX2_LVDS_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44+ and 29-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC2_AUX1_LVDS_DIG EXP_0_TRG_2_AC2_AUX1_LVDS_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC2_AUX2_LVDS_DIG EXP_0_TRG_3_AC2_AUX2_LVDS_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT EXP_0_TRG_2_AC3_AUX1_LVDS_DIG EXP_0_TRG_2_AC3_AUX1_LVDS_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43+ and 42-) [Common Trigger]" M_DEFAULT EXP_0_TRG_3_AC3_AUX2_LVDS_DIG EXP_0_TRG_3_AC3_AUX2_LVDS_DIG_AV yes
"Rotary Encoder Trigger, P0_LVDS_AUX_IN0-1 (DB9: pin8+ and 3-) & (HD44: pin37+ and 23-)" M_DEFAULT EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS_AUX_IN0-1 (HD44: pin32+ and 31-) & (HD44: pin12+ and 28-)" M_DEFAULT EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN0-1 (HD44: pin35+ and 34-) & (HD44: pin12+ and 28-)" M_DEFAULT EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN2-3 (HD44: pin8+ and 24-) & (HD44: pin39+ and 38-)" M_DEFAULT EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN4-5 (HD44: pin7+ and 22-) & (HD44: pin6+ and 5-)" M_DEFAULT EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN6-7 (HD44: pin32+ and 31-) & (HD44: pin1+ and 16-)" M_DEFAULT EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN0-1 (HD44: pin20+ and 4-) & (HD44: pin6+ and 5-)" M_DEFAULT EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN2-3 (HD44: pin7+ and 22-) & (HD44: pin15+ and 30-)" M_DEFAULT EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN4-5 (HD44: pin44+ and 29-) & (HD44: pin32+ and 31-)" M_DEFAULT EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN6-7 (HD44: pin39+ and 38-) & (HD44: pin43+ and 42-)" M_DEFAULT EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV yes
"OLD Rotary Encoder" M_DEFAULT EXP_0_TRG_LVDS_ROTARY_ENCODER EXP_0_TRG_LVDS_ROTARY_ENCODER_AV no
eo_board_specific_value
//
valid = (
(
( ! OPTION_ODYSSEY_CL_DUAL ) * ( ! OPTION_ODYSSEY_CL_FULL ) * ( ! OPTION_ODYSSEY_ANA ) *
( ! OPTION_ODYSSEY_DIG ) *
(
EXP_0_TRG_TIMER0_AC0 | EXP_0_TRG_TIMER0_AC1 | EXP_0_TRG_TIMER0_AC2 | EXP_0_TRG_TIMER0_AC3
)
) ? ADDERROR[ERR_TIMER0_TRG_NOT_AV] :
( (
( ! OPTION_ODYSSEY_CL_DUAL ) * ( ! OPTION_ODYSSEY_CL_FULL ) * ( ! OPTION_ODYSSEY_ANA ) *
( ! OPTION_ODYSSEY_DIG ) *
(
ARM_EXP_0_TRG_TIMER0_AC0 | ARM_EXP_0_TRG_TIMER0_AC1 | ARM_EXP_0_TRG_TIMER0_AC2 | ARM_EXP_0_TRG_TIMER0_AC3
)
) ? ADDERROR[ERR_TIMER0_ARM_TRG_NOT_AV] :
( (
( ! OPTION_ODYSSEY_CL_DUAL ) * ( ! OPTION_ODYSSEY_CL_FULL ) * ( ! OPTION_ODYSSEY_ANA ) *
( ! OPTION_ODYSSEY_DIG ) *
(
EXP_1_TRG_TIMER1_AC0 | EXP_1_TRG_TIMER1_AC1 | EXP_1_TRG_TIMER1_AC2 | EXP_1_TRG_TIMER1_AC3
)
) ? ADDERROR[ERR_TIMER1_TRG_NOT_AV] :
( (
( ! OPTION_ODYSSEY_CL_DUAL ) * ( ! OPTION_ODYSSEY_CL_FULL ) * ( ! OPTION_ODYSSEY_ANA ) *
( ! OPTION_ODYSSEY_DIG ) *
(
ARM_EXP_1_TRG_TIMER1_AC0 | ARM_EXP_1_TRG_TIMER1_AC1 | ARM_EXP_1_TRG_TIMER1_AC2 | ARM_EXP_1_TRG_TIMER1_AC3
)
) ? ADDERROR[ERR_TIMER1_ARM_TRG_NOT_AV] : 0 ) ) )
) ;
//
error_message
ERR_TIMER0_TRG_NOT_AV, "The Timer 1 Trigger Source selected is Not Supported by MIL. Change the Timer 1 Trigger Input Signal."
ERR_TIMER0_ARM_TRG_NOT_AV, "The Timer 1 ARM Trigger Source selected is Not Supported by MIL. Change the Timer 1 ARM Trigger Input Signal."
ERR_TIMER1_TRG_NOT_AV, "The Timer 2 Trigger Source selected is Not Supported by MIL. Change the Timer 2 Trigger Input Signal."
ERR_TIMER1_ARM_TRG_NOT_AV, "The Timer 2 ARM Trigger Source selected is Not Supported by MIL. Change the Timer 2 ARM Trigger Input Signal."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_TRG_FORMAT
//
enable = ENABLE[( EXP_MD_W_TRG )] ;
//
pagelinks = (
(
( ! EXP_TRG_TTL ) * ( ! EXP_TRG_422 ) * ( ! EXP_TRG_OPTO ) *
( ! EXP_TRG_LVDS ) * ( ! EXP_TRG_DEFAULT )
) ? EXP_TRG_TTL.SETVALUE[1] : 0
) ;
//
eo_param
// --------------------------------------
//
GEXP_TRG_POL
//
enable = ENABLE[( EXP_MD_W_TRG )] ;
//
pagelinks = (
( ( ! EXP_TRG_POS ) * ( ! EXP_TRG_NEG ) ) ? EXP_TRG_POS.SETVALUE[1] : 0
) ;
//
eo_param
// --------------------------------------
//
GEXP_CLOCK
//
pagelinks = ( GEXP_GEN_MODE_2.VALID + GEXP_TRG_SIGNAL.VALID + GEXP_FREQUENCY.VALID ) ;
//
board_specific_value
"Clock Generator" M_DEFAULT EXP_CLK_CLKGEN EXP_CLK_CLKGEN_AV yes
"Clock ASY" M_DEFAULT EXP_ASY_CLK EXP_ASY_CLK_AV no
"HSync Clock" M_DEFAULT EXP_CLK_HS EXP_CLK_HS_AV yes
"VSync Clock" M_DEFAULT EXP_CLK_VS EXP_CLK_VS_AV yes
"Timer 2 Output" M_DEFAULT EXP_CLK_TIMER1 EXP_CLK_TIMER1_AV yes
"Timer 3 Output" M_DEFAULT EXP_CLK_TIMER2 EXP_CLK_TIMER2_AV no
"Timer 4 Output" M_DEFAULT EXP_CLK_TIMER3 EXP_CLK_TIMER3_AV no
"Aux Input LVDS " M_DEFAULT EXP_CLK_AUXIN1_LVDS EXP_CLK_AUXIN1_LVDS_AV no
"Aux Input LVDS " M_DEFAULT EXP_CLK_AUXIN3_LVDS EXP_CLK_AUXIN3_LVDS_AV no
"Aux1 Input LVDS (HD44: pin37+ and 23-) [AP0]" M_DEFAULT EXP_CLK_AUXIN1_AC0_CL EXP_CLK_AUXIN1_AC0_CL_AV yes
"Aux3 Input LVDS (HD44: pin12+ and 28-) [AP1]" M_DEFAULT EXP_CLK_AUXIN3_AC1_CL EXP_CLK_AUXIN3_AC1_CL_AV yes
"Aux1 Input LVDS (HD44: pin12+ and 28-) [AP0]" M_DEFAULT EXP_CLK_AUXIN1_AC0_ANA EXP_CLK_AUXIN1_AC0_ANA_AV yes
"Aux3 Input LVDS (HD44: pin39+ and 38-) [AP1]" M_DEFAULT EXP_CLK_AUXIN3_AC1_ANA EXP_CLK_AUXIN3_AC1_ANA_AV yes
"Aux5 Input LVDS (HD44: pin6+ and 5-) [AP2]" M_DEFAULT EXP_CLK_AUXIN5_AC2_ANA EXP_CLK_AUXIN5_AC2_ANA_AV yes
"Aux7 Input LVDS (HD44: pin1+ and 16-) [AP3]" M_DEFAULT EXP_CLK_AUXIN7_AC3_ANA EXP_CLK_AUXIN7_AC3_ANA_AV yes
"Aux2 Input LVDS (HD44: pin6+ and 5-) [AP0]" M_DEFAULT EXP_CLK_AUXIN2_AC0_DIG EXP_CLK_AUXIN2_AC0_DIG_AV yes
"Aux2 Input LVDS (HD44: pin15+ and 30-) [AP1]" M_DEFAULT EXP_CLK_AUXIN2_AC1_DIG EXP_CLK_AUXIN2_AC1_DIG_AV yes
"Aux2 Input LVDS (HD44: pin32+ and 31-) [AP2]" M_DEFAULT EXP_CLK_AUXIN2_AC2_DIG EXP_CLK_AUXIN2_AC2_DIG_AV yes
"Aux2 Input LVDS (HD44: pin43+ and 42-) [AP3]" M_DEFAULT EXP_CLK_AUXIN2_AC3_DIG EXP_CLK_AUXIN2_AC3_DIG_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_FREQUENCY
//
enable = ENABLE[(
EXP_CLK_CLKGEN || EXP_CLK_AUXIN1_AC0_CL || EXP_CLK_AUXIN3_AC1_CL ||
EXP_CLK_AUXIN1_AC0_ANA || EXP_CLK_AUXIN3_AC1_ANA || EXP_CLK_AUXIN5_AC2_ANA || EXP_CLK_AUXIN7_AC3_ANA ||
EXP_CLK_AUXIN2_AC0_DIG || EXP_CLK_AUXIN2_AC1_DIG || EXP_CLK_AUXIN2_AC2_DIG || EXP_CLK_AUXIN2_AC3_DIG
)] ;
//
pagelinks = ( GPCK_FREQUENCY.UPDATE + GEXP_FREQUENCY_2.UPDATE ) ;
//
valid = (
(
EXP_CLK_CLKGEN * ( ! SYC_CAM_GEN ) *
( ( EXP_CLK_FREQ > ( PCK_FREQ + 2 ) ) | ( EXP_CLK_FREQ < ( PCK_FREQ - 2 ) ) )
)
? ADDERROR[ERR_T0_DIG_MASTER_CLKGEN] :
( (
EXP_CLK_CLKGEN * EXP_CLK_2_CLKGEN * SYC_CAM_GEN *
( EXP_CLK_FREQ != EXP_CLK_FREQ_2 )
) ? ADDERROR[ERR_T0_T1_DIFF_CLKGEN] : 0 )
) ;
//
error_message
ERR_T0_DIG_MASTER_CLKGEN, "The Timer 1 Clock Generator Frequency should be the same as Pixel Clock in Digitizer Master Configuration. Readjust the value."
ERR_T0_T1_DIFF_CLKGEN, "The Clock Generator Frequency should be the same for Timer1 and Timer2. Readjust Timer1 or Timer2 at the same frequency."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_ARM_MODE
//
enable = ENABLE[( DEF_TIMER0_ENABLED * EXP_ARM_ENABLE )] ;
//
pagelinks = (
(
DEF_TIMER0_ENABLED & ( ! EXP_ARM_ENABLE ) & ( ! EXP_ARM_DISABLE )
) ? ( EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1] ) : 0
) + GGRB_MODE.UPDATE ;
//
eo_param
// --------------------------------------
//
GEXP_ARM_SOURCE
//
enable = ENABLE[( DEF_TIMER0_ENABLED * EXP_ARM_ENABLE )] ;
//
pagelinks = ( GVDC_PSG_0.VALID + GEXP_GEN_MODE.UPDATE + GEXP_ARM_MODE.UPDATE + GPCK_FREQUENCY.VALID ) ;
//
board_specific_value
"Timer 1 = 0" M_DEFAULT ARM_EXP_0_CNTEQ0 ARM_EXP_0_CNTEQ0_AV yes
"Software Arm" M_DEFAULT ARM_EXP_0_SOFTWARE ARM_EXP_0_SOFTWARE_AV yes
"Timer 2 Output" M_DEFAULT ARM_EXP_0_TIMER1 ARM_EXP_0_TIMER1_AV yes
"Timer 3 Output" M_DEFAULT ARM_EXP_0_TIMER2 ARM_EXP_0_TIMER2_AV no
"Timer 4 Output" M_DEFAULT ARM_EXP_0_TIMER3 ARM_EXP_0_TIMER3_AV no
"Timer 1 Output from AP0" M_DEFAULT ARM_EXP_0_TRG_TIMER0_AC0 ARM_EXP_0_TRG_TIMER0_AC0_AV yes
"Timer 1 Output from AP1" M_DEFAULT ARM_EXP_0_TRG_TIMER0_AC1 ARM_EXP_0_TRG_TIMER0_AC1_AV yes
"Timer 1 Output from AP2" M_DEFAULT ARM_EXP_0_TRG_TIMER0_AC2 ARM_EXP_0_TRG_TIMER0_AC2_AV yes
"Timer 1 Output from AP3" M_DEFAULT ARM_EXP_0_TRG_TIMER0_AC3 ARM_EXP_0_TRG_TIMER0_AC3_AV yes
"PSG HSync" M_DEFAULT ARM_EXP_0_HS_PSG ARM_EXP_0_HS_PSG_AV yes
"PSG VSync" M_DEFAULT ARM_EXP_0_VS_PSG ARM_EXP_0_VS_PSG_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC01_OPTO_CL ARM_EXP_0_TRG_2_AC01_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC01_OPTO_CL ARM_EXP_0_TRG_3_AC01_OPTO_CL_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [AP1 ONLY Trig0]" M_DEFAULT ARM_EXP_0_TRG_0_AC1_OPTO_CL ARM_EXP_0_TRG_0_AC1_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [AP1 ONLY Trig1]" M_DEFAULT ARM_EXP_0_TRG_1_AC1_OPTO_CL ARM_EXP_0_TRG_1_AC1_OPTO_CL_AV yes
"Hardware Port2, TTL_AUX_IO_0 (HD44: pin43) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC01_TTL_CL ARM_EXP_0_TRG_2_AC01_TTL_CL_AV yes
"Hardware Port3, TTL_AUX_IO_1 (HD44: pin15) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC01_TTL_CL ARM_EXP_0_TRG_3_AC01_TTL_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC01_LVDS_CL ARM_EXP_0_TRG_2_AC01_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC01_LVDS_CL ARM_EXP_0_TRG_3_AC01_LVDS_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [AP1 ONLY Trig0]" M_DEFAULT ARM_EXP_0_TRG_0_AC1_LVDS_CL ARM_EXP_0_TRG_0_AC1_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [AP1 ONLY Trig1]" M_DEFAULT ARM_EXP_0_TRG_1_AC1_LVDS_CL ARM_EXP_0_TRG_1_AC1_LVDS_CL_AV yes
"Hardware Port6, P0_OPTO_AUX_IN0 (DB9: pin7+ and 2-)" M_DEFAULT ARM_EXP_0_TRG_0_AC0_OPTO_CL ARM_EXP_0_TRG_0_AC0_OPTO_CL_AV yes
"Hardware Port7, P0_OPTO_AUX_IN1 (DB9: pin4+ and 5-)" M_DEFAULT ARM_EXP_0_TRG_1_AC0_OPTO_CL ARM_EXP_0_TRG_1_AC0_OPTO_CL_AV yes
"Hardware Port8, P0_TTL_AUX_IO_0 (DB9: pin1)" M_DEFAULT ARM_EXP_0_TRG_0_AC0_TTL_CL ARM_EXP_0_TRG_0_AC0_TTL_CL_AV yes
"Hardware Port9, P0_TTL_AUX_IO_1 (HD44: pin13)" M_DEFAULT ARM_EXP_0_TRG_1_AC0_TTL_CL ARM_EXP_0_TRG_1_AC0_TTL_CL_AV yes
"Hardware Port8, P1_TTL_AUX_IO_0 (HD44: pin35)" M_DEFAULT ARM_EXP_0_TRG_0_AC1_TTL_CL ARM_EXP_0_TRG_0_AC1_TTL_CL_AV yes
"Hardware Port9, P1_TTL_AUX_IO_1 (HD44: pin1)" M_DEFAULT ARM_EXP_0_TRG_1_AC1_TTL_CL ARM_EXP_0_TRG_1_AC1_TTL_CL_AV yes
"Hardware Port10, P0_LVDS_AUX_IN0 (DB9: pin8+ and 3-)" M_DEFAULT ARM_EXP_0_TRG_0_AC0_LVDS_CL ARM_EXP_0_TRG_0_AC0_LVDS_CL_AV yes
"Hardware Port11, P0_LVDS_AUX_IN1 (HD44: pin37+ and 23-)" M_DEFAULT ARM_EXP_0_TRG_1_AC0_LVDS_CL ARM_EXP_0_TRG_1_AC0_LVDS_CL_AV yes
"Hardware Port0, P0_OPTO_AUX(TRIG)_IN (DB9: pin7+ and 2-)" M_DEFAULT ARM_EXP_0_TRG_1_AC0_OPTO_ANA ARM_EXP_0_TRG_1_AC0_OPTO_ANA_AV yes
"Hardware Port0, P1_OPTO_AUX(TRIG)_IN (DB9: pin4+ and 5-)" M_DEFAULT ARM_EXP_0_TRG_1_AC1_OPTO_ANA ARM_EXP_0_TRG_1_AC1_OPTO_ANA_AV yes
"Hardware Port0, P2_OPTO_AUX(TRIG)_IN (DB9: pin1+ and 6-)" M_DEFAULT ARM_EXP_0_TRG_1_AC2_OPTO_ANA ARM_EXP_0_TRG_1_AC2_OPTO_ANA_AV yes
"Hardware Port0, P3_OPTO_AUX(TRIG)_IN (DB9: pin8+ and 3-)" M_DEFAULT ARM_EXP_0_TRG_1_AC3_OPTO_ANA ARM_EXP_0_TRG_1_AC3_OPTO_ANA_AV yes
"Hardware Port1, P0_TTL_AUX(TRIG)_IN (DVI 0: pin14)" M_DEFAULT ARM_EXP_0_TRG_0_AC0_TTL_ANA ARM_EXP_0_TRG_0_AC0_TTL_ANA_AV yes
"Hardware Port1, P1_TTL_AUX(TRIG)_IN (DVI 0: pin22)" M_DEFAULT ARM_EXP_0_TRG_0_AC1_TTL_ANA ARM_EXP_0_TRG_0_AC1_TTL_ANA_AV yes
"Hardware Port1, P2_TTL_AUX(TRIG)_IN (DVI 1: pin14)" M_DEFAULT ARM_EXP_0_TRG_0_AC2_TTL_ANA ARM_EXP_0_TRG_0_AC2_TTL_ANA_AV yes
"Hardware Port1, P3_TTL_AUX(TRIG)_IN (DVI 1: pin22)" M_DEFAULT ARM_EXP_0_TRG_0_AC3_TTL_ANA ARM_EXP_0_TRG_0_AC3_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0+ (HD44: pin35) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1+ (HD44: pin12) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2+ (HD44: pin8 ) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3+ (HD44: pin39) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4+ (HD44: pin7 ) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5+ (HD44: pin6 ) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6+ (HD44: pin32) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7+ (HD44: pin1 ) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0 (HD44: pin35+ and 34-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2 (HD44: pin8+ and 24-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7 (HD44: pin1+ and 16-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA_AV yes
"Hardware Port2, P0_OPTO_AUX(TRIG)_IN_0 (HD44: pin2+ and 17-)" M_DEFAULT ARM_EXP_0_TRG_0_AC0_OPTO_DIG ARM_EXP_0_TRG_0_AC0_OPTO_DIG_AV yes
"Hardware Port3, P0_OPTO_AUX(TRIG)_IN_1 (DB9 : pin7+ and 2-)" M_DEFAULT ARM_EXP_0_TRG_1_AC0_OPTO_DIG ARM_EXP_0_TRG_1_AC0_OPTO_DIG_AV yes
"Hardware Port2, P1_OPTO_AUX(TRIG)_IN_0 (HD44: pin12+ and 28-) " M_DEFAULT ARM_EXP_0_TRG_0_AC1_OPTO_DIG ARM_EXP_0_TRG_0_AC1_OPTO_DIG_AV yes
"Hardware Port3, P1_OPTO_AUX(TRIG)_IN_1 (DB9 : pin4+ and 5-) " M_DEFAULT ARM_EXP_0_TRG_1_AC1_OPTO_DIG ARM_EXP_0_TRG_1_AC1_OPTO_DIG_AV yes
"Hardware Port2, P2_OPTO_AUX(TRIG)_IN_0 (HD44: pin13+ and 14-) " M_DEFAULT ARM_EXP_0_TRG_0_AC2_OPTO_DIG ARM_EXP_0_TRG_0_AC2_OPTO_DIG_AV yes
"Hardware Port3, P2_OPTO_AUX(TRIG)_IN_1 (DB9 : pin1+ and 6-) " M_DEFAULT ARM_EXP_0_TRG_1_AC2_OPTO_DIG ARM_EXP_0_TRG_1_AC2_OPTO_DIG_AV yes
"Hardware Port2, P3_OPTO_AUX(TRIG)_IN_0 (HD44: pin23+ and 37-) " M_DEFAULT ARM_EXP_0_TRG_0_AC3_OPTO_DIG ARM_EXP_0_TRG_0_AC3_OPTO_DIG_AV yes
"Hardware Port3, P3_OPTO_AUX(TRIG)_IN_1 (DB9 : pin8+ and 3-) " M_DEFAULT ARM_EXP_0_TRG_1_AC3_OPTO_DIG ARM_EXP_0_TRG_1_AC3_OPTO_DIG_AV yes
"Hardware Port0, P0_TTL_AUX(TRIG)_IO (CON0: pin49)" M_DEFAULT ARM_EXP_0_TRG_1_AC0_TTL_DIG ARM_EXP_0_TRG_1_AC0_TTL_DIG_AV yes
"Hardware Port0, P1_TTL_AUX(TRIG)_IO (CON0: pin99)" M_DEFAULT ARM_EXP_0_TRG_1_AC1_TTL_DIG ARM_EXP_0_TRG_1_AC1_TTL_DIG_AV yes
"Hardware Port0, P2_TTL_AUX(TRIG)_IO (CON1: pin49)" M_DEFAULT ARM_EXP_0_TRG_1_AC2_TTL_DIG ARM_EXP_0_TRG_1_AC2_TTL_DIG_AV yes
"Hardware Port0, P3_TTL_AUX(TRIG)_IO (CON1: pin99)" M_DEFAULT ARM_EXP_0_TRG_1_AC3_TTL_DIG ARM_EXP_0_TRG_1_AC3_TTL_DIG_AV yes
"Hardware Port1, P0_LVDS_AUX(VSYNC)_IN (CON0: pin35+ and 36-) " M_DEFAULT ARM_EXP_0_TRG_0_AC0_LVDS_DIG ARM_EXP_0_TRG_0_AC0_LVDS_DIG_AV yes
"Hardware Port1, P1_LVDS_AUX(VSYNC)_IN (CON0: pin85+ and 86-) " M_DEFAULT ARM_EXP_0_TRG_0_AC1_LVDS_DIG ARM_EXP_0_TRG_0_AC1_LVDS_DIG_AV yes
"Hardware Port1, P2_LVDS_AUX(VSYNC)_IN (CON1: pin35+ and 36-) " M_DEFAULT ARM_EXP_0_TRG_0_AC2_LVDS_DIG ARM_EXP_0_TRG_0_AC2_LVDS_DIG_AV yes
"Hardware Port1, P3_LVDS_AUX(VSYNC)_IN (CON1: pin85+ and 86-) " M_DEFAULT ARM_EXP_0_TRG_0_AC3_LVDS_DIG ARM_EXP_0_TRG_0_AC3_LVDS_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20+ and 4-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15+ and 30-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44+ and 29-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43+ and 42-) [Common Trigger]" M_DEFAULT ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG_AV yes
"Rotary Encoder Trigger, P0_LVDS_AUX_IN0-1 (DB9: pin8+ and 3-) & (HD44: pin37+ and 23-)" M_DEFAULT ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS_AUX_IN0-1 (HD44: pin32+ and 31-) & (HD44: pin12+ and 28-)" M_DEFAULT ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN0-1 (HD44: pin35+ and 34-) & (HD44: pin12+ and 28-)" M_DEFAULT ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN2-3 (HD44: pin8+ and 24-) & (HD44: pin39+ and 38-)" M_DEFAULT ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN4-5 (HD44: pin7+ and 22-) & (HD44: pin6+ and 5-)" M_DEFAULT ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN6-7 (HD44: pin32+ and 31-) & (HD44: pin1+ and 16-)" M_DEFAULT ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN0-1 (HD44: pin20+ and 4-) & (HD44: pin6+ and 5-)" M_DEFAULT ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN2-3 (HD44: pin7+ and 22-) & (HD44: pin15+ and 30-)" M_DEFAULT ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN4-5 (HD44: pin44+ and 29-) & (HD44: pin32+ and 31-)" M_DEFAULT ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN6-7 (HD44: pin39+ and 38-) & (HD44: pin43+ and 42-)" M_DEFAULT ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV yes
"OLD Rotary Encoder" M_DEFAULT ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_ARM_FORMAT
//
enable = ENABLE[( DEF_TIMER0_ENABLED * EXP_ARM_ENABLE )] ;
//
pagelinks = (
(
( ! EXP_ARM_TTL ) * ( ! EXP_ARM_422 ) * ( ! EXP_ARM_OPTO ) * ( ! EXP_ARM_LVDS ) *
( ! EXP_ARM_DEFAULT )
) ? ( EXP_ARM_TTL.SETVALUE[1] + ARM_EXP_0_CNTEQ0.SETVALUE[1] ) : 0
) + GEXP_TRG_FORMAT.VALID ;
//
eo_param
// --------------------------------------
//
GEXP_ARM_POLARITY
//
enable = ENABLE[( DEF_TIMER0_ENABLED * EXP_ARM_ENABLE )] ;
//
pagelinks = (
( ( ! EXP_ARM_POS ) * ( ! EXP_ARM_NEG ) ) ? ( EXP_ARM_POS.SETVALUE[1] + ARM_EXP_0_CNTEQ0.SETVALUE[1] ) : 0
) + GEXP_TRG_FORMAT.VALID ;
//
eo_param
// --------------------------------------
//
GEXP_COMBINE ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
enable = ENABLE[( DEF_TIMER0_ENABLED )] ;
//
pagelinks = GEXP_GEN_MODE_2.VALID ;
//
param_info
Exposure Signal / Timer 1 Advanced
Timer Output Signal
eo_param_info
//
board_specific_value
"Timer 1" M_DEFAULT DUMMY_PAR NO_BOPTION yes
"Timer 1 XOR Timer 2" M_DEFAULT EXP_COMBINE_XOR_T1 M_DEFAULT yes
"Timer 1 XOR Timer 1 of AP1" M_DEFAULT EXP_COMBINE_XOR_T0AC1 M_DEFAULT yes
"Timer 2" M_DEFAULT EXP_COMBINE_T1 M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_PRESCALE1 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Exposure Signal / Timer 1 Advanced
Capture a Trigger Every
eo_param_info
//
enable = ENABLE[( DEF_TIMER0_ENABLED )] ;
//
board_specific_value
1 M_DEFAULT EXP_PRESCALE1_1 M_DEFAULT yes
2 M_DEFAULT EXP_PRESCALE1_2 M_DEFAULT yes
4 M_DEFAULT EXP_PRESCALE1_4 M_DEFAULT yes
8 M_DEFAULT EXP_PRESCALE1_8 M_DEFAULT yes
16 M_DEFAULT EXP_PRESCALE1_16 M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// ********** Exposure Signal Timer2 **********
//
GEXP_GEN_MODE_2
//
enable = ENABLE[1] ;
//
pagelinks = ( GGRB_LINESCAN.UPDATE + GEXP_CLOCK.UPDATE + GEXP_GEN_MODE.UPDATE + GEXP_ARM_MODE_2.VALID ) ;
//
valid = ( ( EXP_CLK_TIMER1 * EXP_CLK_2_TIMER0 ) ? ADDERROR[ERR_2CLKS_TIMER0_TIMER1] : 0 ) ;
//
//valid = (
// ( EXP_CLK_TIMER1 * EXP_CLK_2_TIMER0 ) ? ADDERROR[ERR_2CLKS_TIMER0_TIMER1] :
// ( ( EXP_CLK_2_TIMER0 * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * ( ! EXP_MD_PERD ) ) ? ADDERROR[ERR_NO_PERIODIC_TIMER0] : 0 )
// ) ;
//
error_message
ERR_NO_PERIODIC_TIMER0, "Timer 1 should be set in Periodic."
ERR_PERIODIC_2TIMERS, "1 Timer should be selected at once as Timer clock in Periodic mode."
ERR_2CLKS_TIMER0_TIMER1, "1 Timer Clock Should be selected at once. Select Timer 1 Output or Timer 2 Output as Exposure Clock."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_OUT_TIM_0_2
//
enable = ENABLE[( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 )] ;
//
pagelinks = ( GEXP_TRG_SIGNAL_2.UPDATE + GEXP_CLOCK_2.UPDATE + GEXP_FREQUENCY.VALID + GEXP_FREQUENCY_2.VALID ) ;
//
// TO BE REVIEW WITH NEW FORMAT EXPOSURE TRIGGER INPUT IN INTELLICAM (LVDS/OPTO)
//
valid = (
( ( DEF_TIMER1_TRIGGERS_PIPE_DELAY == 2 ) & ( EXP_OUT_T0_2 < 2 ) ) ? ADDERROR[ERR_TIMER1_DLY2_MIN] :
( ( ( DEF_TIMER1_TRIGGERS_PIPE_DELAY == 3 ) & ( EXP_OUT_T0_2 < 3 ) ) ? ADDERROR[ERR_TIMER1_DLY3_MIN] :
( ( ( DEF_TIMER1_TRIGGERS_PIPE_DELAY == 4 ) & ( EXP_OUT_T0_2 < 4 ) ) ? ADDERROR[ERR_TIMER1_DLY4_MIN] :
( ( ( DEF_TIMER1_TRIGGERS_PIPE_DELAY == 5 ) & ( EXP_OUT_T0_2 < 5 ) ) ? ADDERROR[ERR_TIMER1_DLY5_MIN] :
( DEF_TMR1_CLKFREQ<=TRGFREQ ? ADDERROR[ERR_TIMER1_CLKFREQ<=TRGFREQ] :
( ( ( EXP_OUT_T3_2 > 0 ) & ( EXP_OUT_T2_2 == 0 ) ) ? ADDERROR[ERR_TIMER1_1DLY_PULSE2] : 0 ) ) ) ) )
) ;
//
error_message
ERR_TIMER1_DLY2_MIN, "Delay of Pulse 1 from Timer 2 should be at least 2 counts minimum."
ERR_TIMER1_DLY3_MIN, "Delay of Pulse 1 from Timer 2 should be at least 3 counts minimum."
ERR_TIMER1_DLY4_MIN, "Delay of Pulse 1 from Timer 2 should be at least 4 counts minimum."
ERR_TIMER1_DLY5_MIN, "Delay of Pulse 1 from Timer 2 should be at least 5 counts minimum."
ERR_TIMER1_CLKFREQ<=TRGFREQ, "Frequency of Timer2 Clock should be at least higher than the Trigger Frequency. Set the Exposure Time Smaller or Same as the Trigger Time."
ERR_TIMER1_1DLY_PULSE2, "At least 1 count minimum should be set for Delay 2 when Pulse 2 is activated for Timer 2."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_OUT_TIM_2_2
//
enable = ENABLE[( ( EXP_MD_PERD_2 * ( ! EXP_CLK_TIMER1 ) ) | EXP_MD_W_TRG_2 )] ;
//
eo_param
// --------------------------------------
//
GEXP_OUT_TIM_3_2
//
enable = ENABLE[( ( EXP_MD_PERD_2 * ( ! EXP_CLK_TIMER1 ) ) | EXP_MD_W_TRG_2 )] ;
//
eo_param
// --------------------------------------
//
GEXP_OUT_FORMAT_2
//
pagelinks = GEXP_OUT_FORMAT.VALID ;
//
eo_param
// --------------------------------------
//
GEXP_TRG_SIGNAL_2
//
pagelinks = ( GEXP_CLOCK_2.UPDATE + GVDC_PSG_0.VALID + GPCK_FREQUENCY.VALID ) ;
//
board_specific_value
"TTL Trigger" M_DEFAULT EXP_TRG_TTL_TIMER1 EXP_TRG_TTL_TIMER1_AV no
"TTL Trigger" M_DEFAULT EXP_TRG_TTL_TIMER2 EXP_TRG_TTL_TIMER2_AV no
"Timer 2 = 0" M_DEFAULT EXP_TRG_CNTEQ0_TIMER1 EXP_TRG_CNTEQ0_TIMER1_AV no
"Timer 1 Output" M_DEFAULT EXP_TRG_TIMER0_2 EXP_TRG_TIMER0_2_AV yes
"Timer 3 Output" M_DEFAULT EXP_TRG_TIMER2_2 EXP_TRG_TIMER2_2_AV no
"Timer 4 Output" M_DEFAULT EXP_TRG_TIMER3_2 EXP_TRG_TIMER3_2_AV no
"Timer 2 Output from AP0" M_DEFAULT EXP_1_TRG_TIMER1_AC0 EXP_1_TRG_TIMER1_AC0_AV yes
"Timer 2 Output from AP1" M_DEFAULT EXP_1_TRG_TIMER1_AC1 EXP_1_TRG_TIMER1_AC1_AV yes
"Timer 2 Output from AP2" M_DEFAULT EXP_1_TRG_TIMER1_AC2 EXP_1_TRG_TIMER1_AC2_AV yes
"Timer 2 Output from AP3" M_DEFAULT EXP_1_TRG_TIMER1_AC3 EXP_1_TRG_TIMER1_AC3_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC01_OPTO_CL EXP_1_TRG_2_AC01_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC01_OPTO_CL EXP_1_TRG_3_AC01_OPTO_CL_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [AP1 ONLY Trig0]" M_DEFAULT EXP_1_TRG_0_AC1_OPTO_CL EXP_1_TRG_0_AC1_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [AP1 ONLY Trig1]" M_DEFAULT EXP_1_TRG_1_AC1_OPTO_CL EXP_1_TRG_1_AC1_OPTO_CL_AV yes
"Hardware Port2, TTL_AUX_IO_0 (HD44: pin43) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC01_TTL_CL EXP_1_TRG_2_AC01_TTL_CL_AV yes
"Hardware Port3, TTL_AUX_IO_1 (HD44: pin15) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC01_TTL_CL EXP_1_TRG_3_AC01_TTL_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC01_LVDS_CL EXP_1_TRG_2_AC01_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC01_LVDS_CL EXP_1_TRG_3_AC01_LVDS_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [AP1 ONLY Trig0]" M_DEFAULT EXP_1_TRG_0_AC1_LVDS_CL EXP_1_TRG_0_AC1_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [AP1 ONLY Trig1]" M_DEFAULT EXP_1_TRG_1_AC1_LVDS_CL EXP_1_TRG_1_AC1_LVDS_CL_AV yes
"Hardware Port6, P0_OPTO_AUX_IN0 (DB9: pin7+ and 2-)" M_DEFAULT EXP_1_TRG_0_AC0_OPTO_CL EXP_1_TRG_0_AC0_OPTO_CL_AV yes
"Hardware Port7, P0_OPTO_AUX_IN1 (DB9: pin4+ and 5-)" M_DEFAULT EXP_1_TRG_1_AC0_OPTO_CL EXP_1_TRG_1_AC0_OPTO_CL_AV yes
"Hardware Port8, P0_TTL_AUX_IO_0 (DB9: pin1)" M_DEFAULT EXP_1_TRG_0_AC0_TTL_CL EXP_1_TRG_0_AC0_TTL_CL_AV yes
"Hardware Port9, P0_TTL_AUX_IO_1 (HD44: pin13)" M_DEFAULT EXP_1_TRG_1_AC0_TTL_CL EXP_1_TRG_1_AC0_TTL_CL_AV yes
"Hardware Port8, P1_TTL_AUX_IO_0 (HD44: pin35)" M_DEFAULT EXP_1_TRG_0_AC1_TTL_CL EXP_1_TRG_0_AC1_TTL_CL_AV yes
"Hardware Port9, P1_TTL_AUX_IO_1 (HD44: pin1)" M_DEFAULT EXP_1_TRG_1_AC1_TTL_CL EXP_1_TRG_1_AC1_TTL_CL_AV yes
"Hardware Port10, P0_LVDS_AUX_IN0 (DB9: pin8+ and 3-)" M_DEFAULT EXP_1_TRG_0_AC0_LVDS_CL EXP_1_TRG_0_AC0_LVDS_CL_AV yes
"Hardware Port11, P0_LVDS_AUX_IN1 (HD44: pin37+ and 23-)" M_DEFAULT EXP_1_TRG_1_AC0_LVDS_CL EXP_1_TRG_1_AC0_LVDS_CL_AV yes
"Hardware Port0, P0_OPTO_AUX(TRIG)_IN (DB9: pin7+ and 2-)" M_DEFAULT EXP_1_TRG_1_AC0_OPTO_ANA EXP_1_TRG_1_AC0_OPTO_ANA_AV yes
"Hardware Port0, P1_OPTO_AUX(TRIG)_IN (DB9: pin4+ and 5-)" M_DEFAULT EXP_1_TRG_1_AC1_OPTO_ANA EXP_1_TRG_1_AC1_OPTO_ANA_AV yes
"Hardware Port0, P2_OPTO_AUX(TRIG)_IN (DB9: pin1+ and 6-)" M_DEFAULT EXP_1_TRG_1_AC2_OPTO_ANA EXP_1_TRG_1_AC2_OPTO_ANA_AV yes
"Hardware Port0, P3_OPTO_AUX(TRIG)_IN (DB9: pin8+ and 3-)" M_DEFAULT EXP_1_TRG_1_AC3_OPTO_ANA EXP_1_TRG_1_AC3_OPTO_ANA_AV yes
"Hardware Port1, P0_TTL_AUX(TRIG)_IN (DVI 0: pin14)" M_DEFAULT EXP_1_TRG_0_AC0_TTL_ANA EXP_1_TRG_0_AC0_TTL_ANA_AV yes
"Hardware Port1, P1_TTL_AUX(TRIG)_IN (DVI 0: pin22)" M_DEFAULT EXP_1_TRG_0_AC1_TTL_ANA EXP_1_TRG_0_AC1_TTL_ANA_AV yes
"Hardware Port1, P2_TTL_AUX(TRIG)_IN (DVI 1: pin14)" M_DEFAULT EXP_1_TRG_0_AC2_TTL_ANA EXP_1_TRG_0_AC2_TTL_ANA_AV yes
"Hardware Port1, P3_TTL_AUX(TRIG)_IN (DVI 1: pin22)" M_DEFAULT EXP_1_TRG_0_AC3_TTL_ANA EXP_1_TRG_0_AC3_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0+ (HD44: pin35) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX0_TTL_ANA EXP_1_TRG_2_4AC_AUX0_TTL_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1+ (HD44: pin12) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX1_TTL_ANA EXP_1_TRG_3_4AC_AUX1_TTL_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2+ (HD44: pin8 ) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX2_TTL_ANA EXP_1_TRG_2_4AC_AUX2_TTL_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3+ (HD44: pin39) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX3_TTL_ANA EXP_1_TRG_3_4AC_AUX3_TTL_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4+ (HD44: pin7 ) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX4_TTL_ANA EXP_1_TRG_2_4AC_AUX4_TTL_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5+ (HD44: pin6 ) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX5_TTL_ANA EXP_1_TRG_3_4AC_AUX5_TTL_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6+ (HD44: pin32) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX6_TTL_ANA EXP_1_TRG_2_4AC_AUX6_TTL_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7+ (HD44: pin1 ) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX7_TTL_ANA EXP_1_TRG_3_4AC_AUX7_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0 (HD44: pin35+ and 34-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX0_LVDS_ANA EXP_1_TRG_2_4AC_AUX0_LVDS_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX1_LVDS_ANA EXP_1_TRG_3_4AC_AUX1_LVDS_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2 (HD44: pin8+ and 24-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX2_LVDS_ANA EXP_1_TRG_2_4AC_AUX2_LVDS_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX3_LVDS_ANA EXP_1_TRG_3_4AC_AUX3_LVDS_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX4_LVDS_ANA EXP_1_TRG_2_4AC_AUX4_LVDS_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX5_LVDS_ANA EXP_1_TRG_3_4AC_AUX5_LVDS_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_4AC_AUX6_LVDS_ANA EXP_1_TRG_2_4AC_AUX6_LVDS_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7 (HD44: pin1+ and 16-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_4AC_AUX7_LVDS_ANA EXP_1_TRG_3_4AC_AUX7_LVDS_ANA_AV yes
"Hardware Port2, P0_OPTO_AUX(TRIG)_IN_0 (HD44: pin2+ and 17-)" M_DEFAULT EXP_1_TRG_0_AC0_OPTO_DIG EXP_1_TRG_0_AC0_OPTO_DIG_AV yes
"Hardware Port3, P0_OPTO_AUX(TRIG)_IN_1 (DB9 : pin7+ and 2-)" M_DEFAULT EXP_1_TRG_1_AC0_OPTO_DIG EXP_1_TRG_1_AC0_OPTO_DIG_AV yes
"Hardware Port2, P1_OPTO_AUX(TRIG)_IN_0 (HD44: pin12+ and 28-) " M_DEFAULT EXP_1_TRG_0_AC1_OPTO_DIG EXP_1_TRG_0_AC1_OPTO_DIG_AV yes
"Hardware Port3, P1_OPTO_AUX(TRIG)_IN_1 (DB9 : pin4+ and 5-) " M_DEFAULT EXP_1_TRG_1_AC1_OPTO_DIG EXP_1_TRG_1_AC1_OPTO_DIG_AV yes
"Hardware Port2, P2_OPTO_AUX(TRIG)_IN_0 (HD44: pin13+ and 14-) " M_DEFAULT EXP_1_TRG_0_AC2_OPTO_DIG EXP_1_TRG_0_AC2_OPTO_DIG_AV yes
"Hardware Port3, P2_OPTO_AUX(TRIG)_IN_1 (DB9 : pin1+ and 6-) " M_DEFAULT EXP_1_TRG_1_AC2_OPTO_DIG EXP_1_TRG_1_AC2_OPTO_DIG_AV yes
"Hardware Port2, P3_OPTO_AUX(TRIG)_IN_0 (HD44: pin23+ and 37-) " M_DEFAULT EXP_1_TRG_0_AC3_OPTO_DIG EXP_1_TRG_0_AC3_OPTO_DIG_AV yes
"Hardware Port3, P3_OPTO_AUX(TRIG)_IN_1 (DB9 : pin8+ and 3-) " M_DEFAULT EXP_1_TRG_1_AC3_OPTO_DIG EXP_1_TRG_1_AC3_OPTO_DIG_AV yes
"Hardware Port0, P0_TTL_AUX(TRIG)_IO (CON0: pin49)" M_DEFAULT EXP_1_TRG_1_AC0_TTL_DIG EXP_1_TRG_1_AC0_TTL_DIG_AV yes
"Hardware Port0, P1_TTL_AUX(TRIG)_IO (CON0: pin99)" M_DEFAULT EXP_1_TRG_1_AC1_TTL_DIG EXP_1_TRG_1_AC1_TTL_DIG_AV yes
"Hardware Port0, P2_TTL_AUX(TRIG)_IO (CON1: pin49)" M_DEFAULT EXP_1_TRG_1_AC2_TTL_DIG EXP_1_TRG_1_AC2_TTL_DIG_AV yes
"Hardware Port0, P3_TTL_AUX(TRIG)_IO (CON1: pin99)" M_DEFAULT EXP_1_TRG_1_AC3_TTL_DIG EXP_1_TRG_1_AC3_TTL_DIG_AV yes
"Hardware Port1, P0_LVDS_AUX(VSYNC)_IN (CON0: pin35+ and 36-) " M_DEFAULT EXP_1_TRG_0_AC0_LVDS_DIG EXP_1_TRG_0_AC0_LVDS_DIG_AV yes
"Hardware Port1, P1_LVDS_AUX(VSYNC)_IN (CON0: pin85+ and 86-) " M_DEFAULT EXP_1_TRG_0_AC1_LVDS_DIG EXP_1_TRG_0_AC1_LVDS_DIG_AV yes
"Hardware Port1, P2_LVDS_AUX(VSYNC)_IN (CON1: pin35+ and 36-) " M_DEFAULT EXP_1_TRG_0_AC2_LVDS_DIG EXP_1_TRG_0_AC2_LVDS_DIG_AV yes
"Hardware Port1, P3_LVDS_AUX(VSYNC)_IN (CON1: pin85+ and 86-) " M_DEFAULT EXP_1_TRG_0_AC3_LVDS_DIG EXP_1_TRG_0_AC3_LVDS_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC0_AUX1_TTL_DIG EXP_1_TRG_2_AC0_AUX1_TTL_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC0_AUX2_TTL_DIG EXP_1_TRG_3_AC0_AUX2_TTL_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC1_AUX1_TTL_DIG EXP_1_TRG_2_AC1_AUX1_TTL_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC1_AUX2_TTL_DIG EXP_1_TRG_3_AC1_AUX2_TTL_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC2_AUX1_TTL_DIG EXP_1_TRG_2_AC2_AUX1_TTL_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC2_AUX2_TTL_DIG EXP_1_TRG_3_AC2_AUX2_TTL_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC3_AUX1_TTL_DIG EXP_1_TRG_2_AC3_AUX1_TTL_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC3_AUX2_TTL_DIG EXP_1_TRG_3_AC3_AUX2_TTL_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20+ and 4-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC0_AUX1_LVDS_DIG EXP_1_TRG_2_AC0_AUX1_LVDS_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC0_AUX2_LVDS_DIG EXP_1_TRG_3_AC0_AUX2_LVDS_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC1_AUX1_LVDS_DIG EXP_1_TRG_2_AC1_AUX1_LVDS_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15+ and 30-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC1_AUX2_LVDS_DIG EXP_1_TRG_3_AC1_AUX2_LVDS_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44+ and 29-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC2_AUX1_LVDS_DIG EXP_1_TRG_2_AC2_AUX1_LVDS_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC2_AUX2_LVDS_DIG EXP_1_TRG_3_AC2_AUX2_LVDS_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT EXP_1_TRG_2_AC3_AUX1_LVDS_DIG EXP_1_TRG_2_AC3_AUX1_LVDS_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43+ and 42-) [Common Trigger]" M_DEFAULT EXP_1_TRG_3_AC3_AUX2_LVDS_DIG EXP_1_TRG_3_AC3_AUX2_LVDS_DIG_AV yes
"Rotary Encoder Trigger, P0_LVDS_AUX_IN0-1 (DB9: pin8+ and 3-) & (HD44: pin37+ and 23-)" M_DEFAULT EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS_AUX_IN0-1 (HD44: pin32+ and 31-) & (HD44: pin12+ and 28-)" M_DEFAULT EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN0-1 (HD44: pin35+ and 34-) & (HD44: pin12+ and 28-)" M_DEFAULT EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN2-3 (HD44: pin8+ and 24-) & (HD44: pin39+ and 38-)" M_DEFAULT EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN4-5 (HD44: pin7+ and 22-) & (HD44: pin6+ and 5-)" M_DEFAULT EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN6-7 (HD44: pin32+ and 31-) & (HD44: pin1+ and 16-)" M_DEFAULT EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN0-1 (HD44: pin20+ and 4-) & (HD44: pin6+ and 5-)" M_DEFAULT EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN2-3 (HD44: pin7+ and 22-) & (HD44: pin15+ and 30-)" M_DEFAULT EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN4-5 (HD44: pin44+ and 29-) & (HD44: pin32+ and 31-)" M_DEFAULT EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN6-7 (HD44: pin39+ and 38-) & (HD44: pin43+ and 42-)" M_DEFAULT EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV yes
"OLD Rotary Encoder" M_DEFAULT EXP_1_TRG_LVDS_ROTARY_ENCODER EXP_1_TRG_LVDS_ROTARY_ENCODER_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_TRG_FORMAT_2
//
enable = ENABLE[( EXP_MD_W_TRG_2 )] ;
//
pagelinks = (
(
( ! EXP_TRG_TTL_2 ) * ( ! EXP_TRG_422_2 ) * ( ! EXP_TRG_OPTO_2 ) *
( ! EXP_TRG_LVDS_2 ) * ( ! EXP_TRG_DEFAULT_2 )
) ? EXP_TRG_TTL_2.SETVALUE[1] : 0
) ;
//
eo_param
// --------------------------------------
//
GEXP_TRG_POL_2
//
enable = ENABLE[( EXP_MD_W_TRG_2 )] ;
//
pagelinks = (
( ( ! EXP_TRG_POS_2 ) * ( ! EXP_TRG_NEG_2 ) ) ? EXP_TRG_POS_2.SETVALUE[1] : 0
) ;
//
eo_param
// --------------------------------------
//
GEXP_CLOCK_2
//
pagelinks = ( GEXP_GEN_MODE.VALID + GEXP_TRG_SIGNAL_2.VALID + GEXP_FREQUENCY_2.VALID ) ;
//
board_specific_value
"Clock Generator" M_DEFAULT EXP_CLK_2_CLKGEN EXP_CLK_2_CLKGEN_AV yes
"Clock ASY" M_DEFAULT EXP_ASY_CLK_2 EXP_ASY_CLK_AV_2 no
"HSync Clock" M_DEFAULT EXP_CLK_2_HS EXP_CLK_2_HS_AV yes
"VSync Clock" M_DEFAULT EXP_CLK_2_VS EXP_CLK_2_VS_AV yes
"Timer 1 Output" M_DEFAULT EXP_CLK_2_TIMER0 EXP_CLK_2_TIMER0_AV yes
"Timer 3 Output" M_DEFAULT EXP_CLK_2_TIMER2 EXP_CLK_2_TIMER2_AV no
"Timer 4 Output" M_DEFAULT EXP_CLK_2_TIMER3 EXP_CLK_2_TIMER3_AV no
"Aux Input LVDS " M_DEFAULT EXP_CLK_2_AUXIN1_LVDS EXP_CLK_2_AUXIN1_LVDS_AV no
"Aux Input LVDS " M_DEFAULT EXP_CLK_2_AUXIN3_LVDS EXP_CLK_2_AUXIN3_LVDS_AV no
"Aux1 Input LVDS (HD44: pin37+ and 23-) [AP0]" M_DEFAULT EXP_CLK_2_AUXIN1_AC0_CL EXP_CLK_2_AUXIN1_AC0_CL_AV yes
"Aux3 Input LVDS (HD44: pin12+ and 28-) [AP1]" M_DEFAULT EXP_CLK_2_AUXIN3_AC1_CL EXP_CLK_2_AUXIN3_AC1_CL_AV yes
"Aux1 Input LVDS (HD44: pin12+ and 28-) [AP0]" M_DEFAULT EXP_CLK_2_AUXIN1_AC0_ANA EXP_CLK_2_AUXIN1_AC0_ANA_AV yes
"Aux3 Input LVDS (HD44: pin39+ and 38-) [AP1]" M_DEFAULT EXP_CLK_2_AUXIN3_AC1_ANA EXP_CLK_2_AUXIN3_AC1_ANA_AV yes
"Aux5 Input LVDS (HD44: pin6+ and 5-) [AP2]" M_DEFAULT EXP_CLK_2_AUXIN5_AC2_ANA EXP_CLK_2_AUXIN5_AC2_ANA_AV yes
"Aux7 Input LVDS (HD44: pin1+ and 16-) [AP3]" M_DEFAULT EXP_CLK_2_AUXIN7_AC3_ANA EXP_CLK_2_AUXIN7_AC3_ANA_AV yes
"Aux2 Input LVDS (HD44: pin6+ and 5-) [AP0]" M_DEFAULT EXP_CLK_2_AUXIN2_AC0_DIG EXP_CLK_2_AUXIN2_AC0_DIG_AV yes
"Aux2 Input LVDS (HD44: pin15+ and 30-) [AP1]" M_DEFAULT EXP_CLK_2_AUXIN2_AC1_DIG EXP_CLK_2_AUXIN2_AC1_DIG_AV yes
"Aux2 Input LVDS (HD44: pin32+ and 31-) [AP2]" M_DEFAULT EXP_CLK_2_AUXIN2_AC2_DIG EXP_CLK_2_AUXIN2_AC2_DIG_AV yes
"Aux2 Input LVDS (HD44: pin43+ and 42-) [AP3]" M_DEFAULT EXP_CLK_2_AUXIN2_AC3_DIG EXP_CLK_2_AUXIN2_AC3_DIG_AV yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_FREQUENCY_2
//
enable = ENABLE[(
EXP_CLK_2_CLKGEN || EXP_CLK_2_AUXIN1_AC0_CL || EXP_CLK_2_AUXIN3_AC1_CL ||
EXP_CLK_2_AUXIN1_AC0_ANA || EXP_CLK_2_AUXIN3_AC1_ANA || EXP_CLK_2_AUXIN5_AC2_ANA || EXP_CLK_2_AUXIN7_AC3_ANA ||
EXP_CLK_2_AUXIN2_AC0_DIG || EXP_CLK_2_AUXIN2_AC1_DIG || EXP_CLK_2_AUXIN2_AC2_DIG || EXP_CLK_2_AUXIN2_AC3_DIG
)] ;
//
pagelinks = ( GPCK_FREQUENCY.UPDATE + GEXP_FREQUENCY.UPDATE + GEXP_CLOCK.UPDATE + GSYC_SOURCE.UPDATE ) ;
//
valid = (
(
EXP_CLK_2_CLKGEN * ( ! SYC_CAM_GEN ) *
( ( EXP_CLK_FREQ_2 > ( PCK_FREQ + 2 ) ) | ( EXP_CLK_FREQ_2 < ( PCK_FREQ - 2 ) ) )
)
? ADDERROR[ERR_T1_DIG_MASTER_CLKGEN] :
( (
EXP_CLK_CLKGEN * EXP_CLK_2_CLKGEN * SYC_CAM_GEN *
( EXP_CLK_FREQ != EXP_CLK_FREQ_2 )
) ? ADDERROR[ERR_T0_T1_DIFF_CLKGEN] : 0 )
) ;
//
error_message
ERR_T1_DIG_MASTER_CLKGEN, "The Timer 2 Clock Generator Frequency should be the same as Pixel Clock in Digitizer Master Configuration. Readjust the value."
ERR_T0_T1_DIFF_CLKGEN, "The Clock Generator Frequency should be the same for Timer1 and Timer2. Readjust Timer1 or Timer2 at the same frequency."
eo_error_message
//
eo_param
// --------------------------------------
//
GEXP_ARM_MODE_2
//
enable = ENABLE[( DEF_TIMER1_ENABLED )] ;
//
pagelinks = (
(
DEF_TIMER1_ENABLED & ( ! EXP_ARM_ENABLE_2 ) & ( ! EXP_ARM_DISABLE_2 )
) ? ( EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1] ) : 0
) + GGRB_MODE.UPDATE + GEXP_ARM_SOURCE_2.VALID ;
//
eo_param
// --------------------------------------
//
GEXP_ARM_SOURCE_2
//
enable = ENABLE[( DEF_TIMER1_ENABLED * EXP_ARM_ENABLE_2 )] ;
//
pagelinks = ( GVDC_PSG_0.VALID + GEXP_GEN_MODE_2.UPDATE + GEXP_ARM_MODE_2.UPDATE + GPCK_FREQUENCY.VALID ) ;
//
board_specific_value
"Timer 2 = 0" M_DEFAULT ARM_EXP_1_CNTEQ0 ARM_EXP_1_CNTEQ0_AV yes
"Software Arm" M_DEFAULT ARM_EXP_1_SOFTWARE ARM_EXP_1_SOFTWARE_AV yes
"Timer 1 Output" M_DEFAULT ARM_EXP_1_TIMER0 ARM_EXP_1_TIMER0_AV yes
"Timer 3 Output" M_DEFAULT ARM_EXP_1_TIMER2 ARM_EXP_1_TIMER2_AV no
"Timer 4 Output" M_DEFAULT ARM_EXP_1_TIMER3 ARM_EXP_1_TIMER3_AV no
"Timer 2 Output from AP0" M_DEFAULT ARM_EXP_1_TRG_TIMER1_AC0 ARM_EXP_1_TRG_TIMER1_AC0_AV yes
"Timer 2 Output from AP1" M_DEFAULT ARM_EXP_1_TRG_TIMER1_AC1 ARM_EXP_1_TRG_TIMER1_AC1_AV yes
"Timer 2 Output from AP2" M_DEFAULT ARM_EXP_1_TRG_TIMER1_AC2 ARM_EXP_1_TRG_TIMER1_AC2_AV yes
"Timer 2 Output from AP3" M_DEFAULT ARM_EXP_1_TRG_TIMER1_AC3 ARM_EXP_1_TRG_TIMER1_AC3_AV yes
"PSG HSync" M_DEFAULT ARM_EXP_1_HS_PSG ARM_EXP_1_HS_PSG_AV yes
"PSG VSync" M_DEFAULT ARM_EXP_1_VS_PSG ARM_EXP_1_VS_PSG_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC01_OPTO_CL ARM_EXP_1_TRG_2_AC01_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC01_OPTO_CL ARM_EXP_1_TRG_3_AC01_OPTO_CL_AV yes
"Hardware Port0, OPTO_AUX_IN0 (HD44: pin24+ and 8-) [AP1 ONLY Trig0]" M_DEFAULT ARM_EXP_1_TRG_0_AC1_OPTO_CL ARM_EXP_1_TRG_0_AC1_OPTO_CL_AV yes
"Hardware Port1, OPTO_AUX_IN1 (HD44: pin38+ and 39-) [AP1 ONLY Trig1]" M_DEFAULT ARM_EXP_1_TRG_1_AC1_OPTO_CL ARM_EXP_1_TRG_1_AC1_OPTO_CL_AV yes
"Hardware Port2, TTL_AUX_IO_0 (HD44: pin43) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC01_TTL_CL ARM_EXP_1_TRG_2_AC01_TTL_CL_AV yes
"Hardware Port3, TTL_AUX_IO_1 (HD44: pin15) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC01_TTL_CL ARM_EXP_1_TRG_3_AC01_TTL_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC01_LVDS_CL ARM_EXP_1_TRG_2_AC01_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC01_LVDS_CL ARM_EXP_1_TRG_3_AC01_LVDS_CL_AV yes
"Hardware Port4, LVDS_AUX_IN0 (HD44: pin32+ and 31-) [AP1 ONLY Trig0]" M_DEFAULT ARM_EXP_1_TRG_0_AC1_LVDS_CL ARM_EXP_1_TRG_0_AC1_LVDS_CL_AV yes
"Hardware Port5, LVDS_AUX_IN1 (HD44: pin12+ and 28-) [AP1 ONLY Trig1]" M_DEFAULT ARM_EXP_1_TRG_1_AC1_LVDS_CL ARM_EXP_1_TRG_1_AC1_LVDS_CL_AV yes
"Hardware Port6, P0_OPTO_AUX_IN0 (DB9: pin7+ and 2-)" M_DEFAULT ARM_EXP_1_TRG_0_AC0_OPTO_CL ARM_EXP_1_TRG_0_AC0_OPTO_CL_AV yes
"Hardware Port7, P0_OPTO_AUX_IN1 (DB9: pin4+ and 5-)" M_DEFAULT ARM_EXP_1_TRG_1_AC0_OPTO_CL ARM_EXP_1_TRG_1_AC0_OPTO_CL_AV yes
"Hardware Port8, P0_TTL_AUX_IO_0 (DB9: pin1)" M_DEFAULT ARM_EXP_1_TRG_0_AC0_TTL_CL ARM_EXP_1_TRG_0_AC0_TTL_CL_AV yes
"Hardware Port9, P0_TTL_AUX_IO_1 (HD44: pin13)" M_DEFAULT ARM_EXP_1_TRG_1_AC0_TTL_CL ARM_EXP_1_TRG_1_AC0_TTL_CL_AV yes
"Hardware Port8, P1_TTL_AUX_IO_0 (HD44: pin35)" M_DEFAULT ARM_EXP_1_TRG_0_AC1_TTL_CL ARM_EXP_1_TRG_0_AC1_TTL_CL_AV yes
"Hardware Port9, P1_TTL_AUX_IO_1 (HD44: pin1)" M_DEFAULT ARM_EXP_1_TRG_1_AC1_TTL_CL ARM_EXP_1_TRG_1_AC1_TTL_CL_AV yes
"Hardware Port10, P0_LVDS_AUX_IN0 (DB9: pin8+ and 3-)" M_DEFAULT ARM_EXP_1_TRG_0_AC0_LVDS_CL ARM_EXP_1_TRG_0_AC0_LVDS_CL_AV yes
"Hardware Port11, P0_LVDS_AUX_IN1 (HD44: pin37+ and 23-)" M_DEFAULT ARM_EXP_1_TRG_1_AC0_LVDS_CL ARM_EXP_1_TRG_1_AC0_LVDS_CL_AV yes
"Hardware Port0, P0_OPTO_AUX(TRIG)_IN (DB9: pin7+ and 2-)" M_DEFAULT ARM_EXP_1_TRG_1_AC0_OPTO_ANA ARM_EXP_1_TRG_1_AC0_OPTO_ANA_AV yes
"Hardware Port0, P1_OPTO_AUX(TRIG)_IN (DB9: pin4+ and 5-)" M_DEFAULT ARM_EXP_1_TRG_1_AC1_OPTO_ANA ARM_EXP_1_TRG_1_AC1_OPTO_ANA_AV yes
"Hardware Port0, P2_OPTO_AUX(TRIG)_IN (DB9: pin1+ and 6-)" M_DEFAULT ARM_EXP_1_TRG_1_AC2_OPTO_ANA ARM_EXP_1_TRG_1_AC2_OPTO_ANA_AV yes
"Hardware Port0, P3_OPTO_AUX(TRIG)_IN (DB9: pin8+ and 3-)" M_DEFAULT ARM_EXP_1_TRG_1_AC3_OPTO_ANA ARM_EXP_1_TRG_1_AC3_OPTO_ANA_AV yes
"Hardware Port1, P0_TTL_AUX(TRIG)_IN (DVI 0: pin14)" M_DEFAULT ARM_EXP_1_TRG_0_AC0_TTL_ANA ARM_EXP_1_TRG_0_AC0_TTL_ANA_AV yes
"Hardware Port1, P1_TTL_AUX(TRIG)_IN (DVI 0: pin22)" M_DEFAULT ARM_EXP_1_TRG_0_AC1_TTL_ANA ARM_EXP_1_TRG_0_AC1_TTL_ANA_AV yes
"Hardware Port1, P2_TTL_AUX(TRIG)_IN (DVI 1: pin14)" M_DEFAULT ARM_EXP_1_TRG_0_AC2_TTL_ANA ARM_EXP_1_TRG_0_AC2_TTL_ANA_AV yes
"Hardware Port1, P3_TTL_AUX(TRIG)_IN (DVI 1: pin22)" M_DEFAULT ARM_EXP_1_TRG_0_AC3_TTL_ANA ARM_EXP_1_TRG_0_AC3_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0+ (HD44: pin35) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1+ (HD44: pin12) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2+ (HD44: pin8 ) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3+ (HD44: pin39) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4+ (HD44: pin7 ) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5+ (HD44: pin6 ) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6+ (HD44: pin32) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7+ (HD44: pin1 ) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA_AV yes
"Hardware Port2, LVDS/TTL_AUX_IN0 (HD44: pin35+ and 34-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA_AV yes
"Hardware Port3, LVDS/TTL_AUX_IN1 (HD44: pin12+ and 28-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA_AV yes
"Hardware Port4, LVDS/TTL_AUX_IN2 (HD44: pin8+ and 24-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA_AV yes
"Hardware Port5, LVDS/TTL_AUX_IN3 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA_AV yes
"Hardware Port6, LVDS/TTL_AUX_IN4 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA_AV yes
"Hardware Port7, LVDS/TTL_AUX_IN5 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA_AV yes
"Hardware Port8, LVDS/TTL_AUX_IN6 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA_AV yes
"Hardware Port9, LVDS/TTL_AUX_IN7 (HD44: pin1+ and 16-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA_AV yes
"Hardware Port2, P0_OPTO_AUX(TRIG)_IN_0 (HD44: pin2+ and 17-)" M_DEFAULT ARM_EXP_1_TRG_0_AC0_OPTO_DIG ARM_EXP_1_TRG_0_AC0_OPTO_DIG_AV yes
"Hardware Port3, P0_OPTO_AUX(TRIG)_IN_1 (DB9 : pin7+ and 2-)" M_DEFAULT ARM_EXP_1_TRG_1_AC0_OPTO_DIG ARM_EXP_1_TRG_1_AC0_OPTO_DIG_AV yes
"Hardware Port2, P1_OPTO_AUX(TRIG)_IN_0 (HD44: pin12+ and 28-) " M_DEFAULT ARM_EXP_1_TRG_0_AC1_OPTO_DIG ARM_EXP_1_TRG_0_AC1_OPTO_DIG_AV yes
"Hardware Port3, P1_OPTO_AUX(TRIG)_IN_1 (DB9 : pin4+ and 5-) " M_DEFAULT ARM_EXP_1_TRG_1_AC1_OPTO_DIG ARM_EXP_1_TRG_1_AC1_OPTO_DIG_AV yes
"Hardware Port2, P2_OPTO_AUX(TRIG)_IN_0 (HD44: pin13+ and 14-) " M_DEFAULT ARM_EXP_1_TRG_0_AC2_OPTO_DIG ARM_EXP_1_TRG_0_AC2_OPTO_DIG_AV yes
"Hardware Port3, P2_OPTO_AUX(TRIG)_IN_1 (DB9 : pin1+ and 6-) " M_DEFAULT ARM_EXP_1_TRG_1_AC2_OPTO_DIG ARM_EXP_1_TRG_1_AC2_OPTO_DIG_AV yes
"Hardware Port2, P3_OPTO_AUX(TRIG)_IN_0 (HD44: pin23+ and 37-) " M_DEFAULT ARM_EXP_1_TRG_0_AC3_OPTO_DIG ARM_EXP_1_TRG_0_AC3_OPTO_DIG_AV yes
"Hardware Port3, P3_OPTO_AUX(TRIG)_IN_1 (DB9 : pin8+ and 3-) " M_DEFAULT ARM_EXP_1_TRG_1_AC3_OPTO_DIG ARM_EXP_1_TRG_1_AC3_OPTO_DIG_AV yes
"Hardware Port0, P0_TTL_AUX(TRIG)_IO (CON0: pin49)" M_DEFAULT ARM_EXP_1_TRG_1_AC0_TTL_DIG ARM_EXP_1_TRG_1_AC0_TTL_DIG_AV yes
"Hardware Port0, P1_TTL_AUX(TRIG)_IO (CON0: pin99)" M_DEFAULT ARM_EXP_1_TRG_1_AC1_TTL_DIG ARM_EXP_1_TRG_1_AC1_TTL_DIG_AV yes
"Hardware Port0, P2_TTL_AUX(TRIG)_IO (CON1: pin49)" M_DEFAULT ARM_EXP_1_TRG_1_AC2_TTL_DIG ARM_EXP_1_TRG_1_AC2_TTL_DIG_AV yes
"Hardware Port0, P3_TTL_AUX(TRIG)_IO (CON1: pin99)" M_DEFAULT ARM_EXP_1_TRG_1_AC3_TTL_DIG ARM_EXP_1_TRG_1_AC3_TTL_DIG_AV yes
"Hardware Port1, P0_LVDS_AUX(VSYNC)_IN (CON0: pin35+ and 36-) " M_DEFAULT ARM_EXP_1_TRG_0_AC0_LVDS_DIG ARM_EXP_1_TRG_0_AC0_LVDS_DIG_AV yes
"Hardware Port1, P1_LVDS_AUX(VSYNC)_IN (CON0: pin85+ and 86-) " M_DEFAULT ARM_EXP_1_TRG_0_AC1_LVDS_DIG ARM_EXP_1_TRG_0_AC1_LVDS_DIG_AV yes
"Hardware Port1, P2_LVDS_AUX(VSYNC)_IN (CON1: pin35+ and 36-) " M_DEFAULT ARM_EXP_1_TRG_0_AC2_LVDS_DIG ARM_EXP_1_TRG_0_AC2_LVDS_DIG_AV yes
"Hardware Port1, P3_LVDS_AUX(VSYNC)_IN (CON1: pin85+ and 86-) " M_DEFAULT ARM_EXP_1_TRG_0_AC3_LVDS_DIG ARM_EXP_1_TRG_0_AC3_LVDS_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG_AV yes
"Hardware Port4, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin20+ and 4-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG_AV yes
"Hardware Port5, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin6+ and 5-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG_AV yes
"Hardware Port6, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin7+ and 22-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG_AV yes
"Hardware Port7, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin15+ and 30-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG_AV yes
"Hardware Port8, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin44+ and 29-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG_AV yes
"Hardware Port9, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin32+ and 31-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG_AV yes
"Hardware Port10, LVDS/TTL_AUX(TRIG)_IN_1 (HD44: pin39+ and 38-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG_AV yes
"Hardware Port11, LVDS/TTL_AUX(TRIG)_IN_2 (HD44: pin43+ and 42-) [Common Trigger]" M_DEFAULT ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG_AV yes
"Rotary Encoder Trigger, P0_LVDS_AUX_IN0-1 (DB9: pin8+ and 3-) & (HD44: pin37+ and 23-)" M_DEFAULT ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS_AUX_IN0-1 (HD44: pin32+ and 31-) & (HD44: pin12+ and 28-)" M_DEFAULT ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN0-1 (HD44: pin35+ and 34-) & (HD44: pin12+ and 28-)" M_DEFAULT ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN2-3 (HD44: pin8+ and 24-) & (HD44: pin39+ and 38-)" M_DEFAULT ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN4-5 (HD44: pin7+ and 22-) & (HD44: pin6+ and 5-)" M_DEFAULT ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX_IN6-7 (HD44: pin32+ and 31-) & (HD44: pin1+ and 16-)" M_DEFAULT ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN0-1 (HD44: pin20+ and 4-) & (HD44: pin6+ and 5-)" M_DEFAULT ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN2-3 (HD44: pin7+ and 22-) & (HD44: pin15+ and 30-)" M_DEFAULT ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN4-5 (HD44: pin44+ and 29-) & (HD44: pin32+ and 31-)" M_DEFAULT ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV yes
"Rotary Encoder Trigger, LVDS/TTL_AUX(TRIG)_IN6-7 (HD44: pin39+ and 38-) & (HD44: pin43+ and 42-)" M_DEFAULT ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV yes
"OLD Rotary Encoder" M_DEFAULT ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER_AV no
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_ARM_FORMAT_2
//
enable = ENABLE[( DEF_TIMER1_ENABLED * EXP_ARM_ENABLE_2 )] ;
//
pagelinks = (
(
( ! EXP_ARM_TTL_2 ) * ( ! EXP_ARM_422_2 ) * ( ! EXP_ARM_OPTO_2 ) * ( ! EXP_ARM_LVDS_2 ) *
( ! EXP_ARM_DEFAULT_2 )
) ? ( EXP_ARM_TTL_2.SETVALUE[1] + ARM_EXP_1_CNTEQ0.SETVALUE[1] ) : 0
) ;
//
eo_param
// --------------------------------------
//
GEXP_ARM_POLARITY_2
//
enable = ENABLE[( DEF_TIMER1_ENABLED * EXP_ARM_ENABLE_2 )] ;
//
pagelinks = (
( ( ! EXP_ARM_POS_2 ) * ( ! EXP_ARM_NEG_2 ) ) ? ( EXP_ARM_POS_2.SETVALUE[1] + ARM_EXP_1_CNTEQ0.SETVALUE[1] ) : 0
) ;
//
eo_param
// --------------------------------------
//
GEXP_COMBINE_2 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Exposure Signal / Timer 2 Advanced
Timer Output Signal
eo_param_info
//
enable = ENABLE[( DEF_TIMER1_ENABLED )] ;
//
pagelinks = GEXP_GEN_MODE.VALID ;
//
board_specific_value
"Timer 2" M_DEFAULT DUMMY_PAR NO_BOPTION yes
"Timer 2 XOR Timer 1" M_DEFAULT EXP_COMBINE_2_XOR_T0 M_DEFAULT yes
"Timer 2 XOR Timer 2 of AP1" M_DEFAULT EXP_COMBINE_2_XOR_T1AC1 M_DEFAULT yes
"Timer 1" M_DEFAULT EXP_COMBINE_2_T0 M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GEXP_PRESCALE2 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Exposure Signal / Timer 2 Advanced
Capture a Trigger Every
eo_param_info
//
enable = ENABLE[( DEF_TIMER1_ENABLED )] ;
//
board_specific_value
1 M_DEFAULT EXP_PRESCALE2_1 M_DEFAULT yes
2 M_DEFAULT EXP_PRESCALE2_2 M_DEFAULT yes
4 M_DEFAULT EXP_PRESCALE2_4 M_DEFAULT yes
8 M_DEFAULT EXP_PRESCALE2_8 M_DEFAULT yes
16 M_DEFAULT EXP_PRESCALE2_16 M_DEFAULT yes
eo_board_specific_value
//
eo_param
// --------------------------------------
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #3: COMPATIBILITY WITH OTHERS PRODUCTS
// **********************************************
// **********************************************
//
//
[COMPATIBILITY]
//
// =============================================
//
// ****************
// ALL Boards Olds & News
// ****************
//
//
VDC_DIGITIZER
filter = ( ( DAT_VALUE_READ != 0 ) ? VDC_DIGITIZER.SETVALUE[0] : 0 ) ;
//
VDC_PSG_MODE_1_CHECK
filter = (
(
( DAT_VALUE_READ == 0 ) *
(
( ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_0 * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_1 * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_2 * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_3 * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) )
)
) ? VDC_PSG_MODE_1_CHECK.SETVALUE[1] : 0
) ;
//
VDC_PSG_MODE_2_CHECKS
filter = (
(
( DAT_VALUE_READ == 0 ) *
(
( VDC_USE_PSG_0 * VDC_USE_PSG_1 * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) |
( VDC_USE_PSG_2 * VDC_USE_PSG_3 * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) )
)
) ? VDC_PSG_MODE_2_CHECKS.SETVALUE[1] : 0
) ;
//
VDC_PSG_MODE_3_CHECKS
filter = (
( ( DAT_VALUE_READ == 0 ) * VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * ( ! VDC_USE_PSG_3 ) )
? VDC_PSG_MODE_3_CHECKS.SETVALUE[1] : 0
) ;
// ( ( ( DAT_VALUE_READ == 1 ) * OPTION_SOLIOS_DUAL_ANA )
// ? VDT_DCF_INCOMPATIBLE.SETVALUE[1] : 0 )
//
VDC_PSG_MODE_4_CHECKS
filter = (
( ( DAT_VALUE_READ == 0 ) * VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * VDC_USE_PSG_3 )
? VDC_PSG_MODE_4_CHECKS.SETVALUE[1] : 0
) ;
//
VDC_IN_CH0
filter = (
( DAT_VALUE_READ * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) ?
( VDC_USE_PSG_0.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] +
VDC_IN_CH3.SETVALUE[0] + VDC_PSG_MODE_1_CHECK.SETVALUE[1] ) : 0
) ;
//
VDC_IN_CH1
filter = (
(
DAT_VALUE_READ * (
VDC_ANA | DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
( CLC_MODE_CH0 == 0 )
)
)
? ( VDC_USE_PSG_1.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) : 0
) ;
//
VDC_IN_CH2
filter = (
(
DAT_VALUE_READ * ( VDC_ANA | ( CLC_MODE_CH0 == 0 ) )
)
? ( VDC_USE_PSG_2.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) : 0
) ;
//
VDC_IN_CH3
filter = (
(
DAT_VALUE_READ * ( VDC_ANA | ( CLC_MODE_CH0 == 0 ) )
)
? ( VDC_USE_PSG_3.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) : 0
) ;
//
VDC_USE_PSG_0
filter = (
(
DAT_VALUE_READ * VDC_MONO * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) *
( ! VDC_USE_PSG_3 ) * ( VDC_PSG_MODE_1_CHECK == 0 )
) ? (
VDC_PSG_MODE_1_CHECK.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] +
VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0]
) :
( (
( DAT_VALUE_READ == 0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 )
) ? (
VDC_USE_PSG_0.SETVALUE[1] + VDC_PSG_MODE_1_CHECK.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] +
VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0]
) : 0 )
) ;
//
VDC_USE_PSG_1
filter = (
( DAT_VALUE_READ * ( DEF_ODYSSEY_CL | DEF_HELIOS_CL | DEF_SOLIOS_CL ) )
? (
VDC_USE_PSG_1.SETVALUE[0] + VDC_USE_PSG_0.SETVALUE[1] + VDC_IN_CH0.SETVALUE[0] +
VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0]
) : 0
) ;
//
VDC_422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
CAMERA_LINK_AV ? ( VDC_422.SETVALUE[0] + VDC_LVDS.SETVALUE[1] ) :
( ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) ) ? ( VDC_422.SETVALUE[0] + VDC_LVDS.SETVALUE[1] ) : 0 )
) : 0
) ;
//
VDT_USE_HLOCK
filter = ( ( DAT_VALUE_READ == 1 ) ? VDT_USE_HLOCK.SETVALUE[0] : 0 ) ;
//
VDT_USE_VLOCK
filter = ( ( DAT_VALUE_READ == 1 ) ? VDT_USE_VLOCK.SETVALUE[0] : 0 ) ;
//
PCK_OTH_REC
filter = ( ( DAT_VALUE_READ * PCK_USE_OUT ) ?
( PCK_CAM_GEN.SETVALUE[0] + PCK_CAM_REC.SETVALUE[1] + PCK_CAM_R&G.SETVALUE[0] +
PCK_OTH_REC.SETVALUE[0] + PCK_CAM_XCHG.SETVALUE[1]
) : 0
) ;
//
PCK_IDELAY
filter = ( ( DAT_VALUE_READ < 10000 ) ? PCK_IDELAY.SETVALUE[10000] : 0 ) ;
//
PCK_I422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( CAMERA_LINK_AV | VDC_ANA ) ? ( PCK_I422.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
PCK_USER_IN
filter = 0 ;
//
PCK_ITTL
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( CAMERA_LINK_AV | VDC_ANA ) ? ( PCK_ITTL.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] ) :
( ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) ) ? ( PCK_ITTL.SETVALUE[0] + PCK_ILVDS.SETVALUE[1] ) : 0 )
) : 0
) ;
//
PCK_O422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( CAMERA_LINK_AV | VDC_ANA ) ? ( PCK_O422.SETVALUE[0] + PCK_OLVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
PCK_OTTL
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( CAMERA_LINK_AV | VDC_ANA ) ? ( PCK_OTTL.SETVALUE[0] + PCK_OLVDS.SETVALUE[1] ) :
( ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) ) ? ( PCK_OTTL.SETVALUE[0] + PCK_OLVDS.SETVALUE[1] ) : 0 )
) : 0
) ;
//
SYC_BLK
filter = ( DAT_VALUE_READ ? SYC_BLK.SETVALUE[0] : 0 ) ;
//
SYC_H_I422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( ( VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) | VDC_ANA ) ? ( SYC_H_I422.SETVALUE[0] + SYC_H_ILVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
SYC_V_I422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( ( VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) | VDC_ANA ) ? ( SYC_V_I422.SETVALUE[0] + SYC_V_ILVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
SYC_H_ITTL
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? ( SYC_H_ITTL.SETVALUE[0] + SYC_H_ILVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
SYC_V_ITTL
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? ( SYC_V_ITTL.SETVALUE[0] + SYC_V_ILVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
SYC_H_INEG
filter = (
( DAT_VALUE_READ * ( VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) )
? ( SYC_H_INEG.SETVALUE[0] + SYC_H_IPOS.SETVALUE[1] ) : 0
) ;
//
SYC_V_INEG
filter = (
( DAT_VALUE_READ * ( VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) )
? ( SYC_V_INEG.SETVALUE[0] + SYC_V_IPOS.SETVALUE[1] ) : 0
) ;
//
SYC_H_O422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( CAMERA_LINK_AV | VDC_ANA ) ? ( SYC_H_O422.SETVALUE[0] + SYC_H_OLVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
SYC_V_O422
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( CAMERA_LINK_AV | VDC_ANA ) ? ( SYC_V_O422.SETVALUE[0] + SYC_V_OLVDS.SETVALUE[1] ) : 0
) : 0
) ;
//
SYC_H_OTTL
filter = (
( DAT_VALUE_READ * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? ( SYC_H_OTTL.SETVALUE[0] + SYC_H_OLVDS.SETVALUE[1] ) : 0
) ;
//
SYC_V_OTTL
filter = (
( DAT_VALUE_READ * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? ( SYC_V_OTTL.SETVALUE[0] + SYC_V_OLVDS.SETVALUE[1] ) : 0
) ;
//
EXP_TRG_422
filter = (
( ( DAT_VALUE_READ == 1 ) * ( CAMERA_LINK_AV | VDC_ANA ) ) ? ( EXP_TRG_422.SETVALUE[0] + EXP_TRG_LVDS.SETVALUE[1] ) : 0
) ;
//
EXP_OUT_422
filter = (
( ( DAT_VALUE_READ == 1 ) * ( CAMERA_LINK_AV | VDC_ANA ) ) ? ( EXP_OUT_422.SETVALUE[0] + EXP_OUT_LVDS.SETVALUE[1] ) : 0
) ;
//
EXP_TRG_422_2
filter = (
( ( DAT_VALUE_READ == 1 ) * ( CAMERA_LINK_AV | VDC_ANA ) ) ? ( EXP_TRG_422_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[1] ) : 0
) ;
//
EXP_OUT_422_2
filter = (
( ( DAT_VALUE_READ == 1 ) * ( CAMERA_LINK_AV | VDC_ANA ) ) ? ( EXP_OUT_422_2.SETVALUE[0] + EXP_OUT_LVDS_2.SETVALUE[1] ) : 0
) ;
//
GRB_TRG_422
filter = (
( ( DAT_VALUE_READ == 1 ) * ( CAMERA_LINK_AV | VDC_ANA ) ) ? ( GRB_TRG_422.SETVALUE[0] + GRB_TRG_LVDS.SETVALUE[1] ) : 0
) ;
//
GEN_SAVED_W_ERR
filter = (
( DAT_VALUE_READ == 1 ) ?
(
( GRB_MD_CONT * ( EXP_MD_EXT | EXP_MD_EXT_2 ) ) ? ( EXP_MD_EXT.SETVALUE[0] + EXP_MD_EXT_2.SETVALUE[0] ) :
( (
CAMERA_LINK_AV * ( CLC_MODE_CH0 == 1 ) * VDC_MONO *
( ! (
( ( EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW ) * ( ! EXP_MD_PERD ) * ( ! EXP_MD_W_TRG ) ) |
( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 ) * ( ! EXP_MD_PERD_2 ) * ( ! EXP_MD_W_TRG_2 ) )
)
)
) ?
( CT_CAMERA.SETVALUE[0] + CT_TAPS.SETVALUE[0] + GEN_SAVED_W_ERR.SETVALUE[0] ) :
( (
CAMERA_LINK_AV * VDC_MONO *
(
( CLC_MODE_CH0 == 2 ) | ( CLC_MODE_CH0 == 3 ) | ( CLC_MODE_CH0 == 4 ) | ( CLC_MODE_CH0 == 9 )
) *
( ! (
( ( EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW ) * ( ! EXP_MD_PERD ) * ( ! EXP_MD_W_TRG ) ) |
( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 ) * ( ! EXP_MD_PERD_2 ) * ( ! EXP_MD_W_TRG_2 ) )
)
)
) ?
( CT_CAMERA.SETVALUE[0] + CT_TAPS.SETVALUE[1] + GEN_SAVED_W_ERR.SETVALUE[0] ) :
( (
CAMERA_LINK_AV * VDC_MONO *
(
( CLC_MODE_CH0 == 7 ) | ( CLC_MODE_CH0 == 8 ) | ( CLC_MODE_CH0 == 12 ) | ( CLC_MODE_CH0 == 13 )
) *
( ! (
( ( EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW ) * ( ! EXP_MD_PERD ) * ( ! EXP_MD_W_TRG ) ) |
( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 ) * ( ! EXP_MD_PERD_2 ) * ( ! EXP_MD_W_TRG_2 ) )
)
)
) ?
( CT_CAMERA.SETVALUE[0] + CT_TAPS.SETVALUE[2] + GEN_SAVED_W_ERR.SETVALUE[0] ) :
( (
CAMERA_LINK_AV * VDC_MONO *
( ( CLC_MODE_CH0 == 15 ) | ( CLC_MODE_CH0 == 16 ) ) *
( ! (
( ( EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW ) * ( ! EXP_MD_PERD ) * ( ! EXP_MD_W_TRG ) ) |
( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 ) * ( ! EXP_MD_PERD_2 ) * ( ! EXP_MD_W_TRG_2 ) )
)
)
) ?
( CT_CAMERA.SETVALUE[0] + CT_TAPS.SETVALUE[3] + GEN_SAVED_W_ERR.SETVALUE[0] ) :
( (
( ( EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW ) * ( ! EXP_MD_PERD ) * ( ! EXP_MD_W_TRG ) ) |
( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 ) * ( ! EXP_MD_PERD_2 ) * ( ! EXP_MD_W_TRG_2 ) )
) ?
( EXP_MD_HSY.SETVALUE[0] + EXP_MD_VSY.SETVALUE[0] + EXP_MD_SW.SETVALUE[0] +
EXP_MD_HSY_2.SETVALUE[0] + EXP_MD_VSY_2.SETVALUE[0] + EXP_MD_SW_2.SETVALUE[0] + GEN_SAVED_W_ERR.SETVALUE[0]
) :
( ( CAMERA_LINK_AV * CT_LS * GRB_LS_FREE_RUN * ( GRB_LS_FIXED_LINE | GRB_LS_VARIABLE_LINE ) ) ?
(
GRB_LS_FREE_RUN.SETVALUE[1] + GRB_LS_FIXED_LINE.SETVALUE[0] + GRB_LS_VARIABLE_LINE.SETVALUE[0] +
GEN_SAVED_W_ERR.SETVALUE[0]
) :
( ( ( VDC_USE_PSG_0 == 0 ) * ( VDC_USE_PSG_1 == 0 ) * ( VDC_USE_PSG_2 == 0 ) * ( VDC_USE_PSG_3 == 0 ) ) ?
VDC_USE_PSG_0.SETVALUE[1] : 0 ) ) ) ) ) ) )
) : 0
) ;
//
//
//
//
// ****************
// OLD Boards PULSAR/GENESIS/CORONA/METEORII_MC/CL
// ****************
//
//
CLC_MODE_CH0
filter = (
( ( DAT_VALUE_READ == 4 ) * CAMERA_LINK_AV * ( CLC_MODE == 0 ) * VDC_RGB_COL ) ?
( CT_CAMERA.SETVALUE[0] + CT_TAPS.SETVALUE[0] + CLC_MODE_CH0.SETVALUE[5] + GEN_SAVED_W_ERR.SETVALUE[0] ) : 0
) ;
//
VDT_CL_USE_CAMERA_VALID
filter = (
( ( DAT_VALUE_READ == 0 ) * CT_FS * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[0] :
( ( ( DAT_VALUE_READ == 1 ) * CT_FS * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[1] :
( ( ( DAT_VALUE_READ == 2 ) * CT_FS * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[2] :
( ( ( DAT_VALUE_READ == 0 ) * CT_LS * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[3] :
( ( ( DAT_VALUE_READ == 1 ) * CT_LS * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[4] :
( ( ( DAT_VALUE_READ == 2 ) * CT_LS * VDC_DIG * ( CLC_MODE_CH0 > 0 ) ) ? VDT_CL_USE_CAMERA_VALID.SETVALUE[5] :
0 ) ) ) ) )
) ;
//
CT_TAPS
filter = (
( DAT_VALUE_READ == 0 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[1]
) : 0
) ;
//
TAP_CONFIG
filter = (
( DAT_VALUE_READ == 0x81 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[2]
) :
( ( DAT_VALUE_READ == 3 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[2] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 15 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[4] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 17 ) ?
(
TAP_REGIONSX.SETVALUE[2] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 51 ) ?
(
TAP_REGIONSX.SETVALUE[2] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[2] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 85 ) ?
(
TAP_REGIONSX.SETVALUE[4] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 129 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[2]
) :
( ( DAT_VALUE_READ == 897 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[1] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[4]
) :
( ( DAT_VALUE_READ == 1025 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[2] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 3075 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[2] + TAP_PIXADJX.SETVALUE[2] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 5137 ) ?
(
TAP_REGIONSX.SETVALUE[2] + TAP_REGIONSY.SETVALUE[2] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[1]
) :
( ( DAT_VALUE_READ == 9473 ) ?
(
TAP_REGIONSX.SETVALUE[1] + TAP_REGIONSY.SETVALUE[4] + TAP_PIXADJX.SETVALUE[1] + TAP_PIXADJY.SETVALUE[1]
) : 1 ) ) ) ) ) ) ) ) ) ) )
) ;
//
TAP_ORDERS
filter = ( ( DAT_VALUE_READ == 0 ) ? TAP_ORDERS.SETVALUE[0x343efcea] : 0 ) ;
//
TAP_REGIONSX
filter = ( ( DAT_VALUE_READ == 0 ) ? TAP_REGIONSX.SETVALUE[1] : 0 ) ;
//
TAP_REGIONSY
filter = ( ( DAT_VALUE_READ == 0 ) ? TAP_REGIONSY.SETVALUE[1] : 0 ) ;
//
TAP_PIXADJX
filter = ( ( DAT_VALUE_READ == 0 ) ? TAP_PIXADJX.SETVALUE[1] : 0 ) ;
//
TAP_PIXADJY
filter = ( ( DAT_VALUE_READ == 0 ) ? TAP_PIXADJY.SETVALUE[1] : 0 ) ;
//
TAP_MULTIPLEX_X
filter = (
( DAT_VALUE_READ == 0 ) ? TAP_MULTIPLEX_X.SETVALUE[1] : 1
) ;
//
TAP_MULTIPLEX_Y
filter = (
( DAT_VALUE_READ == 0 ) ? TAP_MULTIPLEX_Y.SETVALUE[1] : 1
) ;
//
GRB_RGB_PATH_FORCED
filter = 0 ;
//
GRB_TRG_DPORT
filter = (
( DAT_VALUE_READ * GRB_MD_HW_TRG * VDC_ANA ) ?
( GRB_TRG_0_AC0_TTL_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * GRB_MD_HW_TRG * CAMERA_LINK_AV ) ?
( GRB_TRG_0_AC0_TTL_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) : 0 )
) ;
//
GRB_TRG_SIGNAL_DPORT
filter = (
( DAT_VALUE_READ * GRB_MD_HW_TRG * VDC_ANA ) ?
( GRB_TRG_0_AC0_TTL_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * GRB_MD_HW_TRG * CAMERA_LINK_AV ) ?
( GRB_TRG_0_AC0_TTL_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) : 0 )
) ;
//
GRB_TRG_APORT
filter = (
( DAT_VALUE_READ * GRB_MD_HW_TRG * VDC_ANA ) ?
( GRB_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * GRB_MD_HW_TRG * CAMERA_LINK_AV ) ?
( GRB_TRG_0_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) : 0 )
) ;
//
GRB_TRG_SIGNAL_APORT
filter = (
( DAT_VALUE_READ * GRB_MD_HW_TRG * VDC_ANA ) ?
( GRB_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * GRB_MD_HW_TRG * CAMERA_LINK_AV ) ?
( GRB_TRG_0_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] + GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0] ) : 0 )
) ;
//
GRB_TRG_SIGNAL_TIMER1
filter = (
( DAT_VALUE_READ * GRB_MD_HW_TRG * CAMERA_LINK_AV * ( ! CLB_CCOUTEN1 ) ) ?
(
GRB_TRG_TIMER0.SETVALUE[1] + CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] +
CLB_CC2.SETVALUE[3] + CLB_CC3.SETVALUE[3] + CLB_CC4.SETVALUE[5]
) :
( ( DAT_VALUE_READ * GRB_MD_HW_TRG * ( ! CAMERA_LINK_AV ) ) ? GRB_TRG_TIMER0.SETVALUE[1] : 0 )
) ;
//
GRB_TRG_SIGNAL_TIMER2
filter = (
( DAT_VALUE_READ * GRB_MD_HW_TRG * CAMERA_LINK_AV * ( ! CLB_CCOUTEN1 ) ) ?
(
GRB_TRG_TIMER1.SETVALUE[1] + CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] +
CLB_CC2.SETVALUE[3] + CLB_CC3.SETVALUE[3] + CLB_CC4.SETVALUE[5]
) :
( ( DAT_VALUE_READ * GRB_MD_HW_TRG * ( ! CAMERA_LINK_AV ) ) ? GRB_TRG_TIMER1.SETVALUE[1] : 0 )
) ;
//
GRAB_ACT_LS_FIXED_LINE
filter = ( DAT_VALUE_READ ? GRB_LS_FIXED_LINE.SETVALUE[1] ) ;
//
GRAB_ACT_LS_VARIABLE_LINE
filter = ( DAT_VALUE_READ ? GRB_LS_VARIABLE_LINE.SETVALUE[1] ) ;
//
GRAB_ACT_LS_FRMFIX_LINEFIX
filter = ( DAT_VALUE_READ ? GRB_LS_FRMFIX_LINEFIX.SETVALUE[1] ) ;
//
GRAB_ACT_LS_FRMVAR_LINEFIX
filter = ( DAT_VALUE_READ ? GRB_LS_FRMVAR_LINEFIX.SETVALUE[1] ) ;
//
GRAB_ACT_LS_FRMFIX_LINEVAR
filter = ( DAT_VALUE_READ ? GRB_LS_FRMFIX_LINEVAR.SETVALUE[1] ) ;
//
GRAB_ACT_LS_FRMVAR_LINEVAR
filter = ( DAT_VALUE_READ ? GRB_LS_FRMVAR_LINEVAR.SETVALUE[1] ) ;
//
GRB_LS_FREE_RUN
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * ( ! EXP_MD_PERD ) * ( ! EXP_MD_W_TRG ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
GRB_LS_FIXED_LINE
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * EXP_MD_PERD ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * EXP_MD_PERD_2 * ( ! EXP_MD_PERD ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
GRB_LS_VARIABLE_LINE
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * EXP_MD_W_TRG ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * EXP_MD_W_TRG_2 * ( ! EXP_MD_W_TRG ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
GRB_LS_FRMFIX_LINEFIX
filter = (
( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_PERD ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_PERD_2 * ( ! EXP_MD_PERD ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
GRB_LS_FRMFIX_LINEVAR
filter = (
( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_W_TRG ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_W_TRG_2 * ( ! EXP_MD_W_TRG ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
GRB_LS_FRMVAR_LINEFIX
filter = (
( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_PERD ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_PERD_2 * ( ! EXP_MD_PERD ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
GRB_LS_FRMVAR_LINEVAR
filter = (
( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_W_TRG ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + ARM_EXP_0_SOFTWARE.SETVALUE[0] + ARM_EXP_0_CNTEQ0.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( ! GRB_MD_CONT ) * CAMERA_LINK_AV * CT_LS * ( ! CLB_CCOUTEN1 ) * ( ! GRB_MD_CONT ) * EXP_MD_W_TRG_2 * ( ! EXP_MD_W_TRG ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + ARM_EXP_1_SOFTWARE.SETVALUE[0] + ARM_EXP_1_CNTEQ0.SETVALUE[1]
) : 0 )
) ;
//
EXP_ASY_CLK
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? ( EXP_CLK_CLKGEN.SETVALUE[1] + EXP_ASY_CLK.SETVALUE[0] ) : 0 ) ;
//
EXP_CLOCK_HSYNC
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_CLK_HS.SETVALUE[1] : 0 ) ;
//
EXP_CLOCK_VSYNC
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_CLK_VS.SETVALUE[1] : 0 ) ;
//
EXP_CLOCK_CRYSTAL
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_CLK_CLKGEN.SETVALUE[1] : 0 ) ;
//
EXP_ASY_CLK_2
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? ( EXP_CLK_2_CLKGEN.SETVALUE[1] + EXP_ASY_CLK_2.SETVALUE[0] ) : 0 ) ;
//
EXP_CLOCK_2_HSYNC
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_CLK_2_HS.SETVALUE[1] : 0 ) ;
//
EXP_CLOCK_2_VSYNC
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_CLK_2_VS.SETVALUE[1] : 0 ) ;
//
EXP_CLOCK_2_CRYSTAL
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_CLK_2_CLKGEN.SETVALUE[1] : 0 ) ;
//
EXP_CLK_AUXIN1_LVDS
filter = (
( DAT_VALUE_READ * VDC_ANA ) ?
( EXP_CLK_AUXIN1_AC0_ANA.SETVALUE[1] + EXP_CLK_AUXIN1_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( CLC_MODE_CH0 > 0 ) ) ?
( EXP_CLK_AUXIN1_AC0_CL.SETVALUE[1] + EXP_CLK_AUXIN1_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_CLK_AUXIN2_AC0_DIG.SETVALUE[1] + EXP_CLK_AUXIN1_LVDS.SETVALUE[0] ) : 0 ) )
) ;
//
EXP_CLK_AUXIN3_LVDS
filter = (
( DAT_VALUE_READ * VDC_ANA ) ?
( EXP_CLK_AUXIN3_AC1_ANA.SETVALUE[1] + EXP_CLK_AUXIN3_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( CLC_MODE_CH0 > 0 ) ) ?
( EXP_CLK_AUXIN3_AC1_CL.SETVALUE[1] + EXP_CLK_AUXIN3_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_CLK_AUXIN2_AC1_DIG.SETVALUE[1] + EXP_CLK_AUXIN3_LVDS.SETVALUE[0] ) : 0 ) )
) ;
//
EXP_CLK_2_AUXIN1_LVDS
filter = (
( DAT_VALUE_READ * VDC_ANA ) ?
( EXP_CLK_2_AUXIN1_AC0_ANA.SETVALUE[1] + EXP_CLK_2_AUXIN1_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( CLC_MODE_CH0 > 0 ) ) ?
( EXP_CLK_2_AUXIN1_AC0_CL.SETVALUE[1] + EXP_CLK_2_AUXIN1_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_CLK_2_AUXIN2_AC0_DIG.SETVALUE[1] + EXP_CLK_2_AUXIN1_LVDS.SETVALUE[0] ) : 0 ) )
) ;
//
EXP_CLK_2_AUXIN3_LVDS
filter = (
( DAT_VALUE_READ * VDC_ANA ) ?
( EXP_CLK_2_AUXIN3_AC1_ANA.SETVALUE[1] + EXP_CLK_2_AUXIN3_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( CLC_MODE_CH0 > 0 ) ) ?
( EXP_CLK_2_AUXIN3_AC1_CL.SETVALUE[1] + EXP_CLK_2_AUXIN3_LVDS.SETVALUE[0] ) :
( ( DAT_VALUE_READ * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_CLK_2_AUXIN2_AC1_DIG.SETVALUE[1] + EXP_CLK_2_AUXIN3_LVDS.SETVALUE[0] ) : 0 ) )
) ;
//
EXP_TRG_SIGNAL_DPORT
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA ) ?
( EXP_0_TRG_0_AC0_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * CAMERA_LINK_AV * EXP_TRG_TTL ) ?
( EXP_0_TRG_0_AC0_TTL_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * CAMERA_LINK_AV * EXP_TRG_422 ) ?
( EXP_0_TRG_0_AC0_LVDS_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[0] + EXP_TRG_LVDS.SETVALUE[1] + EXP_TRG_422.SETVALUE[0] ) : 0 ) )
) ;
//
EXP_TRG_TTL_TIMER1
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_IN_CH0 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_0_AC0_TTL_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_IN_CH1 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_0_AC1_TTL_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA * VDC_IN_CH0 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_0_AC0_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA * ( VDC_IN_CH1 | VDC_USE_PSG_1 ) ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_0_AC1_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA * VDC_IN_CH2 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_0_AC2_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA * VDC_IN_CH3 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_0_AC3_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH0 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_1_AC0_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH1 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_1_AC1_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH2 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_1_AC2_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH3 ) ?
(
EXP_TRG_TTL_TIMER1.SETVALUE[0] + EXP_0_TRG_1_AC3_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0 ) ) ) ) ) ) ) ) )
) ;
//
EXP_TRG_SIGNAL_APORT
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA ) ?
( EXP_0_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * CAMERA_LINK_AV ) ?
( EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) : 0 )
) ;
//
EXP_MD_EXT
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA ) ?
( EXP_0_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] + EXP_MD_EXT.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * CAMERA_LINK_AV ) ?
( EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] + EXP_MD_EXT.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CAMERA_LINK_AV == 0 ) ) ?
( EXP_0_TRG_1_AC0_OPTO_DIG.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] + EXP_MD_EXT.SETVALUE[0]
) : 0 ) )
) ;
//
EXP_TRG_USER_BIT_TIMER1
filter = 0 ;
//
EXP_TRG_CNTEQ0_TIMER1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( EXP_TRG_CNTEQ0_TIMER0.SETVALUE[DAT_VALUE_READ] + EXP_TRG_OPTO.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) : 0 ) ;
//
EXP_TRG_SIGNAL_TIMER2
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_TRG_TIMER1.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) : 0 ) ;
//
EXP_TRG_SIGNAL_TIMER2_WEN
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_TRG_TIMER1.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] ) : 0 ) ;
//
EXP_TRG_SIGNAL_2_DPORT
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA ) ?
( EXP_1_TRG_0_AC0_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_422_2.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * CAMERA_LINK_AV * EXP_TRG_TTL_2 ) ?
( EXP_1_TRG_0_AC0_TTL_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_422_2.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * CAMERA_LINK_AV * EXP_TRG_422_2 ) ?
( EXP_1_TRG_0_AC0_LVDS_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[1] + EXP_TRG_422_2.SETVALUE[0] ) : 0 ) )
) ;
//
EXP_TRG_TTL_TIMER2
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_IN_CH0 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_0_AC0_TTL_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_IN_CH1 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_0_AC1_TTL_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA * VDC_IN_CH0 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_0_AC0_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA * VDC_IN_CH1 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_0_AC1_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA * VDC_IN_CH2 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_0_AC2_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA * VDC_IN_CH3 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_0_AC3_TTL_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH0 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_1_AC0_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH1 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_1_AC1_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH2 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_1_AC2_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_DIG * ( CLC_MODE_CH0 == 0 ) * VDC_IN_CH3 ) ?
(
EXP_TRG_TTL_TIMER2.SETVALUE[0] + EXP_1_TRG_1_AC3_TTL_DIG.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0 ) ) ) ) ) ) ) ) )
) ;
//
EXP_TRG_SIGNAL_2_APORT
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA ) ?
( EXP_1_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0] ) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * CAMERA_LINK_AV ) ?
( EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0] ) : 0 )
) ;
//
EXP_MD_EXT_2
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA ) ?
( EXP_1_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0] + EXP_MD_EXT_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * CAMERA_LINK_AV ) ?
( EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_LVDS_2.SETVALUE[0] +
EXP_TRG_TTL_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0] + EXP_MD_EXT_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_DIG * ( CAMERA_LINK_AV == 0 ) ) ?
( EXP_1_TRG_1_AC0_OPTO_DIG.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0] + EXP_MD_EXT.SETVALUE[0]
) : 0 ) )
) ;
//
EXP_TRG_SIGNAL_2_TIMER1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_TRG_TIMER0_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_422_2.SETVALUE[0] ) : 0 ) ;
//
EXP_TRG_SIGNAL_2_TIMER1_WEN
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_TRG_TIMER0_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_422_2.SETVALUE[0] ) : 0 ) ;
//
EXP_TRG_USER_BIT_TIMER2
filter = 0 ;
//
EXP_TRG_CNTEQ0_TIMER2
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_TRG_CNTEQ0_TIMER1.SETVALUE[DAT_VALUE_READ] + EXP_TRG_OPTO_2.SETVALUE[0] + EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_422_2.SETVALUE[0] ) : 0 ) ;
//
//
// ****************
// Odyssey OLD Members ONLY!
// ****************
//
//
//
GRB_TRG_LVDS_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_0 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
GRB_TRG_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_0 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( GRB_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
GRB_TRG_0_AC0_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_0_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_0_LVDSOPTO_AC1_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_0_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_0_TTL_AC1_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_0_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_1_AC0_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_2_AC0_CL
filter = 0 ;
//
GRB_TRG_3_AC0_CL
filter = 0 ;
//
GRB_TRG_0_AC1_CL
filter = 0 ;
//
GRB_TRG_1_AC1_CL
filter = 0 ;
//
GRB_TRG_2_AC1_CL
filter = 0 ;
//
GRB_TRG_3_AC1_CL
filter = 0 ;
//
GRB_TRG_1_LVDSOPTO_AC1_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_1_TTL_AC1_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC0_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_2_AC01_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_2_AC01_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_3_LVDSOPTO_AC01_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_3_AC01_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_3_TTL_AC01_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_3_AC01_OPTO_CL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_TTL_AC0_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_TTL_AC1_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC1_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_TTL_AC2_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC2_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_TTL_AC3_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC3_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_OPTO_AC0_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_OPTO_AC1_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC1_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_OPTO_AC2_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC2_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_OPTO_AC3_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_1_AC3_OPTO_ANA.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_0_AC1_OPTO_CL
filter = ( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ? ( GRB_TRG_0_AC1_OPTO_CL.SETVALUE[0] + GRB_TRG_2_AC01_OPTO_CL.SETVALUE[1] ) : 0 ) ;
//
GRB_TRG_1_AC1_OPTO_CL
filter = ( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ? ( GRB_TRG_1_AC1_OPTO_CL.SETVALUE[0] + GRB_TRG_3_AC01_OPTO_CL.SETVALUE[1] ) : 0 ) ;
//
GRB_TRG_0_AC1_LVDS_CL
filter = ( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ? ( GRB_TRG_0_AC1_LVDS_CL.SETVALUE[0] + GRB_TRG_2_AC01_LVDS_CL.SETVALUE[1] ) : 0 ) ;
//
GRB_TRG_1_AC1_LVDS_CL
filter = ( ( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ? ( GRB_TRG_1_AC1_LVDS_CL.SETVALUE[0] + GRB_TRG_3_AC01_LVDS_CL.SETVALUE[1] ) : 0 ) ;
//
GRB_TRG_AUX0_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_2_4AC_AUX0_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX1_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_3_4AC_AUX1_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX2_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_2_4AC_AUX2_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX3_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_3_4AC_AUX3_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX4_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_2_4AC_AUX4_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX5_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_3_4AC_AUX5_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX6_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_2_4AC_AUX6_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_AUX7_ANA
filter = (
( ( DAT_VALUE_READ == 1 ) * GRB_MD_HW_TRG ) ?
(
GRB_TRG_3_4AC_AUX7_TTL_ANA.SETVALUE[1] + GRB_TRG_TTL.SETVALUE[1] + GRB_TRG_OPTO.SETVALUE[0] +
GRB_TRG_LVDS.SETVALUE[0] + GRB_TRG_422.SETVALUE[0]
) : 0
) ;
//
GRB_TRG_CAPTURE_AC1
filter = 0 ;
//
GRB_TRG_CAPTURE_AC2
filter = 0 ;
//
GRB_TRG_CAPTURE_AC3
filter = 0 ;
//
GRB_TRG_USER1_IN
filter = 0 ;
//
GRB_TRG_USER2_IN
filter = 0 ;
//
GRB_TRG_USER3_IN
filter = 0 ;
//
GRB_TRG_USER4_IN
filter = 0 ;
//
GRB_TRG_USR0_ANA
filter = 0 ;
//
GRB_TRG_USR1_ANA
filter = 0 ;
//
GRB_TRG_USR2_ANA
filter = 0 ;
//
GRB_TRG_USR3_ANA
filter = 0 ;
//
GRB_TRG_USR4_ANA
filter = 0 ;
//
GRB_TRG_USR5_ANA
filter = 0 ;
//
GRB_TRG_USR6_ANA
filter = 0 ;
//
GRB_TRG_USR7_ANA
filter = 0 ;
//
GRB_TRG_AC1
filter = 0 ;
//
// ****************
// Timers 0/1 members
//
EXP_ARM_SOURCE
filter = 0 ;
//
EXP_ARM_SOURCE_2
filter = 0 ;
//
ARM_EXP_0_CNTEQ0
filter = (
DAT_VALUE_READ ?
( EXP_ARM_TTL.SETVALUE[1] + EXP_ARM_OPTO.SETVALUE[0] + EXP_ARM_LVDS.SETVALUE[0] +
EXP_ARM_DEFAULT.SETVALUE[0]
) : 0
) ;
//
ARM_EXP_0_SOFTWARE
filter = (
DAT_VALUE_READ ?
( EXP_ARM_TTL.SETVALUE[1] + EXP_ARM_OPTO.SETVALUE[0] + EXP_ARM_LVDS.SETVALUE[0] +
EXP_ARM_DEFAULT.SETVALUE[0]
) : 0
) ;
//
ARM_EXP_0_TIMER1
filter = (
DAT_VALUE_READ ?
( EXP_ARM_TTL.SETVALUE[1] + EXP_ARM_OPTO.SETVALUE[0] + EXP_ARM_LVDS.SETVALUE[0] +
EXP_ARM_DEFAULT.SETVALUE[0]
) : 0
) ;
//
ARM_EXP_1_CNTEQ0
filter = (
DAT_VALUE_READ ?
( EXP_ARM_TTL_2.SETVALUE[1] + EXP_ARM_OPTO_2.SETVALUE[0] + EXP_ARM_LVDS_2.SETVALUE[0] +
EXP_ARM_DEFAULT_2.SETVALUE[0]
) : 0
) ;
//
ARM_EXP_1_SOFTWARE
filter = (
DAT_VALUE_READ ?
( EXP_ARM_TTL_2.SETVALUE[1] + EXP_ARM_OPTO_2.SETVALUE[0] + EXP_ARM_LVDS_2.SETVALUE[0] +
EXP_ARM_DEFAULT_2.SETVALUE[0]
) : 0
) ;
//
ARM_EXP_1_TIMER0
filter = (
DAT_VALUE_READ ?
( EXP_ARM_TTL_2.SETVALUE[1] + EXP_ARM_OPTO_2.SETVALUE[0] + EXP_ARM_LVDS_2.SETVALUE[0] +
EXP_ARM_DEFAULT_2.SETVALUE[0]
) : 0
) ;
//
ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
ARM_EXP_0_TRG_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( ARM_EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
ARM_EXP_1_TRG_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( ARM_EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
EXP_MD_PERD
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV * ( ! CLB_CCOUTEN1 ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( VDC_ANA | ( ! CAMERA_LINK_AV ) ) ) ?
(
EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0]
) : 0 )
) ;
//
EXP_MD_PERD_2
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV * ( ! CLB_CCOUTEN1 ) ) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0]
) :
( ( DAT_VALUE_READ * ( VDC_ANA | ( ! CAMERA_LINK_AV ) ) ) ?
(
EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0]
) : 0 )
) ;
//
EXP_MD_W_TRG
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV *
(
( ( ! OPTION_ODYSSEY_CL_FULL ) * ( ! OPTION_ODYSSEY_CL_DUAL ) * ( ! CLB_CCOUTEN1 ) ) |
( ( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL ) * ( EXP_ARM_POS | EXP_ARM_NEG ) * ( ! CLB_CCOUTEN1 ) )
)
) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] +
EXP_OUT_DLYD.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * ( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL ) *
( EXP_ARM_POS == 0 ) * ( EXP_ARM_NEG == 0 ) * ( ! CLB_CCOUTEN1 )
) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[1] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] +
EXP_ARM_POS.SETVALUE[1] + ARM_EXP_0_TRG_TIMER0_AC0.SETVALUE[0] + ARM_EXP_0_TRG_TIMER0_AC1.SETVALUE[0] +
ARM_EXP_0_TRG_TIMER0_AC2.SETVALUE[0] + ARM_EXP_0_TRG_TIMER0_AC3.SETVALUE[0] +
ARM_EXP_0_CNTEQ0.SETVALUE[1] + EXP_OUT_DLYD.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * ( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL ) *
( EXP_ARM_POS == 0 ) * ( EXP_ARM_NEG == 0 ) * CLB_CCOUTEN1
) ?
(
EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + EXP_ARM_POS.SETVALUE[1] +
ARM_EXP_0_TRG_TIMER0_AC0.SETVALUE[0] + ARM_EXP_0_TRG_TIMER0_AC1.SETVALUE[0] +
ARM_EXP_0_TRG_TIMER0_AC2.SETVALUE[0] + ARM_EXP_0_TRG_TIMER0_AC3.SETVALUE[0] +
ARM_EXP_0_CNTEQ0.SETVALUE[1] + EXP_OUT_DLYD.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( VDC_ANA | ( ! CAMERA_LINK_AV ) ) *
( ! OPTION_ODYSSEY_DIG ) * ( ! OPTION_ODYSSEY_ANA )
) ?
(
EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + EXP_OUT_DLYD.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( VDC_ANA | ( ! CAMERA_LINK_AV ) ) * ( EXP_ARM_POS == 0 ) * ( EXP_ARM_NEG == 0 ) *
( OPTION_ODYSSEY_DIG | OPTION_ODYSSEY_ANA )
) ?
(
EXP_ARM_ENABLE.SETVALUE[1] + EXP_ARM_DISABLE.SETVALUE[0] + EXP_ARM_POS.SETVALUE[1] +
ARM_EXP_0_TRG_TIMER0_AC0.SETVALUE[0] + ARM_EXP_0_TRG_TIMER0_AC1.SETVALUE[0] +
ARM_EXP_0_TRG_TIMER0_AC2.SETVALUE[0] + ARM_EXP_0_TRG_TIMER0_AC3.SETVALUE[0] +
ARM_EXP_0_CNTEQ0.SETVALUE[1] + EXP_OUT_DLYD.SETVALUE[1]
) : 0 ) ) ) )
) ;
//
EXP_MD_W_TRG_2
filter = (
( DAT_VALUE_READ * CAMERA_LINK_AV *
(
( ( ! OPTION_ODYSSEY_CL_FULL ) * ( ! OPTION_ODYSSEY_CL_DUAL ) * ( ! CLB_CCOUTEN1 ) ) |
( ( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL ) * ( EXP_ARM_POS_2 | EXP_ARM_NEG_2 ) * ( ! CLB_CCOUTEN1 ) )
)
) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] +
EXP_OUT_DLYD_2.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * ( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL ) *
( EXP_ARM_POS_2 == 0 ) * ( EXP_ARM_NEG_2 == 0 ) * ( ! CLB_CCOUTEN1 )
) ?
(
CLB_CCOUTEN1.SETVALUE[1] + CLB_CC1.SETVALUE[2] + CLB_CC2.SETVALUE[5] + CLB_CC3.SETVALUE[5] +
CLB_CC4.SETVALUE[5] + EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] +
EXP_ARM_POS_2.SETVALUE[1] + ARM_EXP_1_TRG_TIMER1_AC0.SETVALUE[0] + ARM_EXP_1_TRG_TIMER1_AC1.SETVALUE[0] +
ARM_EXP_1_TRG_TIMER1_AC2.SETVALUE[0] + ARM_EXP_1_TRG_TIMER1_AC3.SETVALUE[0] +
ARM_EXP_1_CNTEQ0.SETVALUE[1] + EXP_OUT_DLYD_2.SETVALUE[1]
) :
( ( DAT_VALUE_READ * CAMERA_LINK_AV * ( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL ) *
( EXP_ARM_POS_2 == 0 ) * ( EXP_ARM_NEG_2 == 0 ) * CLB_CCOUTEN1
) ?
(
EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + EXP_ARM_POS_2.SETVALUE[1] +
ARM_EXP_1_TRG_TIMER1_AC0.SETVALUE[0] + ARM_EXP_1_TRG_TIMER1_AC1.SETVALUE[0] +
ARM_EXP_1_TRG_TIMER1_AC2.SETVALUE[0] + ARM_EXP_1_TRG_TIMER1_AC3.SETVALUE[0] +
ARM_EXP_1_CNTEQ0.SETVALUE[1] + EXP_OUT_DLYD_2.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( VDC_ANA | ( ! CAMERA_LINK_AV ) ) *
( ! OPTION_ODYSSEY_DIG ) * ( ! OPTION_ODYSSEY_ANA )
) ?
(
EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + EXP_OUT_DLYD_2.SETVALUE[1]
) :
( ( DAT_VALUE_READ * ( VDC_ANA | ( ! CAMERA_LINK_AV ) ) * ( EXP_ARM_POS_2 == 0 ) * ( EXP_ARM_NEG_2 == 0 ) *
( OPTION_ODYSSEY_DIG | OPTION_ODYSSEY_ANA )
) ?
(
EXP_ARM_ENABLE_2.SETVALUE[1] + EXP_ARM_DISABLE_2.SETVALUE[0] + EXP_ARM_POS_2.SETVALUE[1] +
ARM_EXP_1_TRG_TIMER1_AC0.SETVALUE[0] + ARM_EXP_1_TRG_TIMER1_AC1.SETVALUE[0] +
ARM_EXP_1_TRG_TIMER1_AC2.SETVALUE[0] + ARM_EXP_1_TRG_TIMER1_AC3.SETVALUE[0] +
ARM_EXP_1_CNTEQ0.SETVALUE[1] + EXP_OUT_DLYD_2.SETVALUE[1]
) : 0 ) ) ) )
) ;
//
EXP_0_TRG_LVDS_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
EXP_0_TRG_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_0_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
EXP_TRG_0_TIMER0_AC0_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_0_TIMER0_LVDSOPTO_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_0_TIMER0_TTL_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_1_TRG_LVDS_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
EXP_1_TRG_ROTARY_ENCODER
filter = (
( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_0 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_DIG * ( CLC_MODE_CH0 > 0 ) * VDC_USE_PSG_1 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * ( ( VDC_MONO * VDC_USE_PSG_0 ) | VDC_RGB_COL ) ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * VDC_MONO * VDC_USE_PSG_1 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * VDC_MONO * VDC_USE_PSG_2 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_ANA * VDC_MONO * VDC_USE_PSG_3 ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER.SETVALUE[1] ) :
( ( ( DAT_VALUE_READ == 1 ) * EXP_MD_W_TRG_2 * VDC_DIG * ( CLC_MODE_CH0 == 0 ) ) ?
( EXP_1_TRG_LVDS_ROTARY_ENCODER.SETVALUE[0] + EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER.SETVALUE[1] ) :
0 ) ) ) ) ) )
) ;
//
EXP_TRG_1_TIMER0_AC0_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_1_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_1_TIMER0_LVDSOPTO_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_1_TIMER0_TTL_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_2_TIMER0_AC01_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_2_AC01_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_3_TIMER0_TTL_AC01_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_3_AC01_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_3_TIMER0_LVDSOPTO_AC01_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_3_AC01_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER0_AC0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER0_AC1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_1_AC1_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER0_AC2_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_1_AC2_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER0_AC3_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_1_AC3_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_0_TRG_0_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( EXP_0_TRG_0_AC1_OPTO_CL.SETVALUE[0] + EXP_0_TRG_2_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
EXP_0_TRG_1_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( EXP_0_TRG_1_AC1_OPTO_CL.SETVALUE[0] + EXP_0_TRG_3_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
EXP_1_TRG_0_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_1_TRG_0_AC1_OPTO_CL.SETVALUE[0] + EXP_1_TRG_2_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
EXP_1_TRG_1_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_1_TRG_1_AC1_OPTO_CL.SETVALUE[0] + EXP_1_TRG_3_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_0_TRG_0_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( ARM_EXP_0_TRG_0_AC1_OPTO_CL.SETVALUE[0] + ARM_EXP_0_TRG_2_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_0_TRG_1_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( ARM_EXP_0_TRG_1_AC1_OPTO_CL.SETVALUE[0] + ARM_EXP_0_TRG_3_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_1_TRG_0_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( ARM_EXP_1_TRG_0_AC1_OPTO_CL.SETVALUE[0] + ARM_EXP_1_TRG_2_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_1_TRG_1_AC1_OPTO_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( ARM_EXP_1_TRG_1_AC1_OPTO_CL.SETVALUE[0] + ARM_EXP_1_TRG_3_AC01_OPTO_CL.SETVALUE[1] ) : 0
) ;
//
EXP_0_TRG_0_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( EXP_0_TRG_0_AC1_LVDS_CL.SETVALUE[0] + EXP_0_TRG_2_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
EXP_0_TRG_1_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( EXP_0_TRG_1_AC1_LVDS_CL.SETVALUE[0] + EXP_0_TRG_3_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
EXP_1_TRG_0_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_1_TRG_0_AC1_LVDS_CL.SETVALUE[0] + EXP_1_TRG_2_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
EXP_1_TRG_1_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( EXP_1_TRG_1_AC1_LVDS_CL.SETVALUE[0] + EXP_1_TRG_3_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_0_TRG_0_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( ARM_EXP_0_TRG_0_AC1_LVDS_CL.SETVALUE[0] + ARM_EXP_0_TRG_2_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_0_TRG_1_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
( ARM_EXP_0_TRG_1_AC1_LVDS_CL.SETVALUE[0] + ARM_EXP_0_TRG_3_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_1_TRG_0_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( ARM_EXP_1_TRG_0_AC1_LVDS_CL.SETVALUE[0] + ARM_EXP_1_TRG_2_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
ARM_EXP_1_TRG_1_AC1_LVDS_CL
filter = (
( ( DAT_VALUE_READ == 1 ) * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
( ARM_EXP_1_TRG_1_AC1_LVDS_CL.SETVALUE[0] + ARM_EXP_1_TRG_3_AC01_LVDS_CL.SETVALUE[1] ) : 0
) ;
//
EXP_TRG_TTL_TIMER0_AC0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC0_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_TTL_TIMER0_AC1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC1_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_TTL_TIMER0_AC2_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC2_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_TTL_TIMER0_AC3_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_0_AC3_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR0_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_2_4AC_AUX0_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR1_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_3_4AC_AUX1_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR2_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_2_4AC_AUX2_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR3_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_3_4AC_AUX3_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR4_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_2_4AC_AUX4_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR5_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_3_4AC_AUX5_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR6_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_2_4AC_AUX6_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR7_TIMER0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_0_TRG_3_4AC_AUX7_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL.SETVALUE[1] + EXP_TRG_OPTO.SETVALUE[0] +
EXP_TRG_LVDS.SETVALUE[0] + EXP_TRG_422.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_0_TIMER1_AC0_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ?
(
EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_0_TIMER1_LVDSOPTO_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_0_TIMER1_TTL_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_1_TIMER1_AC0_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_2_TIMER1_AC0_CL
filter = 0 ;
//
EXP_TRG_3_TIMER1_AC0_CL
filter = 0 ;
//
EXP_TRG_0_TIMER1_AC1_CL
filter = 0 ;
//
EXP_TRG_1_TIMER1_AC1_CL
filter = 0 ;
//
EXP_TRG_2_TIMER1_AC1_CL
filter = 0 ;
//
EXP_TRG_3_TIMER1_AC1_CL
filter = 0 ;
//
EXP_TRG_0_TIMER2_AC0_CL
filter = 0 ;
//
EXP_TRG_1_TIMER2_AC0_CL
filter = 0 ;
//
EXP_TRG_2_TIMER2_AC0_CL
filter = 0 ;
//
EXP_TRG_3_TIMER2_AC0_CL
filter = 0 ;
//
EXP_TRG_0_TIMER2_AC1_CL
filter = 0 ;
//
EXP_TRG_1_TIMER2_AC1_CL
filter = 0 ;
//
EXP_TRG_2_TIMER2_AC1_CL
filter = 0 ;
//
EXP_TRG_3_TIMER2_AC1_CL
filter = 0 ;
//
EXP_TRG_1_TIMER1_LVDSOPTO_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_1_TIMER1_TTL_AC1_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC0_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_2_TIMER1_AC01_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_2_AC01_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_3_TIMER1_TTL_AC01_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_3_AC01_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_3_TIMER1_LVDSOPTO_AC01_CL
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_3_AC01_OPTO_CL.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER1_AC0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_1_AC0_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER1_AC1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_1_AC1_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER1_AC2_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_1_AC2_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER1_AC3_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_1_AC3_OPTO_ANA.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_OPTO_TIMER2_AC0_ANA
filter = 0 ;
//
EXP_TRG_OPTO_TIMER2_AC1_ANA
filter = 0 ;
//
EXP_TRG_OPTO_TIMER2_AC2_ANA
filter = 0 ;
//
EXP_TRG_OPTO_TIMER2_AC3_ANA
filter = 0 ;
//
EXP_TRG_TTL_TIMER2_AC0_ANA
filter = 0 ;
//
EXP_TRG_TTL_TIMER2_AC1_ANA
filter = 0 ;
//
EXP_TRG_TTL_TIMER2_AC2_ANA
filter = 0 ;
//
EXP_TRG_TTL_TIMER2_AC3_ANA
filter = 0 ;
//
EXP_TRG_TTL_TIMER1_AC0_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC0_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_TTL_TIMER1_AC1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC1_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_TTL_TIMER1_AC2_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC2_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_TTL_TIMER1_AC3_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_0_AC3_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR0_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_2_4AC_AUX0_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR1_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_3_4AC_AUX1_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR2_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_2_4AC_AUX2_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR3_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_3_4AC_AUX3_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR4_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_2_4AC_AUX4_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR5_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_3_4AC_AUX5_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR6_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_2_4AC_AUX6_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USR7_TIMER1_ANA
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ?
(
EXP_1_TRG_3_4AC_AUX7_TTL_ANA.SETVALUE[1] + EXP_TRG_TTL_2.SETVALUE[1] + EXP_TRG_OPTO_2.SETVALUE[0] +
EXP_TRG_LVDS_2.SETVALUE[0] + EXP_TRG_422_2.SETVALUE[0]
) : 0
) ;
//
EXP_TRG_USER1_IN_TIMER1
filter = 0 ;
//
EXP_TRG_USER2_IN_TIMER1
filter = 0 ;
//
EXP_TRG_USER3_IN_TIMER1
filter = 0 ;
//
EXP_TRG_USER4_IN_TIMER1
filter = 0 ;
//
EXP_TRG_USER1_IN_TIMER2
filter = 0 ;
//
EXP_TRG_USER2_IN_TIMER2
filter = 0 ;
//
EXP_TRG_USER3_IN_TIMER2
filter = 0 ;
//
EXP_TRG_USER4_IN_TIMER2
filter = 0 ;
//
EXP_TRG_USR0_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR1_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR2_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR3_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR4_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR5_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR6_TIMER2_ANA
filter = 0 ;
//
EXP_TRG_USR7_TIMER2_ANA
filter = 0 ;
//
EXP_CLK_TIMER2
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_CLK_TIMER1.SETVALUE[1] : 0 ) ;
//
EXP_CLK_2_TIMER1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_CLK_2_TIMER0.SETVALUE[1] : 0 ) ;
//
EXP_CLK_USRIN2_LVDS
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA ) ?
EXP_CLK_AUXIN1_AC0_ANA.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * ( CLC_MODE_CH0 > 0 ) ) ?
EXP_CLK_AUXIN1_AC0_CL.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * ( CLC_MODE_CH0 == 0 ) ) ?
EXP_CLK_AUXIN2_AC0_DIG.SETVALUE[1] : 0 ) )
) ;
//
EXP_CLK_USRIN2_OPTO
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * VDC_ANA ) ?
EXP_CLK_AUXIN1_AC0_ANA.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * ( CLC_MODE_CH0 > 0 ) ) ?
EXP_CLK_AUXIN1_AC0_CL.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) * ( CLC_MODE_CH0 == 0 ) ) ?
EXP_CLK_AUXIN2_AC0_DIG.SETVALUE[1] : 0 ) )
) ;
//
EXP_CLK_2_USRIN2_LVDS
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA ) ?
EXP_CLK_2_AUXIN1_AC0_ANA.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * ( CLC_MODE_CH0 > 0 ) ) ?
EXP_CLK_2_AUXIN1_AC0_CL.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * ( CLC_MODE_CH0 == 0 ) ) ?
EXP_CLK_2_AUXIN2_AC0_DIG.SETVALUE[1] : 0 ) )
) ;
//
EXP_CLK_2_USRIN2_OPTO
filter = (
( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * VDC_ANA ) ?
EXP_CLK_2_AUXIN1_AC0_ANA.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * ( CLC_MODE_CH0 > 0 ) ) ?
EXP_CLK_2_AUXIN1_AC0_CL.SETVALUE[1] :
( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * ( CLC_MODE_CH0 == 0 ) ) ?
EXP_CLK_2_AUXIN2_AC0_DIG.SETVALUE[1] : 0 ) )
) ;
//
EXP_COMBINE_T2
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_COMBINE_T1.SETVALUE[1] : 0 ) ;
//
EXP_COMBINE_XOR_T2
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_COMBINE_XOR_T1.SETVALUE[1] : 0 ) ;
//
EXP_COMBINE_XOR_T1AC1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD | EXP_MD_W_TRG ) ) ? EXP_COMBINE_XOR_T0AC1.SETVALUE[1] : 0 ) ;
//
EXP_COMBINE_2_T1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_COMBINE_2_T0.SETVALUE[1] : 0 ) ;
//
EXP_COMBINE_2_XOR_T1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_COMBINE_2_XOR_T0.SETVALUE[1] : 0 ) ;
//
EXP_COMBINE_2_XOR_T2AC1
filter = ( ( DAT_VALUE_READ * ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ) ? EXP_COMBINE_2_XOR_T1AC1.SETVALUE[1] : 0 ) ;
//
//
// ****************
// Odyssey without CC1-4 page in intellicam !
// ****************
// All in commentory : ONLY Odyssey Exposure Software Arm NOT supported.
// When supported, ONLY ALL Boards without ARM support setted automaticly to
// SOFWARE ARM BUT COULD BE SETTED AFTER ON TO SOMETHING ELSE BY USER in Intellicam..
//
//GRB_TRG_TIMER0
//filter = (
// ( DAT_VALUE_READ * GRB_MD_HW_TRG * CT_FS * ( ! EXP_ARM_POS ) * ( ! EXP_ARM_NEG ) ) ?
// ( ARM_EXP_0_SOFTWARE.SETVALUE[1] + ARM_EXP_0_CNTEQ0.SETVALUE[0] ) : 0
// ) ;
//
//GRB_TRG_TIMER1
//filter = (
// ( DAT_VALUE_READ * GRB_MD_HW_TRG * CT_FS * ( ! EXP_ARM_POS_2 ) * ( ! EXP_ARM_NEG_2 ) ) ?
// ( ARM_EXP_1_SOFTWARE.SETVALUE[1] + ARM_EXP_1_CNTEQ0.SETVALUE[0] ) : 0
// ) ;
//
//
// ****************
// Odyssey without PCK/HREF PLL page in intellicam !
// ****************
//
SYC_MD_CSYN
filter = (
(
DAT_VALUE_READ * VDC_ANA *
( ! SLOW_SCAN_PLL_HREFSEL_DEFAULT ) * ( ! SLOW_SCAN_PLL_HREFSEL_NONE ) *
( ! SLOW_SCAN_PLL_HREFSEL_DVI ) * ( ! SLOW_SCAN_PLL_HREFSEL_AUX ) *
( ! SLOW_SCAN_PLL_HREFSEL_VIDEO ) * ( ! SLOW_SCAN_PLL_HREFSEL_DVI_OTHERAC )
) ? ( SLOW_SCAN_PLL_HREFSEL_DEFAULT.SETVALUE[1] + SLOW_SCAN_PLL_PCKSEL_DEFAULT.SETVALUE[1] ) :
( (
VDC_ANA * ( ! SYC_CAM_GEN ) * SYC_DIG * SLOW_SCAN_PLL_HREFSEL_NONE * SLOW_SCAN_PLL_PCKSEL_NONE
) ? (
SLOW_SCAN_PLL_HREFSEL_DEFAULT.SETVALUE[1] + SLOW_SCAN_PLL_PCKSEL_DEFAULT.SETVALUE[1] +
SLOW_SCAN_PLL_HREFSEL_NONE.SETVALUE[0] + SLOW_SCAN_PLL_PCKSEL_NONE.SETVALUE[0]
) : 0 )
) ;
//
//
//
// --------------------------------------
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #4: COMMON BOARD LIMITATION
// **********************************************
// **********************************************
//
//
[COMMON_OPTIONS]
//
// =============================================
//
// ******** Camera type ********
//
VDC_USE_PSG_AV yes
//
// ******** Camera type ********
//
//-->Only two types FS and LS
CT_LINE_SCAN_AVAIL yes
CT_FRAM_SCAN_AVAIL yes
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 8 8 2 2 0 0 0
//
BOPTION_NOT_AV no
//
GTAP_AV yes
//
CT_MAX_CAMERA array 4 4 2 2 0 0 0
// dig ana
CT_MAX_CONNECTORS array 8 4
//
//
// ******** Camera BAYER Format type ********
//
CT_BAYER_DISABLE_AV yes
//
CT_BAYER_BG_AV yes
//
CT_BAYER_GB_AV yes
//
CT_BAYER_GR_AV yes
//
CT_BAYER_RG_AV yes
//
//
// --------------------------------------
//
// ******** Standards of video signal Available ********
// ana dig
YUVVID_AVAIL array 0 0
YUV_INPUT_AVAIL array 0 0
CHROMI_IN_AVAIL array 0 0
//
MONO_DIG_INPUT_AVAIL array 0 1 2 3
RGB_DIG_INPUT_AVAIL array 0
//
// ******** Video input AC/DC Coupling Available ********
VDC_MIL_CHANNEL_0_AV equ
value = (
VDC_ANA |
( CAMERA_LINK_AV * VDC_USE_PSG_0 )
) ;
VDC_MIL_CHANNEL_1_AV equ
value = (
VDC_ANA |
( CAMERA_LINK_AV * VDC_USE_PSG_1 )
) ;
//
VDC_0_AC_WITH_DC_AV yes
VDC_0_DC_WITH_DC_AV yes
VDC_0_DC_WITHOUT_DC_AV yes
//
VDC_0_NO_FILTER_AV equ
value = OPTION_ODYSSEY_ANA ;
VDC_0_FILTER_0_AV yes
VDC_0_FILTER_1_AV equ
value = ( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) ;
//
VDC_1_AC_WITH_DC_AV yes
VDC_1_DC_WITH_DC_AV yes
VDC_1_DC_WITHOUT_DC_AV yes
//
VDC_1_NO_FILTER_AV equ
value = OPTION_ODYSSEY_ANA ;
VDC_1_FILTER_0_AV yes
VDC_1_FILTER_1_AV equ
value = ( OPTION_HELIOS_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) ;
//
VDC_2_AC_WITH_DC_AV yes
VDC_2_DC_WITH_DC_AV yes
VDC_2_DC_WITHOUT_DC_AV yes
//
VDC_2_NO_FILTER_AV equ
value = OPTION_ODYSSEY_ANA ;
VDC_2_FILTER_0_AV yes
VDC_2_FILTER_1_AV equ
value = ( OPTION_HELIOS_ANA | OPTION_SOLIOS_QUAD_ANA ) ;
//
VDC_3_AC_WITH_DC_AV yes
VDC_3_DC_WITH_DC_AV yes
VDC_3_DC_WITHOUT_DC_AV yes
//
VDC_3_NO_FILTER_AV equ
value = OPTION_ODYSSEY_ANA ;
VDC_3_FILTER_0_AV yes
VDC_3_FILTER_1_AV equ
value = ( OPTION_HELIOS_ANA | OPTION_SOLIOS_QUAD_ANA ) ;
//
// ******** Information on clamping position Available ********
//
CLAMP_SYNC_AVAIL equ
value = (
(
VDC_ANA * ( VDT_HSYNC > 0 ) * ( ! TM_ENABLE ) *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
)
) | TM_ENABLE
) ;
//
CLAMP_BPORCH_AVAIL equ
value = (
(
VDC_ANA * ( VDT_HBPORCH > 0 ) * ( ! TM_ENABLE ) *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
)
) | TM_ENABLE | ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC )
) ;
//
CLAMP_FPORCH_AVAIL equ
value = (
(
VDC_ANA * ( VDT_HFPORCH > 0 ) * ( ! TM_ENABLE ) *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
)
) | TM_ENABLE
) ;
//
// --------------------------------------
//
// ******** Video timing ********
//
VID_STD_RS170_PCLK 12272700
VID_STD_RS170_HORZ array 58 58 24 640
VID_STD_RS170_VERT array 6 30 9 480
//
VID_STD_CCIR_PCLK 14750000
VID_STD_CCIR_HORZ array 69 86 21 768
VID_STD_CCIR_VERT array 5 40 4 576
//
VID_STD_CL_PCLK 20000000
VID_STD_CL_HORZ array 0 0 0 1024
VID_STD_CL_VERT array 0 0 0 1024
//
VDT_HSY_CNT_MIN 0
VDT_HBP_CNT_MIN 0
VDT_HACT_CNT_MIN 9
VDT_HFP_CNT_MIN 0
VDT_HSY+HBP_CNT_MIN 0
VDT_VSY_CNT_MIN 0
VDT_VBP_CNT_MIN 0
VDT_VACT_CNT_MIN 1
VDT_VFP_CNT_MIN 0
VDT_VSY+VBP_CNT_MIN 0
//
//
// --------------------------------------
//
// ******** Pixel clock ********
//
PCK_USE_DELAY_PICO_AV yes
//
//PCLK_IN_POS_POL_AV no
//PCLK_IN_NEG_POL_AV no
//PCLK_OUT_POS_POL_AV no
//PCLK_OUT_NEG_POL_AV no
//HIGH_SPEED_GRAB no
//
// --------------------------------------
//
// ******** Synchronisation signal ********
//
// ** Serration & equalization Available on csync pulse
VDT_SERRATION_AVAIL no
VDT_EQUALIZAT_AVAIL no
//
// ******** Information about block sync. supported in input//output sync signal ********
SYC_CAM_LATENCY_AV no
SYC_CAM_LATMAX_HTF 100
//
// ******** Sync input Source Type Available ********
SYC_SOURCE_VCR_AV no
//
// ******** Information about availability of input // output sync signal. ********
SYC_DIG_C_IN_AV equ
value = VDC_ANA ;
//
SYC_DIG_C_OUT_AV no
//
CSYN_IN_TTL_AV no
CSYN_IN_RS422_AV no
CSYN_IN_LVDS_AV no
CSYN_OUT_TTL_AV no
CSYN_OUT_RS422_AV no
CSYN_OUT_LVDS_AV no
CSYN_IN_POS_POL_AV no
CSYN_IN_NEG_POL_AV no
CSYN_OUT_NEG_POL_AV no
CSYN_OUT_POS_POL_AV no
//
// ** Info about availability of analog csync separate from video signal,
// based on the video type signal. (to reflect the Bt812 limitation)
//
SYC_ASEP_O_MONO_AV yes
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//
// ** Information on sync. signal that must have the same direction **
// (both generated or both received, not one received other generated)
SYC_HVC_SAME_FORMAT yes
SYC_HS&VS_MUST_SDIR no
SYC_HS&CS_MUST_SDIR yes
SYC_VS&CS_MUST_SDIR yes
//
// ** Information if a sync. signal may be in and out at the same time.
//
SYC_HSY_MAY_I&O yes
SYC_VSY_MAY_I&O yes
SYC_CSY_MAY_I&O yes
SYC_ANAL_O_DIGVID_AV no
//
// ******** PLL HRef Source selection ********
//
SLOW_SCAN_PLL_HREFSEL_DEFAULT_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_HREFSEL_NONE_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_HREFSEL_DVI_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_HREFSEL_AUX_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_HREFSEL_VIDEO_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_HREFSEL_DVI_OTHERAC_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_HREFSEL_DVI_AC1_AV equ
value = VDC_ANA ;
//
//
// ******** PLL PCK Source selection ********
//
SLOW_SCAN_PLL_PCKSEL_DEFAULT_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_PCKSEL_NONE_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_PCKSEL_DVI_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_PCKSEL_AUX_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_PCKSEL_VIDEO_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_PCKSEL_DVI_OTHERAC_AV equ
value = VDC_ANA ;
//
SLOW_SCAN_PLL_PCKSEL_DVI_AC1_AV equ
value = VDC_ANA ;
//
// --------------------------------------
//
// ******** Grab Activation ********
//
//
GRAB_ACT_NXT_FRM_AV equ
value = ( ( ! GRB_MD_CONT ) * CT_FS ) ;
//
GRAB_ACT_IMM_AV equ
value = ( ! GRB_MD_CONT ) ;
//
GRAB_ACT_IMM_SKNF_AV equ
value = ( ( ! GRB_MD_CONT ) * CT_FS ) ;
//
GRAB_LS_FREE_RUN_AV equ
value = ( GRB_MD_CONT * CT_LS ) ;
//
GRAB_LS_FIXED_LINE_AV equ
value = ( GRB_MD_CONT * CT_LS ) ;
//
GRAB_LS_VARIABLE_LINE_AV equ
value = ( GRB_MD_CONT * CT_LS ) ;
//
GRAB_LS_FRMFIX_LINEFIX_AV equ
value = ( CT_LS * ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) ) ;
//
GRAB_LS_FRMFIX_LINEVAR_AV equ
value = ( CT_LS * ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) ) ;
//
GRAB_LS_FRMVAR_LINEFIX_AV equ
value = ( CT_LS * ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) ) ;
//
GRAB_LS_FRMVAR_LINEVAR_AV equ
value = ( CT_LS * ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) ) ;
//
//
// ******** Grab Trigger ********
//
// ** Grab Source Trigger information **
//
//
GRB_TRG_TIMER0_AV equ
value = ( CT_FS | ( CT_LS * ( ! GRB_MD_CONT ) ) ) ;
//
GRB_TRG_TIMER1_AV equ
value = ( CT_FS | ( CT_LS * ( ! GRB_MD_CONT ) ) ) ;
//
GRB_TRG_TIMER2_AV equ
value = 0 ;
//
GRB_TRG_TIMER3_AV equ
value = 0 ;
//
GRB_TRG_HS_PSG_AV equ
value = ( CAMERA_LINK_AV * CT_LS ) ;
//
GRB_TRG_VS_PSG_AV equ
value = CT_FS ;
//
GRB_TRG_0_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_1_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_0_AC1_OPTO_CL_AV no
//
GRB_TRG_1_AC1_OPTO_CL_AV no
//
GRB_TRG_2_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_0_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_1_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_0_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_1_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_2_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_0_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_1_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_0_AC1_LVDS_CL_AV no
//
GRB_TRG_1_AC1_LVDS_CL_AV no
//
GRB_TRG_2_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
// Analog Module
//
GRB_TRG_1_AC0_OPTO_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_1_AC1_OPTO_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_1_AC2_OPTO_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_1_AC3_OPTO_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_0_AC0_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_0_AC1_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_0_AC2_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_0_AC3_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_2_4AC_AUX0_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX1_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_4AC_AUX2_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX3_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_4AC_AUX4_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX5_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_4AC_AUX6_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX7_TTL_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_2_4AC_AUX0_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX1_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_4AC_AUX2_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX3_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_4AC_AUX4_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX5_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_4AC_AUX6_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_4AC_AUX7_LVDS_ANA_AV equ
value = ( VDC_ANA * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
// Digital Module
//
GRB_TRG_0_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_1_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_0_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_1_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_0_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_1_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_0_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_1_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_OPTO | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_0_AC0_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_0_AC1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_0_AC2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_0_AC3_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_1_AC0_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
GRB_TRG_1_AC1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
GRB_TRG_1_AC2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
GRB_TRG_1_AC3_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
GRB_TRG_2_AC0_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC1_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC2_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC3_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC0_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC1_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC2_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC3_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_TTL | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC0_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC1_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC2_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_2_AC3_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC0_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC1_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC2_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
GRB_TRG_3_AC3_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) ) ;
//
//
// --------------------------------------
//
// ******** Exposure ********
//
// ** Synchronous clock signal maximum frequency (in Hz) **
// (maximum timer operation frequency) PCLK
EXP_SYN_CLK_MAX_FREQ equ
value = (
( VDC_ANA * 105000000 ) +
( ( ! VDC_ANA ) * 80000000 )
) ;
//
EXP_SYN_CLK_MAX_FREQ_2 equ
value = (
( VDC_ANA * 105000000 ) +
( ( ! VDC_ANA ) * 80000000 )
) ;
//
// ** Exposure asynchronous clock signal information **
EXP_ASY_CLK_AV no
//
// ** Asynchr. clock frequency (in Hz)
//%%%%%%%%%%EXP_ASY_CLK_FREQ 27000000
//
EXP_ASY_CLK_AV_2 no
//
// ** Asynchr. clock frequency (in Hz)
//%%%%%%%%%%EXP_ASY_CLK_FREQ_2 27000000
//
// ** Asynchr. generator clock frequency (in Hz) ** USERCLK
EXP_CLK_CLKGEN_AV equ
value = (
(
(
EXP_CLK_CLKGEN | EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL |
EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ
) || PCK_FREQ
) ;
//
// ** Asynchr. generator clock frequency (in Hz) ** USERCLK
//
EXP_CLK_2_CLKGEN_AV equ
value = (
( EXP_CLK_2_CLKGEN * EXP_CLK_FREQ_2 ) || 1
) ;
//
EXP_CLK_HS_AV equ
value = ( ( PCK_FREQ / VDT_HTOTAL ) + 0.5 ) ;
//value = VDT_HSYNC_FREQ ;
//
EXP_CLK_VS_AV equ
value = ( ( PCK_FREQ / ( VDT_HTOTAL * VDT_VTOTAL ) ) + 0.5 ) ;
//value = VDT_VSYNC_FREQ ;
//
EXP_CLK_2_HS_AV equ
value = ( ( PCK_FREQ / VDT_HTOTAL ) + 0.5 ) ;
//value = VDT_HSYNC_FREQ ;
//
EXP_CLK_2_VS_AV equ
value = ( ( PCK_FREQ / ( VDT_HTOTAL * VDT_VTOTAL ) ) + 0.5 ) ;
//value = VDT_VSYNC_FREQ ;
//
EXP_CLK_TIMER1_AV equ
value = (
DEF_TIMER0_ENABLED |
(
(
( EXP_SYN_CLK_2 * PCK_FREQ ) +
( EXP_CLK_2_CLKGEN * EXP_CLK_FREQ_2 ) +
( EXP_CLK_2_HS * VDT_HSYNC_FREQ ) +
( EXP_CLK_2_VS *
( ( VDT_VSYNC_FREQ * 2 * VDT_INTERL ) + ( VDT_VSYNC_FREQ * VDT_NINTRL ) )
) +
(
(
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL |
EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA |
EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG |
EXP_CLK_2_AUXIN2_AC2_DIG | EXP_CLK_2_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ_2
)
) /
(
( 2 ^ EXP_CLK_DIVF ) * ( 2 ^ EXP_CLK_DVED_2 ) *
(
(
( EXP_OUT_T0_2 + EXP_OUT_T1_2 + EXP_OUT_T2_2 + EXP_OUT_T3_2 ) *
(
( ( EXP_OUT_T1_2 > 0 ) * ( EXP_OUT_T3_2 == 0 ) ) |
( ( EXP_OUT_T1_2 == 0 ) * ( EXP_OUT_T3_2 > 0 ) )
)
) |
(
( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) * ( EXP_OUT_T1_2 > 0 ) *
(
( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) < ( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) ) |
( ( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) == 0 ) |
( ( EXP_OUT_T0_2 == EXP_OUT_T2_2 ) * ( EXP_OUT_T1_2 == EXP_OUT_T3_2 ) )
)
) |
(
( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) * ( EXP_OUT_T3_2 > 0 ) *
(
( ( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) < ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) ) |
( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) == 0 )
)
)
)
)
)
) ;
//
EXP_CLK_TIMER2_AV equ
value = 0 ;
//
EXP_CLK_TIMER3_AV equ
value = 0 ;
//
EXP_CLK_2_TIMER0_AV equ
value = (
DEF_TIMER1_ENABLED |
(
(
( EXP_SYN_CLK * PCK_FREQ ) +
( EXP_CLK_CLKGEN * EXP_CLK_FREQ ) +
( EXP_CLK_HS * VDT_HSYNC_FREQ ) +
( EXP_CLK_VS *
( ( VDT_VSYNC_FREQ * 2 * VDT_INTERL ) + ( VDT_VSYNC_FREQ * VDT_NINTRL ) )
) +
(
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL |
EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA |
EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA |
EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ
)
) /
(
( 2 ^ EXP_CLK_DVED_2 ) * ( 2 ^ EXP_CLK_DIVF ) *
(
(
( EXP_OUT_T0 + EXP_OUT_T1 + EXP_OUT_T2 + EXP_OUT_T3 ) *
(
( ( EXP_OUT_T1 > 0 ) * ( EXP_OUT_T3 == 0 ) ) |
( ( EXP_OUT_T1 == 0 ) * ( EXP_OUT_T3 > 0 ) )
)
) |
(
( EXP_OUT_T0 + EXP_OUT_T1 ) * ( EXP_OUT_T1 > 0 ) *
(
( ( EXP_OUT_T0 + EXP_OUT_T1 ) < ( EXP_OUT_T2 + EXP_OUT_T3 ) ) |
( ( EXP_OUT_T2 + EXP_OUT_T3 ) == 0 ) |
( ( EXP_OUT_T0 == EXP_OUT_T2 ) * ( EXP_OUT_T1 == EXP_OUT_T3 ) )
)
) |
(
( EXP_OUT_T2 + EXP_OUT_T3 ) * ( EXP_OUT_T3 > 0 ) *
(
( ( EXP_OUT_T2 + EXP_OUT_T3 ) < ( EXP_OUT_T0 + EXP_OUT_T1 ) ) |
( ( EXP_OUT_T0 + EXP_OUT_T1 ) == 0 )
)
)
)
)
)
) ;
//
EXP_CLK_2_TIMER2_AV equ
value = 0 ;
//
EXP_CLK_2_TIMER3_AV equ
value = 0 ;
//
EXP_CLK_AUXIN1_AC0_CL_AV equ
value = (
EXP_CLK_FREQ * DEF_AC0_PROGRAMMED * VDC_DIG * CAMERA_LINK_AV * ( ! GRB_TRG_1_AC0_LVDS_CL ) *
( ! EXP_0_TRG_1_AC0_LVDS_CL ) * ( ! EXP_1_TRG_1_AC0_LVDS_CL ) * ( ! ARM_EXP_0_TRG_1_AC0_LVDS_CL ) *
( ! ARM_EXP_1_TRG_1_AC0_LVDS_CL ) * ( ! GRB_TRG_1_AC0_TTL_CL ) * ( ! EXP_0_TRG_1_AC0_TTL_CL ) *
( ! EXP_1_TRG_1_AC0_TTL_CL ) * ( ! ARM_EXP_0_TRG_1_AC0_TTL_CL ) * ( ! ARM_EXP_1_TRG_1_AC0_TTL_CL )
) ;
//
EXP_CLK_AUXIN3_AC1_CL_AV equ
value = (
EXP_CLK_FREQ * DEF_AC1_PROGRAMMED * VDC_DIG * CAMERA_LINK_AV * ( ! GRB_TRG_1_AC1_LVDS_CL ) *
( ! EXP_0_TRG_1_AC1_LVDS_CL ) * ( ! EXP_1_TRG_1_AC1_LVDS_CL ) * ( ! ARM_EXP_0_TRG_1_AC1_LVDS_CL ) *
( ! ARM_EXP_1_TRG_1_AC1_LVDS_CL ) * ( ! GRB_TRG_1_AC1_TTL_CL ) * ( ! EXP_0_TRG_1_AC1_TTL_CL ) *
( ! EXP_1_TRG_1_AC1_TTL_CL ) * ( ! ARM_EXP_0_TRG_1_AC1_TTL_CL ) * ( ! ARM_EXP_1_TRG_1_AC1_TTL_CL )
) ;
//
EXP_CLK_AUXIN1_AC0_ANA_AV equ
value = (
EXP_CLK_FREQ * DEF_AC0_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX1_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX1_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX1_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA )
) ;
//
EXP_CLK_AUXIN3_AC1_ANA_AV equ
value = (
EXP_CLK_FREQ * DEF_AC1_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX3_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX3_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX3_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA )
) ;
//
EXP_CLK_AUXIN5_AC2_ANA_AV equ
value = (
EXP_CLK_FREQ * DEF_AC2_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX5_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX5_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX5_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA )
) ;
//
EXP_CLK_AUXIN7_AC3_ANA_AV equ
value = (
EXP_CLK_FREQ * DEF_AC3_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX7_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX7_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX7_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA )
) ;
//
EXP_CLK_AUXIN2_AC0_DIG_AV equ
value = (
EXP_CLK_FREQ * DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC0_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC0_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC0_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG )
) ;
//
EXP_CLK_AUXIN2_AC1_DIG_AV equ
value = (
EXP_CLK_FREQ * DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC1_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC1_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC1_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG )
) ;
//
EXP_CLK_AUXIN2_AC2_DIG_AV equ
value = (
EXP_CLK_FREQ * DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC2_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC2_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC2_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG )
) ;
//
EXP_CLK_AUXIN2_AC3_DIG_AV equ
value = (
EXP_CLK_FREQ * DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC3_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC3_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC3_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG )
) ;
//
EXP_CLK_2_AUXIN1_AC0_CL_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC0_PROGRAMMED * VDC_DIG * CAMERA_LINK_AV * ( ! GRB_TRG_1_AC0_LVDS_CL ) *
( ! EXP_0_TRG_1_AC0_LVDS_CL ) * ( ! EXP_1_TRG_1_AC0_LVDS_CL ) * ( ! ARM_EXP_0_TRG_1_AC0_LVDS_CL ) *
( ! ARM_EXP_1_TRG_1_AC0_LVDS_CL ) * ( ! GRB_TRG_1_AC0_TTL_CL ) * ( ! EXP_0_TRG_1_AC0_TTL_CL ) *
( ! EXP_1_TRG_1_AC0_TTL_CL ) * ( ! ARM_EXP_0_TRG_1_AC0_TTL_CL ) * ( ! ARM_EXP_1_TRG_1_AC0_TTL_CL )
) ;
//
EXP_CLK_2_AUXIN3_AC1_CL_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC1_PROGRAMMED * VDC_DIG * CAMERA_LINK_AV * ( ! GRB_TRG_1_AC1_LVDS_CL ) *
( ! EXP_0_TRG_1_AC1_LVDS_CL ) * ( ! EXP_1_TRG_1_AC1_LVDS_CL ) * ( ! ARM_EXP_0_TRG_1_AC1_LVDS_CL ) *
( ! ARM_EXP_1_TRG_1_AC1_LVDS_CL ) * ( ! GRB_TRG_1_AC1_TTL_CL ) * ( ! EXP_0_TRG_1_AC1_TTL_CL ) *
( ! EXP_1_TRG_1_AC1_TTL_CL ) * ( ! ARM_EXP_0_TRG_1_AC1_TTL_CL ) * ( ! ARM_EXP_1_TRG_1_AC1_TTL_CL )
) ;
//
EXP_CLK_2_AUXIN1_AC0_ANA_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC0_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX1_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX1_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX1_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA )
) ;
//
EXP_CLK_2_AUXIN3_AC1_ANA_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC1_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX3_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX3_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX3_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA )
) ;
//
EXP_CLK_2_AUXIN5_AC2_ANA_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC2_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX5_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX5_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX5_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA )
) ;
//
EXP_CLK_2_AUXIN7_AC3_ANA_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC3_PROGRAMMED * VDC_ANA *
( ! GRB_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! EXP_0_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA ) *
( ! EXP_1_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA ) * ( ! GRB_TRG_3_4AC_AUX7_TTL_ANA ) *
( ! EXP_0_TRG_3_4AC_AUX7_TTL_ANA ) * ( ! ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA ) * ( ! EXP_1_TRG_3_4AC_AUX7_TTL_ANA ) *
( ! ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA )
) ;
//
EXP_CLK_2_AUXIN2_AC0_DIG_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC0_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC0_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC0_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG )
) ;
//
EXP_CLK_2_AUXIN2_AC1_DIG_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC1_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC1_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC1_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG )
) ;
//
EXP_CLK_2_AUXIN2_AC2_DIG_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC2_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC2_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC2_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG )
) ;
//
EXP_CLK_2_AUXIN2_AC3_DIG_AV equ
value = (
EXP_CLK_FREQ_2 * DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
( ! GRB_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! EXP_0_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG ) *
( ! EXP_1_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG ) * ( ! GRB_TRG_3_AC3_AUX2_TTL_DIG ) *
( ! EXP_0_TRG_3_AC3_AUX2_TTL_DIG ) * ( ! ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG ) * ( ! EXP_1_TRG_3_AC3_AUX2_TTL_DIG ) *
( ! ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG )
) ;
//
// ** Exposure Triggers sources AS BOARDS TYPE **
// ************************** TIMERS TRIGGERS **************************
// Camera Link Boards
//
EXP_DEL_TRG_DEFAULT_AV yes
//
EXP_NDEL_TRG_DEFAULT_AV yes
//
EXP_DEL_TRG_DEFAULT_AV_2 yes
//
EXP_NDEL_TRG_DEFAULT_AV_2 yes
//
EXP_TRG_ON_EXT_AV no
//
EXP_TRG_ON_EXT_AV_2 no
//
EXP_TRG_ON_HSY_AV yes
//
EXP_TRG_ON_VSY_AV yes
//
EXP_TRG_ON_SW_AV yes
//
EXP_TRG_TIMER1_AV equ
value = ( ( ! EXP_TRG_TIMER0_2 ) * ( ! EXP_CLK_2_TIMER0 ) ) ;
//
EXP_TRG_ON_HSY_AV_2 yes
//
EXP_TRG_ON_VSY_AV_2 yes
//
EXP_TRG_ON_SW_AV_2 yes
//
EXP_TRG_TIMER0_2_AV equ
value = ( ( ! EXP_TRG_TIMER1 ) * ( ! EXP_CLK_TIMER1 ) ) ;
//
EXP_0_TRG_TIMER0_AC0_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC1_PROGRAMMED
) ;
//
EXP_0_TRG_TIMER0_AC1_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC0_PROGRAMMED
) ;
//
EXP_0_TRG_TIMER0_AC2_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC3_PROGRAMMED
) ;
//
EXP_0_TRG_TIMER0_AC3_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC2_PROGRAMMED
) ;
//
ARM_EXP_0_CNTEQ0_AV yes
//
ARM_EXP_1_CNTEQ0_AV yes
//
ARM_EXP_0_TRG_TIMER0_AC0_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC1_PROGRAMMED
) ;
//
ARM_EXP_0_TRG_TIMER0_AC1_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC0_PROGRAMMED
) ;
//
ARM_EXP_0_TRG_TIMER0_AC2_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC3_PROGRAMMED
) ;
//
ARM_EXP_0_TRG_TIMER0_AC3_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG * DEF_AC2_PROGRAMMED
) ;
//
EXP_1_TRG_TIMER1_AC0_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC1_PROGRAMMED
) ;
//
EXP_1_TRG_TIMER1_AC1_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC0_PROGRAMMED
) ;
//
EXP_1_TRG_TIMER1_AC2_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC3_PROGRAMMED
) ;
//
EXP_1_TRG_TIMER1_AC3_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC2_PROGRAMMED
) ;
//
ARM_EXP_1_TRG_TIMER1_AC0_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC1_PROGRAMMED
) ;
//
ARM_EXP_1_TRG_TIMER1_AC1_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC0_PROGRAMMED
) ;
//
ARM_EXP_1_TRG_TIMER1_AC2_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC3_PROGRAMMED
) ;
//
ARM_EXP_1_TRG_TIMER1_AC3_AV equ
value = (
( OPTION_ODYSSEY_CL_FULL | OPTION_ODYSSEY_CL_DUAL | OPTION_ODYSSEY_ANA | OPTION_ODYSSEY_DIG ) *
EXP_MD_W_TRG_2 * DEF_AC2_PROGRAMMED
) ;
//
EXP_0_TRG_0_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC1_OPTO_CL_AV no
//
EXP_0_TRG_1_AC1_OPTO_CL_AV no
//
EXP_0_TRG_2_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_0_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_2_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC1_LVDS_CL_AV no
//
EXP_0_TRG_1_AC1_LVDS_CL_AV no
//
EXP_0_TRG_2_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_1_TRG_0_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC1_OPTO_CL_AV no
//
EXP_1_TRG_1_AC1_OPTO_CL_AV no
//
EXP_1_TRG_2_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_0_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_2_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC1_LVDS_CL_AV no
//
EXP_1_TRG_1_AC1_LVDS_CL_AV no
//
EXP_1_TRG_2_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
//
// ** Analog Boards **
//
EXP_0_TRG_1_AC0_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC1_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC2_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC3_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_2_4AC_AUX0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_4AC_AUX2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_4AC_AUX4_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX5_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_4AC_AUX6_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX7_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX1_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX3_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX5_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_4AC_AUX6_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_4AC_AUX7_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_1_TRG_1_AC0_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC1_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC2_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC3_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_2_4AC_AUX0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_4AC_AUX2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_4AC_AUX4_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX5_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_4AC_AUX6_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX7_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX1_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_4AC_AUX2_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX3_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_4AC_AUX4_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX5_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_4AC_AUX6_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_4AC_AUX7_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
// ** Digital Boards **
//
EXP_0_TRG_0_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC0_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_0_AC3_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC0_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_1_AC3_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_2_AC0_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_AC1_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_AC2_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_AC3_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC0_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC1_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC2_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC3_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_AC1_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_AC2_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC1_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC2_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) ) ;
//
EXP_1_TRG_0_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_OPTO_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC0_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_0_AC3_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC0_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
EXP_1_TRG_1_AC3_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
EXP_1_TRG_2_AC0_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC1_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC2_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC3_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC0_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC1_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC2_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC3_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_TTL_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC2_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_2_AC3_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC2_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) ) ;
//
//
// ************************** TIMERS ARM **************************
// Camera Link module
//
//
ARM_EXP_0_CNTEQ0_AV equ
value = ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ;
//
ARM_EXP_0_SOFTWARE_AV equ
value = ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ;
//
ARM_EXP_0_TIMER1_AV equ
value = ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ;
//
ARM_EXP_0_HS_PSG_AV equ
value = ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ;
//
ARM_EXP_0_VS_PSG_AV equ
value = ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ;
//
ARM_EXP_0_TRG_0_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC1_OPTO_CL_AV no
//
ARM_EXP_0_TRG_1_AC1_OPTO_CL_AV no
//
ARM_EXP_0_TRG_2_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_0_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_2_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC1_LVDS_CL_AV no
//
ARM_EXP_0_TRG_1_AC1_LVDS_CL_AV no
//
ARM_EXP_0_TRG_2_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_1_CNTEQ0_AV equ
value = ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ;
//
ARM_EXP_1_SOFTWARE_AV equ
value = ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ;
//
ARM_EXP_1_TIMER0_AV equ
value = ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ;
//
ARM_EXP_1_HS_PSG_AV equ
value = ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ;
//
ARM_EXP_1_VS_PSG_AV equ
value = ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ;
//
ARM_EXP_1_TRG_0_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC0_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC1_OPTO_CL_AV no
//
ARM_EXP_1_TRG_1_AC1_OPTO_CL_AV no
//
ARM_EXP_1_TRG_2_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC01_OPTO_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_0_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC0_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC1_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_2_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC01_TTL_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC0_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC1_LVDS_CL_AV no
//
ARM_EXP_1_TRG_1_AC1_LVDS_CL_AV no
//
ARM_EXP_1_TRG_2_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC01_LVDS_CL_AV equ
value = ( CAMERA_LINK_AV * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
//
// ** Analog Boards **
//
ARM_EXP_0_TRG_1_AC0_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC1_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC2_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC3_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_1_TRG_1_AC0_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC1_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC2_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC3_OPTO_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA_AV equ
value = ( VDC_ANA * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
//
// ** Digital Boards **
//
//
ARM_EXP_0_TRG_0_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC0_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_0_AC3_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC0_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_1_AC3_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) ) ;
//
ARM_EXP_1_TRG_0_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC0_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC1_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC2_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC3_OPTO_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_OPTO_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC0_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_0_AC3_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC0_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC0_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC1_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC2_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_1_AC3_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) * DEF_AC3_PROGRAMMED ) ;
//
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_TTL_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG_AV equ
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) ) ;
//
//
//
//%%%%%%%%%%EXP_SYN_CLK_MAX_FREQ 100000000
EXP_CLK_DVED_AV yes
EXP_CLK_MAXDIV_FACT 16
EXP_DELYED_FR_TRG_AV yes
EXP_TIMER_MAX_VALUE 0xffffff
EXP_TIMER_MIN_VALUE 0
EXP_CHK_MAXSUM_PERD no
EXP_CHK_MAXSUM_DEL no
EXP_CHK_MAXSUM_NDEL no
EXP_TRG_ON_EXT_AV no
EXP_NDEL_TRG_TTL_AV yes
EXP_NDEL_TRG_422_AV no
EXP_NDEL_TRG_LVDS_AV yes
EXP_NDEL_TRG_OPTO_AV yes
EXP_NDEL_TRG_DEFAULT_AV yes
EXP_DEL_TRG_TTL_AV yes
EXP_DEL_TRG_422_AV no
EXP_DEL_TRG_LVDS_AV yes
EXP_DEL_TRG_OPTO_AV yes
//EXP_DEL_TRG_DEFAULT_AV yes
EXP_NDEL_OUT_TTL_AV yes
EXP_NDEL_OUT_422_AV no
EXP_NDEL_OUT_LVDS_AV yes
EXP_NDEL_OUT_OPTO_AV no
EXP_NDEL_OUT_DEFAULT_AV yes
EXP_DEL_OUT_TTL_AV yes
EXP_DEL_OUT_422_AV no
EXP_DEL_OUT_LVDS_AV yes
EXP_DEL_OUT_DEFAULT_AV yes
EXP_DEL_OUT_OPTO_AV no
EXP_MD_PERD_AV yes
EXP_MD_WITH_TRG_AV yes
EXP_PERD_CLKDVED_AV yes
EXP_DEL_CLKDVED_AV yes
EXP_NDEL_CLKDVED_AV yes
EXP_TEX_CLKDVED_AV yes
EXP_THSY_CLKDVED_AV yes
EXP_TVSY_CLKDVED_AV yes
EXP_TSW_CLKDVED_AV yes
EXP_ARM_ENABLE_AV yes
EXP_ARM_DISABLE_AV yes
EXP_ARM_POS_AV yes
EXP_ARM_NEG_AV yes
EXP_ARM_TTL_AV yes
EXP_ARM_422_AV no
EXP_ARM_OPTO_AV yes
EXP_ARM_LVDS_AV yes
EXP_ARM_DEFAULT_AV yes
//
//%%%%%%%%%%EXP_SYN_CLK_MAX_FREQ_2 100000000
EXP_CLK_DVED_AV_2 yes
EXP_CLK_MAXDIV_FACT_2 16
EXP_DELYED_FR_TRG_AV_2 yes
EXP_TIMER_MAX_VALUE_2 0xffffff
EXP_TIMER_MIN_VALUE_2 0
EXP_CHK_MAXSUM_PERD_2 no
EXP_CHK_MAXSUM_DEL_2 no
EXP_CHK_MAXSUM_NDEL_2 no
EXP_TRG_ON_EXT_AV_2 no
EXP_NDEL_TRG_TTL_AV_2 yes
EXP_NDEL_TRG_422_AV_2 no
EXP_NDEL_TRG_LVDS_AV_2 yes
EXP_NDEL_TRG_OPTO_AV_2 yes
EXP_NDEL_TRG_DEFAULT_AV_2 yes
EXP_DEL_TRG_TTL_AV_2 yes
EXP_DEL_TRG_422_AV_2 no
EXP_DEL_TRG_LVDS_AV_2 yes
EXP_DEL_TRG_OPTO_AV_2 yes
//EXP_DEL_TRG_DEFAULT_AV_2 yes
EXP_NDEL_OUT_TTL_AV_2 yes
EXP_NDEL_OUT_422_AV_2 no
EXP_NDEL_OUT_LVDS_AV_2 yes
EXP_NDEL_OUT_OPTO_AV_2 no
EXP_DEL_OUT_TTL_AV_2 yes
EXP_DEL_OUT_422_AV_2 no
EXP_DEL_OUT_LVDS_AV_2 yes
EXP_DEL_OUT_OPTO_AV_2 no
EXP_MD_PERD_AV_2 yes
EXP_MD_WITH_TRG_AV_2 yes
EXP_PERD_CLKDVED_AV_2 yes
EXP_DEL_CLKDVED_AV_2 yes
EXP_NDEL_CLKDVED_AV_2 yes
EXP_TEX_CLKDVED_AV_2 yes
EXP_THSY_CLKDVED_AV_2 yes
EXP_TVSY_CLKDVED_AV_2 yes
EXP_TSW_CLKDVED_AV_2 yes
EXP_ARM_ENABLE_AV_2 yes
EXP_ARM_DISABLE_AV_2 yes
EXP_ARM_POS_AV_2 yes
EXP_ARM_NEG_AV_2 yes
EXP_ARM_TTL_AV_2 yes
EXP_ARM_422_AV_2 no
EXP_ARM_OPTO_AV_2 yes
EXP_ARM_LVDS_AV_2 yes
EXP_ARM_DEFAULT_AV_2 yes
//
// --------------------------------------
//
// ******** none classified board options ********
//
SYC_ANA_IN_CH_AV array 1 1 1 1
RS_330_SUPPORTED no
VACTIVE_INTERL_EVEN no
//
// ** horizontal & vertical absolute maximum value **
// (be sure to give an absolute maximum, so keep a margin of safety
// from the maximum value found in the HW registers.)
// (Intellicam absolute maximum of 0xffffffff)
//
VDT_HORIZ_MAX_VAL 0x1000000
VDT_VERT_MAX_VAL 0x100000
//
// ** Minimum timings state value (in pixel count)
// (based on HW limitation, pipeline, line buffer etc...)
//
VDT_HSY_CNT_MIN 0
VDT_HBP_CNT_MIN 0
VDT_HACT_CNT_MIN 0
VDT_HFP_CNT_MIN 0
VDT_HSY+HBP_CNT_MIN 0
VDT_VSY_CNT_MIN 0
VDT_VBP_CNT_MIN 0
VDT_VACT_CNT_MIN 0
VDT_VFP_CNT_MIN 0
VDT_VSY+VBP_CNT_MIN 0
//
// ** Vertical active value that must be a multiple value, based on
// the video type signal. analog digital
//--> Where does ON_DIG comes from????
//--> Other signal type as CCOL, RGB, SVID, YUV
VACT_MULTV_ON_DIG 1
VACT_MULTV_ON_MONO array 1 1
VACT_MULTV_ON_MONOHI array 1 1
//
// ** Horizontal active value that must be a multiple value, based on
// the video type signal.
HACT_MULTV_ON_DIG 1
HACT_MULTV_ON_MONO array 1 1
HACT_MULTV_ON_MONOHI array 1 1
//
VTOT_ARR_ON_MONO no
VTOT_ARR_ON_CCOL array 525 625
VTOT_ARR_ON_RGB no
VTOT_ARR_ON_SVID no
VTOT_ARR_ON_YUV no
VTOT_ARR_ON_MONOHI no
CLAMP_TIMING_MIN array 0 0 0 0
//
// --------------------------------------
//
// Configuration modes Availables
//
VDT_CL_USE_CAMERA_VALID_LS_AV equ
value = CT_LS ;
//
VDT_CL_USE_CAMERA_VALID_LS_CL_AV equ
value = ( CAMERA_LINK_AV * CT_LS ) ;
//
VDT_CL_USE_CAMERA_VALID_FS_AV equ
value = CT_FS ;
//
VDT_CL_USE_CAMERA_VALID_FS_CL_AV equ
value = ( CAMERA_LINK_AV * CT_FS ) ;
//
// --------------------------------------
//
// ******** Camera Link common section ********
//
// Current configuration mode
CLC_MODE_B1_MONO_AV equ
value = ( ( CLC_MODE == 0 ) * VDC_MONO ) ;
//
CLC_MODE_B2_MONO_AV equ
value = ( ( CLC_MODE == 0 ) * VDC_MONO ) ;
//
CLC_MODE_B3_MONO_AV equ
value = ( ( CLC_MODE == 0 ) * VDC_MONO ) ;
//
CLC_MODE_B4_MONO_AV equ
value = ( ( CLC_MODE == 0 ) * VDC_MONO ) ;
//
CLC_MODE_B5_RGB_AV equ
value = ( ( CLC_MODE == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ) ;
//
CLC_MODE_B6_RGB_AV equ
value = ( ( CLC_MODE == 0 ) * ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ) ;
//
CLC_MODE_B7_MONO_AV equ
value = ( ( CLC_MODE == 0 ) * VDC_MONO ) ;
//
CLC_MODE_B8_MONO_AV equ
value = ( ( CLC_MODE == 0 ) * VDC_MONO ) ;
//
CLC_MODE_M1_MONO_AV equ
value = ( ( CLC_MODE == 1 ) * VDC_MONO ) ;
//
CLC_MODE_M2_RGB_AV equ
value = ( ( CLC_MODE == 1 ) * ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ) ;
//
CLC_MODE_M3_RGB_AV equ
value = ( ( CLC_MODE == 1 ) * ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ) ;
//
CLC_MODE_M4_MONO_AV equ
value = ( ( CLC_MODE == 1 ) * VDC_MONO ) ;
//
CLC_MODE_M5_MONO_AV equ
value = ( ( CLC_MODE == 1 ) * VDC_MONO ) ;
//
CLC_MODE_M6_RGB_AV equ
value = ( ( CLC_MODE == 1 ) * ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ) ;
//
CLC_MODE_M7_MONO_AV equ
value = ( ( CLC_MODE == 1 ) * VDC_MONO ) ;
//
CLC_MODE_FULL_AV equ
value = ( CLC_MODE == 2 ) ;
//
CLC_MODE_FULL_4TAPS_AV equ
value = ( CLC_MODE == 2 ) ;
//
CAMERA_LINK_AV no
// Configuration modes Availables
CL_CONFIG_BASE_AV no
CL_CONFIG_MEDIUM_AV no
CL_CONFIG_FULL_AV no
// Channels availability
CL_CHANNEL0_AV no
// CC1 signal source
CL_CC1_DISABLE_AV no
CL_CC1_TIMER_1_AV no
CL_CC1_TIMER_2_AV no
CL_CC1_USROUT_0_HIGH_AV no
CL_CC1_USROUT_0_LOW_AV no
CL_CC1_USROUT_1_HIGH_AV no
CL_CC1_USROUT_1_LOW_AV no
CL_CC1_PSG_VSYNC_AV no
CL_CC1_PSG_HSYNC_AV no
CL_CC1_PCLK_AV no
// CC2 signal source
CL_CC2_DISABLE_AV no
CL_CC2_TIMER_1_AV no
CL_CC2_TIMER_2_AV no
CL_CC2_USROUT_0_HIGH_AV no
CL_CC2_USROUT_0_LOW_AV no
CL_CC2_USROUT_1_HIGH_AV no
CL_CC2_USROUT_1_LOW_AV no
CL_CC2_PSG_VSYNC_AV no
CL_CC2_PSG_HSYNC_AV no
CL_CC2_PCLK_AV no
// CC3 signal source
CL_CC3_DISABLE_AV no
CL_CC3_TIMER_1_AV no
CL_CC3_TIMER_2_AV no
CL_CC3_USROUT_0_HIGH_AV no
CL_CC3_USROUT_0_LOW_AV no
CL_CC3_USROUT_1_HIGH_AV no
CL_CC3_USROUT_1_LOW_AV no
CL_CC3_PSG_VSYNC_AV no
CL_CC3_PSG_HSYNC_AV no
CL_CC3_PCLK_AV no
// CC4 signal source
CL_CC4_DISABLE_AV no
CL_CC4_TIMER_1_AV no
CL_CC4_TIMER_2_AV no
CL_CC4_USROUT_0_HIGH_AV no
CL_CC4_USROUT_0_LOW_AV no
CL_CC4_USROUT_1_HIGH_AV no
CL_CC4_USROUT_1_LOW_AV no
CL_CC4_PSG_VSYNC_AV no
CL_CC4_PSG_HSYNC_AV no
CL_CC4_PCLK_AV no
//
//// --------------------------------------
////
//// ******** User Bits ********
////
//// 3 TTL Users bits / Camera Link Base
//
//USR_BIT_3_AV equ
//value = OPTION? (! Dual Base ) ;
////
//USR_BIT_4_AV equ
//value = OPTION? (! Dual Base ) ;
////
//USR_BIT_5_AV equ
//value = OPTION? (! Dual Base ) ;
////
USR_ITTL_AV equ
value = ( ! USR_OTTL ) ;
//
USR_OTTL_AV equ
value = ( ! USR_ITTL ) ;
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #5: BOARD LIMITATION DESCRIPTION (A)
// **********************************************
// **********************************************
//
//
//
// =============================================
//
[OPTION_SOLIOS_CL_DUAL]
SOLIOS/CL/DUAL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL yes
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : SOLIOS MODULE CAMERA LINK DUAL BASE
//
//
// =============================================
// SOLIOS/CL/DUAL
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video CAMERA NUMBER format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_CAMERA array 8 0 8 8 0 0 0
//
// ******** Standards of video signal Available ********
// ana dig
// ana dig
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// SOLIOS/CL/DUAL
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 1000000 66000000 1000000 66000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 1000 165000000
//
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// SOLIOS/CL/DUAL
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// SOLIOS/CL/DUAL
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// SOLIOS/CL/DUAL
// ******** Camera Link controls groups ********
//
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV no
CL_CONFIG_FULL_AV no
CL_CHANNEL0_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_HIGH_AV yes
CL_CC1_USROUT_0_LOW_AV yes
CL_CC1_USROUT_1_HIGH_AV yes
CL_CC1_USROUT_1_LOW_AV yes
CL_CC1_PSG_VSYNC_AV yes
CL_CC1_PSG_HSYNC_AV yes
CL_CC1_PCLK_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_HIGH_AV yes
CL_CC2_USROUT_0_LOW_AV yes
CL_CC2_USROUT_1_HIGH_AV yes
CL_CC2_USROUT_1_LOW_AV yes
CL_CC2_PSG_VSYNC_AV yes
CL_CC2_PSG_HSYNC_AV yes
CL_CC2_PCLK_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_HIGH_AV yes
CL_CC3_USROUT_0_LOW_AV yes
CL_CC3_USROUT_1_HIGH_AV yes
CL_CC3_USROUT_1_LOW_AV yes
CL_CC3_PSG_VSYNC_AV yes
CL_CC3_PSG_HSYNC_AV yes
CL_CC3_PCLK_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_HIGH_AV yes
CL_CC4_USROUT_0_LOW_AV yes
CL_CC4_USROUT_1_HIGH_AV yes
CL_CC4_USROUT_1_LOW_AV yes
CL_CC4_PSG_VSYNC_AV yes
CL_CC4_PSG_HSYNC_AV yes
CL_CC4_PCLK_AV yes
//
// --------------------------------------
// SOLIOS/CL/DUAL
// ******** Test module CL ********
//
TM_TESTMODE_AV yes
//
// =============================================
//
[OPTION_SOLIOS_CL_MEDIUM]
SOLIOS/CL/MEDIUM
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM yes
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : SOLIOS MODULE CAMERA LINK FULL
//
//
// --------------------------------------
// SOLIOS/CL/MEDIUM
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Video CAMERA NUMBER format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_CAMERA array 8 0 8 8 0 0 0
//
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// SOLIOS/CL/MEDIUM
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 1000000 66000000 1000000 66000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 1000 165000000
//
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_IN_DELAY_STEP 1
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// SOLIOS/CL/MEDIUM
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// SOLIOS/CL/MEDIUM
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// SOLIOS/CL/MEDIUM
// ******** Camera Link controls groups ********
//
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV yes
CL_CONFIG_FULL_AV no
CL_CHANNEL0_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_HIGH_AV yes
CL_CC1_USROUT_0_LOW_AV yes
CL_CC1_USROUT_1_HIGH_AV yes
CL_CC1_USROUT_1_LOW_AV yes
CL_CC1_PSG_VSYNC_AV yes
CL_CC1_PSG_HSYNC_AV yes
CL_CC1_PCLK_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_HIGH_AV yes
CL_CC2_USROUT_0_LOW_AV yes
CL_CC2_USROUT_1_HIGH_AV yes
CL_CC2_USROUT_1_LOW_AV yes
CL_CC2_PSG_VSYNC_AV yes
CL_CC2_PSG_HSYNC_AV yes
CL_CC2_PCLK_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_HIGH_AV yes
CL_CC3_USROUT_0_LOW_AV yes
CL_CC3_USROUT_1_HIGH_AV yes
CL_CC3_USROUT_1_LOW_AV yes
CL_CC3_PSG_VSYNC_AV yes
CL_CC3_PSG_HSYNC_AV yes
CL_CC3_PCLK_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_HIGH_AV yes
CL_CC4_USROUT_0_LOW_AV yes
CL_CC4_USROUT_1_HIGH_AV yes
CL_CC4_USROUT_1_LOW_AV yes
CL_CC4_PSG_VSYNC_AV yes
CL_CC4_PSG_HSYNC_AV yes
CL_CC4_PCLK_AV yes
//
// --------------------------------------
// SOLIOS/CL/MEDIUM
// ******** Test module CL ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_SOLIOS_SINGLE_ANA]
SOLIOS/ANALOG/SINGLE
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA yes
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY ANALOG MODULE
//
//
// SOLIOS/SINGLE/ANA
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video Bayer Format Available ********
//
CT_BAYER_DISABLE_AV yes
//
CT_BAYER_BG_AV no
//
CT_BAYER_GB_AV no
//
CT_BAYER_GR_AV no
//
CT_BAYER_RG_AV no
//
//
// ******** Video TAPS format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 1 1 0 0 0 0 0
//
CT_MAX_CAMERA array 1 1 0 0 0 0 0
//
// dig ana
CT_MAX_CONNECTORS array 1 1
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS no
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 0 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0
CCOL_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 0 3122
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 1 0
VDC_VID_WIDTH_10_AV array 1 0
VDC_VID_WIDTH_12_AV array 0 0
VDC_VID_WIDTH_14_AV array 0 0
VDC_VID_WIDTH_16_AV array 0 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// SOLIOS/SINGLE/ANA
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 10000 65000000 10000 65000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 10000 210000000
//
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
//
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
PCLK_OUT_HF_MAXVAL 105000000
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// SOLIOS/SINGLE/ANA
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// SOLIOS/SINGLE/ANA
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// SOLIOS/SINGLE/ANA
// ******** Test module ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_SOLIOS_DUAL_ANA]
SOLIOS/ANALOG/DUAL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA yes
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY ANALOG MODULE
//
//
// SOLIOS/DUAL/ANA
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video Bayer Format Available ********
//
CT_BAYER_DISABLE_AV yes
//
CT_BAYER_BG_AV no
//
CT_BAYER_GB_AV no
//
CT_BAYER_GR_AV no
//
CT_BAYER_RG_AV no
//
//
// ******** Video TAPS format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 2 2 0 0 0 0 0
//
CT_MAX_CAMERA array 2 2 0 0 0 0 0
//
// dig ana
CT_MAX_CONNECTORS array 2 2
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS no
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 0 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1
CCOL_INPUT_AVAIL array 0 1
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 0 3122
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 1 0
VDC_VID_WIDTH_10_AV array 1 0
VDC_VID_WIDTH_12_AV array 0 0
VDC_VID_WIDTH_14_AV array 0 0
VDC_VID_WIDTH_16_AV array 0 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// SOLIOS/DUAL/ANA
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 10000 65000000 10000 65000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 10000 210000000
//
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
//
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
PCLK_OUT_HF_MAXVAL 105000000
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// SOLIOS/DUAL/ANA
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// SOLIOS/DUAL/ANA
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// SOLIOS/DUAL/ANA
// ******** Test module ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_SOLIOS_QUAD_ANA]
SOLIOS/ANALOG/QUAD
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA yes
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY ANALOG MODULE
//
//
// SOLIOS/QUAD/ANA
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video Bayer Format Available ********
//
CT_BAYER_DISABLE_AV yes
//
CT_BAYER_BG_AV no
//
CT_BAYER_GB_AV no
//
CT_BAYER_GR_AV no
//
CT_BAYER_RG_AV no
//
//
// ******** Video TAPS format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 4 4 1 1 1 0 0
//
CT_MAX_CAMERA array 4 4 1 1 1 0 0
//
// dig ana
CT_MAX_CONNECTORS array 4 4
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS no
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 0 3122
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 1 0
VDC_VID_WIDTH_10_AV array 1 0
VDC_VID_WIDTH_12_AV array 0 0
VDC_VID_WIDTH_14_AV array 0 0
VDC_VID_WIDTH_16_AV array 0 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// SOLIOS/QUAD/ANA
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 10000 65000000 10000 65000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 10000 210000000
//
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
//
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
PCLK_OUT_HF_MAXVAL 105000000
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// SOLIOS/QUAD/ANA
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// SOLIOS/QUAD/ANA
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// SOLIOS/QUAD/ANA
// ******** Test module ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_SOLIOS_DIG]
SOLIOS/DIGITAL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG yes
//
// Board Type : SOLIOS DIGITAL MODULE
//
//
// SOLIOS/DIG
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL yes
DIG_VID_422 yes
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 0 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// SOLIOS/DIG
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_LVDS_AV yes
PCLK_OUT_RS422_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 0 60000000 0 60000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 0 60000000
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// SOLIOS/DIG
//
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// SOLIOS/DIG
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// SOLIOS/DIG
// ******** Test module Digital ********
//
TM_TESTMODE_AV yes
//
// =============================================
//
[OPTION_HELIOS_CL_DUAL]
HELIOS/CL/DUAL
OPTION_HELIOS_CL_DUAL yes
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : HELIOS MODULE CAMERA LINK DUAL BASE
//
//
// =============================================
// HELIOS/CL/DUAL
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video CAMERA NUMBER format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_CAMERA array 8 0 8 8 0 0 0
//
// ******** Standards of video signal Available ********
// ana dig
// ana dig
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// HELIOS/CL/DUAL
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 1000000 85000000 1000000 85000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 1000 165000000
//
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// HELIOS/CL/DUAL
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// HELIOS/CL/DUAL
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// HELIOS/CL/DUAL
// ******** Camera Link controls groups ********
//
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV no
CL_CONFIG_FULL_AV no
CL_CHANNEL0_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_HIGH_AV yes
CL_CC1_USROUT_0_LOW_AV yes
CL_CC1_USROUT_1_HIGH_AV yes
CL_CC1_USROUT_1_LOW_AV yes
CL_CC1_PSG_VSYNC_AV yes
CL_CC1_PSG_HSYNC_AV yes
CL_CC1_PCLK_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_HIGH_AV yes
CL_CC2_USROUT_0_LOW_AV yes
CL_CC2_USROUT_1_HIGH_AV yes
CL_CC2_USROUT_1_LOW_AV yes
CL_CC2_PSG_VSYNC_AV yes
CL_CC2_PSG_HSYNC_AV yes
CL_CC2_PCLK_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_HIGH_AV yes
CL_CC3_USROUT_0_LOW_AV yes
CL_CC3_USROUT_1_HIGH_AV yes
CL_CC3_USROUT_1_LOW_AV yes
CL_CC3_PSG_VSYNC_AV yes
CL_CC3_PSG_HSYNC_AV yes
CL_CC3_PCLK_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_HIGH_AV yes
CL_CC4_USROUT_0_LOW_AV yes
CL_CC4_USROUT_1_HIGH_AV yes
CL_CC4_USROUT_1_LOW_AV yes
CL_CC4_PSG_VSYNC_AV yes
CL_CC4_PSG_HSYNC_AV yes
CL_CC4_PCLK_AV yes
//
// --------------------------------------
// HELIOS/CL/DUAL
// ******** Test module CL ********
//
TM_TESTMODE_AV yes
//
// =============================================
//
[OPTION_HELIOS_CL_FULL]
HELIOS/CL/FULL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL yes
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : HELIOS MODULE CAMERA LINK FULL
//
//
// --------------------------------------
// HELIOS/CL/FULL
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Video CAMERA NUMBER format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_CAMERA array 8 0 8 8 0 0 0
//
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// HELIOS/CL/FULL
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 1000000 85000000 1000000 85000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 1000 165000000
//
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_IN_DELAY_STEP 1
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// HELIOS/CL/FULL
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// HELIOS/CL/FULL
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// HELIOS/CL/FULL
// ******** Camera Link controls groups ********
//
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV yes
CL_CONFIG_FULL_AV yes
CL_CHANNEL0_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_HIGH_AV yes
CL_CC1_USROUT_0_LOW_AV yes
CL_CC1_USROUT_1_HIGH_AV yes
CL_CC1_USROUT_1_LOW_AV yes
CL_CC1_PSG_VSYNC_AV yes
CL_CC1_PSG_HSYNC_AV yes
CL_CC1_PCLK_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_HIGH_AV yes
CL_CC2_USROUT_0_LOW_AV yes
CL_CC2_USROUT_1_HIGH_AV yes
CL_CC2_USROUT_1_LOW_AV yes
CL_CC2_PSG_VSYNC_AV yes
CL_CC2_PSG_HSYNC_AV yes
CL_CC2_PCLK_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_HIGH_AV yes
CL_CC3_USROUT_0_LOW_AV yes
CL_CC3_USROUT_1_HIGH_AV yes
CL_CC3_USROUT_1_LOW_AV yes
CL_CC3_PSG_VSYNC_AV yes
CL_CC3_PSG_HSYNC_AV yes
CL_CC3_PCLK_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_HIGH_AV yes
CL_CC4_USROUT_0_LOW_AV yes
CL_CC4_USROUT_1_HIGH_AV yes
CL_CC4_USROUT_1_LOW_AV yes
CL_CC4_PSG_VSYNC_AV yes
CL_CC4_PSG_HSYNC_AV yes
CL_CC4_PCLK_AV yes
//
// --------------------------------------
// HELIOS/CL/FULL
// ******** Test module CL ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_HELIOS_ANA]
HELIOS/ANALOG
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA yes
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY ANALOG MODULE
//
//
// HELIOS/ANA
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video Bayer Format Available ********
//
CT_BAYER_DISABLE_AV yes
//
CT_BAYER_BG_AV no
//
CT_BAYER_GB_AV no
//
CT_BAYER_GR_AV no
//
CT_BAYER_RG_AV no
//
//
// ******** Video TAPS format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 4 4 1 1 1 0 0
//
CT_MAX_CAMERA array 4 4 1 1 1 0 0
//
// dig ana
CT_MAX_CONNECTORS array 4 4
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS no
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 0 3122
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 1 0
VDC_VID_WIDTH_10_AV array 1 0
VDC_VID_WIDTH_12_AV array 0 0
VDC_VID_WIDTH_14_AV array 0 0
VDC_VID_WIDTH_16_AV array 0 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// HELIOS/ANA
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 10000 210000000 10000 210000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 10000 210000000
//
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
//
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
PCLK_OUT_HF_MAXVAL 105000000
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// HELIOS/ANA
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// HELIOS/ANA
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// HELIOS/ANA
// ******** Test module ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_HELIOS_DIG]
HELIOS/DIGITAL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG yes
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : HELIOS DIGITAL MODULE
//
//
// HELIOS/DIG
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL yes
DIG_VID_422 yes
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 0 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// HELIOS/DIG
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_LVDS_AV yes
PCLK_OUT_RS422_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 0 60000000 0 60000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 0 60000000
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// HELIOS/DIG
//
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// HELIOS/DIG
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// HELIOS/DIG
// ******** Test module Digital ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_ODYSSEY_CL_DUAL]
ODYSSEY/CL/DUAL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL yes
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY MODULE CAMERA LINK DUAL BASE
//
//
// =============================================
// ODYSSEY/CL/DUAL
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Video CAMERA NUMBER format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_CAMERA array 8 0 8 8 0 0 0
//
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// ODYSSEY/CL/DUAL
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 1000000 85000000 1000000 85000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 1000 165000000
//
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// ODYSSEY/CL/DUAL
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// ODYSSEY/CL/DUAL
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// ODYSSEY/CL/DUAL
// ******** Camera Link controls groups ********
//
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV no
CL_CONFIG_FULL_AV no
CL_CHANNEL0_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_HIGH_AV yes
CL_CC1_USROUT_0_LOW_AV yes
CL_CC1_USROUT_1_HIGH_AV yes
CL_CC1_USROUT_1_LOW_AV yes
CL_CC1_PSG_VSYNC_AV yes
CL_CC1_PSG_HSYNC_AV yes
CL_CC1_PCLK_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_HIGH_AV yes
CL_CC2_USROUT_0_LOW_AV yes
CL_CC2_USROUT_1_HIGH_AV yes
CL_CC2_USROUT_1_LOW_AV yes
CL_CC2_PSG_VSYNC_AV yes
CL_CC2_PSG_HSYNC_AV yes
CL_CC2_PCLK_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_HIGH_AV yes
CL_CC3_USROUT_0_LOW_AV yes
CL_CC3_USROUT_1_HIGH_AV yes
CL_CC3_USROUT_1_LOW_AV yes
CL_CC3_PSG_VSYNC_AV yes
CL_CC3_PSG_HSYNC_AV yes
CL_CC3_PCLK_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_HIGH_AV yes
CL_CC4_USROUT_0_LOW_AV yes
CL_CC4_USROUT_1_HIGH_AV yes
CL_CC4_USROUT_1_LOW_AV yes
CL_CC4_PSG_VSYNC_AV yes
CL_CC4_PSG_HSYNC_AV yes
CL_CC4_PCLK_AV yes
//
// --------------------------------------
// ODYSSEY/CL/DUAL
// ******** Test module CL ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_ODYSSEY_CL_FULL]
ODYSSEY/CL/FULL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL yes
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY MODULE CAMERA LINK
//
//
// =============================================
// ODYSSEY/CL/FULL
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Video CAMERA NUMBER format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_CAMERA array 8 0 8 8 0 0 0
//
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// ODYSSEY/CL/FULL
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 1000000 85000000 1000000 85000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 1000 165000000
//
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// ODYSSEY/CL/FULL
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// ODYSSEY/CL/FULL
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// ODYSSEY/CL/FULL
// ******** Camera Link controls groups ********
//
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV yes
CL_CONFIG_FULL_AV yes
CL_CHANNEL0_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_HIGH_AV yes
CL_CC1_USROUT_0_LOW_AV yes
CL_CC1_USROUT_1_HIGH_AV yes
CL_CC1_USROUT_1_LOW_AV yes
CL_CC1_PSG_VSYNC_AV yes
CL_CC1_PSG_HSYNC_AV yes
CL_CC1_PCLK_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_HIGH_AV yes
CL_CC2_USROUT_0_LOW_AV yes
CL_CC2_USROUT_1_HIGH_AV yes
CL_CC2_USROUT_1_LOW_AV yes
CL_CC2_PSG_VSYNC_AV yes
CL_CC2_PSG_HSYNC_AV yes
CL_CC2_PCLK_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_HIGH_AV yes
CL_CC3_USROUT_0_LOW_AV yes
CL_CC3_USROUT_1_HIGH_AV yes
CL_CC3_USROUT_1_LOW_AV yes
CL_CC3_PSG_VSYNC_AV yes
CL_CC3_PSG_HSYNC_AV yes
CL_CC3_PCLK_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_HIGH_AV yes
CL_CC4_USROUT_0_LOW_AV yes
CL_CC4_USROUT_1_HIGH_AV yes
CL_CC4_USROUT_1_LOW_AV yes
CL_CC4_PSG_VSYNC_AV yes
CL_CC4_PSG_HSYNC_AV yes
CL_CC4_PCLK_AV yes
//
// --------------------------------------
// ODYSSEY/CL/FULL
// ******** Test module CL ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_ODYSSEY_ANA]
ODYSSEY/ANALOG
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA yes
OPTION_ODYSSEY_DIG no
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY ANALOG MODULE
//
//
// ODYSSEY/ANA
//
// ******** Internal PSG Video Signal Ckeck mark option Available ********
//
//
// ******** Video Bayer Format Available ********
//
CT_BAYER_DISABLE_AV yes
//
CT_BAYER_BG_AV no
//
CT_BAYER_GB_AV no
//
CT_BAYER_GR_AV no
//
CT_BAYER_RG_AV no
//
// ******** Video TAPS format ********
//
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 4 4 1 1 1 0 0
//
CT_MAX_CAMERA array 4 4 1 1 1 0 0
//
// dig ana
CT_MAX_CONNECTORS array 4 4
//
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
DIG_VID_LVDS no
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 0 3122
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 1 0
VDC_VID_WIDTH_10_AV array 1 0
VDC_VID_WIDTH_12_AV array 0 0
VDC_VID_WIDTH_14_AV array 0 0
VDC_VID_WIDTH_16_AV array 0 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// ODYSSEY/ANA
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_IN_LVDS_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
PCLK_OUT_LVDS_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
//
// ** Pixel clock frequency limit (in Hz) **
// first two number: normal acqu. freq. limit,
// two next number: high speed freq limit (alternated channel grab)
//
PCLK_FREQ_LIMIT array 10000 210000000 10000 210000000
//
// ** PLL clock frequency limit (in Hz) **
PLL_FREQ_LIMIT array 10000 210000000
//
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
//
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
PCLK_OUT_HF_MAXVAL 105000000
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// ODYSSEY/ANA
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_IN_LVDS_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
HSYN_OUT_LVDS_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_IN_LVDS_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
VSYN_OUT_LVDS_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// ODYSSEY/ANA
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// ODYSSEY/ANA
// ******** Test module ********
//
TM_TESTMODE_AV yes
//
// =============================================
[OPTION_ODYSSEY_DIG]
ODYSSEY/DIGITAL
OPTION_HELIOS_CL_DUAL no
OPTION_HELIOS_CL_FULL no
OPTION_HELIOS_ANA no
OPTION_HELIOS_DIG no
OPTION_ODYSSEY_CL_DUAL no
OPTION_ODYSSEY_CL_FULL no
OPTION_ODYSSEY_ANA no
OPTION_ODYSSEY_DIG yes
OPTION_SOLIOS_CL_DUAL no
OPTION_SOLIOS_CL_MEDIUM no
OPTION_SOLIOS_SINGLE_ANA no
OPTION_SOLIOS_DUAL_ANA no
OPTION_SOLIOS_QUAD_ANA no
OPTION_SOLIOS_DIG no
//
// Board Type : ODYSSEY DIGITAL MODULE
//
//
// ODYSSEY/DIG
//
//
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL no
DIG_VID_AVAIL yes
DIG_VID_TTL yes
DIG_VID_422 yes
DIG_VID_LVDS yes
DIG_VID_OPTO no
//
// ******** Standards of video signal Available ********
// ana dig
MONO_VID_AVAIL array 0 1
RGB_COL_VID_AVAIL array 0 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
//
// ******** Information on input Available ********
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
// ******** Video Bus width Available ********
// ana dig
VID_8BITS array 0 1
VDC_VID_WIDTH_10_AV array 0 1
VDC_VID_WIDTH_12_AV array 0 1
VDC_VID_WIDTH_14_AV array 0 1
VDC_VID_WIDTH_16_AV array 0 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// ODYSSEY/DIG
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV yes
PCLK_IN_LVDS_AV yes
PCLK_IN_RS422_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_LVDS_AV yes
PCLK_OUT_RS422_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 0 60000000 0 60000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 0 60000000
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 10000
PCK_IN_DELAY_MAXVAL 138000
PCK_IN_DELAY_STEP 500
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK ( Generator CLK ) can do (105 MHz)
//
// ******** Pclk output signal availability based on the video type signal ********
// ana dig
PCLK_OUT_HF_MAXVAL 105000000
//
// ** Pclk output signal availability based on the video type signal
// ana dig
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID array 0 0
PCLK_OUT_AV_O_YUV array 0 0
PCLK_OUT_AV_O_MONOHI array 1 1
//
// --------------------------------------
// ODYSSEY/DIG
//
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV yes
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 0
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_LVDS_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_LVDS_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_LVDS_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_LVDS_AV yes
VSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
// --------------------------------------
// ODYSSEY/DIG
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_HW_TRG_LVDS_AV yes
GRAB_HW_TRG_OPTO_AV yes
GRAB_HW_TRG_DEFAULT_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
//GRAB_ACT_NXT_FRM_AV yes
//GRAB_ACT_IMM_AV yes
//GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//
// --------------------------------------
// ODYSSEY/DIG
// ******** Test module Digital ********
//
TM_TESTMODE_AV yes
//
// =============================================
//
//
// **********************************************
// **********************************************
// Section #6 : DEFINE VALUES
// **********************************************
// **********************************************
//
//
// N.B.
// DEFINE using in his equation other DEFINE(S) MUST be placed after these ones.
// Reason: DEFINE value must be updated by intellicam
// DEFINE utilisant dans son equation d'autre(s) DEFINE(s) doit etre toujours place apres ceux-ci.
// Raison : Valeur du DEFINE doit etre update par Intellicam
//
//
[DEFINE_VALUE]
//
// =============================================
// ******** ODYSSEY Board Type ********
//
//DEF_EXPOSENT
//value = ( 1 / ( PCK_FREQ * ( 0.000000001 ) ) ) ;
//
//
//
DEF_ODYSSEY_CL
value = OPTION_ODYSSEY_CL_FULL ;
// --------------------------------------
DEF_ODYSSEY_CL_DUAL
value = OPTION_ODYSSEY_CL_DUAL ;
// --------------------------------------
DEF_ODYSSEY_ANA
value = OPTION_ODYSSEY_ANA ;
// --------------------------------------
DEF_ODYSSEY_DIG
value = OPTION_ODYSSEY_DIG ;
// --------------------------------------
DEF_HELIOS_CL
value = OPTION_HELIOS_CL_FULL ;
// --------------------------------------
DEF_HELIOS_CL_DUAL
value = OPTION_HELIOS_CL_DUAL ;
// --------------------------------------
DEF_HELIOS_ANA
value = OPTION_HELIOS_ANA ;
// --------------------------------------
DEF_HELIOS_DIG
value = OPTION_HELIOS_DIG ;
// --------------------------------------
DEF_SOLIOS_CL
value = OPTION_SOLIOS_CL_MEDIUM ;
// --------------------------------------
DEF_SOLIOS_CL_DUAL
value = OPTION_SOLIOS_CL_DUAL ;
// --------------------------------------
DEF_SOLIOS_ANA
value = ( OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA | OPTION_SOLIOS_QUAD_ANA ) ;
// --------------------------------------
DEF_SOLIOS_DIG
value = OPTION_SOLIOS_DIG ;
// --------------------------------------
//
// ******** Acquisition Controlled Programmed ********
//
//
DEF_AC0_PROGRAMMED
value = VDC_USE_PSG_0 ;
//
DEF_AC1_PROGRAMMED
value = (
VDC_USE_PSG_1 *
(
( VDC_ANA * VDC_MONO * ( CT_TAPS == 0 ) ) |
CAMERA_LINK_AV |
(
VDC_DIG * ( CAMERA_LINK_AV == 0 ) * VDC_MONO *
( ( CT_TAPS == 0 ) | ( ( CT_TAPS == 1 ) * VDC_WD8 ) )
)
)
) ;
//
DEF_AC2_PROGRAMMED
value = (
VDC_USE_PSG_2 *
(
(
VDC_ANA * VDC_MONO *
(
( CT_TAPS == 0 ) | ( ( CT_CAMERA == 0 ) * ( CT_TAPS == 1 ) ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 1 ) )
)
) +
(
VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
(
( ( CT_CAMERA > 1 ) * ( ( CT_TAPS == 0 ) | ( ( CT_TAPS == 1 ) * VDC_WD8 ) ) ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS < 2 ) ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 2 ) * VDC_WD8 ) |
(
( CT_CAMERA == 0 ) *
(
( CT_TAPS == 0 ) | ( ( CT_TAPS == 1 ) * VDC_MONO ) |
( ( CT_TAPS == 2 ) * VDC_WD8 )
)
)
)
)
)
) ;
//
DEF_AC3_PROGRAMMED
value = (
VDC_USE_PSG_3 *
(
(
VDC_ANA * VDC_MONO *
(
( ( CT_CAMERA == 0 ) * ( CT_TAPS == 0 ) ) |
( ( CT_CAMERA == 3 ) * ( CT_TAPS == 0 ) ) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 0 ) )
)
) +
(
VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
(
(
( ( CT_CAMERA == 0 ) | ( CT_CAMERA == 3 ) ) * VDC_MONO *
( ( CT_TAPS == 0 ) | ( ( CT_TAPS == 1 ) * VDC_WD8 ) )
) |
( ( CT_CAMERA == 1 ) * ( CT_TAPS == 0 ) * VDC_MONO )
)
)
)
) ;
//
DEF_AC0_CL_TRG2_TTL_ACTIF
value = (
CAMERA_LINK_AV *
(
( GRB_TRG_TTL * GRB_TRG_2_AC01_TTL_CL ) |
( EXP_TRG_TTL * EXP_0_TRG_2_AC01_TTL_CL ) |
( EXP_ARM_TTL * ARM_EXP_0_TRG_2_AC01_TTL_CL ) |
( EXP_TRG_TTL_2 * EXP_1_TRG_2_AC01_TTL_CL ) |
( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_2_AC01_TTL_CL )
)
) ;
//
DEF_AC1_CL_TRG3_TTL_ACTIF
value = (
CAMERA_LINK_AV *
(
( GRB_TRG_TTL * GRB_TRG_3_AC01_TTL_CL ) |
( EXP_TRG_TTL * EXP_0_TRG_3_AC01_TTL_CL ) |
( EXP_ARM_TTL * ARM_EXP_0_TRG_3_AC01_TTL_CL ) |
( EXP_TRG_TTL_2 * EXP_1_TRG_3_AC01_TTL_CL ) |
( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_3_AC01_TTL_CL )
)
) ;
//
// --------------------------------------
//
// ******** Video Timings entered group ********
//
DEF_HTOTAL_ENTRY
value = ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) ;
// --------------------------------------
DEF_HACTIVE_ENTRY
value = ( DEF_HTOTAL_ENTRY - VDT_HSYNC - VDT_HBPORCH - VDT_HFPORCH ) ;
// --------------------------------------
DEF_VTOTAL_ENTRY
value = ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) ;
// --------------------------------------
DEF_VACTIVE_ENTRY
value = ( DEF_VTOTAL_ENTRY - VDT_VSYNC - VDT_VBPORCH - VDT_VFPORCH ) ;
// --------------------------------------
DEF_HSY_HBP
value = ( VDT_HSYNC + VDT_HBPORCH ) ;
// --------------------------------------
DEF_VSY_VBP
value = ( VDT_VSYNC + VDT_VBPORCH ) ;
// --------------------------------------
//
// ******** Video Format group ********
//
DEF_NTSC
value = (
( ( PCK_FREQ == 12272700 ) * ( VDT_HTOTAL == 780 ) * ( VDT_VTOTAL == 525 ) ) +
( ( PCK_FREQ == 13500000 ) * ( VDT_HTOTAL == 858 ) * ( VDT_VTOTAL == 525 ) )
) ;
// --------------------------------------
DEF_PAL
value = (
( ( PCK_FREQ == 14750000 ) * ( VDT_HTOTAL == 944 ) * ( VDT_VTOTAL == 625 ) ) +
( ( PCK_FREQ == 13500000 ) * ( VDT_HTOTAL == 864 ) * ( VDT_VTOTAL == 625 ) )
) ;
// --------------------------------------
DEF_CCIR601
value = (
( PCK_FREQ == 13500000 ) *
(
( ( VDT_HTOTAL == 858 ) * ( VDT_VTOTAL == 525 ) ) ||
( ( VDT_HTOTAL == 864 ) * ( VDT_VTOTAL == 625 ) )
)
) ;
// --------------------------------------
//
// ******** Video Type group ********
//
DEF_MONO_CAM
value = VDC_MONO ;
// --------------------------------------
DEF_COLOR_CAM
value = ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ;
// --------------------------------------
//
// ******** Hor. Vert. validation group ********
//
DEF_VACTIVE_ODD
value = ( VDT_VACTIVE % 2 ) ;
// --------------------------------------
DEF_VTOTAL_ENTRY_NOTSTD
value = (
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 525 ) *
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 625 )
) ;
// --------------------------------------
DEF_VDELAY_MIN
value = 0 ;
// --------------------------------------
// Vertical Blank = 0 OR Line Scan
//
DEF_VSVAL_EQUA_ZERO
value = ( ( VDT_VSYNC + VDT_VBPORCH - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) == 0 ) ;
// --------------------------------------
// Patch for FPGA : If VBlank = 0 ( VSVAL=0 & VEVAL=VTOTAL ) => HBLANK = 3 CLK MIN { [( HSVAL - 0 ) + ( VDT_HTOTAL - HEVAL )] >= 3 }
// Excepted Line Scan
DEF_VEVAL_EQUA_VTOTAL
value = (
(
(
CT_FS *
(
(
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) *
( ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) <= ( VDT_VTOTAL - 1 ) )
) +
(
( ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) - VDT_VTOTAL ) *
( ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) > ( VDT_VTOTAL - 1 ) )
)
)
) & 0xFFFFF
)
>= ( VDT_VTOTAL - 1 )
) ;
// --------------------------------------
DEF_HDELAY
value = (
VDC_ANA *
(
( 4 * ( TM_ENABLE == 0 ) ) + ( VDC_DIG * 3 * SYC_DIG * SYC_CAM_GEN * ( ! PCK_CAM_GEN ) ) +
( ( SYC_DIG + SYC_CAM_GEN ) * ( PCK_FREQ > 20000000 ) ) +
( VDC_ANA * SYC_DIG * SYC_CAM_GEN * ( TM_ENABLE == 0 ) )
)
) ;
// --------------------------------------
DEF_HCLAMP_MARGIN
value = (
( VDT_CLP_BPO * ( VDT_HBPORCH >= 8 ) * 8 ) +
( VDT_CLP_SYN * ( VDT_HSYNC >= 8 ) * 8 ) +
( VDT_CLP_FPO * ( VDT_HFPORCH >= 8 ) * 8 )
) ;
// --------------------------------------
DEF_MIN_CNT_CLAMP
value = ( VDC_ANA * ( ( PCK_FREQ / 1250000 ) + 0.5 ) ) ;
// --------------------------------------
DEF_DIGITIZER_MASTER
value = ( ( SYC_CAM_GEN == 0 ) | PCK_CAM_REC | PCK_CAM_R&G ) ;
//
//value = ( ( ! SYC_CAM_GEN ) | PCK_CAM_REC | PCK_CAM_R&G | TM_ENABLE ) ;
// --------------------------------------
DEF_ERR_HCLAMP_MIN
value = ( VDC_ANA * ( ! TM_ENABLE ) * ( ! VDC_0_DC_WITHOUT_DC ) *
( ! VDC_1_DC_WITHOUT_DC ) * ( ! VDC_2_DC_WITHOUT_DC ) * ( ! VDC_3_DC_WITHOUT_DC ) *
(
(
(
VDC_ANA *
(
( VDT_CLP_BPO * VDT_HBPORCH ) +
( VDT_CLP_SYN * VDT_HSYNC ) +
( VDT_CLP_FPO * VDT_HFPORCH ) +
( DEF_DIGITIZER_MASTER * SYC_DIG * SYC_CAM_LATENCY )
)
) &
(
( ( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) < (
DEF_MIN_CNT_CLAMP + ( 2 * DEF_HCLAMP_MARGIN ) + 1 +
( SYC_DIG * SYC_CAM_GEN * ( TM_ENABLE == 0 ) * 3 )
)
)
) ;
// --------------------------------------
DEF_CASE_HVBLANK_ZERO
value = (
( ! VDC_ANA ) *
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HFPORCH ) < 3 ) *
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VFPORCH ) == 0 )
) ;
// --------------------------------------
DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO
value = (
DEF_CASE_HVBLANK_ZERO * ( 3 - ( VDT_HSYNC + VDT_HBPORCH + VDT_HFPORCH ) )
) ;
//
// --------------------------------------
DEF_ADD_HTOTAL_EQUA_HEVAL
value = (
(
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) +
( TM_ENABLE * CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID != 0 ) *
( VDT_CL_USE_CAMERA_VALID != 3 )
) - ( ( VDT_HTOTAL * ( VDT_HTOTAL == DEF_HTOTAL_ENTRY ) ) + DEF_HTOTAL_ENTRY )
) *
(
(
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) +
(
TM_ENABLE * CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID != 0 ) *
( VDT_CL_USE_CAMERA_VALID != 3 )
)
) > ( ( ( VDT_HTOTAL - 1 ) * ( VDT_HTOTAL == DEF_HTOTAL_ENTRY ) ) + DEF_HTOTAL_ENTRY )
)
) ;
//
// --------------------------------------
DEF_ERR_NGHECNT_HTOTAL_MIN
value = (
VDC_ANA * ( TM_ENABLE == 0 ) *
(
(
(
( ( ( ( 25000000 / PCK_FREQ ) * DEF_HTOTAL_ENTRY ) - 26 + 0.5 ) <= 0xffff ) *
( ( ( 25000000 / PCK_FREQ ) * DEF_HTOTAL_ENTRY ) - 26 + 0.5 )
) +
(
( ( ( ( 25000000 / PCK_FREQ ) * DEF_HTOTAL_ENTRY ) - 26 + 0.5 ) > 0xffff ) * 0x0000ffff
)
) <= 1
)
) ;
// --------------------------------------
DEF_HFPORCH_MIN_ANA
value = 0 ;
// --------------------------------------
DEF_TEST_MODE_HBP_MIN_ANA
value = ( VDT_HBPORCH < ( VDC_ANA * TM_ENABLE ) ) ;
// --------------------------------------
DEF_TEST_MODE_HFP_MIN
value = (
TM_ENABLE * ( VDT_HFPORCH == 0 ) *
(
( CT_FS * CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID == 0 ) ) |
( VDC_DIG * ( ! CAMERA_LINK_AV ) ) | VDC_ANA
)
) ;
// --------------------------------------
DEF_TEST_MODE_VFP_MIN
value = (
( VDT_VFPORCH < ( VDC_ANA * VDT_NINTRL * TM_ENABLE ) ) |
( ( VDT_VFPORCH == 0 ) * CT_FS * VDC_DIG * CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID == 0 ) * TM_ENABLE )
) ;
// --------------------------------------
DEF_TEST_MODE_HSY_HBP_MIN_CL
value = ( ( VDT_HSYNC + VDT_HBPORCH ) < ( CAMERA_LINK_AV * TM_ENABLE ) ) ;
// --------------------------------------
DEF_TEST_MODE_VBLANK_MIN_ANA
value = (
TM_ENABLE *
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VFPORCH ) < ( 3 * VDC_ANA * VDT_INTERL ) )
) ;
// --------------------------------------
DEF_TEST_MODE_VBLANK_MIN_CL
value = (
TM_ENABLE *
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VFPORCH ) < ( CAMERA_LINK_AV * ( TM_PIXELMODE == 0 ) ) )
) ;
// --------------------------------------
DEF_HSVAL_EQUA_ZERO
value = (
(
(
VDT_HSYNC + VDT_HBPORCH + DEF_HDELAY +
(
DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY
) -
(
SYC_DIG * ( VDC_ANA | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * VDT_HSYNC
)
) &
(
( ( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) <= 0
) ;
// --------------------------------------
DEF_HEVAL_EQUA_HTOTAL
value = (
(
(
(
(
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) - 1
) *
(
(
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) - 1
)
<= ( ( VDT_HTOTAL > 0 ) * ( VDT_HTOTAL - 1 + DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO + DEF_ADD_HTOTAL_EQUA_HEVAL ) )
)
) +
(
( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY )
- VDT_HTOTAL - 1
) *
(
( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY )
- VDT_HTOTAL - 1
)
> ( ( VDT_HTOTAL > 0 ) * ( VDT_HTOTAL - 1 + DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO ) )
)
)
) >=
(
( VDT_HTOTAL > 0 ) * ( VDT_HTOTAL - 1 + DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO + DEF_ADD_HTOTAL_EQUA_HEVAL )
)
) & (
( ( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * 0x00FFFFFF ) +
( VDC_ANA * 0x0000FFFF )
)
) ;
// --------------------------------------
DEF_TIMER0_ENABLED
value = ( EXP_MD_PERD | EXP_MD_W_TRG ) ;
// --------------------------------------
DEF_TIMER1_ENABLED
value = ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ;
//
// --------------------------------------
DEF_TIMER0_FREQ_NO_T1CLK
value = (
(
( EXP_CLK_HS * ( PCK_FREQ / VDT_HTOTAL ) ) +
( EXP_CLK_VS * ( PCK_FREQ / ( VDT_HTOTAL * VDT_VTOTAL ) ) ) +
( EXP_SYN_CLK * PCK_FREQ ) +
( EXP_CLK_CLKGEN * EXP_CLK_FREQ ) +
(
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA |
EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA |
EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ
)
) / ( 2 ^ EXP_CLK_DIVF )
) ;
//
// --------------------------------------
DEF_TIMER1_FREQ_NO_T0CLK
value = (
(
( EXP_CLK_2_HS * ( PCK_FREQ / VDT_HTOTAL ) ) +
( EXP_CLK_2_VS * ( PCK_FREQ / ( VDT_HTOTAL * VDT_VTOTAL ) ) ) +
( EXP_SYN_CLK_2 * PCK_FREQ ) +
( EXP_CLK_2_CLKGEN * EXP_CLK_FREQ_2 ) +
(
(
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA |
EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ_2
)
) / ( 2 ^ EXP_CLK_DVED_2 )
) ;
//
// --------------------------------------
DEF_TIMER0_FREQ
value = (
( ( ! EXP_CLK_TIMER1 ) * DEF_TIMER0_FREQ_NO_T1CLK ) +
(
EXP_CLK_TIMER1 * EXP_MD_PERD_2 *
(
DEF_TIMER1_FREQ_NO_T0CLK /
( ( 2 ^ EXP_CLK_DIVF ) * ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) )
)
) +
(
EXP_CLK_TIMER1 * EXP_MD_W_TRG_2 *
(
( EXP_MD_HSY_2 * VDT_HSYNC_FREQ ) +
( EXP_MD_VSY_2 * VDT_VSYNC_FREQ )
)
)
) ;
//
// --------------------------------------
DEF_TIMER1_FREQ
value = (
( ( ! EXP_CLK_2_TIMER0 ) * DEF_TIMER1_FREQ_NO_T0CLK ) +
(
EXP_CLK_2_TIMER0 * EXP_MD_PERD *
(
DEF_TIMER0_FREQ_NO_T1CLK /
( ( 2 ^ EXP_CLK_DVED_2 ) * ( EXP_OUT_T0 + EXP_OUT_T1 ) )
)
) +
(
EXP_CLK_2_TIMER0 * EXP_MD_W_TRG *
(
( EXP_MD_HSY * VDT_HSYNC_FREQ ) +
( EXP_MD_VSY * VDT_VSYNC_FREQ )
)
)
) ;
//
// --------------------------------------
DEF_TIMER0_T1CLK_PERD_FREQ
value = (
( ! ( EXP_MD_PERD_2 * EXP_TRG_TIMER1 ) ) |
(
( EXP_MD_PERD_2 * EXP_TRG_TIMER1 ) *
(
(
( EXP_SYN_CLK_2 * PCK_FREQ ) +
( EXP_CLK_2_CLKGEN * EXP_CLK_FREQ_2 ) +
( EXP_CLK_2_HS * VDT_HSYNC_FREQ ) +
( EXP_CLK_2_VS *
( ( VDT_VSYNC_FREQ * 2 * VDT_INTERL ) + ( VDT_VSYNC_FREQ * VDT_NINTRL ) )
) +
(
(
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA |
EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ_2
)
) /
(
( 2 ^ EXP_CLK_DIVF ) * ( 2 ^ EXP_CLK_DVED_2 ) *
(
(
( EXP_OUT_T0_2 + EXP_OUT_T1_2 + EXP_OUT_T2_2 + EXP_OUT_T3_2 ) *
(
( ( EXP_OUT_T1_2 > 0 ) * ( EXP_OUT_T3_2 == 0 ) ) |
( ( EXP_OUT_T1_2 == 0 ) * ( EXP_OUT_T3_2 > 0 ) )
)
) |
(
( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) * ( EXP_OUT_T1_2 > 0 ) *
(
( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) < ( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) ) |
( ( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) == 0 ) |
( ( EXP_OUT_T0_2 == EXP_OUT_T2_2 ) * ( EXP_OUT_T1_2 == EXP_OUT_T3_2 ) )
)
) |
(
( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) * ( EXP_OUT_T3_2 > 0 ) *
(
( ( EXP_OUT_T2_2 + EXP_OUT_T3_2 ) < ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) ) |
( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) == 0 )
)
)
)
)
)
)
) ;
// --------------------------------------
DEF_TIMER1_T0CLK_PERD_FREQ
value = (
( ! ( EXP_MD_PERD * EXP_TRG_TIMER0_2 ) ) |
(
( EXP_MD_PERD * EXP_TRG_TIMER0_2 ) *
(
(
( EXP_SYN_CLK * PCK_FREQ ) +
( EXP_CLK_CLKGEN * EXP_CLK_FREQ ) +
( EXP_CLK_HS * VDT_HSYNC_FREQ ) +
( EXP_CLK_VS *
( ( VDT_VSYNC_FREQ * 2 * VDT_INTERL ) + ( VDT_VSYNC_FREQ * VDT_NINTRL ) )
) +
(
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL |
EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA |
EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA |
EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ
)
) /
(
( 2 ^ EXP_CLK_DVED_2 ) * ( 2 ^ EXP_CLK_DIVF ) *
(
(
( EXP_OUT_T0 + EXP_OUT_T1 + EXP_OUT_T2 + EXP_OUT_T3 ) *
(
( ( EXP_OUT_T1 > 0 ) * ( EXP_OUT_T3 == 0 ) ) |
( ( EXP_OUT_T1 == 0 ) * ( EXP_OUT_T3 > 0 ) )
)
) |
(
( EXP_OUT_T0 + EXP_OUT_T1 ) * ( EXP_OUT_T1 > 0 ) *
(
( ( EXP_OUT_T0 + EXP_OUT_T1 ) < ( EXP_OUT_T2 + EXP_OUT_T3 ) ) |
( ( EXP_OUT_T2 + EXP_OUT_T3 ) == 0 ) |
( ( EXP_OUT_T0 == EXP_OUT_T2 ) * ( EXP_OUT_T1 == EXP_OUT_T3 ) )
)
) |
(
( EXP_OUT_T2 + EXP_OUT_T3 ) * ( EXP_OUT_T3 > 0 ) *
(
( ( EXP_OUT_T2 + EXP_OUT_T3 ) < ( EXP_OUT_T0 + EXP_OUT_T1 ) ) |
( ( EXP_OUT_T0 + EXP_OUT_T1 ) == 0 )
)
)
)
)
)
)
) ;
// --------------------------------------
DEF_TMR0_CLKFREQ<=TRGFREQ
value = ( DEF_TIMER0_ENABLED * EXP_MD_W_TRG *
(
(
DEF_TIMER0_FREQ / ( EXP_OUT_T0 + EXP_OUT_T1 + EXP_OUT_T2 + EXP_OUT_T3 )
) <
(
( EXP_MD_HSY * ( VDT_HSYNC_FREQ ) ) +
( EXP_MD_VSY * ( VDT_VSYNC_FREQ ) ) +
(
EXP_TRG_TIMER1 *
(
( EXP_MD_PERD_2 * ( DEF_TIMER1_FREQ / ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) ) ) +
(
EXP_MD_W_TRG_2 *
(
( EXP_MD_HSY_2 * VDT_HSYNC_FREQ ) +
( EXP_MD_VSY_2 * VDT_VSYNC_FREQ )
)
)
)
)
)
)
) ;
//
//value = ( DEF_TIMER0_ENABLED * EXP_MD_W_TRG *
// (
// EXP_CLK_FREQ <
// (
// ( EXP_MD_HSY * VDT_HSYNC_FREQ ) +
// ( EXP_MD_VSY * VDT_VSYNC_FREQ ) +
// (
// EXP_TRG_TIMER1 *
// (
// ( EXP_MD_PERD_2 * DEF_TIMER0_T1CLK_PERD_FREQ ) +
// (
// EXP_MD_W_TRG_2 *
// (
// ( EXP_MD_HSY_2 * VDT_HSYNC_FREQ ) +
// ( EXP_MD_VSY_2 * VDT_VSYNC_FREQ )
// )
// )
// )
// )
// )
// )
// ) ;
// --------------------------------------
DEF_TMR1_CLKFREQ<=TRGFREQ
value = ( DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 *
(
(
DEF_TIMER1_FREQ / ( EXP_OUT_T0_2 + EXP_OUT_T1_2 + EXP_OUT_T2_2 + EXP_OUT_T3_2 )
) <
(
( EXP_MD_HSY_2 * ( VDT_HSYNC_FREQ ) ) +
( EXP_MD_VSY_2 * ( VDT_VSYNC_FREQ ) ) +
(
EXP_TRG_TIMER0_2 *
(
( EXP_MD_PERD * ( DEF_TIMER0_FREQ / ( EXP_OUT_T0 + EXP_OUT_T1 ) ) ) +
(
EXP_MD_W_TRG *
(
( EXP_MD_HSY * VDT_HSYNC_FREQ ) +
( EXP_MD_VSY * VDT_VSYNC_FREQ )
)
)
)
)
)
)
) ;
//
//value = ( DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 *
// (
// EXP_CLK_FREQ_2 <
// (
// ( EXP_MD_HSY_2 * VDT_HSYNC_FREQ ) +
// ( EXP_MD_VSY_2 * VDT_VSYNC_FREQ ) +
// (
// EXP_TRG_TIMER0_2 *
// (
// ( EXP_MD_PERD * DEF_TIMER1_T0CLK_PERD_FREQ ) +
// (
// EXP_MD_W_TRG *
// (
// ( EXP_MD_HSY * VDT_HSYNC_FREQ ) +
// ( EXP_MD_VSY * VDT_VSYNC_FREQ )
// )
// )
// )
// )
// )
// )
// ) ;
// --------------------------------------
DEF_TIMER0_TRIGGERS_PIPE_DELAY
value = (
(
2 * DEF_TIMER0_ENABLED * EXP_MD_W_TRG * EXP_TRG_TIMER1 *
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL |
EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA |
EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA |
EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
)
) +
( 3 * DEF_TIMER0_ENABLED * EXP_MD_W_TRG *
(
(
(
EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL |
EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
) *
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_3_AC01_TTL_CL |
EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL | EXP_0_TRG_0_AC0_TTL_ANA | EXP_0_TRG_0_AC1_TTL_ANA |
EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL |
EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL | EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG |
EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG | EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG |
EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG | EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG |
EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG |
EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
)
) |
(
( EXP_CLK_HS | EXP_CLK_TIMER1 ) * ( EXP_MD_VSY )
) |
(
(
EXP_CLK_TIMER1 | EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL |
EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
) *
(
EXP_MD_HSY | EXP_MD_VSY | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_1_AC0_TTL_CL |
EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_3_AC01_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL |
EXP_0_TRG_0_AC0_TTL_ANA | EXP_0_TRG_0_AC1_TTL_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA |
EXP_0_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL |
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
)
) |
( EXP_CLK_CLKGEN * EXP_MD_HSY )
)
) +
( 4 * DEF_TIMER0_ENABLED * EXP_MD_W_TRG *
(
(
EXP_CLK_TIMER1 *
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG
)
) |
( ( EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS ) * EXP_TRG_TIMER1 ) |
(
EXP_SYN_CLK *
(
EXP_MD_HSY | EXP_MD_VSY | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_1_AC0_TTL_CL |
EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_3_AC01_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL |
EXP_0_TRG_0_AC0_TTL_ANA | EXP_0_TRG_0_AC1_TTL_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA |
EXP_0_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL |
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER |
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
EXP_CLK_CLKGEN *
(
EXP_MD_VSY | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_2_AC01_TTL_CL |
EXP_0_TRG_3_AC01_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL | EXP_0_TRG_0_AC0_TTL_ANA |
EXP_0_TRG_0_AC1_TTL_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
EXP_0_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA |
EXP_0_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
)
)
) +
( 5 * DEF_TIMER0_ENABLED * EXP_MD_W_TRG *
(
(
( EXP_CLK_CLKGEN ) *
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL |
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
)
) |
(
EXP_SYN_CLK *
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG
)
)
)
)
) ;
// --------------------------------------
DEF_TIMER1_TRIGGERS_PIPE_DELAY
value = (
(
2 * DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 * EXP_TRG_TIMER0_2 *
(
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL |
EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA |
EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG |
EXP_CLK_2_AUXIN2_AC2_DIG | EXP_CLK_2_AUXIN2_AC3_DIG
)
) +
( 3 * DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 *
(
(
(
EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_AUXIN1_AC0_CL |
EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA |
EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG |
EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG | EXP_CLK_2_AUXIN2_AC3_DIG
) *
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_3_AC01_TTL_CL |
EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL | EXP_1_TRG_0_AC0_TTL_ANA | EXP_1_TRG_0_AC1_TTL_ANA |
EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA | EXP_1_TRG_2_4AC_AUX0_TTL_ANA | EXP_1_TRG_2_4AC_AUX2_TTL_ANA |
EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_TTL_ANA | EXP_1_TRG_3_4AC_AUX3_TTL_ANA |
EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA | EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL |
EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_3_AC01_LVDS_CL | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG |
EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG | EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG |
EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG | EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG |
EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG |
EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) |
( ( EXP_CLK_2_HS | EXP_CLK_2_TIMER0 ) * ( EXP_MD_VSY_2 ) ) |
(
(
EXP_CLK_2_TIMER0 | EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL |
EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG |
EXP_CLK_2_AUXIN2_AC2_DIG | EXP_CLK_2_AUXIN2_AC3_DIG
) *
(
EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_1_AC0_TTL_CL |
EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_3_AC01_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL |
EXP_1_TRG_0_AC0_TTL_ANA | EXP_1_TRG_0_AC1_TTL_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA |
EXP_1_TRG_2_4AC_AUX0_TTL_ANA | EXP_1_TRG_2_4AC_AUX2_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_TTL_ANA | EXP_1_TRG_3_4AC_AUX3_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA |
EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) |
( EXP_CLK_2_CLKGEN * EXP_MD_HSY_2 )
)
) +
( 4 * DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 *
(
(
EXP_CLK_2_TIMER0 *
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG
)
) |
(
( EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS ) * EXP_TRG_TIMER0_2
) |
(
EXP_SYN_CLK_2 *
(
EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_1_AC0_TTL_CL |
EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_3_AC01_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL |
EXP_1_TRG_0_AC0_TTL_ANA | EXP_1_TRG_0_AC1_TTL_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA |
EXP_1_TRG_2_4AC_AUX0_TTL_ANA | EXP_1_TRG_2_4AC_AUX2_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_TTL_ANA | EXP_1_TRG_3_4AC_AUX3_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA |
EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER |
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
EXP_CLK_2_CLKGEN &
(
EXP_MD_VSY_2 | EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_2_AC01_TTL_CL |
EXP_1_TRG_3_AC01_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL | EXP_1_TRG_0_AC0_TTL_ANA |
EXP_1_TRG_0_AC1_TTL_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA | EXP_1_TRG_2_4AC_AUX0_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
)
)
) +
( 5 * DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 *
(
(
( EXP_CLK_2_CLKGEN ) *
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) |
(
EXP_SYN_CLK_2 *
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG
)
)
)
)
) ;
// --------------------------------------
DEF_TIMER0_TRIG_INVERTED_POL
value = (
(
EXP_TRG_OPTO *
(
( ! EXP_MD_HSY ) * ( ! EXP_MD_VSY ) * ( ! EXP_MD_SW ) *
( ! EXP_TRG_TIMER1 ) * ( ! EXP_TRG_TIMER0_2 )
)
) |
(
VDC_ANA * SYC_DIG * ( ( EXP_MD_HSY * SYC_H_IPOS ) | ( EXP_MD_VSY * SYC_V_IPOS ) )
)
) ;
// --------------------------------------
DEF_TIMER1_TRIG_INVERTED_POL
value = (
(
EXP_TRG_OPTO_2 *
(
( ! EXP_MD_HSY_2 ) * ( ! EXP_MD_VSY_2 ) * ( ! EXP_MD_SW_2 ) *
( ! EXP_TRG_TIMER1 ) * ( ! EXP_TRG_TIMER0_2 )
)
) |
(
VDC_ANA * SYC_DIG * ( ( EXP_MD_HSY_2 * SYC_H_IPOS ) | ( EXP_MD_VSY_2 * SYC_V_IPOS ) )
)
) ;
//
// --------------------------------------
//
// ******** Video Input Channel Section ********
//
DEF_HW_CHANNEL_USED
value = ( VDC_USE_PSG_0 + ( VDC_USE_PSG_1 * 2 ) + ( VDC_USE_PSG_2 * 4 ) + ( VDC_USE_PSG_3 * 8 ) ) ;
//
// --------------------------------------
//
// ******** Video Analog Section ********
//
DEF_ATTENUATOR
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
// --------------------------------------
DEF_CODE_GAIN
value = (
(
(
( 1024000 * DEF_ATTENUATOR ) /
(
VDL_AMPL - ( VDL_USE_DEFVAL * ( VDT_HSYNC_FREQ > 15713 ) * ( VDT_HSYNC_FREQ < 15755 ) * 40 ) -
( ( ! VDL_USE_DEFVAL ) * VDL_PEDEST * VDL_PED_AMP )
)
) + 0.5
) & 0xfff
) ;
// --------------------------------------
DEF_CODE_OFFSET
// SYNC. = 0.286 V (586) 0.300 V (614)
// DC Offset from OP Amplifiers => 0x4D or 77 Removed when Boards calibrated
//
value = (
(
( VDL_POS_SWG *
( 2048 + ( VDT_CLP_SYN * 586 ) +
( VDL_USE_DEFVAL * ( VDT_HSYNC_FREQ > 15713 ) * ( VDT_HSYNC_FREQ < 15755 ) * 0x6f ) ) +
( ( ! VDL_USE_DEFVAL ) * VDL_PEDEST *
( ( ( 2048 * VDL_PED_AMP ) / 1000 ) + 0.5 )
)
) +
(
VDL_NEG_SWG *
( 2048 - ( VDT_CLP_SYN * 586 ) )
)
) & 0xfff
) ;
//
// --------------------------------------
//
// ******** Valid defines group ********
//
DEF_CL_BUS_WIDTH
value = (
CAMERA_LINK_AV *
(
(
(
( CLC_MODE_CH0 == 2 ) | ( CLC_MODE_CH0 == 5 ) | ( CLC_MODE_CH0 == 6 ) |
( CLC_MODE_CH0 == 7 ) | ( CLC_MODE_CH0 == 0xB ) | ( CLC_MODE_CH0 == 0xC ) |
( CLC_MODE_CH0 == 0xF ) | ( CLC_MODE_CH0 == 0x10 )
) * 8
) +
(
(
( CLC_MODE_CH0 == 3 ) | ( CLC_MODE_CH0 == 8 ) | ( CLC_MODE_CH0 == 0xA ) |
( CLC_MODE_CH0 == 0xD )
) * 12
) +
(
(
( CLC_MODE_CH0 == 4 ) | ( CLC_MODE_CH0 == 9 ) | ( CLC_MODE_CH0 == 0xE ) |
( CLC_MODE_CH0 == 0x11 )
) * 16
)
)
) ;
// --------------------------------------
DEF_CL_NUM_TAPS
value = (
CAMERA_LINK_AV *
(
(
( CLC_MODE_CH0 == 1 ) | ( CLC_MODE_CH0 == 5 ) | ( CLC_MODE_CH0 == 0xA ) |
( CLC_MODE_CH0 == 0xB ) | ( CLC_MODE_CH0 == 0xE )
) +
(
(
( CLC_MODE_CH0 == 2 ) | ( CLC_MODE_CH0 == 3 ) | ( CLC_MODE_CH0 == 4 ) |
( CLC_MODE_CH0 == 6 ) | ( CLC_MODE_CH0 == 9 )
) * 2
) +
(
(
( CLC_MODE_CH0 == 7 ) | ( CLC_MODE_CH0 == 8 ) | ( CLC_MODE_CH0 == 0xC ) |
( CLC_MODE_CH0 == 0xD ) | ( CLC_MODE_CH0 == 0x11 )
) * 4
) +
(
( CLC_MODE_CH0 == 0xB ) * 6
) +
(
(
( CLC_MODE_CH0 == 0xF ) | ( CLC_MODE_CH0 == 0x10 )
) * 8
)
)
) ;
// --------------------------------------
DEF_ERR_BUS_WIDTH
value = (
(
CAMERA_LINK_AV *
(
(
VDC_WD8 *
(
( CLC_MODE_CH0 == 3 ) | ( CLC_MODE_CH0 == 4 ) | ( CLC_MODE_CH0 == 8 ) |
( CLC_MODE_CH0 == 9 ) | ( CLC_MODE_CH0 == 0xA ) | ( CLC_MODE_CH0 == 0xD ) |
( CLC_MODE_CH0 == 0xE )
)
) +
(
( VDC_VID_WIDTH_10 | VDC_VID_WIDTH_12 ) *
(
( CLC_MODE_CH0 != 1 ) * ( CLC_MODE_CH0 != 3 ) * ( CLC_MODE_CH0 != 8 ) *
( CLC_MODE_CH0 != 0xA ) * ( CLC_MODE_CH0 != 0xD )
)
) +
(
( VDC_VID_WIDTH_14 | VDC_VID_WIDTH_16 | VDC_WD16 ) *
(
( CLC_MODE_CH0 != 1 ) * ( CLC_MODE_CH0 != 4 ) * ( CLC_MODE_CH0 != 9 ) *
( CLC_MODE_CH0 != 0xE )
)
)
)
) +
(
VDC_ANA *
( ( ! VDC_WD8 ) * ( ! VDC_VID_WIDTH_10 ) )
)
) ;
// --------------------------------------
DEF_GRAB_PSG_CHANGE_ERROR
value = (
(
( ! VDC_USE_PSG_0 ) *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_0_AC0_TTL_CL | GRB_TRG_1_AC0_TTL_CL |
GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_0_AC0_TTL_ANA |
GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_1_AC0_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_1 ) *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
GRB_TRG_0_AC1_TTL_CL | GRB_TRG_1_AC1_TTL_CL | GRB_TRG_1_AC1_OPTO_ANA | GRB_TRG_0_AC1_TTL_ANA |
GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_1_AC1_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_2 ) *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG |
GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_1_AC2_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_3 ) *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
GRB_TRG_1_AC3_OPTO_ANA | GRB_TRG_0_AC3_TTL_ANA | GRB_TRG_0_AC3_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG |
GRB_TRG_0_AC3_LVDS_DIG | GRB_TRG_1_AC3_TTL_DIG
)
)
) ;
// --------------------------------------
DEF_EXP0_PSG_CHANGE_ERROR
value = (
(
( ! VDC_USE_PSG_0 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_1_AC0_TTL_CL |
EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_0_AC0_TTL_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_1_AC0_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_1 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_0_AC1_TTL_ANA |
EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_1_AC1_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_2 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG |
EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_1_AC2_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_3 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
EXP_0_TRG_1_AC3_OPTO_ANA | EXP_0_TRG_0_AC3_TTL_ANA | EXP_0_TRG_0_AC3_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG |
EXP_0_TRG_0_AC3_LVDS_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
)
) ;
// --------------------------------------
DEF_ARM_EXP0_PSG_CHANGE_ERROR
value = (
(
( ! VDC_USE_PSG_0 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
ARM_EXP_0_TRG_0_AC0_OPTO_CL | ARM_EXP_0_TRG_1_AC0_OPTO_CL | ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC0_TTL_CL |
ARM_EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC0_OPTO_ANA | ARM_EXP_0_TRG_0_AC0_TTL_ANA |
ARM_EXP_0_TRG_0_AC0_OPTO_DIG | ARM_EXP_0_TRG_1_AC0_OPTO_DIG | ARM_EXP_0_TRG_0_AC0_LVDS_DIG | ARM_EXP_0_TRG_1_AC0_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_1 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
ARM_EXP_0_TRG_0_AC1_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL | ARM_EXP_0_TRG_1_AC1_OPTO_ANA | ARM_EXP_0_TRG_0_AC1_TTL_ANA |
ARM_EXP_0_TRG_0_AC1_OPTO_DIG | ARM_EXP_0_TRG_1_AC1_OPTO_DIG | ARM_EXP_0_TRG_0_AC1_LVDS_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_2 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
ARM_EXP_0_TRG_1_AC2_OPTO_ANA | ARM_EXP_0_TRG_0_AC2_TTL_ANA | ARM_EXP_0_TRG_0_AC2_OPTO_DIG | ARM_EXP_0_TRG_1_AC2_OPTO_DIG |
ARM_EXP_0_TRG_0_AC2_LVDS_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_3 ) * EXP_MD_W_TRG *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
ARM_EXP_0_TRG_1_AC3_OPTO_ANA | ARM_EXP_0_TRG_0_AC3_TTL_ANA | ARM_EXP_0_TRG_0_AC3_OPTO_DIG | ARM_EXP_0_TRG_1_AC3_OPTO_DIG |
ARM_EXP_0_TRG_0_AC3_LVDS_DIG | ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
)
) ;
// --------------------------------------
DEF_EXP1_PSG_CHANGE_ERROR
value = (
(
( ! VDC_USE_PSG_0 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_1_AC0_TTL_CL |
EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_0_AC0_TTL_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_1_AC0_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_1 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_0_AC1_TTL_ANA |
EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_1_AC1_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_2 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG |
EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_1_AC2_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_3 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
EXP_1_TRG_1_AC3_OPTO_ANA | EXP_1_TRG_0_AC3_TTL_ANA | EXP_1_TRG_0_AC3_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG |
EXP_1_TRG_0_AC3_LVDS_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
)
) ;
// --------------------------------------
DEF_ARM_EXP1_PSG_CHANGE_ERROR
value = (
(
( ! VDC_USE_PSG_0 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
ARM_EXP_1_TRG_0_AC0_OPTO_CL | ARM_EXP_1_TRG_1_AC0_OPTO_CL | ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC0_TTL_CL |
ARM_EXP_1_TRG_0_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC0_OPTO_ANA | ARM_EXP_1_TRG_0_AC0_TTL_ANA |
ARM_EXP_1_TRG_0_AC0_OPTO_DIG | ARM_EXP_1_TRG_1_AC0_OPTO_DIG | ARM_EXP_1_TRG_0_AC0_LVDS_DIG | ARM_EXP_1_TRG_1_AC0_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_1 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) *
(
ARM_EXP_1_TRG_0_AC1_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL | ARM_EXP_1_TRG_1_AC1_OPTO_ANA | ARM_EXP_1_TRG_0_AC1_TTL_ANA |
ARM_EXP_1_TRG_0_AC1_OPTO_DIG | ARM_EXP_1_TRG_1_AC1_OPTO_DIG | ARM_EXP_1_TRG_0_AC1_LVDS_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_2 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
ARM_EXP_1_TRG_1_AC2_OPTO_ANA | ARM_EXP_1_TRG_0_AC2_TTL_ANA | ARM_EXP_1_TRG_0_AC2_OPTO_DIG | ARM_EXP_1_TRG_1_AC2_OPTO_DIG |
ARM_EXP_1_TRG_0_AC2_LVDS_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG
)
) |
(
( ! VDC_USE_PSG_3 ) * EXP_MD_W_TRG_2 *
(
( VDC_MONO * VDC_ANA ) |
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG )
) *
(
ARM_EXP_1_TRG_1_AC3_OPTO_ANA | ARM_EXP_1_TRG_0_AC3_TTL_ANA | ARM_EXP_1_TRG_0_AC3_OPTO_DIG | ARM_EXP_1_TRG_1_AC3_OPTO_DIG |
ARM_EXP_1_TRG_0_AC3_LVDS_DIG | ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
) ;
// --------------------------------------
DEF_ERR_INTERNAL_TRG0_2_FORMATS_SEL
value = (
(
CAMERA_LINK_AV *
( GRB_TRG_TTL | EXP_TRG_TTL | EXP_ARM_TTL | EXP_TRG_TTL_2 | EXP_ARM_TTL_2 ) *
( ! (
GRB_TRG_VS_PSG | GRB_TRG_TIMER0 | GRB_TRG_TIMER1 | EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW |
ARM_EXP_0_CNTEQ0 | ARM_EXP_0_SOFTWARE | ARM_EXP_0_TIMER1 | ARM_EXP_0_HS_PSG | ARM_EXP_0_VS_PSG |
EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 | ARM_EXP_1_CNTEQ0 | ARM_EXP_1_SOFTWARE |
ARM_EXP_1_TIMER0 | ARM_EXP_1_HS_PSG | ARM_EXP_1_VS_PSG | GRB_TRG_HS_PSG
)
) *
(
GRB_TRG_0_AC0_OPTO_CL | EXP_0_TRG_0_AC0_OPTO_CL | ARM_EXP_0_TRG_0_AC0_OPTO_CL |
EXP_1_TRG_0_AC0_OPTO_CL | ARM_EXP_1_TRG_0_AC0_OPTO_CL |
GRB_TRG_0_AC0_LVDS_CL | EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_0_AC0_LVDS_CL |
EXP_1_TRG_0_AC0_LVDS_CL | ARM_EXP_1_TRG_0_AC0_LVDS_CL | GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER |
GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER
)
) |
(
( CAMERA_LINK_AV | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_0_AC0_OPTO_CL | EXP_0_TRG_0_AC0_OPTO_CL | ARM_EXP_0_TRG_0_AC0_OPTO_CL | EXP_1_TRG_0_AC0_OPTO_CL |
ARM_EXP_1_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_0_AC2_OPTO_DIG |
GRB_TRG_0_AC3_OPTO_DIG | EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG |
EXP_0_TRG_0_AC3_OPTO_DIG | ARM_EXP_0_TRG_0_AC0_OPTO_DIG | ARM_EXP_0_TRG_0_AC1_OPTO_DIG | ARM_EXP_0_TRG_0_AC2_OPTO_DIG |
ARM_EXP_0_TRG_0_AC3_OPTO_DIG | EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG |
EXP_1_TRG_0_AC3_OPTO_DIG | ARM_EXP_1_TRG_0_AC0_OPTO_DIG | ARM_EXP_1_TRG_0_AC1_OPTO_DIG | ARM_EXP_1_TRG_0_AC2_OPTO_DIG |
ARM_EXP_1_TRG_0_AC3_OPTO_DIG
) *
(
GRB_TRG_0_AC0_LVDS_CL | EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_0_AC0_LVDS_CL | EXP_1_TRG_0_AC0_LVDS_CL |
ARM_EXP_1_TRG_0_AC0_LVDS_CL |
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG |
GRB_TRG_0_AC3_LVDS_DIG | EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG |
EXP_0_TRG_0_AC3_LVDS_DIG | ARM_EXP_0_TRG_0_AC0_LVDS_DIG | ARM_EXP_0_TRG_0_AC1_LVDS_DIG | ARM_EXP_0_TRG_0_AC2_LVDS_DIG |
ARM_EXP_0_TRG_0_AC3_LVDS_DIG | EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG |
EXP_1_TRG_0_AC3_LVDS_DIG | ARM_EXP_1_TRG_0_AC0_LVDS_DIG | ARM_EXP_1_TRG_0_AC1_LVDS_DIG | ARM_EXP_1_TRG_0_AC2_LVDS_DIG |
ARM_EXP_1_TRG_0_AC3_LVDS_DIG
)
)
) ;
//
//value = (
// (
// CAMERA_LINK_AV *
// (
// GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC1_OPTO_CL | EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_0_AC1_OPTO_CL |
// ARM_EXP_0_TRG_0_AC0_OPTO_CL | ARM_EXP_0_TRG_0_AC1_OPTO_CL | EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_0_AC1_OPTO_CL |
// ARM_EXP_1_TRG_0_AC0_OPTO_CL | ARM_EXP_1_TRG_0_AC1_OPTO_CL
// ) *
// (
// GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_0_AC1_LVDS_CL | EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_0_AC1_LVDS_CL |
// ARM_EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_0_AC1_LVDS_CL | EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_0_AC1_LVDS_CL |
// ARM_EXP_1_TRG_0_AC0_LVDS_CL | ARM_EXP_1_TRG_0_AC1_LVDS_CL
// )
// ) |
// (
// VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
// (
// GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG |
// GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_0_AC3_OPTO_DIG | EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG |
// EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG | ARM_EXP_0_TRG_0_AC0_OPTO_DIG | ARM_EXP_0_TRG_0_AC1_OPTO_DIG |
// ARM_EXP_0_TRG_0_AC2_OPTO_DIG | ARM_EXP_0_TRG_0_AC3_OPTO_DIG | EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG |
// EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG | ARM_EXP_1_TRG_0_AC0_OPTO_DIG | ARM_EXP_1_TRG_0_AC1_OPTO_DIG |
// ARM_EXP_1_TRG_0_AC2_OPTO_DIG | ARM_EXP_1_TRG_0_AC3_OPTO_DIG
// ) *
// (
// GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG |
// GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG | EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG |
// EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC3_LVDS_DIG | ARM_EXP_0_TRG_0_AC0_LVDS_DIG | ARM_EXP_0_TRG_0_AC1_LVDS_DIG |
// ARM_EXP_0_TRG_0_AC2_LVDS_DIG | ARM_EXP_0_TRG_0_AC3_LVDS_DIG | EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG |
// EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC3_LVDS_DIG | ARM_EXP_1_TRG_0_AC0_LVDS_DIG | ARM_EXP_1_TRG_0_AC1_LVDS_DIG |
// ARM_EXP_1_TRG_0_AC2_LVDS_DIG | ARM_EXP_1_TRG_0_AC3_LVDS_DIG
// )
// )
// ) ;
//
// --------------------------------------
DEF_ERR_INTERNAL_TRG1_2_FORMATS_SEL
value = (
(
CAMERA_LINK_AV *
( GRB_TRG_TTL | EXP_TRG_TTL | EXP_ARM_TTL | EXP_TRG_TTL_2 | EXP_ARM_TTL_2 ) *
( ! (
GRB_TRG_VS_PSG | GRB_TRG_TIMER0 | GRB_TRG_TIMER1 | EXP_MD_HSY | EXP_MD_VSY | EXP_MD_SW |
ARM_EXP_0_CNTEQ0 | ARM_EXP_0_SOFTWARE | ARM_EXP_0_TIMER1 | ARM_EXP_0_HS_PSG | ARM_EXP_0_VS_PSG |
EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_MD_SW_2 | ARM_EXP_1_CNTEQ0 | ARM_EXP_1_SOFTWARE |
ARM_EXP_1_TIMER0 | ARM_EXP_1_HS_PSG | ARM_EXP_1_VS_PSG | GRB_TRG_HS_PSG
)
) *
(
GRB_TRG_1_AC0_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_CL | ARM_EXP_0_TRG_1_AC0_OPTO_CL |
EXP_1_TRG_1_AC0_OPTO_CL | ARM_EXP_1_TRG_1_AC0_OPTO_CL |
GRB_TRG_1_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC0_LVDS_CL |
EXP_1_TRG_1_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC0_LVDS_CL |
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG |
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG | ARM_EXP_0_TRG_1_AC3_TTL_DIG |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG |
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG | ARM_EXP_1_TRG_1_AC3_TTL_DIG
) *
(
GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG |
ARM_EXP_0_TRG_1_AC0_OPTO_DIG | ARM_EXP_0_TRG_1_AC1_OPTO_DIG | ARM_EXP_0_TRG_1_AC2_OPTO_DIG | ARM_EXP_0_TRG_1_AC3_OPTO_DIG |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG |
ARM_EXP_1_TRG_1_AC0_OPTO_DIG | ARM_EXP_1_TRG_1_AC1_OPTO_DIG | ARM_EXP_1_TRG_1_AC2_OPTO_DIG | ARM_EXP_1_TRG_1_AC3_OPTO_DIG
)
)
) ;
//
//value = (
// (
// CAMERA_LINK_AV *
// (
// (
// (
// GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL |
// EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL | ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL |
// ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL
// ) *
// ( GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_1_AC1_OPTO_CL )
// ) |
// (
// (
// GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL |
// EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL | ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL |
// ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL
// ) *
// (
// GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_1_AC1_LVDS_CL |
// ARM_EXP_0_TRG_1_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC1_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_1_AC1_LVDS_CL |
// ARM_EXP_1_TRG_1_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC1_LVDS_CL
// )
// )
// )
// ) |
// (
// VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
// (
// (
// GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG |
// EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG |
// ARM_EXP_0_TRG_1_AC0_OPTO_DIG | ARM_EXP_0_TRG_1_AC1_OPTO_DIG | ARM_EXP_0_TRG_1_AC2_OPTO_DIG | ARM_EXP_0_TRG_1_AC3_OPTO_DIG |
// EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG |
// ARM_EXP_1_TRG_1_AC0_OPTO_DIG | ARM_EXP_1_TRG_1_AC1_OPTO_DIG | ARM_EXP_1_TRG_1_AC2_OPTO_DIG | ARM_EXP_1_TRG_1_AC3_OPTO_DIG
// ) *
// (
// GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG |
// EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG |
// ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG | ARM_EXP_0_TRG_1_AC3_TTL_DIG |
// EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG |
// ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG | ARM_EXP_1_TRG_1_AC3_TTL_DIG
// )
// )
// )
// ) ;
//
// --------------------------------------
DEF_ERR_INTERNAL_TRG2_2_FORMATS_SEL
value = (
(
CAMERA_LINK_AV *
(
GRB_TRG_2_AC01_TTL_CL | EXP_0_TRG_2_AC01_TTL_CL | ARM_EXP_0_TRG_2_AC01_TTL_CL |
EXP_1_TRG_2_AC01_TTL_CL | ARM_EXP_1_TRG_2_AC01_TTL_CL
) *
(
GRB_TRG_2_AC01_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | ARM_EXP_0_TRG_2_AC01_OPTO_CL |
EXP_1_TRG_2_AC01_OPTO_CL | ARM_EXP_1_TRG_2_AC01_OPTO_CL
)
) |
(
CAMERA_LINK_AV *
(
GRB_TRG_2_AC01_TTL_CL | EXP_0_TRG_2_AC01_TTL_CL | ARM_EXP_0_TRG_2_AC01_TTL_CL |
EXP_1_TRG_2_AC01_TTL_CL | ARM_EXP_1_TRG_2_AC01_TTL_CL
) *
(
GRB_TRG_2_AC01_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | ARM_EXP_0_TRG_2_AC01_LVDS_CL |
EXP_1_TRG_2_AC01_LVDS_CL | ARM_EXP_1_TRG_2_AC01_LVDS_CL
)
) |
(
CAMERA_LINK_AV *
(
GRB_TRG_2_AC01_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | ARM_EXP_0_TRG_2_AC01_OPTO_CL |
EXP_1_TRG_2_AC01_OPTO_CL | ARM_EXP_1_TRG_2_AC01_OPTO_CL
) *
(
GRB_TRG_2_AC01_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | ARM_EXP_0_TRG_2_AC01_LVDS_CL |
EXP_1_TRG_2_AC01_LVDS_CL | ARM_EXP_1_TRG_2_AC01_LVDS_CL
)
) |
(
VDC_ANA *
(
(
(
GRB_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
EXP_1_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA
) *
(
GRB_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA
) *
(
GRB_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA
)
) |
(
(
GRB_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA
) *
(
GRB_TRG_3_4AC_AUX3_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA
) *
(
GRB_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA
)
) |
(
(
GRB_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA |
EXP_1_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA
) *
(
GRB_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA
) *
(
GRB_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA |
EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA
)
) |
(
(
GRB_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA
) *
(
GRB_TRG_3_4AC_AUX7_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA
) *
(
GRB_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA |
EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA
)
)
)
) |
(
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG
) *
(
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG
) *
(
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG |
EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG
) *
(
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG
) *
(
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
)
) ;
//
//value = (
// (
// CAMERA_LINK_AV *
// (
// (
// GRB_TRG_2_AC01_TTL_CL *
// (
// GRB_TRG_2_AC01_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | ARM_EXP_0_TRG_2_AC01_OPTO_CL | EXP_1_TRG_2_AC01_OPTO_CL |
// ARM_EXP_1_TRG_2_AC01_OPTO_CL
// )
// ) |
// (
// GRB_TRG_2_AC01_TTL_CL *
// (
// GRB_TRG_2_AC01_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | ARM_EXP_0_TRG_2_AC01_LVDS_CL |
// EXP_1_TRG_2_AC01_LVDS_CL | ARM_EXP_1_TRG_2_AC01_LVDS_CL
// )
// )
// )
// ) |
// (
// VDC_ANA *
// (
// (
// (
// GRB_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA
// ) *
// (
// GRB_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA
// ) *
// (
// GRB_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA
// ) *
// (
// GRB_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA
// ) *
// (
// GRB_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA
// ) *
// (
// GRB_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA
// ) *
// (
// GRB_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA |
// EXP_1_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA
// )
// )
// )
// ) |
// (
// VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
// (
// (
// (
// GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG
// ) *
// (
// GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG
// ) *
// (
// GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG
// ) *
// (
// GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG
// ) *
// (
// GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG
// ) *
// (
// GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG
// ) *
// (
// GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
// )
// )
// )
// )
// ) ;
//
// --------------------------------------
DEF_ERR_INTERNAL_TRG3_2_FORMATS_SEL
value = (
(
CAMERA_LINK_AV *
(
GRB_TRG_3_AC01_TTL_CL | EXP_0_TRG_3_AC01_TTL_CL | ARM_EXP_0_TRG_3_AC01_TTL_CL |
EXP_1_TRG_3_AC01_TTL_CL | ARM_EXP_1_TRG_3_AC01_TTL_CL
) *
(
GRB_TRG_3_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL | ARM_EXP_0_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_3_AC01_OPTO_CL | ARM_EXP_1_TRG_3_AC01_OPTO_CL
)
) |
(
CAMERA_LINK_AV *
(
GRB_TRG_3_AC01_TTL_CL | EXP_0_TRG_3_AC01_TTL_CL | ARM_EXP_0_TRG_3_AC01_TTL_CL |
EXP_1_TRG_3_AC01_TTL_CL | ARM_EXP_1_TRG_3_AC01_TTL_CL
) *
(
GRB_TRG_3_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL | ARM_EXP_0_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_3_AC01_LVDS_CL | ARM_EXP_1_TRG_3_AC01_LVDS_CL
)
) |
(
CAMERA_LINK_AV *
(
GRB_TRG_3_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL | ARM_EXP_0_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_3_AC01_OPTO_CL | ARM_EXP_1_TRG_3_AC01_OPTO_CL
) *
(
GRB_TRG_3_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL | ARM_EXP_0_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_3_AC01_LVDS_CL | ARM_EXP_1_TRG_3_AC01_LVDS_CL
)
) |
(
VDC_ANA *
(
(
(
GRB_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA
) *
(
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA
) *
(
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA
) *
(
GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA
) *
(
GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER
)
)
)
) |
(
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG
) *
(
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_1_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG
) *
(
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG |
EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG
) *
(
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
(
GRB_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG
) *
(
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
)
) ;
//
//value = (
// (
// CAMERA_LINK_AV *
// (
// (
// GRB_TRG_3_AC01_TTL_CL *
// (
// GRB_TRG_3_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL | ARM_EXP_0_TRG_3_AC01_OPTO_CL |
// EXP_1_TRG_3_AC01_OPTO_CL | ARM_EXP_1_TRG_3_AC01_OPTO_CL
// )
// ) |
// (
// GRB_TRG_3_AC01_TTL_CL *
// (
// GRB_TRG_3_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL | ARM_EXP_0_TRG_3_AC01_LVDS_CL |
// EXP_1_TRG_3_AC01_LVDS_CL | ARM_EXP_1_TRG_3_AC01_LVDS_CL
// )
// )
// )
// ) |
// (
// VDC_ANA *
// (
// (
// (
// GRB_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA
// ) *
// (
// GRB_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA
// ) *
// (
// GRB_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA
// ) *
// (
// GRB_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA
// ) *
// (
// GRB_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA
// ) *
// (
// GRB_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
// ) |
// (
// (
// GRB_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA
// ) *
// (
// GRB_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
// EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
// )
// )
// ) |
// (
// VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
// (
// (
// (
// GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG
// ) *
// (
// GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG
// ) *
// (
// GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG
// ) *
// (
// GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG
// ) *
// (
// GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG
// ) *
// (
// GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
// )
// ) |
// (
// (
// GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG
// ) *
// (
// GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
// )
// )
// )
// )
// ) ;
//
// --------------------------------------
DEF_PCK_DELAY_STEP
value = (
( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG ) * ( PCK_IDELAY / 4000 ) ) +
( VDC_ANA * ( PCK_IDELAY > 10000 ) * ( ( PCK_IDELAY - 10000 ) / 500 ) )
) ;
// --------------------------------------
DEF_DIG1_TAPDIR
value = ( REGION_DIRECTIONS % 10 ) ;
// --------------------------------------
DEF_DIG2_TAPDIR
value = ( ( REGION_DIRECTIONS % 100 ) / 10 ) ;
// --------------------------------------
DEF_DIG3_TAPDIR
value = ( ( REGION_DIRECTIONS % 1000 ) / 100 ) ;
// --------------------------------------
DEF_DIG4_TAPDIR
value = ( ( REGION_DIRECTIONS % 10000 ) / 1000 ) ;
// --------------------------------------
DEF_DIG5_TAPDIR
value = ( ( REGION_DIRECTIONS % 100000 ) / 10000 ) ;
// --------------------------------------
DEF_DIG6_TAPDIR
value = ( ( REGION_DIRECTIONS % 1000000 ) / 100000 ) ;
// --------------------------------------
DEF_DIG7_TAPDIR
value = ( ( REGION_DIRECTIONS % 10000000 ) / 1000000 ) ;
// --------------------------------------
DEF_DIG8_TAPDIR
value = ( ( REGION_DIRECTIONS % 100000000 ) / 10000000 ) ;
// --------------------------------------
DEF_DIG8_TAPORDER
value = ( ( TAP_ORDERS % 100000000 ) / 10000000 ) ;
// --------------------------------------
DEF_DIG7_TAPORDER
value = ( ( TAP_ORDERS % 10000000 ) / 1000000 ) ;
// --------------------------------------
DEF_DIG6_TAPORDER
value = ( ( TAP_ORDERS % 1000000 ) / 100000 ) ;
// --------------------------------------
DEF_DIG5_TAPORDER
value = ( ( TAP_ORDERS % 100000 ) / 10000 ) ;
// --------------------------------------
DEF_DIG4_TAPORDER
value = ( ( TAP_ORDERS % 10000 ) / 1000 ) ;
// --------------------------------------
DEF_DIG3_TAPORDER
value = ( ( TAP_ORDERS % 1000 ) / 100 ) ;
// --------------------------------------
DEF_DIG2_TAPORDER
value = ( ( TAP_ORDERS % 100 ) / 10 ) ;
// --------------------------------------
DEF_DIG1_TAPORDER
value = ( TAP_ORDERS % 10 ) ;
// --------------------------------------
DEF_TAPS_MULTIPLEX_X
value = (
( ( TAP_REGIONSX > 1 ) | ( TAP_PIXADJX > 1 ) ) *
(
( CLC_MODE_CH0 == 4 ) | ( ( CLC_MODE_CH0 > 5 ) * ( CLC_MODE_CH0 < 9 ) ) |
( CLC_MODE_CH0 == 0xF )
)
) ;
// --------------------------------------
DEF_TAPS_MULTIPLEX_Y
value = (
( ( TAP_REGIONSY > 1 ) | ( TAP_PIXADJY > 1 ) ) *
(
( CLC_MODE_CH0 == 4 ) | ( ( CLC_MODE_CH0 > 5 ) * ( CLC_MODE_CH0 < 9 ) ) |
( CLC_MODE_CH0 == 0xF )
)
) ;
//
//
// =============================================
//
//
// **********************************************
// **********************************************
// Section #7 : BOARD REGISTER DEFINITION
// **********************************************
// **********************************************
//
//
[PARAMETER]
//
// =============================================
//
INFO_CUSTOM
DCF for Specific Customer 0 = Not Specific Patch
eo_information
2
// --------------------------------------
Custompatches regular
Custom Specific driver Setting
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_REGISTER_REV
Registers Revision
eo_information
1
0 32 unsigned flag_overflow
//
// Include new registers.
//
value = 1 ;
//
no_define_value
//
// =============================================
//
INFO_XSIZE
Horizontal image size
eo_information
1
640 24 unsigned flag_overflow
//
value = (
( VDT_HACTIVE * TAP_REGIONSX * TAP_PIXADJX ) / ( TAP_MULTIPLEX_X + ( TAP_MULTIPLEX_X == 0 ) )
) ;
//
no_define_value
//
// =============================================
//
INFO_YSIZE
Vertical image size
eo_information
1
480 20 unsigned flag_overflow
//
value = (
( VDT_VACTIVE * TAP_REGIONSY * TAP_PIXADJY ) / ( TAP_MULTIPLEX_Y + ( TAP_MULTIPLEX_Y == 0 ) )
) ;
//
no_define_value
//
// =============================================
//
INFO_TYPE
Video Scan Mode
eo_information
2
// --------------------------------------
typescan regular
Camera Type Scan
eo_information
0 3 unsigned flag_overflow
//
value = (
CT_LS +
( 2 * CT_FS )
) ;
//
define_value
reserved
Line scan
Frame scan
Area scan
Others
reserved
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_BAYER
Bayer Format
eo_information
2
// --------------------------------------
bayer_mode regular
Bayer Format
eo_information
0 3 unsigned flag_overflow
//
value = (
CT_BAYER_GB +
( CT_BAYER_BG * 2 ) +
( CT_BAYER_RG * 3 ) +
( CT_BAYER_GR * 4 )
) ;
//
define_value
No Bayer
Bayer_GB
Bayer_BG
Bayer_RG
Bayer_GR
reserved
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_BURSTSIZE
Burst size Transfer from FPGA to OASIS
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
//
INFO_CAM
Camera characteristics operation
eo_information
5
// --------------------------------------
cam_scanmode regular
Camera Scan Mode
eo_information
0 1 unsigned flag_overflow
//
value = VDT_INTERL ;
//
define_value
Camera non-interlaced
Camera interlaced
//
// --------------------------------------
cam_color regular
Camera Color mode
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ;
//
define_value
Monochrome
Color
//
// --------------------------------------
cam_yc regular
Camera Y/C Format
eo_information
0 1 unsigned flag_overflow
//
value = VDC_SVID ;
//
define_value
Camera NOT Y/C
Camera Y/C
//
// --------------------------------------
cam_timelock regular
Camera Input Lock Mode
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Normal fast Input lock
VCR Input mode
//
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_GRABPATH
Path used for the Grab
eo_information
2
// --------------------------------------
path_used regular
Path used for the Grab
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Decoder Path
RGB Path
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SSPCLKSEL
PLL PCLK Reference Selection
eo_information
2
// --------------------------------------
sspclksel regular
PLL PCLK Reference Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
( ! DEF_DIGITIZER_MASTER ) *
(
SLOW_SCAN_PLL_PCKSEL_DVI +
( SLOW_SCAN_PLL_PCKSEL_AUX * 2 ) +
( SLOW_SCAN_PLL_PCKSEL_VIDEO * 3 ) +
( SLOW_SCAN_PLL_PCKSEL_DVI_OTHERAC * 4 ) +
( SLOW_SCAN_PLL_PCKSEL_DVI_AC1 * 5 )
)
) ;
//
define_value
None
CHSYNC pin on DVI
CHSYNC pin on Auxiliairy (HD44)
CHSYNC pin on Video Input (Noise Gating)
CHSYNC pin on DVI fron Other AC
CHSYNC pin on DVI from AC1
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SSHREFSEL
PLL Horizontal Reference Selection
eo_information
2
// --------------------------------------
sshrefsel regular
PLL Horizontal Reference Selection
eo_information
3 3 unsigned flag_overflow
//
value = (
( ! DEF_DIGITIZER_MASTER ) *
(
(
SLOW_SCAN_PLL_HREFSEL_DVI | ( SLOW_SCAN_PLL_HREFSEL_DEFAULT * VDC_ANA * SYC_DIG )
) +
( SLOW_SCAN_PLL_HREFSEL_AUX * 2 ) +
(
(
SLOW_SCAN_PLL_HREFSEL_VIDEO |
( SLOW_SCAN_PLL_HREFSEL_DEFAULT * VDC_ANA * SYC_ANA * SYC_MD_CSYN )
) * 3
) +
( SLOW_SCAN_PLL_HREFSEL_DVI_OTHERAC * 4 ) +
( SLOW_SCAN_PLL_HREFSEL_DVI_AC1 * 5 )
)
) ;
//
define_value
None
CHSYNC pin on DVI
CHSYNC pin on Auxiliairy (HD44)
CHSYNC pin on Video Input (Noise Gating)
CHSYNC pin on DVI fron Other AC
CHSYNC pin on DVI from AC1
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_PIXCLK
Pixel clock frequency
eo_information
1
0 32 unsigned flag_overflow
//
value = PCK_FREQ ;
//
no_define_value
//
// =============================================
//
INFO_CLOCKDELAY
Pixel Clock Line Delay
eo_information
1
10000 32 unsigned flag_overflow
//
// Value in pS
value = (
( ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * 4000 * DEF_PCK_DELAY_STEP ) - DEF_PCK_DELAY_STEP ) +
( ( VDC_ANA * ( 10000 + ( 500 * DEF_PCK_DELAY_STEP ) ) ) + DEF_PCK_DELAY_STEP )
) ;
//
no_define_value
//
// =============================================
//
INFO_USRCLK
User Clock
eo_information
1
0 32 unsigned flag_overflow
//
// Clock Generator
//
value = (
( DEF_DIGITIZER_MASTER * PCK_FREQ ) |
(
( ! DEF_DIGITIZER_MASTER ) *
( ( EXP_CLK_CLKGEN * EXP_CLK_FREQ ) | ( EXP_CLK_2_CLKGEN * EXP_CLK_FREQ_2 ) )
)
) ;
//
no_define_value
//
// =============================================
//
INFO_SAMPLEMODE
Sampling Mode (Physical input channel needed at same time per sampling)
eo_information
2
// --------------------------------------
samplemode regular
Sampling mode
eo_information
0 1 unsigned flag_overflow
//
// Analog module ONLY
value = 0 ;
//
define_value
Sampling 4 X 10 bits Channels
Sampling 2 X 10 bits Channels
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SIGNALTYPE
Input Signal Type
eo_information
2
// --------------------------------------
InputSignalType regular
Input Signal Type
eo_information
0 2 unsigned flag_overflow
//
value = (
VDC_ANA +
( VDC_DIG * ( CLC_MODE_CH0 > 0 ) * 2 ) +
( VDC_DIG * ( CLC_MODE_CH0 == 0 ) * 3 )
) ;
//
define_value
Loadable DCF
Analog Input Signal Type
Camera Link Input Signal Type
Digital Input Signal Type
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_INPUTSOURCE
Input Source operation mode
eo_information
5
// --------------------------------------
insel0 regular
Input 0 Select
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ( ! VDC_MIL_CHANNEL ) * 2 ) +
( VDC_MIL_CHANNEL * 4 )
)
)
)
) ;
//
define_value
None
Input A in DC Coupling
Input A in AC Coupling
Input B in DC Coupling
Input B in AC Coupling
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
insel1 regular
Input 1 Select
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ( ! VDC_MIL_CHANNEL ) * 2 ) +
( VDC_MIL_CHANNEL * 4 )
)
)
)
) ;
//
define_value
None
Input A in DC Coupling
Input A in AC Coupling
Input B in DC Coupling
Input B in AC Coupling
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
insel2 regular
Input 2 Select
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ( ! VDC_MIL_CHANNEL ) * 2 ) +
( VDC_MIL_CHANNEL * 4 )
)
)
)
) ;
//
define_value
None
Input A in DC Coupling
Input A in AC Coupling
Input B in DC Coupling
Input B in AC Coupling
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
insel3 regular
Input 3 Select
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ( ! VDC_MIL_CHANNEL ) * 2 ) +
( VDC_MIL_CHANNEL * 4 )
)
)
)
) ;
//
define_value
None
Input A in DC Coupling
Input A in AC Coupling
Input B in DC Coupling
Input B in AC Coupling
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_CHANNEL
Logical Channel specification
eo_information
2
// --------------------------------------
Cam_Info_channel regular
Logical Input Channel Selection
eo_information
1 4 unsigned flag_overflow
// Keep in mind 8 Cameras & 8 Taps more then 4 inputs! TBD
value = (
(
(
VDC_ANA | CAMERA_LINK_AV | ( CLC_MODE_CH0 > 0 ) |
( VDC_DIG * ( ( CLC_MODE_CH0 == 0 ) | ( CAMERA_LINK_AV == 0 ) ) * ( TM_ENABLE == 0 ) )
) *
(
(
( ( CT_CAMERA == 0 ) | ( ( CT_CAMERA > 0 ) * ( CT_TAPS > 0 ) ) ) *
( VDC_USE_PSG_0 + ( VDC_USE_PSG_1 * 2 ) + ( VDC_USE_PSG_2 * 4 ) + ( VDC_USE_PSG_3 * 8 ) )
) +
( ( CT_CAMERA > 0 ) * ( CT_TAPS == 0 ) ) +
( ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) )
)
) +
(
VDC_DIG * ( ( CLC_MODE_CH0 == 0 ) | ( CAMERA_LINK_AV == 0 ) ) * TM_ENABLE *
(
( CT_TAPS == 0 ) + ( ( CT_TAPS == 1 ) * 3 ) + ( ( CT_TAPS == 2 ) * 0xf )
)
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SYNCGRABCHAN
Sync. channel same as Video
eo_information
2
// --------------------------------------
syncgrabch regular
Sync Channel following Video
eo_information
1 1 unsigned flag_overflow
//
value = (
( VDC_ANA * VDC_MONO * SYC_ANA * SYC_COMP ) | ( VDC_ANA * SYC_DIG ) | CAMERA_LINK_AV
) ;
//
define_value
Sync. channel independent from Video
Sync. channel follow the Video
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SYNCCHANNEL
Sync. channel selected
eo_information
2
// --------------------------------------
syncchannel regular
Sync Channel Selection
eo_information
0 8 unsigned flag_overflow
// CH0-3
value = (
(
VDC_ANA * SYC_ANA *
(
( SYC_COMP * SYC_IN_CH ) |
(
SYC_SEP *
(
( ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) * 3 ) |
( VDC_MONO * SYC_IN_CH )
)
)
)
) +
(
VDC_ANA * SYC_DIG * VDC_MONO *
(
VDC_USE_PSG_1 +
( VDC_USE_PSG_2 * 2 ) +
( VDC_USE_PSG_3 * 3 )
)
) +
( ( DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL ) * VDC_USE_PSG_1 ) +
( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_SEP * SYC_IN_CH )
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_ATTENUATION
Input Signal Divider Attenuator ( Analog ONLY )
eo_information
8
// --------------------------------------
Attenuator_ch0 regular
Channel 0 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch1 regular
Channel 1 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch2 regular
Channel 2 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch3 regular
Channel 3 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch4 regular
Channel 4 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch5 regular
Channel 5 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch6 regular
Channel 6 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
Attenuator_ch7 regular
Channel 7 Attenuator
eo_information
1 4 unsigned flag_overflow
value = ( 1 + ( VDL_AMPL > 1200 ) ) ;
//
define_value
reserved
Attenuator OFF
Attenuator ON ( Input Signal divided by 2 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// =============================================
//
INFO_GAIN0
GAIN on Channel 0
eo_information
2
// --------------------------------------
gain0 regular
Gain on Channel 0
eo_information
0x5b7 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_GAIN ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_GAIN1
GAIN on Channel 1
eo_information
2
// --------------------------------------
gain1 regular
Gain on Channel 1
eo_information
0x5b7 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_GAIN ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_GAIN2
GAIN on Channel 2
eo_information
2
// --------------------------------------
gain2 regular
Gain on Channel 2
eo_information
0x5b7 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_GAIN ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_GAIN3
GAIN on Channel 3
eo_information
2
// --------------------------------------
gain3 regular
Gain on Channel 3
eo_information
0x5b7 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_GAIN ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_OFFSET0
OFFSET on Channel 0
eo_information
2
// --------------------------------------
offset0 regular
Offset on Channel 0
eo_information
0x5b7 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_OFFSET ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_OFFSET1
OFFSET on Channel 1
eo_information
2
// --------------------------------------
offset1 regular
Offset on Channel 1
eo_information
0x800 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_OFFSET ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_OFFSET2
OFFSET on Channel 2
eo_information
2
// --------------------------------------
offset2 regular
Gain on Channel 2
eo_information
0x800 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_OFFSET ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_OFFSET3
OFFSET on Channel 3
eo_information
2
// --------------------------------------
offset3 regular
Offset on Channel 3
eo_information
0x800 12 unsigned flag_overflow
// Direct value between 0 - 4095
value = DEF_CODE_OFFSET ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_CLAMP
Clamping Flag used or Not
eo_information
2
// --------------------------------------
clamp regular
Clamping used or not
eo_information
0 2 unsigned flag_overflow
//
value = VDC_DIG ;
//
define_value
Clamp Active
Clamp Inactive
Clamp Auto
Reserved
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_LUTBUFID
LUT Buffer ID
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//0 = Transparent LUT
//1-2^32 = Buffer ID
//
// =============================================
//
INFO_LUTPROG
LUT to be programmed
eo_information
2
// --------------------------------------
lutprog regular
Programming Lut
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Don't program the LUT
Program the LUT
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_LUTMODE
LUT SIZE 8/12 BITS USED
eo_information
2
// --------------------------------------
lutmode regular
Use LUT 8 Bits
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//value = (
// ( ! ( DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL ) ) *
// (
// ( CLC_MODE_CH0 == 2 ) | ( CLC_MODE_CH0 == 5 ) |
// ( CLC_MODE_CH0 == 7 ) | ( CLC_MODE_CH0 == 10 )
// )
// ) ;
//
define_value
Don't use LUT 8 Bits
Use LUT 8 Bits
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_LUTPALETTE
LUT Palette Selection
eo_information
2
// --------------------------------------
lutpalette regular
Lut Palette Selection
eo_information
0 4 unsigned flag_overflow
//
// Always 0
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// ********** Camera Link Infos **********
//
INFO_CLMODE
Camera Link Configuration Mode
eo_information
//4
2
// --------------------------------------
channel0 regular
Channel 0 configuration mode
eo_information
0 2 unsigned flag_overflow
//
value = CLC_MODE ;
//
define_value
Base
Medium
Full
reserved
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_TESTMODE
Grab Test Module
eo_information
2
// --------------------------------------
gtm regular
Grab Test Module
eo_information
0 1 unsigned flag_overflow
//
value = TM_ENABLE ;
//
define_value
Grab Module Test Disabled
Grab Module Test Enabled
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_BITSPERCOMPONENT
Number of Bits per Component
eo_information
2
// --------------------------------------
bitpercomponent regular
eo_information
0 5 unsigned flag_overflow
//
value = (
( VDC_WD8 * 8 ) +
( VDC_VID_WIDTH_10 * 10 ) +
( VDC_VID_WIDTH_12 * 12 ) +
( VDC_VID_WIDTH_14 * 14 ) +
( ( VDC_WD16 | VDC_VID_WIDTH_16 ) * 16 )
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
//
INFO_NUMCOMPONENTS
Number of Components on 64 Bits Bus
eo_information
2
// --------------------------------------
numcomponents regular
eo_information
1 4 unsigned flag_overflow
//
value = (
TAP_REGIONSX * TAP_REGIONSY * TAP_PIXADJX * TAP_PIXADJY *
( VDC_MONO + ( ( VDC_RGB_COL | VDC_RGB_PACK ) * 3 ) )
) & 0x0000000F ;
//
define_value
reserved
1 Component / Bus (64Bits)
2 Components / Bus (64Bits)
3 Components / Bus (64Bits)
4 Components / Bus (64Bits)
5 Components / Bus (64Bits)
6 Components / Bus (64Bits)
7 Components / Bus (64Bits)
8 Components / Bus (64Bits)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
//
INFO_COMPONENTSPERPIXEL
Number of Components per Pixels
eo_information
2
// --------------------------------------
componentsperpixel regular
eo_information
1 4 unsigned flag_overflow
// TBD!!!!!
value = (
VDC_MONO +
( ( VDC_RGB_COL | VDC_RGB_PACK ) * 3 ) +
( VDC_RGB_ALPHA * 4 )
) ;
//
define_value
reserved
1 Component / Pixel
2 Components / Pixel
3 Components / Pixel
4 Components / Pixel
5 Components / Pixel
6 Components / Pixel
7 Components / Pixel
8 Components / Pixel
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_PACKEDCOMPONENTS
RGB Packed Format
eo_information
2
// --------------------------------------
RGBpacked regular
RGB Packed Format
eo_information
0 1 unsigned flag_overflow
//
value = VDC_RGB_PACK ;
//
define_value
RGB Normal
RGB Packed
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_HDELAY
Horizontal Pixels pipe delay
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_LINEDELAY
Offset Lines Delay between channels
eo_information
1
1 32 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_TIMEMULTICH
Total Clock Cycles to load same Pixel on ALL Taps
eo_information
1
1 32 unsigned flag_overflow
//
value = (
1 +
( ( TAP_MULTIPLEX_X > 1 ) | ( TAP_MULTIPLEX_Y > 1 ) | ( VDC_RGB_COL * ( CLC_MODE_CH0 == 6 ) ) )
) ;
//
no_define_value
//
// =============================================
//
INFO_TIMEMULTIPIX
Total Clock Cycles to load 1 Pixel in 1 Tap
eo_information
1
1 32 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// ********** Taps Section **********
//
INFO_XTAPSPERCH
Non Adjacent Pixel on X
eo_information
1
0 32 unsigned flag_overflow
//
value = TAP_REGIONSX ;
//
no_define_value
//
// =============================================
//
INFO_YTAPSPERCH
Non Adjacent Pixel on Y
eo_information
1
0 32 unsigned flag_overflow
//
value = TAP_REGIONSY ;
//
no_define_value
//
// =============================================
//
INFO_XTAPSPERCHADJ
Adjacent Pixel on X
eo_information
1
0 32 unsigned flag_overflow
//
value = TAP_PIXADJX ;
//
no_define_value
//
// =============================================
//
INFO_YTAPSPERCHADJ
Adjacent Pixel on Y
eo_information
1
0 32 unsigned flag_overflow
//
value = TAP_PIXADJY ;
//
no_define_value
//
// =============================================
//
INFO_TAPSDIR
Taps Direction Info
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
( DEF_DIG8_TAPDIR * 0x10000000 ) +
( DEF_DIG7_TAPDIR * 0x01000000 ) +
( DEF_DIG6_TAPDIR * 0x00100000 ) +
( DEF_DIG5_TAPDIR * 0x00010000 ) +
( DEF_DIG4_TAPDIR * 0x00001000 ) +
( DEF_DIG3_TAPDIR * 0x00000100 ) +
( DEF_DIG2_TAPDIR * 0x00000010 ) +
DEF_DIG1_TAPDIR
) & (
( ( ( TAP_REGIONSX * TAP_REGIONSY ) == 1 ) * 0x00000003 ) +
( ( ( TAP_REGIONSX * TAP_REGIONSY ) == 2 ) * 0x00000033 ) +
( ( ( TAP_REGIONSX * TAP_REGIONSY ) == 4 ) * 0x00003333 ) +
( ( ( TAP_REGIONSX * TAP_REGIONSY ) == 8 ) * 0x33333333 )
)
) ;
//
//value = (
// ( DEF_DIG8_TAPDIR * 0x10000000 ) +
// ( DEF_DIG7_TAPDIR * 0x01000000 ) +
// ( DEF_DIG6_TAPDIR * 0x00100000 ) +
// ( DEF_DIG5_TAPDIR * 0x00010000 ) +
// ( DEF_DIG4_TAPDIR * 0x00001000 ) +
// ( DEF_DIG3_TAPDIR * 0x00000100 ) +
// ( DEF_DIG2_TAPDIR * 0x00000010 ) +
// DEF_DIG1_TAPDIR
// ) ;
//
no_define_value
//
// 0:Beginning UP Left
// 1:Beginning UP Right
// 2:Beginning Bottom Left
// 3:Beginning Bottom Right
//
// 32 Bits Long word
// 0x Digit8 Digit7 Digit6 Digit5 Digit4 Digit3 Digit2 Digit1
// 0x Tap8 Tap7 Tap6 Tap5 Tap4 Tap3 Tap2 Tap1
// 0 0 0 0 0 0 0 0
// | | | | | | | |
// 3 3 3 3 3 3 3 3
//
// Equation for direction of each pixels including Pixels adjacent
//value = (
// (
// ( ( TAP_REGIONSX * TAP_REGIONSY ) == 1 ) *
// (
// DEF_DIG1_TAPDIR +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 1 ) * 10 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 2 ) * 100 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 2 ) * 1000 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 4 ) * 10000 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 4 ) * 100000 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 4 ) * 1000000 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) > 4 ) * 10000000 )
// )
// ) +
// (
// ( ( TAP_REGIONSX * TAP_REGIONSY ) == 2 ) *
// (
// DEF_DIG1_TAPDIR +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 10 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 10 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 100 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 1000 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 10 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 100 ) +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 1000 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 10000 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 100000 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 1000000 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 4 ) * 10000000 )
// )
// ) +
// (
// ( ( TAP_REGIONSX * TAP_REGIONSY ) == 4 ) *
// (
// DEF_DIG1_TAPDIR +
// ( DEF_DIG1_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 10 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 100 ) +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 1000 ) +
// ( DEF_DIG3_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 10000 ) +
// ( DEF_DIG3_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 100000 ) +
// ( DEF_DIG4_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 1000000 ) +
// ( DEF_DIG4_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 2 ) * 10000000 )
// )
// ) +
// (
// ( ( TAP_REGIONSX * TAP_REGIONSY ) == 8 ) *
// (
// DEF_DIG1_TAPDIR +
// ( DEF_DIG2_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 10 ) +
// ( DEF_DIG3_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 100 ) +
// ( DEF_DIG4_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 1000 ) +
// ( DEF_DIG5_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 10000 ) +
// ( DEF_DIG6_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 100000 ) +
// ( DEF_DIG7_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 1000000 ) +
// ( DEF_DIG8_TAPDIR * ( ( TAP_PIXADJX * TAP_PIXADJY ) == 1 ) * 10000000 )
// )
// )
// ) ;
//
//
// =============================================
//
INFO_TAPSORDER
Taps Output Order
eo_information
1
0x76543210 32 unsigned flag_overflow
//
value = (
( DEF_DIG8_TAPORDER * 0x10000000 ) +
( DEF_DIG7_TAPORDER * 0x01000000 ) +
( DEF_DIG6_TAPORDER * 0x00100000 ) +
( DEF_DIG5_TAPORDER * 0x00010000 ) +
( DEF_DIG4_TAPORDER * 0x00001000 ) +
( DEF_DIG3_TAPORDER * 0x00000100 ) +
( DEF_DIG2_TAPORDER * 0x00000010 ) +
DEF_DIG1_TAPORDER
) ;
//
no_define_value
//
// =============================================
//
INFO_HARDGRABTRIG
Hardware Grab Trigger2/3 Configuration
eo_information
3
// --------------------------------------
trigger2folgrb regular
Trigger2 Pinout Follow Grab Channal
eo_information
1 1 unsigned flag_overflow
//
value = (
(
VDC_ANA * VDC_MONO *
(
( DEF_AC0_PROGRAMMED * ( VDC_MONO | VDC_RGB_COL ) * ( GRB_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA ) ) |
( DEF_AC1_PROGRAMMED * VDC_MONO * ( GRB_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA ) ) |
( DEF_AC2_PROGRAMMED * VDC_MONO * ( GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA ) ) |
( DEF_AC3_PROGRAMMED * VDC_MONO * ( GRB_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA ) )
)
) +
(
VDC_DIG * ( ! CAMERA_LINK_AV ) * DEF_AC0_PROGRAMMED *
( GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG )
)
) ;
//
define_value
Trigger2 pinout is fixed
Trigger2 pinout follow grab channal
// --------------------------------------
trigger3folgrb regular
Trigger3 Pinout Follow Grab Channal
eo_information
1 1 unsigned flag_overflow
//
value = (
(
VDC_ANA * VDC_MONO *
(
( DEF_AC0_PROGRAMMED * ( VDC_MONO | VDC_RGB_COL ) * ( GRB_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA ) ) |
( DEF_AC1_PROGRAMMED * VDC_MONO * ( GRB_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA ) ) |
( DEF_AC2_PROGRAMMED * VDC_MONO * ( GRB_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA ) ) |
( DEF_AC3_PROGRAMMED * VDC_MONO * ( GRB_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA ) )
)
) +
(
VDC_DIG * ( ! CAMERA_LINK_AV ) * DEF_AC0_PROGRAMMED *
( GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG )
)
) ;
//
define_value
Trigger3 pinout is fixed
Trigger3 pinout follow grab channal
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_TRIGSRC
GRAB Trigger Source
eo_information
2
// --------------------------------------
grbtrgsrc regular
Grab Trigger Source
eo_information
0 6 unsigned flag_overflow
//
value = (
GRB_MD_CONT +
( GRB_MD_SW_TRG * 2 ) +
( GRB_MD_HW_TRG * GRB_TRG_HS_PSG * 3 ) +
( GRB_MD_HW_TRG * GRB_TRG_VS_PSG * 4 ) +
( GRB_MD_HW_TRG * GRB_TRG_TIMER0 * 5 ) +
( GRB_MD_HW_TRG * GRB_TRG_TIMER1 * 6 ) +
( GRB_MD_HW_TRG * GRB_TRG_TIMER2 * 7 ) +
( GRB_MD_HW_TRG * GRB_TRG_TIMER3 * 8 ) +
( GRB_MD_HW_TRG *
(
GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_0_AC1_TTL_CL |
GRB_TRG_0_AC1_OPTO_CL | GRB_TRG_0_AC1_LVDS_CL |
GRB_TRG_0_AC0_TTL_ANA | GRB_TRG_0_AC1_TTL_ANA | GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC3_TTL_ANA |
GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_0_AC3_OPTO_DIG |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG |
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
) * 15
) +
( GRB_MD_HW_TRG *
(
GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC1_TTL_CL |
GRB_TRG_1_AC1_OPTO_CL | GRB_TRG_1_AC1_LVDS_CL |
GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_1_AC1_OPTO_ANA | GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_1_AC3_OPTO_ANA |
GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG
) * 16
) +
( GRB_MD_HW_TRG *
(
GRB_TRG_2_AC01_OPTO_CL | GRB_TRG_2_AC01_TTL_CL | GRB_TRG_2_AC01_LVDS_CL | GRB_TRG_2_4AC_AUX0_TTL_ANA |
GRB_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_2_AC0_AUX1_TTL_DIG |
GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG
) * 17
) +
( GRB_MD_HW_TRG *
(
GRB_TRG_3_AC01_OPTO_CL | GRB_TRG_3_AC01_TTL_CL | GRB_TRG_3_AC01_LVDS_CL | GRB_TRG_3_4AC_AUX1_TTL_ANA |
GRB_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
GRB_TRG_3_4AC_AUX3_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA | GRB_TRG_3_AC0_AUX2_TTL_DIG |
GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG
) * 18
) +
(
GRB_MD_HW_TRG * 19 *
(
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
) ;
//
no_define_value
// 0 : Reserved
// 1 : Continuous
// 2 : Software
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Timer 1 Output
// 7 : Timer 2 Output
// 8 : Timer 3 Output
// 9-14: Reserved
// 15: Trigger 0
// 16: Trigger 1
// 17: Trigger 2
// 18: Trigger 3
// 19 : Rotary Encoder Grab Trigger
// 20-38: Reserved
// 39: Capture Signal from AC1
// 40: Capture Signal from AC2
// 41: Capture Signal from AC3
// 42-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// ********** Timer 0 Section **********
//
INFO_T0DELAY
Timer 0 delay for First Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = ( ( EXP_OUT_T0 > DEF_TIMER0_TRIGGERS_PIPE_DELAY ) * ( EXP_OUT_T0 - DEF_TIMER0_TRIGGERS_PIPE_DELAY ) ) ;
//
no_define_value
//
// =============================================
//
INFO_T0DELAY1
Timer 0 delay for Second Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = EXP_OUT_T2 ;
//
no_define_value
//
// =============================================
//
INFO_T0TRIGSRC
Timer 0 Trigger Source
eo_information
2
// --------------------------------------
t0trgsrc regular
Timer 0 Trigger Source
eo_information
0 6 unsigned flag_overflow
//
value = (
EXP_MD_PERD +
( EXP_MD_SW * 2 * ( EXP_MD_PERD == 0 ) ) +
( EXP_MD_HSY * 3 * ( EXP_MD_PERD == 0 ) ) +
( EXP_MD_VSY * 4 * ( EXP_MD_PERD == 0 ) ) +
( EXP_TRG_TIMER1 * 6 * ( EXP_MD_PERD == 0 ) ) +
( EXP_TRG_TIMER2 * 7 * ( EXP_MD_PERD == 0 ) ) +
( EXP_TRG_TIMER3 * 8 * ( EXP_MD_PERD == 0 ) ) +
(
EXP_MD_W_TRG * 9 *
( EXP_0_TRG_TIMER0_AC0 + EXP_0_TRG_TIMER0_AC1 + EXP_0_TRG_TIMER0_AC2 + EXP_0_TRG_TIMER0_AC3 )
) +
(
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_0_AC1_TTL_CL |
EXP_0_TRG_0_AC1_OPTO_CL | EXP_0_TRG_0_AC1_LVDS_CL |
EXP_0_TRG_0_AC0_TTL_ANA | EXP_0_TRG_0_AC1_TTL_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC3_LVDS_DIG |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
) * 15 * ( EXP_MD_PERD == 0 )
) +
(
(
EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_1_AC1_TTL_CL |
EXP_0_TRG_1_AC1_OPTO_CL | EXP_0_TRG_1_AC1_LVDS_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG
) * 16 * ( EXP_MD_PERD == 0 )
) +
(
(
EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG
) * 17 * ( EXP_MD_PERD == 0 )
) +
(
(
EXP_0_TRG_3_AC01_OPTO_CL | EXP_0_TRG_3_AC01_TTL_CL | EXP_0_TRG_3_AC01_LVDS_CL | EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
EXP_0_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
) * 18 * ( EXP_MD_PERD == 0 )
) +
(
19 * ( EXP_MD_PERD == 0 ) *
(
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
) ;
//
no_define_value
// 0 : NONE
// 1 : Continuous
// 2 : Software
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Reserved
// 6 : Timer 1 Output
// 7 : Timer 2 Output
// 8 : Timer 3 Output
// 9 : Timer 0 Output from Other AC
// 10-14: Reserved
// 15: Trigger 0
// 16: Trigger 1
// 17: Trigger 2
// 18: Trigger 3
// 19: Rotary Encoder Timer 1 Trigger
// 20-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T0CLKSRC
Time 0 Clock Source Select
eo_information
2
// --------------------------------------
t0clksrcsel regular
Timer 0 Clock Source Select
eo_information
0 6 unsigned flag_overflow
//
value = (
( EXP_CLK_HS * 3 ) +
( EXP_CLK_VS * 4 ) +
( EXP_CLK_TIMER1 * 6 ) +
( EXP_CLK_TIMER2 * 7 ) +
( EXP_CLK_TIMER3 * 8 ) +
( EXP_SYN_CLK * 13 ) +
( EXP_CLK_CLKGEN * 14 ) +
(
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA |
EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA |
EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * 47
)
) ;
//
no_define_value
// 0 : Reserved
// 1 : Reserved
// 2 : Reserved
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Reserved
// 6 : Timer 1 Output
// 7 : Timer 2 Output
// 8 : Timer 3 Output
// 9-12: Reserved
// 13: Pixel Clock
// 14: Clock Generator
// 15-46: Reserved
// 47: Auxiliary Input LVDS
// 48-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T0USRCLK
Timer 0 Auxiliairy Clock Frequency
eo_information
2
// --------------------------------------
t0usrclk regular
Timer 0 Auxiliairy Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
value = (
( EXP_CLK_HS * ( PCK_FREQ / VDT_HTOTAL ) ) +
( EXP_CLK_VS * ( PCK_FREQ / ( VDT_HTOTAL * VDT_VTOTAL ) ) ) +
( EXP_SYN_CLK * PCK_FREQ ) +
( EXP_CLK_CLKGEN * EXP_CLK_FREQ ) +
(
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA |
EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA |
EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ
) +
(
EXP_CLK_TIMER1 *
(
(
( EXP_CLK_2_HS * ( PCK_FREQ / VDT_HTOTAL ) ) +
( EXP_CLK_2_VS * ( PCK_FREQ / ( VDT_HTOTAL * VDT_VTOTAL ) ) ) +
( EXP_SYN_CLK_2 * PCK_FREQ ) +
( EXP_CLK_2_CLKGEN * EXP_CLK_FREQ_2 ) +
(
(
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA |
EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * EXP_CLK_FREQ_2
)
) / ( EXP_OUT_T0_2 * EXP_OUT_T1_2 )
) 0.5
)
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T0OTHERUSRCLK
Timer 0 Other Clock Frequency
eo_information
2
// --------------------------------------
t0otherusrclk regular
Timer 0 Other Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// ********** Timer 1 Section **********
//
INFO_T1DELAY
Timer 1 delay for First Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = ( ( EXP_OUT_T0_2 > DEF_TIMER1_TRIGGERS_PIPE_DELAY ) * ( EXP_OUT_T0_2 - DEF_TIMER1_TRIGGERS_PIPE_DELAY ) ) ;
//
no_define_value
//
// =============================================
//
INFO_T1DELAY1
Timer 1 delay for Second Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = EXP_OUT_T2_2 ;
//
no_define_value
//
// =============================================
//
INFO_T1TRIGSRC
Timer 1 Trigger Source
eo_information
2
// --------------------------------------
t1trgsrc regular
Timer 1 Trigger Source
eo_information
0 6 unsigned flag_overflow
//
value = (
EXP_MD_PERD_2 +
( EXP_MD_SW_2 * 2 * ( EXP_MD_PERD_2 == 0 ) ) +
( EXP_MD_HSY_2 * 3 * ( EXP_MD_PERD_2 == 0 ) ) +
( EXP_MD_VSY_2 * 4 * ( EXP_MD_PERD_2 == 0 ) ) +
( EXP_TRG_TIMER0_2 * 5 * ( EXP_MD_PERD_2 == 0 ) ) +
( EXP_TRG_TIMER2_2 * 7 * ( EXP_MD_PERD_2 == 0 ) ) +
( EXP_TRG_TIMER3_2 * 8 * ( EXP_MD_PERD_2 == 0 ) ) +
(
EXP_MD_W_TRG_2 * 9 *
( EXP_1_TRG_TIMER1_AC0 + EXP_1_TRG_TIMER1_AC1 + EXP_1_TRG_TIMER1_AC2 + EXP_1_TRG_TIMER1_AC3 )
) +
(
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_0_AC1_TTL_CL |
EXP_1_TRG_0_AC1_OPTO_CL | EXP_1_TRG_0_AC1_LVDS_CL |
EXP_1_TRG_0_AC0_TTL_ANA | EXP_1_TRG_0_AC1_TTL_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC3_LVDS_DIG |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
) * 15 * ( EXP_MD_PERD == 0 )
) +
(
(
EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_1_AC1_TTL_CL |
EXP_1_TRG_1_AC1_OPTO_CL | EXP_1_TRG_1_AC1_LVDS_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG
) * 16 * ( EXP_MD_PERD == 0 )
) +
(
(
EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_2_4AC_AUX0_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_AC0_AUX1_TTL_DIG |
EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
) * 17 * ( EXP_MD_PERD == 0 )
) +
(
(
EXP_1_TRG_3_AC01_OPTO_CL | EXP_1_TRG_3_AC01_TTL_CL | EXP_1_TRG_3_AC01_LVDS_CL | EXP_1_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_3_AC0_AUX2_TTL_DIG |
EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
) * 18 * ( EXP_MD_PERD == 0 )
) +
(
19 * ( EXP_MD_PERD_2 == 0 ) *
(
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
) ;
//
no_define_value
// 0 : NONE
// 1 : Continuous
// 2 : Software
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Reserved
// 7 : Timer 2 Output
// 8 : Timer 3 Output
// 9 : Timer 1 Output from Other AC
// 10-14: Reserved
// 15: Trigger 0
// 16: Trigger 1
// 17: Trigger 2
// 18: Trigger 3
// 19: Rotary Encoder Timer 2 Trigger
// 20-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T1CLKSRC
Time 1 Clock Source Select
eo_information
2
// --------------------------------------
t1clksrcsel1 regular
Timer 1 Clock Source Select
eo_information
0 6 unsigned flag_overflow
//
value = (
( EXP_CLK_2_HS * 3 ) +
( EXP_CLK_2_VS * 4 ) +
( EXP_CLK_2_TIMER0 * 5 ) +
( EXP_CLK_2_TIMER2 * 7 ) +
( EXP_CLK_2_TIMER3 * 8 ) +
( EXP_SYN_CLK_2 * 13 ) +
( EXP_CLK_2_CLKGEN * 14 ) +
(
(
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA |
EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * 47
)
) ;
//
no_define_value
// 0 : Reserved
// 1 : Reserved
// 2 : Reserved
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Reserved
// 7 : Timer 2 Output
// 8 : Timer 3 Output
// 9-12: Reserved
// 13: Pixel Clock
// 14: Clock Generator
// 15-46: Reserved
// 47: Auxiliary Input LVDS
// 48-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T1USRCLK
Timer 1 Auxiliairy Clock Frequency
eo_information
2
// --------------------------------------
t1usrclk regular
Timer 1 Auxiliairy Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
value = EXP_CLK_FREQ_2 ;
//value = ( ( EXP_CLK_2_AUXIN1_LVDS || EXP_CLK_2_AUXIN3_LVDS ) * EXP_CLK_FREQ_2 ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T1OTHERUSRCLK
Timer 1 Other Clock Frequency
eo_information
2
// --------------------------------------
t1otherusrclk regular
Timer 1 Other Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// ********** Timer 2 Section **********
//
INFO_T2DELAY
Timer 2 delay for First Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_T2DELAY1
Timer 2 delay for Second Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_T2TRIGSRC
Timer 2 Trigger Source
eo_information
2
// --------------------------------------
t2trgsrc regular
Timer 2 Trigger Source
eo_information
0 6 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// 0 : NONE
// 1 : Continuous
// 2 : Software
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Timer 1 Output
// 7 : Reserved
// 8 : Timer 3 Output
// 9 : Timer 2 Output from Other AC
// 10-14: Reserved
// 15: Trigger 0
// 16: Trigger 1
// 17: Trigger 2
// 18: Trigger 3
// 19: Rotary Encoder Timer 2 Trigger
// 20-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T2CLKSRC
Time 2 Clock Source Select
eo_information
2
// --------------------------------------
t2clksrcsel regular
Timer 2 Clock Source Select
eo_information
0 6 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// 0 : Reserved
// 1 : Reserved
// 2 : Reserved
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Timer 1 Output
// 7 : Reserved
// 8 : Timer 3 Output
// 9-12: Reserved
// 13: Pixel Clock
// 14: Clock Generator
// 15-46: Reserved
// 47: Auxiliary Input LVDS
// 48-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T2USRCLK
Timer 0 Auxiliairy Clock Frequency
eo_information
2
// --------------------------------------
t2usrclk regular
Timer 2 Auxiliairy Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T2OTHERUSRCLK
Timer 2 Other Clock Frequency
eo_information
2
// --------------------------------------
t2otherusrclk regular
Timer 2 Other Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// ********** Timer 3 Section **********
//
INFO_T3DELAY
Timer 3 delay for First Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_T3DELAY1
Timer 3 delay for Second Pulse generated
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_T3TRIGSRC
Timer 3 Trigger Source
eo_information
2
// --------------------------------------
t3trgsrc regular
Timer 3 Trigger Source
eo_information
0 6 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// 0 : NONE
// 1 : Continuous
// 2 : Software
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Timer 1 Output
// 7 : Timer 2 Output
// 8 : Reserved
// 9 : Rotary Encoder Timer 2 Trigger
// 10-14: Reserved
// 15: Trigger 0
// 16: Trigger 1
// 17: Trigger 2
// 18: Trigger 3
// 19: Rotary Encoder Timer 2 Trigger
// 20-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T3CLKSRC
Time 3 Clock Source Select
eo_information
2
// --------------------------------------
t3clksrcsel regular
Timer 3 Clock Source Select
eo_information
0 6 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// 0 : Reserved
// 1 : Reserved
// 2 : Reserved
// 3 : HS from FPGA
// 4 : VS from FPGA
// 5 : Timer 0 Output
// 6 : Timer 1 Output
// 7 : Timer 2 Output
// 8-12: Reserved
// 13: Pixel Clock
// 14: Clock Generator
// 15-46: Reserved
// 47: Auxiliary Input LVDS
// 48-54: Reserved
// --------------------------------------
reserved protected
eo_information
0 26 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T3USRCLK
Timer 3 Auxiliairy Clock Frequency
eo_information
2
// --------------------------------------
t3usrclk regular
Timer 3 Auxiliairy Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T3OTHERUSRCLK
Timer 3 Other Clock Frequency
eo_information
2
// --------------------------------------
t3otherusrclk regular
Timer 3 Other Clock Frequency
eo_information
0 28 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MISC
miscellenous Infos
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
// ********** Specific MIL INFO Registers **********
//
INFO_DEPTH
Pixel Width Size
eo_information
1
8 8 unsigned flag_overflow
//
value = ( VDC_WD8 ? 8 :
( VDC_VID_WIDTH_10 ? 10 :
( VDC_VID_WIDTH_12 ? 12 :
( VDC_VID_WIDTH_14 ? 14 :
( ( VDC_WD16 | VDC_VID_WIDTH_16 ) ? 16 : 8 ) ) ) )
) ;
//
no_define_value
//
// =============================================
//
INFO_BAND
Video Band Size
eo_information
1
1 8 unsigned flag_overflow
//
value = ( VDC_MONO ? 1 :
( VDC_RGB_ALPHA ? 4 : 3 )
) ;
//
no_define_value
//1 : Monochrome / RGB Packed
//3 : RGB Color
//4 : RGB (Alpha) Color
//
// =============================================
//
INFO_INPUT
Input Channel Selected
eo_information
1
0 8 unsigned flag_overflow
//
value = (
( VDC_MONO & VDC_USE_PSG_1 ) ? 1 :
( ( VDC_MONO & VDC_USE_PSG_2 ) ? 2 :
( ( VDC_MONO & VDC_USE_PSG_3 ) ? 3 :
( ( DEF_ODYSSEY_DIG & VDC_TTL ) ? 4 :
( ( DEF_ODYSSEY_DIG & VDC_422 ) ? 5 :
0 ) ) ) )
) ;
//
no_define_value
//0 : Analog Channel 0
//1 : Analog Channel 1
//2 : Analog Channel 2
//3 : Analog Channel 3
//4 : Digital TTL
//5 : Digital 422
//
// =============================================
//
INFO_MODULE_422
Digital video and sync module
eo_information
1
0 32 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) ? 0x60f00 :
0 ) ;
//
no_define_value
//
// =============================================
//
//
INFO_FORMAT
Input Video Type
eo_information
4
// --------------------------------------
Pal regular
Pal Input Signal
eo_information
0 1 unsigned flag_overflow
//
value = DEF_PAL ;
//
no_define_value
// --------------------------------------
Ntsc regular
NTSC Input Signal
eo_information
0 1 unsigned flag_overflow
//
value = DEF_NTSC ;
//
no_define_value
// --------------------------------------
CCir601 regular
Ccir601 Input Format Signal
eo_information
0 1 unsigned flag_overflow
//
value = DEF_CCIR601 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_INPUT_MUX_SEL
Physical Input muxed channel selected
eo_information
3
// --------------------------------------
Vid_Input_mux_sel regular
Physical Video Input muxed channel selected
eo_information
0 2 unsigned flag_overflow
//
//Depend Intellicam number video Input ( 4 ) and AC/DC coupled input
value = VDC_MIL_CHANNEL ;
//
define_value
Input mux 0
Input mux 1
Input mux 2
Input mux 3
// --------------------------------------
Sync_Input_mux_sel regular
Physical Sync Input muxed channel selected
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Input mux 0
Input mux 1
Input mux 2
Input mux 3
//
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_CHANNEL
Software Video Channel
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
( ( CT_CAMERA == 0 ) | ( ( CT_CAMERA > 0 ) * ( CT_TAPS > 0 ) ) ) *
( VDC_USE_PSG_0 + ( VDC_USE_PSG_1 * 2 ) + ( VDC_USE_PSG_2 * 4 ) + ( VDC_USE_PSG_3 * 8 ) )
) +
( ( CT_CAMERA > 0 ) * ( CT_TAPS == 0 ) ) +
( ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) )
) ;
//
no_define_value
//
// =============================================
//
INFO_M_CHANNEL_SYNC
Input Sync. Channel
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
VDC_ANA * SYC_ANA *
(
( SYC_COMP * SYC_IN_CH ) |
(
SYC_SEP *
(
( ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) * 3 ) |
( VDC_MONO * SYC_IN_CH )
)
)
)
) +
( ( DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL ) * VDC_USE_PSG_1 ) +
( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_SEP * SYC_IN_CH )
) ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_INPUT_GAIN
Input Gain Code
eo_information
1
1 32 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
//
// =============================================
//
INFO_M_INPUT_FILTER
Input Filters Selection
eo_information
2
// --------------------------------------
infltrsel regular
Input Filter Selection
eo_information
1 3 unsigned flag_overflow
//
value = (
(
( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA |
OPTION_SOLIOS_QUAD_ANA
) *
(
( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) +
(
( VDC_0_FILTER_1 | VDC_1_FILTER_1 | VDC_2_FILTER_1 | VDC_3_FILTER_1 ) *
( ( ! VDC_0_FILTER_0 ) * ( ! VDC_1_FILTER_0 ) * ( ! VDC_2_FILTER_0 ) * ( ! VDC_3_FILTER_0 ) )
* 2
)
)
) +
(
OPTION_ODYSSEY_ANA *
(
( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) +
(
( VDC_0_NO_FILTER | VDC_1_NO_FILTER | VDC_2_NO_FILTER | VDC_3_NO_FILTER ) *
( ( ! VDC_0_FILTER_0 ) | ( ! VDC_1_FILTER_0 ) | ( ! VDC_2_FILTER_0 ) | ( ! VDC_3_FILTER_0 ) )
* 2
)
)
)
) ;
//
define_value
All Filters Bypassed
Low-pass Filter at 7.5 Mhz
Low-pass Filter at 40 Mhz
reserved
reserved
reserved
reserved
reserved
//
//
//..............................
//All Filters Bypassed
//Low-pass Filter at 7.5 Mhz
//Low-pass Filter at 12.5 Mhz
//Low-pass Filter at 20 Mhz
//Low-pass Filter at 50 Mhz
// Set new filter setting depend boards
// Filter Sel 0 1
// PMC ODY MOD Bypass 50Mhz
// ODY/HELios XA 40Mhz 7.5Mhz
// Solios XA 32Mhz 7.5Mhz
//value = (
// ( OPTION_HELIOS_ANA | OPTION_SOLIOS_SINGLE_ANA | OPTION_SOLIOS_DUAL_ANA |
// OPTION_SOLIOS_QUAD_ANA
// ) *
// (
// ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) +
// ( ( VDC_0_FILTER_1 | VDC_1_FILTER_1 | VDC_2_FILTER_1 | VDC_3_FILTER_1 ) * 2 )
// )
// ) ;
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_TRIGGER_ENABLE
Grab Trigger Enable
eo_information
2
// --------------------------------------
grbtrgen regular
Grab Trigger Enable
eo_information
1 1 unsigned flag_overflow
//
value = ( ! GRB_MD_CONT ) ;
//
define_value
Disabled
Enabled
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_TRIGGER_MODE
Grab Trigger Polarity
eo_information
2
// --------------------------------------
grbtrgmode regular
Grab Trigger Polarity
eo_information
1 2 unsigned flag_overflow
//
value = (
( GRB_TRG_POS | ( ( ! GRB_TRG_POS ) * ( ! GRB_TRG_NEG ) ) ) +
( GRB_TRG_NEG * 2 )
) ;
//
define_value
Level Low
Rising Edge
Falling Edge
Level High
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_TRIGGER_FORMAT
Grab Trigger Input Format
eo_information
2
// --------------------------------------
grbtrgfmt regular
Grab Trigger Polarity
eo_information
0 2 unsigned flag_overflow
//
value = (
(
GRB_TRG_TTL |
(
GRB_TRG_DEFAULT *
(
GRB_TRG_0_AC0_TTL_CL | GRB_TRG_1_AC0_TTL_CL | GRB_TRG_2_AC01_TTL_CL | GRB_TRG_3_AC01_TTL_CL |
GRB_TRG_0_AC1_TTL_CL | GRB_TRG_1_AC1_TTL_CL | GRB_TRG_0_AC0_TTL_ANA | GRB_TRG_0_AC1_TTL_ANA |
GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC3_TTL_ANA | GRB_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_3_4AC_AUX1_TTL_ANA |
GRB_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_3_4AC_AUX5_TTL_ANA |
GRB_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG |
GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG | GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG |
GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG |
GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
)
)
) +
(
(
GRB_TRG_LVDS |
(
GRB_TRG_DEFAULT *
(
GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_2_AC01_LVDS_CL | GRB_TRG_3_AC01_LVDS_CL |
GRB_TRG_0_AC1_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL |
GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG
)
)
) * 2
)
) & 0x3 ;
//
define_value
Opto
TTL
LVDS
422
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_TRIGGER_SOURCE
Grab Trigger Source
eo_information
2
// --------------------------------------
Grbtrgsrc regular
Grab Trigger Source
eo_information
0 16 unsigned flag_overflow
//
value = (
GRB_MD_SW_TRG + ( GRB_TRG_TIMER0 * 2 ) + ( GRB_TRG_TIMER1 * 3 ) + ( GRB_TRG_HS_PSG * 10 ) +
( GRB_TRG_VS_PSG * 11 ) +
(
(
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
) * 15
) +
(
(
GRB_TRG_2_AC01_OPTO_CL | GRB_TRG_0_AC1_OPTO_CL | GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_1_AC1_OPTO_ANA |
GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_1_AC3_OPTO_ANA | GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG |
GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
) * 100
) +
(
(
GRB_TRG_3_AC01_OPTO_CL | GRB_TRG_1_AC1_OPTO_CL | GRB_TRG_0_AC0_TTL_ANA |
GRB_TRG_0_AC1_TTL_ANA | GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC3_TTL_ANA |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG |
GRB_TRG_0_AC3_LVDS_DIG
) * 101
) +
(
(
GRB_TRG_2_AC01_TTL_CL | GRB_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_0_AC2_OPTO_DIG |
GRB_TRG_0_AC3_OPTO_DIG
) * 102
) +
(
(
GRB_TRG_3_AC01_TTL_CL | GRB_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG |
GRB_TRG_1_AC3_OPTO_DIG
) * 103
) +
(
(
GRB_TRG_2_AC01_LVDS_CL | GRB_TRG_0_AC1_LVDS_CL | GRB_TRG_2_4AC_AUX2_TTL_ANA |
GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG
) * 104
) +
(
(
GRB_TRG_3_AC01_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL | GRB_TRG_3_4AC_AUX3_TTL_ANA |
GRB_TRG_3_4AC_AUX3_LVDS_ANA | GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG
) * 105
) +
(
(
GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA |
GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG
) * 106
) +
(
(
GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA |
GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG
) * 107
) +
(
(
GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL | GRB_TRG_2_4AC_AUX6_TTL_ANA |
GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG
) * 108
) +
(
(
GRB_TRG_1_AC0_TTL_CL | GRB_TRG_3_4AC_AUX7_LVDS_ANA | GRB_TRG_1_AC1_TTL_CL |
GRB_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG
) * 109
) +
( ( GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG ) * 110 ) +
( ( GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG ) * 111 )
) ;
//
no_define_value
// 0 : None
// 1 : Software
// 2 : Timer 1
// 3 : Timer 2
// 4 : Timer 3
// 5 : Timer 4
// 6 : Timer 5
// 7 : Timer 6
// 8 : Timer 7
// 9 : Timer 8
// 10 : PSG HSYNC
// 11 : PSG VSYNC
// 12 : Reserved
// 13 : Periodic
// 14 : Reserved
// 15 : Rotary Encoder Grab Trigger
// 16-99 : Reserved
// 100 : Hardware Port 0
// 101 : Hardware Port 1
// 102 : Hardware Port 2
// 103 : Hardware Port 3
// 104 : Hardware Port 4
// 105 : Hardware Port 5
// 106 : Hardware Port 6
// 107 : Hardware Port 7
// 108 : Hardware Port 8
// 109 : Hardware Port 9
// 110 : Hardware Port 10
// 111 : Hardware Port 11
// 112 : Hardware Port 12
// 113 : Hardware Port 13
// 114 : Hardware Port 14
// 115 : Hardware Port 15
// 116 : Hardware Port 16
// 117 : Hardware Port 17
// 118 : Hardware Port 18
// 119 : Hardware Port 19
// 120 : Hardware Port 20
// 121 : Hardware Port 21
// 122 : Hardware Port 22
// 123 : Hardware Port 23
// 124 : Hardware Port 24
// 125 : Hardware Port 25
// 126 : Hardware Port 26
// 127 : Hardware Port 27
// 128 : Hardware Port 28
// 129 : Hardware Port 29
// 130 : Hardware Port 30
// 131 : Hardware Port 31
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_MODE
Exposure 0 Output Polarity
eo_information
2
// --------------------------------------
Exp0mode regular
Exposure 0 Output Polarity
eo_information
0 1 unsigned flag_overflow
//
value = EXP_OUT_NEG ;
//
define_value
Positive Output
Negative Output
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TRIGGER_MODE
Exposure 0 Trigger Polarity
eo_information
2
// --------------------------------------
Exp0trgmode regular
Exposure 0 Trigger Polarity
eo_information
1 2 unsigned flag_overflow
//
value = (
(
( EXP_TRG_POS * ( ! DEF_TIMER0_TRIG_INVERTED_POL ) ) |
( EXP_TRG_NEG * DEF_TIMER0_TRIG_INVERTED_POL ) |
( ( ! EXP_TRG_POS ) & ( ! EXP_TRG_NEG ) )
) +
( 2 *
(
( EXP_TRG_NEG * ( ! DEF_TIMER0_TRIG_INVERTED_POL ) ) |
( EXP_TRG_POS * DEF_TIMER0_TRIG_INVERTED_POL )
)
)
) ;
//
define_value
Level Low
Rising Edge
Falling Edge
Level High
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TRIGGER_FORMAT
Exposure 0 Trigger Format
eo_information
2
// --------------------------------------
exp0trgfmt regular
Exposure 0 Trigger Format
eo_information
0 2 unsigned flag_overflow
//
value = (
(
EXP_TRG_TTL |
(
EXP_TRG_DEFAULT *
(
EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_3_AC01_TTL_CL |
EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL | EXP_0_TRG_0_AC0_TTL_ANA | EXP_0_TRG_0_AC1_TTL_ANA |
EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG |
EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
)
) +
(
(
EXP_TRG_LVDS |
(
EXP_TRG_DEFAULT *
(
EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL |
EXP_0_TRG_0_AC1_LVDS_CL | EXP_0_TRG_1_AC1_LVDS_CL |
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC3_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
)
)
) * 2
)
) & 0x3 ;
//
define_value
Opto
TTL
LVDS
422
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TRIGGER_SOURCE
Exposure 0 Trigger Source
eo_information
2
// --------------------------------------
Exp0trgsrc regular
Exposure 0 Trigger Source
eo_information
0 16 unsigned flag_overflow
//
value = (
( EXP_MD_SW * ( EXP_MD_PERD == 0 ) ) + ( EXP_TRG_TIMER1 * ( EXP_MD_PERD == 0 ) * 3 ) + ( EXP_MD_HSY * ( EXP_MD_PERD == 0 ) * 10 ) +
( EXP_MD_VSY * ( EXP_MD_PERD == 0 ) * 11 ) + ( EXP_MD_PERD * 13 ) +
(
( EXP_MD_PERD == 0 ) * 15 *
(
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) +
(
(
EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_0_AC1_OPTO_CL | EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA |
EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA | EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG |
EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
) * 100
) +
(
(
EXP_0_TRG_3_AC01_OPTO_CL | EXP_0_TRG_1_AC1_OPTO_CL | EXP_0_TRG_0_AC0_TTL_ANA |
EXP_0_TRG_0_AC1_TTL_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG |
EXP_0_TRG_0_AC3_LVDS_DIG
) * 101
) +
(
(
EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG |
EXP_0_TRG_0_AC3_OPTO_DIG
) * 102
) +
(
(
EXP_0_TRG_3_AC01_TTL_CL | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG |
EXP_0_TRG_1_AC3_OPTO_DIG
) * 103
) +
(
(
EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_0_AC1_LVDS_CL | EXP_0_TRG_2_4AC_AUX2_TTL_ANA |
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG
) * 104
) +
(
(
EXP_0_TRG_3_AC01_LVDS_CL | EXP_0_TRG_1_AC1_LVDS_CL | EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG
) * 105
) +
(
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_LVDS_ANA |
EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG
) * 106
) +
(
(
EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA |
EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG
) * 107
) +
(
(
EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL | EXP_0_TRG_2_4AC_AUX6_TTL_ANA |
EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG
) * 108
) +
(
(
EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_0_TRG_1_AC1_TTL_CL |
EXP_0_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG
) * 109
) +
( ( EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG ) * 110 ) +
( ( EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG ) * 111 )
) ;
//
no_define_value
// 0 : None
// 1 : Software
// 2 : Timer 1
// 3 : Timer 2
// 4 : Timer 3
// 5 : Timer 4
// 6 : Timer 5
// 7 : Timer 6
// 8 : Timer 7
// 9 : Timer 8
// 10 : PSG HSYNC
// 11 : PSG VSYNC
// 12 : Reserved
// 13 : Periodic
// 14 : Reserved
// 15 : Rotary Encoder Timer 1 Trigger
// 16-99 : Reserved
// 100 : Hardware Port 0
// 101 : Hardware Port 1
// 102 : Hardware Port 2
// 103 : Hardware Port 3
// 104 : Hardware Port 4
// 105 : Hardware Port 5
// 106 : Hardware Port 6
// 107 : Hardware Port 7
// 108 : Hardware Port 8
// 109 : Hardware Port 9
// 110 : Hardware Port 10
// 111 : Hardware Port 11
// 112 : Hardware Port 12
// 113 : Hardware Port 13
// 114 : Hardware Port 14
// 115 : Hardware Port 15
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TIME_DELAY1
Exposure 0 Time Delay of first Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
( EXP_OUT_T0 > DEF_TIMER0_TRIGGERS_PIPE_DELAY ) * ( EXP_OUT_T0 - DEF_TIMER0_TRIGGERS_PIPE_DELAY ) *
(
(
EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_TIMER1 | EXP_CLK_AUXIN1_AC0_CL |
EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER0_FREQ + ( ( DEF_TIMER0_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
//value = (
// (
// ( EXP_OUT_T0 > DEF_TIMER0_TRIGGERS_PIPE_DELAY ) * ( EXP_OUT_T0 - DEF_TIMER0_TRIGGERS_PIPE_DELAY ) *
// (
// (
// (
// EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_AUXIN1_AC0_CL |
// EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
// EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
// EXP_CLK_AUXIN2_AC3_DIG
// ) * ( 1000000000 / EXP_CLK_FREQ )
// ) +
// ( EXP_CLK_TIMER1 * EXP_MD_PERD_2 * DEF_TIMER0_T1CLK_PERD_FREQ )
// )
// ) + 0.5
// ) ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TIME_DELAY2
Exposure 0 Time Delay of second Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
EXP_OUT_T2 *
(
(
EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_TIMER1 | EXP_CLK_AUXIN1_AC0_CL |
EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER0_FREQ + ( ( DEF_TIMER0_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TIME1
Exposure 0 Activation Time of first Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
EXP_OUT_T1 *
(
(
EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_TIMER1 | EXP_CLK_AUXIN1_AC0_CL |
EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER0_FREQ + ( ( DEF_TIMER0_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_TIME2
Exposure 0 Activation Time of second Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
EXP_OUT_T3 *
(
(
EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_TIMER1 | EXP_CLK_AUXIN1_AC0_CL |
EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
EXP_CLK_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER0_FREQ + ( ( DEF_TIMER0_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
//value = (
// (
// EXP_OUT_T3 *
// (
// (
// (
// EXP_SYN_CLK | EXP_CLK_CLKGEN | EXP_CLK_HS | EXP_CLK_VS | EXP_CLK_AUXIN1_AC0_CL |
// EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN5_AC2_ANA |
// EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG | EXP_CLK_AUXIN2_AC2_DIG |
// EXP_CLK_AUXIN2_AC3_DIG
// ) * ( 1000000000 / EXP_CLK_FREQ )
// ) +
// ( EXP_CLK_TIMER1 * EXP_MD_PERD_2 * DEF_TIMER0_T1CLK_PERD_FREQ )
// )
// ) + 0.5
// ) ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_MODE
Exposure 1 Output Polarity
eo_information
2
// --------------------------------------
Exp1mode regular
Exposure 1 Output Polarity
eo_information
0 1 unsigned flag_overflow
//
value = EXP_OUT_NEG_2 ;
//
define_value
Positive Output
Negative Output
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TRIGGER_MODE
Exposure 1 Trigger Polarity
eo_information
2
// --------------------------------------
Exp1trgmode regular
Exposure 1 Trigger Polarity
eo_information
1 2 unsigned flag_overflow
//
value = (
(
( EXP_TRG_POS_2 * ( ! DEF_TIMER1_TRIG_INVERTED_POL ) ) |
( EXP_TRG_NEG_2 * DEF_TIMER1_TRIG_INVERTED_POL ) |
( ( ! EXP_TRG_POS_2 ) * ( ! EXP_TRG_NEG_2 ) )
) +
(
2 *
(
( EXP_TRG_NEG_2 * ( ! DEF_TIMER1_TRIG_INVERTED_POL ) ) |
( EXP_TRG_POS_2 * DEF_TIMER1_TRIG_INVERTED_POL )
)
)
) ;
//
define_value
Level Low
Rising Edge
Falling Edge
Level High
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TRIGGER_FORMAT
Exposure 1 Trigger Format
eo_information
2
// --------------------------------------
exp1trgfmt regular
Exposure 1 Trigger Format
eo_information
0 2 unsigned flag_overflow
//
value = (
(
EXP_TRG_TTL_2 |
(
EXP_TRG_DEFAULT_2 *
(
EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_3_AC01_TTL_CL |
EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL | EXP_1_TRG_0_AC0_TTL_ANA | EXP_1_TRG_0_AC1_TTL_ANA |
EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA | EXP_1_TRG_2_4AC_AUX0_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_TTL_ANA | EXP_1_TRG_3_4AC_AUX3_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_TTL_ANA |
EXP_1_TRG_2_4AC_AUX6_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA | EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG |
EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
)
) +
(
(
EXP_TRG_LVDS_2 |
(
EXP_TRG_DEFAULT_2 *
(
EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_0_AC1_LVDS_CL | EXP_1_TRG_1_AC1_LVDS_CL |
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC3_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
)
) * 2
)
) & 0x3 ;
//
define_value
Opto
TTL
LVDS
422
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TRIGGER_SOURCE
Exposure 1 Trigger Source
eo_information
2
// --------------------------------------
Exp1trgsrc regular
Exposure 1 Trigger Source
eo_information
0 16 unsigned flag_overflow
//
value = (
( EXP_MD_SW_2 * ( EXP_MD_PERD_2 == 0 ) ) + ( EXP_TRG_TIMER0_2 * ( EXP_MD_PERD_2 == 0 ) * 2 ) +
( EXP_MD_HSY_2 * ( EXP_MD_PERD_2 == 0 ) * 10 ) + ( EXP_MD_VSY_2 * ( EXP_MD_PERD_2 == 0 ) * 11 ) + ( EXP_MD_PERD_2 * 13 ) +
(
( EXP_MD_PERD_2 == 0 ) * 15 *
(
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) +
(
(
EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_0_AC1_OPTO_CL | EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA |
EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA | EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG |
EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
) * 100
) +
(
(
EXP_1_TRG_3_AC01_OPTO_CL | EXP_1_TRG_1_AC1_OPTO_CL | EXP_1_TRG_0_AC0_TTL_ANA |
EXP_1_TRG_0_AC1_TTL_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG |
EXP_1_TRG_0_AC3_LVDS_DIG
) * 101
) +
(
(
EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_2_4AC_AUX0_TTL_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG |
EXP_1_TRG_0_AC3_OPTO_DIG
) * 102
) +
(
(
EXP_1_TRG_3_AC01_TTL_CL | EXP_1_TRG_3_4AC_AUX1_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG |
EXP_1_TRG_1_AC3_OPTO_DIG
) * 103
) +
(
(
EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_0_AC1_LVDS_CL | EXP_1_TRG_2_4AC_AUX2_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG
) * 104
) +
(
(
EXP_1_TRG_3_AC01_LVDS_CL | EXP_1_TRG_1_AC1_LVDS_CL | EXP_1_TRG_3_4AC_AUX3_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG
) * 105
) +
(
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA |
EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG
) * 106
) +
(
(
EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG
) * 107
) +
(
(
EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL | EXP_1_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG
) * 108
) +
(
(
EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_1_AC1_TTL_CL |
EXP_1_TRG_3_4AC_AUX7_TTL_ANA | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG
) * 109
) +
( ( EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG ) * 110 ) +
( ( EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG ) * 111 )
) ;
//
no_define_value
// 0 : None
// 1 : Software
// 2 : Timer 1
// 3 : Timer 2
// 4 : Timer 3
// 5 : Timer 4
// 6 : Timer 5
// 7 : Timer 6
// 8 : Timer 7
// 9 : Timer 8
// 10 : PSG HSYNC
// 11 : PSG VSYNC
// 12 : Reserved
// 13 : Periodic
// 14 : Reserved
// 15 : Rotary Encoder Timer 2 Trigger
// 16-99 : Reserved
// 100 : Hardware Port 0
// 101 : Hardware Port 1
// 102 : Hardware Port 2
// 103 : Hardware Port 3
// 104 : Hardware Port 4
// 105 : Hardware Port 5
// 106 : Hardware Port 6
// 107 : Hardware Port 7
// 108 : Hardware Port 8
// 109 : Hardware Port 9
// 110 : Hardware Port 10
// 111 : Hardware Port 11
// 112 : Hardware Port 12
// 113 : Hardware Port 13
// 114 : Hardware Port 14
// 115 : Hardware Port 15
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY1
Exposure 1 Time Delay of first Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
( EXP_OUT_T0_2 > DEF_TIMER1_TRIGGERS_PIPE_DELAY ) * ( EXP_OUT_T0_2 - DEF_TIMER1_TRIGGERS_PIPE_DELAY ) *
(
(
EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_TIMER0 | EXP_CLK_2_AUXIN1_AC0_CL |
EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER1_FREQ + ( ( DEF_TIMER1_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY2
Exposure 1 Time Delay of second Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
EXP_OUT_T2_2 *
(
(
EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_TIMER0 | EXP_CLK_2_AUXIN1_AC0_CL |
EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER1_FREQ + ( ( DEF_TIMER1_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TIME1
Exposure 1 Activation Time of first Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
EXP_OUT_T1_2 *
(
(
EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_TIMER0 | EXP_CLK_2_AUXIN1_AC0_CL |
EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER1_FREQ + ( ( DEF_TIMER1_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
//value = (
// (
// EXP_OUT_T1_2 *
// (
// (
// (
// EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_AUXIN1_AC0_CL |
// EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
// EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
// EXP_CLK_2_AUXIN2_AC3_DIG
// ) * ( 1000000000 / EXP_CLK_FREQ_2 )
// ) +
// ( EXP_CLK_2_TIMER0 * EXP_MD_PERD * DEF_TIMER1_T0CLK_PERD_FREQ )
// )
// ) + 0.5
// ) ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TIME2
Exposure 1 Activation Time of second Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = (
(
EXP_OUT_T3_2 *
(
(
EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_TIMER0 | EXP_CLK_2_AUXIN1_AC0_CL |
EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
EXP_CLK_2_AUXIN2_AC3_DIG
) * ( 1000000000 / ( DEF_TIMER1_FREQ + ( ( DEF_TIMER1_FREQ == 0 ) * 1000000000 ) ) )
)
) + 0.5
) & 0xffffffff ;
//
//value = (
// (
// EXP_OUT_T3_2 *
// (
// (
// (
// EXP_SYN_CLK_2 | EXP_CLK_2_CLKGEN | EXP_CLK_2_HS | EXP_CLK_2_VS | EXP_CLK_2_AUXIN1_AC0_CL |
// EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA |
// EXP_CLK_2_AUXIN7_AC3_ANA | EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG |
// EXP_CLK_2_AUXIN2_AC3_DIG
// ) * ( 1000000000 / EXP_CLK_FREQ_2 )
// ) +
// ( EXP_CLK_2_TIMER0 * EXP_MD_PERD * DEF_TIMER1_T0CLK_PERD_FREQ )
// )
// ) + 0.5
// ) ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_MODE
Exposure 2 Output Polarity
eo_information
2
// --------------------------------------
Exp2mode regular
Exposure 2 Output Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Positive Output
Negative Output
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TRIGGER_MODE
Exposure 2 Trigger Polarity
eo_information
2
// --------------------------------------
Exp2trgmode regular
Exposure 1 Trigger Polarity
eo_information
1 2 unsigned flag_overflow
//
value = 1 ;
//
define_value
Level Low
Rising Edge
Falling Edge
Level High
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TRIGGER_FORMAT
Exposure 2 Trigger Format
eo_information
2
// --------------------------------------
exp1trgfmt regular
Exposure 1 Trigger Format
eo_information
0 2 unsigned flag_overflow
//
value = 1 ;
//
define_value
Opto
TTL
LVDS
422
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY1
Exposure 2 Time Delay of first Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY2
Exposure 2 Time Delay of second Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TIME1
Exposure 2 Activation Time of first Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TIME2
Exposure 2 Activation Time of second Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_MODE
Exposure 3 Output Polarity
eo_information
2
// --------------------------------------
Exp3mode regular
Exposure 3 Output Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Positive Output
Negative Output
// --------------------------------------
reserved protected
eo_information
0 31 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TRIGGER_MODE
Exposure 3 Trigger Polarity
eo_information
2
// --------------------------------------
Exp3trgmode regular
Exposure 3 Trigger Polarity
eo_information
1 2 unsigned flag_overflow
//
value = 1 ;
//
define_value
Level Low
Rising Edge
Falling Edge
Level High
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TRIGGER_FORMAT
Exposure 3 Trigger Format
eo_information
2
// --------------------------------------
exp3trgfmt regular
Exposure 3 Trigger Format
eo_information
0 2 unsigned flag_overflow
//
value = 1 ;
//
define_value
Opto
TTL
LVDS
422
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TIME_DELAY1
Exposure 3 Time Delay of first Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TIME_DELAY2
Exposure 3 Time Delay of second Pulse after Trigger
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TIME1
Exposure 3 Activation Time of first Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TIME2
Exposure 3 Activation Time of second Pulse
eo_information
1
0 32 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
// REGISTERS NOT USED ANYMORE : COMPATIBILITY DCFs LOAD
//
// =============================================
//
//
// =============================================
//
INFO_MODE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SIGNALBLACKLVL
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_SIGNALWHITELVL
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_LUTINSIZE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 5 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_LUTOUTSIZE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 5 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_CLCONFIGMODE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_PACKEDPIXELS
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T0TRGSRC
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T1TRGSRC
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T2TRGSRC
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T3TRGSRC
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T1EXPMOD
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T1DELAY2
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T2EXPMOD
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_T2DELAY2
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_0_CLOCK_SOURCE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_CLOCK_SOURCE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_CLOCK_SOURCE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_CLOCK_SOURCE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TIME
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TIME
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_1_TIME_DELAY
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TIME_DELAY
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TRIGGER_SOURCE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_3_TRIGGER_SOURCE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TRIGGER_MODE
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_M_GRAB_EXPOSURE_2_TRIGGER_FORMAT
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//***************************************************************************************************
//***************************************************************************************************
//***************************************************************************************************
//***************************************************************************************************
// <<<<<<<<<<< INFO_MASK >>>>>>>>>>>
// =============================================
//
INFO_MASK_TRGIN
Dynamic Triggers Input registers Mask
eo_information
5
// --------------------------------------
trigger0mask regular
Trigger0 Input Mask
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Trigger0 Bit Field in Trgin register NOT Updated
Trigger0 Bit Field in Trgin register Overwrited
// --------------------------------------
trigger1mask regular
Trigger1 Input Mask
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Trigger1 Bit Field in Trgin register NOT Updated
Trigger1 Bit Field in Trgin register Overwrited
// --------------------------------------
trigger2mask regular
Trigger2 Input Mask
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Trigger2 Bit Field in Trgin register NOT Updated
Trigger2 Bit Field in Trgin register Overwrited
// --------------------------------------
trigger3mask regular
Trigger3 Input Mask
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Trigger3 Bit Field in Trgin register NOT Updated
Trigger3 Bit Field in Trgin register Overwrited
// --------------------------------------
reserved protected
eo_information
0 28 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_USROUTDYN
Users Bits Output Dynamic Mask
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) |
( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 )
)
) ;
//
define_value
AP0 User 0 Output Available
AP0 User 0 Output Used
//
// --------------------------------------
usr1out regular
User 1 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) |
( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 )
)
) ;
//
define_value
AP0 User 1 Output Available
AP0 User 1 Output Used
//
// --------------------------------------
usr2out regular
User 2 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 2 Output Available
AP0 User 2 Output Used
//
// --------------------------------------
usr3out regular
User 3 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 3 Output Available
AP0 User 3 Output Used
//
// --------------------------------------
usr4out regular
User 4 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 4 Output Available
AP0 User 4 Output Used
//
// --------------------------------------
usr5out regular
User 5 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 5 Output Available
AP0 User 5 Output Used
//
// --------------------------------------
usr6out regular
User 6 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 6 Output Available
AP0 User 6 Output Used
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_USROUT0
Users Bits Output Mask for AP0
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC0_PROGRAMMED *
(
( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) |
( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 )
)
) ;
//
define_value
AP0 User 0 Output Available
AP0 User 0 Output Used
//
// --------------------------------------
usr1out regular
User 1 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC0_PROGRAMMED *
(
( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) |
( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 )
)
) ;
//
define_value
AP0 User 1 Output Available
AP0 User 1 Output Used
//
// --------------------------------------
usr2out regular
User 2 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 2 Output Available
AP0 User 2 Output Used
//
// --------------------------------------
usr3out regular
User 3 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 3 Output Available
AP0 User 3 Output Used
//
// --------------------------------------
usr4out regular
User 4 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 4 Output Available
AP0 User 4 Output Used
//
// --------------------------------------
usr5out regular
User 5 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 5 Output Available
AP0 User 5 Output Used
//
// --------------------------------------
usr6out regular
User 6 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP0 User 6 Output Available
AP0 User 6 Output Used
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_USROUT1
Users Bits Output Mask for AP1
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC1_PROGRAMMED *
(
( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) |
( CLB_CC1 == 4 ) | ( CLB_CC2 == 4 ) | ( CLB_CC3 == 4 ) | ( CLB_CC4 == 4 )
)
) ;
//
define_value
AP1 User 0 Output Available
AP1 User 0 Output Used
//
// --------------------------------------
usr1out regular
User 1 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC1_PROGRAMMED *
(
( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) |
( CLB_CC1 == 6 ) | ( CLB_CC2 == 6 ) | ( CLB_CC3 == 6 ) | ( CLB_CC4 == 6 )
)
) ;
//
define_value
AP1 User 1 Output Available
AP1 User 1 Output Used
//
// --------------------------------------
usr2out regular
User 2 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP1 User 2 Output Available
AP1 User 2 Output Used
//
// --------------------------------------
usr3out regular
User 3 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP1 User 3 Output Available
AP1 User 3 Output Used
//
// --------------------------------------
usr4out regular
User 4 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP1 User 4 Output Available
AP1 User 4 Output Used
//
// --------------------------------------
usr5out regular
User 5 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP1 User 5 Output Available
AP1 User 5 Output Used
//
// --------------------------------------
usr6out regular
User 6 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP1 User 6 Output Available
AP1 User 6 Output Used
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_USROUT2
Users Bits Output Mask for AP2
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC2_PROGRAMMED *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
) ;
//
define_value
AP2 User 0 Output Available
AP2 User 0 Output Used
//
// --------------------------------------
usr1out regular
User 1 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC2_PROGRAMMED *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
) ;
//
define_value
AP2 User 1 Output Available
AP2 User 1 Output Used
//
// --------------------------------------
usr2out regular
User 2 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP2 User 2 Output Available
AP2 User 2 Output Used
//
// --------------------------------------
usr3out regular
User 3 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP2 User 3 Output Available
AP2 User 3 Output Used
//
// --------------------------------------
usr4out regular
User 4 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP2 User 4 Output Available
AP2 User 4 Output Used
//
// --------------------------------------
usr5out regular
User 5 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP2 User 5 Output Available
AP2 User 5 Output Used
//
// --------------------------------------
usr6out regular
User 6 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP2 User 6 Output Available
AP2 User 6 Output Used
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_USROUT3
Users Bits Output Mask for AP3
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC3_PROGRAMMED *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
) ;
//
define_value
AP3 User 0 Output Available
AP3 User 0 Output Used
//
// --------------------------------------
usr1out regular
User 1 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC3_PROGRAMMED *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
) ;
//
define_value
AP3 User 1 Output Available
AP3 User 1 Output Used
//
// --------------------------------------
usr2out regular
User 2 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP3 User 2 Output Available
AP3 User 2 Output Used
//
// --------------------------------------
usr3out regular
User 3 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP3 User 3 Output Available
AP3 User 3 Output Used
//
// --------------------------------------
usr4out regular
User 4 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP3 User 4 Output Available
AP3 User 4 Output Used
//
// --------------------------------------
usr5out regular
User 5 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP3 User 5 Output Available
AP3 User 5 Output Used
//
// --------------------------------------
usr6out regular
User 6 Output Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
AP3 User 6 Output Available
AP3 User 6 Output Used
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLCLDYNL
Input/Output Control Dynamic MASK CL Low ***** Camera Link Module ONLY *****
eo_information
8
// --------------------------------------
clcc0sel regular
Camera Link Camera Control 0 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc1sel regular
Camera Link Camera Control 1 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc2sel regular
Camera Link Camera Control 2 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc3sel regular
Camera Link Camera Control 3 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
io0sel regular
Input/Output 0 Mask Selection in TTL Format << AP0:DB9-1 / AP1:HD44-35 >>
eo_information
0 4 unsigned flag_overflow
// Select always User USR1
//value = 0 ;
//
no_define_value
//
// --------------------------------------
io1sel regular
Input/Output 1 Mask Selection in TTL Format << AP0:HD44-13 / AP1:HD44-1 >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
io2sel regular
Input/Output 2 Mask Selection in TTL Format << AP0:HD44-43 / AP1:HD44-15 >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
out0sel regular
Output 0 Mask Selection in LVDS Format << AP0:HD44(20+4-) / AP1:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_LVDS * 0xF ) ;
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLCLDYNH
Input Output Control Dynamic MASK CL High ***** Camera Link Module ONLY *****
eo_information
3
// --------------------------------------
out1sel regular
Output 1 Mask Selection in LVDS Format << AP0:HD44(19+3-) / AP1:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 * 0xF ) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Mask Selection
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * VDT_INTERL * 0xF ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLCL0L
Input/Output Mask Control CL AP0 Low ***** Camera Link Module ONLY *****
eo_information
8
// --------------------------------------
clcc0sel regular
Camera Link Camera Control 0 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc1sel regular
Camera Link Camera Control 1 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc2sel regular
Camera Link Camera Control 2 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc3sel regular
Camera Link Camera Control 3 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
io0sel regular
Input/Output 0 Mask Selection in TTL Format << AP0:DB9-1 >>
eo_information
0 4 unsigned flag_overflow
// Select always User USR1
value = 0 ;
//
no_define_value
//
// --------------------------------------
io1sel regular
Input/Output 1 Mask Selection in TTL Format << AP0:HD44-13 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
io2sel regular
Input/Output 2 Mask Selection in TTL Format << AP0:HD44-43 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
out0sel regular
Output 0 Mask Selection in LVDS Format << AP0:HD44(20+4-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_LVDS * 0xF ) ;
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLCL0H
Input Output Control CL APO High ***** Camera Link Module ONLY *****
eo_information
3
// --------------------------------------
out1sel regular
Output 1 Mask Selection in LVDS Format << AP0:HD44(19+3-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 * 0xF ) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Mask Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * VDT_INTERL * 0xF ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLCL1L
Input/Output Control CL AP1 Low ***** Camera Link Module ONLY *****
eo_information
8
// --------------------------------------
clcc0sel regular
Camera Link Camera Control 0 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc1sel regular
Camera Link Camera Control 1 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc2sel regular
Camera Link Camera Control 2 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
clcc3sel regular
Camera Link Camera Control 3 Mask Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
io0sel regular
Input/Output 0 Mask Selection in TTL Format << AP1:HD44-35 >>
eo_information
0 4 unsigned flag_overflow
// Select always User USR1
value = 0 ;
//
no_define_value
//
// --------------------------------------
io1sel regular
Input/Output 1 Mask Selection in TTL Format << AP1:HD44-1 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
io2sel regular
Input/Output 2 Mask Selection in TTL Format << AP1:HD44-15 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 * 0xF ) ;
//
no_define_value
//
// --------------------------------------
out0sel regular
Output 0 Mask Selection in LVDS Format << AP1:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_LVDS * 0xF ) ;
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLCL1H
Input Output Control CL AP1 High ***** Camera Link Module ONLY *****
eo_information
3
// --------------------------------------
out1sel regular
Output 1 Mask Selection in LVDS Format << AP1:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 * 0xF ) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Mask Selection
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * VDT_INTERL * 0xF ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
INFO_MASK_IOCTLANDYN
Input/Output Control Dynamic MASK Analog AP ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output Mask User2/Exp0 << AP0:DVI0(23) / AP1:DVI0(6) / AP2:DVI1(23) / AP3:DVI1(6) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
out0sel regular
Out0 Mask Sel << AP0:HD44(15+30-) / AP1:HD44(43+42-) / AP2:HD44(40+25-) / AP3:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA * 0xF *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) |
( SYC_H_OUT * EXP_OUT_DEFAULT )
)
) ;
//
//value = (
// VDC_ANA * 0xF *
// (
// ( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) |
// ( SYC_H_OUT * EXP_OUT_DEFAULT ) | ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) )
// )
// ) ;
no_define_value
// --------------------------------------
out1sel regular
Out1 Mask Sel << AP0:HD44(44+29-) / AP1:HD44(11+27-) / AP2:HD44(20+4-) / AP3:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA * 0xF *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) |
( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
)
) ;
//
//value = (
// VDC_ANA * 0xF *
// (
// ( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) |
// ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) | ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) )
// )
// ) ;
no_define_value
// --------------------------------------
auxinfmt regular
Auxiliary Input Format Mask
eo_information
0 2 unsigned flag_overflow
//
value = (
VDC_ANA * 0x3 * ( DEF_TIMER0_ENABLED | DEF_TIMER1_ENABLED | ( GRB_MD_HW_TRG ) ) *
(
( ! GRB_TRG_1_AC0_OPTO_ANA ) * ( ! GRB_TRG_1_AC1_OPTO_ANA ) * ( ! GRB_TRG_1_AC2_OPTO_ANA ) *
( ! GRB_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC1_OPTO_ANA ) *
( ! EXP_0_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC0_OPTO_ANA ) *
( ! EXP_1_TRG_1_AC1_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC3_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC1_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC2_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC1_OPTO_ANA ) *
( ! ARM_EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC3_OPTO_ANA )
)
) ;
//
no_define_value
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format Mask
eo_information
0 2 unsigned flag_overflow
//
value = (
VDC_ANA * 0x3 *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS | ( SYC_H_OUT * EXP_OUT_DEFAULT ) ) ) |
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) ) )
)
) ;
//value = (
// VDC_ANA * 0x3 *
// (
// EXP_OUT_TTL | EXP_OUT_LVDS | EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_H_OUT * EXP_OUT_DEFAULT ) |
// ( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
// )
// ) ;
//
//value = (
// VDC_ANA * 0x3 *
// (
// EXP_OUT_TTL | EXP_OUT_LVDS | EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_H_OUT * EXP_OUT_DEFAULT ) |
// ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) | ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) )
// )
// ) ;
no_define_value
// --------------------------------------
fldinsel regular
Field Input Selection Mask
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
INFO_MASK_IOCTLAN0
Input/Output Control MASK Analog AP0 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output Mask User2/Exp0 << AP0:DVI0(23) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
out0sel regular
Out0 Mask Sel AP0 << AP0:HD44(15+30-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) |
( SYC_H_OUT * EXP_OUT_DEFAULT )
)
) ;
//
no_define_value
// --------------------------------------
out1sel regular
Out1 Mask Sel AP0 << AP0:HD44(44+29-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) |
( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
)
) ;
//
no_define_value
// --------------------------------------
auxinfmt regular
Auxiliary Input Format Mask AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA * 0x3 * ( DEF_TIMER0_ENABLED | DEF_TIMER1_ENABLED | ( GRB_MD_HW_TRG ) ) *
(
( ! GRB_TRG_1_AC0_OPTO_ANA ) * ( ! GRB_TRG_1_AC1_OPTO_ANA ) * ( ! GRB_TRG_1_AC2_OPTO_ANA ) *
( ! GRB_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC1_OPTO_ANA ) *
( ! EXP_0_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC0_OPTO_ANA ) *
( ! EXP_1_TRG_1_AC1_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC3_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC1_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC2_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC1_OPTO_ANA ) *
( ! ARM_EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC3_OPTO_ANA )
)
) ;
//
no_define_value
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format Mask AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA * 0x3 *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS | ( SYC_H_OUT * EXP_OUT_DEFAULT ) ) ) |
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) ) )
)
) ;
//value = (
// DEF_AC0_PROGRAMMED * VDC_ANA * 0x3 *
// (
// EXP_OUT_TTL | EXP_OUT_LVDS | EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_H_OUT * EXP_OUT_DEFAULT ) |
// ( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
// )
// ) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Selection Mask AP0
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
INFO_MASK_IOCTLAN1
Input/Output Control MASK Analog AP1 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output Mask User2/Exp0 AP1 << AP1:DVI0(6) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
out0sel regular
Out0 Mask Sel AP1 << AP1:HD44(43+42-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) |
( SYC_H_OUT * EXP_OUT_DEFAULT )
)
) ;
//
no_define_value
// --------------------------------------
out1sel regular
Out1 Mask Sel AP1 << AP1:HD44(11+27-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) |
( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
)
) ;
//
no_define_value
// --------------------------------------
auxinfmt regular
Auxiliary Input Format Mask AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA * 0x3 * ( DEF_TIMER0_ENABLED | DEF_TIMER1_ENABLED | ( GRB_MD_HW_TRG ) ) *
(
( ! GRB_TRG_1_AC0_OPTO_ANA ) * ( ! GRB_TRG_1_AC1_OPTO_ANA ) * ( ! GRB_TRG_1_AC2_OPTO_ANA ) *
( ! GRB_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC1_OPTO_ANA ) *
( ! EXP_0_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC0_OPTO_ANA ) *
( ! EXP_1_TRG_1_AC1_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC3_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC1_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC2_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC1_OPTO_ANA ) *
( ! ARM_EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC3_OPTO_ANA )
)
) ;
//
no_define_value
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format Mask AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA * 0x3 *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS | ( SYC_H_OUT * EXP_OUT_DEFAULT ) ) ) |
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) ) )
)
) ;
//value = (
// DEF_AC1_PROGRAMMED * VDC_ANA * 0x3 *
// (
// EXP_OUT_TTL | EXP_OUT_LVDS | EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_H_OUT * EXP_OUT_DEFAULT ) |
// ( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
// )
// ) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Selection Mask AP1
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
INFO_MASK_IOCTLAN2
Input/Output Control MASK Analog AP2 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output Mask User2/Exp0 AP2 << AP2:DVI1(23) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
out0sel regular
Out0 Mask Sel AP2 << AP2:HD44(40+25-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) |
( SYC_H_OUT * EXP_OUT_DEFAULT )
)
) ;
//
no_define_value
// --------------------------------------
out1sel regular
Out1 Mask Sel AP2 << AP2:HD44(20+4-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) |
( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
)
) ;
//
no_define_value
// --------------------------------------
auxinfmt regular
Auxiliary Input Format Mask AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA * 0x3 * ( DEF_TIMER0_ENABLED | DEF_TIMER1_ENABLED | ( GRB_MD_HW_TRG ) ) *
(
( ! GRB_TRG_1_AC0_OPTO_ANA ) * ( ! GRB_TRG_1_AC1_OPTO_ANA ) * ( ! GRB_TRG_1_AC2_OPTO_ANA ) *
( ! GRB_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC1_OPTO_ANA ) *
( ! EXP_0_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC0_OPTO_ANA ) *
( ! EXP_1_TRG_1_AC1_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC3_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC1_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC2_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC1_OPTO_ANA ) *
( ! ARM_EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC3_OPTO_ANA )
)
) ;
//
no_define_value
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format Mask AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA * 0x3 *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS | ( SYC_H_OUT * EXP_OUT_DEFAULT ) ) ) |
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) ) )
)
) ;
//value = (
// DEF_AC2_PROGRAMMED * VDC_ANA * 0x3 *
// (
// EXP_OUT_TTL | EXP_OUT_LVDS | EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_H_OUT * EXP_OUT_DEFAULT ) |
// ( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
// )
// ) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Selection Mask AP2
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
INFO_MASK_IOCTLAN3
Input/Output Control MASK Analog AP3 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output Mask User2/Exp0 AP3 << AP3:DVI1(6) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * DEF_TIMER0_ENABLED * EXP_OUT_TTL * 0xF ) ;
//
no_define_value
// --------------------------------------
out0sel regular
Out0 Mask Sel AP3 << AP3:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) |
( SYC_H_OUT * EXP_OUT_DEFAULT )
)
) ;
//
no_define_value
// --------------------------------------
out1sel regular
Out1 Mask Sel AP3 << AP3:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA * 0xF *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) |
( SYC_V_OUT * EXP_OUT_DEFAULT_2 )
)
) ;
//
no_define_value
// --------------------------------------
auxinfmt regular
Auxiliary Input Format Mask AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA * 0x3 * ( DEF_TIMER0_ENABLED | DEF_TIMER1_ENABLED | ( GRB_MD_HW_TRG ) ) *
(
( ! GRB_TRG_1_AC0_OPTO_ANA ) * ( ! GRB_TRG_1_AC1_OPTO_ANA ) * ( ! GRB_TRG_1_AC2_OPTO_ANA ) *
( ! GRB_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC1_OPTO_ANA ) *
( ! EXP_0_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC0_OPTO_ANA ) *
( ! EXP_1_TRG_1_AC1_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! EXP_1_TRG_1_AC3_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC1_OPTO_ANA ) * ( ! ARM_EXP_0_TRG_1_AC2_OPTO_ANA ) *
( ! ARM_EXP_0_TRG_1_AC3_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC0_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC1_OPTO_ANA ) *
( ! ARM_EXP_1_TRG_1_AC2_OPTO_ANA ) * ( ! ARM_EXP_1_TRG_1_AC3_OPTO_ANA )
)
) ;
//
no_define_value
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format Mask AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA * 0x3 *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS | ( SYC_H_OUT * EXP_OUT_DEFAULT ) ) ) |
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 | ( SYC_V_OUT * EXP_OUT_DEFAULT_2 ) ) )
)
) ;
//
no_define_value
// --------------------------------------
fldinsel regular
Field Input Selection Mask AP3
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLDIDYN
Input/Output Control Dynamic Digital ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * PCK_USE_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * EXP_OUT_TTL * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
in1fmt regular
Input 1 Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = (
// VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
// (
// GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG |
// GRB_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
// EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
// ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
// EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG |
// EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
// ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
// GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
// EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
// EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
// ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
// EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
// ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
// )
// ) ;
//
no_define_value
//
// --------------------------------------
in2fmt regular
Input 2 Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = (
// VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
// (
// GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG |
// GRB_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
// EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
// ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
// EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG |
// EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
// ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
// GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
// EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
// EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
// ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
// EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
// ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
// )
// ) ;
//
no_define_value
//
// --------------------------------------
out1fmt regular
Output 1 Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2fmt regular
Output 2 Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3fmt regular
Output 3 Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4fmt regular
Output 4 Format Mask
eo_information
0 2 unsigned flag_overflow
//
//value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction Mask
eo_information
0 1 unsigned flag_overflow
//
//value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLDI0
Input/Output Control Digital Mask AP0 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * PCK_USE_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * EXP_OUT_TTL * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
in1fmt regular
Input 1 Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG |
GRB_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG |
EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
in2fmt regular
Input 2 Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG |
GRB_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG |
EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
out1fmt regular
Output 1 Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2fmt regular
Output 2 Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3fmt regular
Output 3 Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4fmt regular
Output 4 Format Mask of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLDI1
Input/Output Control Digital Mask AP1 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * PCK_USE_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * EXP_OUT_TTL * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
in1fmt regular
Input 1 Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG |
GRB_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG |
EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
in2fmt regular
Input 2 Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG |
GRB_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG |
EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
out1fmt regular
Output 1 Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2fmt regular
Output 2 Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3fmt regular
Output 3 Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4fmt regular
Output 4 Format Mask of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLDI2
Input/Output Control Digital Mask AP2 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * PCK_USE_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * EXP_OUT_TTL * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
in1fmt regular
Input 1 Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG |
GRB_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG |
EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
in2fmt regular
Input 2 Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG |
GRB_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG |
EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
out1fmt regular
Output 1 Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2fmt regular
Output 2 Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3fmt regular
Output 3 Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4fmt regular
Output 4 Format Mask of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_IOCTLDI3
Input/Output Control Digital Mask AP3 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * PCK_USE_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * EXP_OUT_TTL * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
in1fmt regular
Input 1 Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG |
GRB_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG |
EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG |
EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG |
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
in2fmt regular
Input 2 Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * 3 *
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG |
GRB_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG |
EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
) ;
//
no_define_value
//
// --------------------------------------
out1fmt regular
Output 1 Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * SYC_H_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out2fmt regular
Output 2 Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * SYC_V_OUT * 3 ) ;
//
no_define_value
//
// --------------------------------------
out3fmt regular
Output 3 Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
out4fmt regular
Output 4 Format Mask of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED * 3 ) ;
//
no_define_value
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLCLDYN
Enable Control CL Dynamic Mask ***** Camera Link Module ONLY *****
eo_information
9
// --------------------------------------
syncout0 regular
<< HS : AP0:HD44(41+26-)/AP1:HD44(6+5-) VS : AP0:HD44(40+25-)/AP1:HD44(36+21-) >>
eo_information
0 1 unsigned flag_overflow
//
//value = ( SYC_H_OUT | SYC_V_OUT ) ;
//
define_value
Synchronization Output Available
Synchronization Output Used
//
// --------------------------------------
ttl0in regular
TTL User 0 Input Dynamic Mask Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV *
// (
// ( GRB_TRG_TTL * ( GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL * ( EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL * ( ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL_2 * ( EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL ) )
// )
// ) ;
//
define_value
TTL AUX 0 input Available
TTL AUX 0 input Used
//
// --------------------------------------
ttl1in regular
TTL User 1 Input Dynamic Mask Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV *
// (
// ( GRB_TRG_TTL * ( GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL * ( EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL * ( ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL_2 * ( EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL ) )
// )
// ) ;
//
define_value
TTL AUX 1 input Available
TTL AUX 1 input Used
//
// --------------------------------------
ttl2in regular
TTL User 2 Input Dynamic Mask Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV *
// (
// ( GRB_TRG_TTL * GRB_TRG_2_AC01_TTL_CL ) |
// ( EXP_TRG_TTL * EXP_0_TRG_2_AC01_TTL_CL ) |
// ( EXP_ARM_TTL * ARM_EXP_0_TRG_2_AC01_TTL_CL ) |
// ( EXP_TRG_TTL_2 * EXP_1_TRG_2_AC01_TTL_CL ) |
// ( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_2_AC01_TTL_CL )
// )
// ) ;
//
define_value
TTL AUX 2 input Available
TTL AUX 2 input Used
//
// --------------------------------------
ttl0out regular
TTL User 0 Output Dynamic Mask Enable
eo_information
0 1 unsigned flag_overflow
//
//value = 0 ;
//
define_value
TTL AUX 0 Output Available
TTL AUX 0 Output Used
//
// --------------------------------------
ttl1out regular
TTL User 1 Output Dynamic Mask Enable << AP0:HD44-13 / AP1:HD44-1 >>
eo_information
0 1 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
TTL AUX 1 Output Available
TTL AUX 1 Output Used
//
// --------------------------------------
ttl2out regular
TTL User 2 Output Dynamic Mask Enable << AP0:HD44-43 / AP1:HD44-15 >>
eo_information
0 1 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 ) ;
//
define_value
TTL AUX 2 Output Available
TTL AUX 2 Output Used
//
// --------------------------------------
cl0cc regular
Camera Link 0 Camera Controls Dynamic Mask Enable
eo_information
0 1 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * CLB_CCOUTEN1 ) ;
//
define_value
Camera Link 0 Camera Controls Available
Camera Link 0 Camera Controls Used
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLCL0
Enable Control CL Mask AP0 ***** Camera Link Module ONLY *****
eo_information
9
// --------------------------------------
syncout0 regular
Synchronisation Output Mask of AP0 << HS : AP0:HD44(41+26-) VS : AP0:HD44(40+25-) >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
Synchronization Output Available
Synchronization Output Used
//
// --------------------------------------
ttl0in regular
TTL User 0 Input Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 0 input Available
TTL AUX 0 input Used
//
// --------------------------------------
ttl1in regular
TTL User 1 Input Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 1 input Available
TTL AUX 1 input Used
//
// --------------------------------------
ttl2in regular
TTL User 2 Input Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC0_PROGRAMMED | DEF_AC0_CL_TRG2_TTL_ACTIF ) * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * GRB_TRG_2_AC01_TTL_CL ) |
( EXP_TRG_TTL * EXP_0_TRG_2_AC01_TTL_CL ) |
( EXP_ARM_TTL * ARM_EXP_0_TRG_2_AC01_TTL_CL ) |
( EXP_TRG_TTL_2 * EXP_1_TRG_2_AC01_TTL_CL ) |
( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_2_AC01_TTL_CL )
)
) ;
//
define_value
TTL AUX 2 input Available
TTL AUX 2 input Used
//
// --------------------------------------
ttl0out regular
TTL User 0 Output Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( USR_OTTL * USR_BIT_0_OTH0 ) ) ;
//
define_value
TTL AUX 0 Output Available
TTL AUX 0 Output Used
//
// --------------------------------------
ttl1out regular
TTL User 1 Output Enable Mask of AP0 << AP0:HD44-13 >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
TTL AUX 1 Output Available
TTL AUX 1 Output Used
//
// --------------------------------------
ttl2out regular
TTL User 2 Output Enable Mask of AP0 << AP0:HD44-43 >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 ) ;
//
define_value
TTL AUX 2 Output Available
TTL AUX 2 Output Used
//
// --------------------------------------
cl0cc regular
Camera Link 0 Camera Controls Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 ) ;
//
define_value
Camera Link 0 Camera Controls Available
Camera Link 0 Camera Controls Used
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLCL1
Enable Control CL Mask AP1 ***** Camera Link Module ONLY *****
eo_information
9
// --------------------------------------
syncout0 regular
Synchronisation Output Mask of AP1 << HS : AP1:HD44(6+5-) VS : AP1:HD44(36+21-) >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
Synchronization Output Available
Synchronization Output Used
//
// --------------------------------------
ttl0in regular
TTL User 0 Input Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 0 input Available
TTL AUX 0 input Used
//
// --------------------------------------
ttl1in regular
TTL User 1 Input Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 1 input Available
TTL AUX 1 input Used
//
// --------------------------------------
ttl2in regular
TTL User 2 Input Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC1_PROGRAMMED | DEF_AC1_CL_TRG3_TTL_ACTIF ) * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * GRB_TRG_3_AC01_TTL_CL ) |
( EXP_TRG_TTL * EXP_0_TRG_3_AC01_TTL_CL ) |
( EXP_ARM_TTL * ARM_EXP_0_TRG_3_AC01_TTL_CL ) |
( EXP_TRG_TTL_2 * EXP_1_TRG_3_AC01_TTL_CL ) |
( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_3_AC01_TTL_CL )
)
) ;
//
define_value
TTL AUX 2 input Available
TTL AUX 2 input Used
//
// --------------------------------------
ttl0out regular
TTL User 0 Output Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( USR_OTTL * USR_BIT_0_OTH0 ) ) ;
//
define_value
TTL AUX 0 Output Available
TTL AUX 0 Output Used
//
// --------------------------------------
ttl1out regular
TTL User 1 Output Enable Mask of AP1 << AP0:HD44-1 >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
TTL AUX 1 Output Available
TTL AUX 1 Output Used
//
// --------------------------------------
ttl2out regular
TTL User 2 Output Enable Mask of AP1 << AP0:HD44-15 >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 ) ;
//
define_value
TTL AUX 2 Output Available
TTL AUX 2 Output Used
//
// --------------------------------------
cl0cc regular
Camera Link 0 Camera Controls Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 ) ;
//
define_value
Camera Link 0 Camera Controls Available
Camera Link 0 Camera Controls Used
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLANDYN
Enable Control 1 Dynamic Mask ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
Input/Output Synchronization Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = ( VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
HS/VS Input/Output Available
HS/VS Input/Output Used
//
// --------------------------------------
ttllvdsen regular
TTL/LVDS Synchronization Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
TTL/LVDS Synchronization Available
TTL/LVDS Synchronization Used
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
//Enable Control Analog AP0 ***** Analog Module ONLY *****
INFO_MASK_ENCTLAN0
Enable Control Analog Mask AP0 ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
//Input/Output Synchronization Enable of AP0
inouten regular
<<IN= HS : AP0:DVI_0(13+12-) / HD44(35+34-) || VS : AP0:DVI_0(5+4-) / HD44(12+28-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = ( DEF_AC0_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
HS/VS Input/Output Available
HS/VS Input/Output Used
//
// --------------------------------------
//TTL/LVDS Synchronization Enable of AP0
ttllvdsen regular
<<OUT= HS : AP0:DVI_0(13+12-) / HD44(15+30-) || VS : AP0:DVI_0(5+4-) / HD44(44+29-)>>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
TTL/LVDS Synchronization Available
TTL/LVDS Synchronization Used
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLAN1
Enable Control Analog Mask AP1 ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
<<IN= HS : AP1:DVI_0(10+9-) / HD44(8+24-) || VS : AP1:DVI_0(2+1-) / HD44(39+38-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = ( DEF_AC1_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
HS/VS Input/Output Available
HS/VS Input/Output Used
//
// --------------------------------------
ttllvdsen regular
<<OUT= HS : AP1:DVI_0(10+9-) / HD44(43+42-) || VS : AP1:DVI_0(2+1-) / HD44(11+27-)>>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
TTL/LVDS Synchronization Available
TTL/LVDS Synchronization Used
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLAN2
Enable Control Analog Mask AP2 ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
<<IN= HS : AP1:DVI_1(13+12-) / HD44(7+22-) || VS : AP1:DVI_1(5+4-) / HD44(6+5-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = ( DEF_AC2_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
HS/VS Input/Output Available
HS/VS Input/Output Used
//
// --------------------------------------
ttllvdsen regular
<<OUT= HS : AP1:DVI_1(13+12-) / HD44(40+25-) || VS : AP1:DVI_1(5+4-) / HD44(20+4-)>>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
TTL/LVDS Synchronization Available
TTL/LVDS Synchronization Used
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLAN3
Enable Control Analog Mask AP3 ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
<<IN= HS : AP1:DVI_1(10+9-) / HD44(32+31-) || VS : AP1:DVI_1(2+1-) / HD44(1+16-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
HS/VS Input/Output Available
HS/VS Input/Output Used
//
// --------------------------------------
ttllvdsen regular
<<OUT= HS : AP1:DVI_1(10+9-) / HD44(33+18-) || VS : AP1:DVI_1(2+1-) / HD44(2+17-)>>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA * ( SYC_H_IN | SYC_V_IN | SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
TTL/LVDS Synchronization Available
TTL/LVDS Synchronization Used
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLDIDYN
Enable Control Digital Dynamic Mask ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Available
Aux1 TTL/LVDS input Used
//
// --------------------------------------
in2en regular
Input 2 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA |
EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG | EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN3_AC1_CL |
EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN5_AC2_ANA | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC0_DIG | EXP_CLK_2_AUXIN2_AC1_DIG | EXP_CLK_2_AUXIN2_AC2_DIG | EXP_CLK_2_AUXIN2_AC3_DIG
)
) ;
//
define_value
Aux2 TTL/LVDS input Available
Aux2 TTL/LVDS input Used
//
// --------------------------------------
in3en regular
Input 3 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = (
VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Available
Aux3 TTL input Used
//
// --------------------------------------
out1en regular
Output 1 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Available
Aux1 TTL/LVDS output Used
//
// --------------------------------------
out2en regular
Output 2 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Available
Aux2 TTL/LVDS output Used
//
// --------------------------------------
out3en regular
Output 3 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Available
Aux3 TTL/LVDS output Used
//
// --------------------------------------
out4en regular
Output 4 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Available
Aux4 TTL/LVDS output Used
//
// --------------------------------------
out5en regular
Output 5 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Available
Aux5 TTL/LVDS output Used
//
// --------------------------------------
out6en regular
Output 6 Enable Dynamic Mask
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Available
Aux6 TTL/LVDS output Used
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLDI0
Enable Control Digital Mask AP0 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Available
Aux1 TTL/LVDS input Used
//
// --------------------------------------
in2en regular
Input 2 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN2_AC0_DIG |
EXP_CLK_2_AUXIN1_AC0_CL | EXP_CLK_2_AUXIN1_AC0_ANA | EXP_CLK_2_AUXIN2_AC0_DIG
)
) ;
//
define_value
Aux2 TTL/LVDS input Available
Aux2 TTL/LVDS input Used
//
// --------------------------------------
in3en regular
Input 3 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Available
Aux3 TTL input Used
//
// --------------------------------------
out1en regular
Output 1 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Available
Aux1 TTL/LVDS output Used
//
// --------------------------------------
out2en regular
Output 2 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Available
Aux2 TTL/LVDS output Used
//
// --------------------------------------
out3en regular
Output 3 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Available
Aux3 TTL/LVDS output Used
//
// --------------------------------------
out4en regular
Output 4 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Available
Aux4 TTL/LVDS output Used
//
// --------------------------------------
out5en regular
Output 5 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Available
Aux5 TTL/LVDS output Used
//
// --------------------------------------
out6en regular
Output 6 Enable Mask of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Available
Aux6 TTL/LVDS output Used
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLDI1
Enable Control Digital Mask AP1 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Available
Aux1 TTL/LVDS input Used
//
// --------------------------------------
in2en regular
Input 2 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN3_AC1_ANA | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_2_AUXIN3_AC1_CL | EXP_CLK_2_AUXIN3_AC1_ANA | EXP_CLK_2_AUXIN2_AC1_DIG
)
) ;
//
define_value
Aux2 TTL/LVDS input Available
Aux2 TTL/LVDS input Used
//
// --------------------------------------
in3en regular
Input 3 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Available
Aux3 TTL input Used
//
// --------------------------------------
out1en regular
Output 1 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Available
Aux1 TTL/LVDS output Used
//
// --------------------------------------
out2en regular
Output 2 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Available
Aux2 TTL/LVDS output Used
//
// --------------------------------------
out3en regular
Output 3 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Available
Aux3 TTL/LVDS output Used
//
// --------------------------------------
out4en regular
Output 4 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Available
Aux4 TTL/LVDS output Used
//
// --------------------------------------
out5en regular
Output 5 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Available
Aux5 TTL/LVDS output Used
//
// --------------------------------------
out6en regular
Output 6 Enable Mask of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Available
Aux6 TTL/LVDS output Used
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLDI2
Enable Control Digital Mask AP2 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Available
Aux1 TTL/LVDS input Used
//
// --------------------------------------
in2en regular
Input 2 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_2_AUXIN5_AC2_ANA |
EXP_CLK_2_AUXIN2_AC2_DIG
)
) ;
//
define_value
Aux2 TTL/LVDS input Available
Aux2 TTL/LVDS input Used
//
// --------------------------------------
in3en regular
Input 3 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Available
Aux3 TTL input Used
//
// --------------------------------------
out1en regular
Output 1 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Available
Aux1 TTL/LVDS output Used
//
// --------------------------------------
out2en regular
Output 2 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Available
Aux2 TTL/LVDS output Used
//
// --------------------------------------
out3en regular
Output 3 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Available
Aux3 TTL/LVDS output Used
//
// --------------------------------------
out4en regular
Output 4 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Available
Aux4 TTL/LVDS output Used
//
// --------------------------------------
out5en regular
Output 5 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Available
Aux5 TTL/LVDS output Used
//
// --------------------------------------
out6en regular
Output 6 Enable Mask of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Available
Aux6 TTL/LVDS output Used
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MASK_ENCTLDI3
Enable Control Digital Mask AP3 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Available
Aux1 TTL/LVDS input Used
//
// --------------------------------------
in2en regular
Input 2 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG
)
) |
EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC3_DIG | EXP_CLK_2_AUXIN7_AC3_ANA |
EXP_CLK_2_AUXIN2_AC3_DIG
)
) ;
//
define_value
Aux2 TTL/LVDS input Available
Aux2 TTL/LVDS input Used
//
// --------------------------------------
in3en regular
Input 3 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Available
Aux3 TTL input Used
//
// --------------------------------------
out1en regular
Output 1 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Available
Aux1 TTL/LVDS output Used
//
// --------------------------------------
out2en regular
Output 2 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Available
Aux2 TTL/LVDS output Used
//
// --------------------------------------
out3en regular
Output 3 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Available
Aux3 TTL/LVDS output Used
//
// --------------------------------------
out4en regular
Output 4 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Available
Aux4 TTL/LVDS output Used
//
// --------------------------------------
out5en regular
Output 5 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Available
Aux5 TTL/LVDS output Used
//
// --------------------------------------
out6en regular
Output 6 Enable Mask of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Available
Aux6 TTL/LVDS output Used
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
// <<<<<<<<<<< INFO_MASK >>>>>>>>>>>
//***************************************************************************************************
//***************************************************************************************************
//***************************************************************************************************
//***************************************************************************************************
// =============================================
//
// =============================================
//
//
// *********************************************
// FPGA Chip VIDEO(BEGIN) ACQ. CTRL
// *********************************************
//
// =============================================
//
//
// =============================================
//
DIG_HCNT
Horizontal Count
eo_information
2
// --------------------------------------
hcnt protected
Horizontal Count
eo_information
1 24 unsigned flag_overflow
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HTOTAL
Horizontal Total Count
eo_information
2
// --------------------------------------
htotal regular
Horizontal Total Count
eo_information
1 24 unsigned flag_overflow
//
value = (
(
( VDT_HTOTAL > 0 ) *
(
VDT_HTOTAL - 1 + DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO + DEF_ADD_HTOTAL_EQUA_HEVAL +
( TM_ENABLE * CT_FS * CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID > 0 ) )
)
) &
(
( VDC_DIG * 0x00FFFFFF ) +
( VDC_ANA * 0x0000FFFF )
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HSCNT
Horizontal Set Count
eo_information
2
// --------------------------------------
hscnt regular
Horizontal Set Count
eo_information
1 24 unsigned flag_overflow
//
value = (
0 &
(
( VDC_DIG * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HECNT
Horizontal End Count
eo_information
2
// --------------------------------------
hecnt protected
Horizontal End Count
eo_information
1 24 unsigned flag_overflow
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HSSYNC
Horizontal Start Sync
eo_information
2
// --------------------------------------
hssync regular
Horizontal Start Sync
eo_information
1 24 unsigned flag_overflow
//
value = (
0 &
(
( VDC_DIG * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HESYNC
Horizontal End Sync
eo_information
2
// --------------------------------------
hesync regular
Horizontal End Sync
eo_information
1 24 unsigned flag_overflow
//
value = (
( ( VDT_HSYNC > 1 ) * ( VDT_HSYNC - 1 ) ) &
(
( VDC_DIG * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HSVAL
Horizontal Start Valid
eo_information
2
// --------------------------------------
hsval regular
Horizontal Start Valid
eo_information
1 24 unsigned flag_overflow
//
value = (
(
( ( ! ( VDC_ANA * SYC_CAM_GEN * SYC_DIG * ( TM_ENABLE == 0 ) ) ) * ( VDT_HSYNC + VDT_HBPORCH ) ) +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) + DEF_HDELAY +
( VDC_ANA * SYC_CAM_GEN * SYC_DIG * ( VDT_HBPORCH - SYC_CAM_LATENCY ) )
) &
(
( VDC_DIG * 0x00FFFFFF ) +
( VDC_ANA * 0x0000FFFF )
)
) ;
//
no_define_value
//
//
//..............................
// Replaced to include New FPGA Option Camera Valids Delayed in CL
//value = (
// (
// VDT_HSYNC + VDT_HBPORCH + DEF_HDELAY + ( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY )
// ) &
// (
// ( VDC_DIG * 0x00FFFFFF ) +
// ( VDC_ANA * 0x0000FFFF )
// )
// ) ;
//
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HEVAL
Horizontal End Valid
eo_information
2
// --------------------------------------
heval regular
Horizontal End Valid
eo_information
1 24 unsigned flag_overflow
//
value = (
(
(
(
( ( ! ( VDC_ANA * SYC_CAM_GEN * SYC_DIG * ( TM_ENABLE == 0 ) ) ) * VDT_HSYNC ) + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) - 1 - ( VDC_ANA * SYC_DIG * SYC_CAM_GEN * SYC_CAM_LATENCY )
) *
(
(
( ( ! ( VDC_ANA * SYC_CAM_GEN * SYC_DIG * ( TM_ENABLE == 0 ) ) ) * VDT_HSYNC ) + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY ) - 1 - ( VDC_ANA * SYC_DIG * SYC_CAM_GEN * SYC_CAM_LATENCY )
)
<= ( ( VDT_HTOTAL > 0 ) * ( VDT_HTOTAL - 1 + DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO + DEF_ADD_HTOTAL_EQUA_HEVAL ) )
)
) +
(
( ( ( ! ( VDC_ANA * SYC_CAM_GEN * SYC_DIG * ( TM_ENABLE == 0 ) ) ) * VDT_HSYNC ) + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY )
- VDT_HTOTAL - 1
) *
(
( ( ( ! ( VDC_ANA * SYC_CAM_GEN * SYC_DIG * ( TM_ENABLE == 0 ) ) ) * VDT_HSYNC ) + VDT_HBPORCH + VDT_HACTIVE + DEF_HDELAY +
( DEF_DIGITIZER_MASTER * VDC_ANA * SYC_CAM_LATENCY )
- VDT_HTOTAL - 1
)
> ( ( VDT_HTOTAL > 0 ) * ( VDT_HTOTAL - 1 + DEF_ADD_3MAX_TOTAL_HVBLANK_ZERO ) )
)
)
) &
(
( VDC_DIG * 0x00FFFFFF ) +
( VDC_ANA * 0x0000FFFF )
)
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HSCLM
Horizontal Start Clamping
eo_information
2
// --------------------------------------
hsclm regular
Horizontal Start Clamping
eo_information
1 24 unsigned flag_overflow
//
// Sample-Hold(15ns) Hold-Sample(40ns) => Total 55ns min clamping?
// ****** Clamping in back porch OUTSIDE the Color Burst Area ****** Reason: Stability
// Front Porch (to be review)
value = (
(
VDC_ANA *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
) *
(
( VDT_CLP_BPO *
(
( ( SYC_ANA | DEF_DIGITIZER_MASTER ) * ( VDT_HSYNC + DEF_HCLAMP_MARGIN ) ) +
(
SYC_DIG * SYC_CAM_GEN * ( DEF_HCLAMP_MARGIN -
( SYC_CAM_LATENCY * ( SYC_CAM_LATENCY <= DEF_HCLAMP_MARGIN ) ) -
( DEF_HCLAMP_MARGIN * ( SYC_CAM_LATENCY > DEF_HCLAMP_MARGIN ) )
)
)
)
) +
(
VDT_CLP_SYN *
(
( ( SYC_ANA | DEF_DIGITIZER_MASTER ) * DEF_HCLAMP_MARGIN ) +
( SYC_DIG * SYC_CAM_GEN * ( VDT_HTOTAL + DEF_HCLAMP_MARGIN - VDT_HSYNC - SYC_CAM_LATENCY ) )
)
) +
(
VDT_CLP_FPO *
(
( ( SYC_ANA | DEF_DIGITIZER_MASTER ) * ( VDT_HTOTAL + DEF_HCLAMP_MARGIN - VDT_HFPORCH ) ) +
( SYC_DIG * SYC_CAM_GEN * ( VDT_HTOTAL + DEF_HCLAMP_MARGIN - VDT_HSYNC - VDT_HFPORCH - SYC_CAM_LATENCY ) )
)
) +
( DEF_DIGITIZER_MASTER * SYC_DIG * SYC_CAM_LATENCY )
)
) &
(
( VDC_DIG * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HECLM
Horizontal End Clamping
eo_information
2
// --------------------------------------
heclm regular
Horizontal End Clamping
eo_information
1 24 unsigned flag_overflow
//
// Front Porch (to be review)
value = (
(
VDC_ANA *
(
VDC_0_AC_WITH_DC | VDC_0_DC_WITH_DC | VDC_1_AC_WITH_DC | VDC_1_DC_WITH_DC |
VDC_2_AC_WITH_DC | VDC_2_DC_WITH_DC | VDC_3_AC_WITH_DC | VDC_3_DC_WITH_DC
) *
(
( VDT_CLP_BPO * (
( ( SYC_ANA | DEF_DIGITIZER_MASTER ) * ( VDT_HSYNC + VDT_HBPORCH - DEF_HCLAMP_MARGIN ) ) +
( SYC_DIG * SYC_CAM_GEN * ( VDT_HBPORCH - DEF_HCLAMP_MARGIN - SYC_CAM_LATENCY ) ) - 1
)
) +
( VDT_CLP_SYN * (
( ( SYC_ANA | DEF_DIGITIZER_MASTER ) * ( VDT_HSYNC - DEF_HCLAMP_MARGIN ) ) +
( SYC_DIG * SYC_CAM_GEN * ( VDT_HTOTAL - DEF_HCLAMP_MARGIN - SYC_CAM_LATENCY ) ) - 1
)
) +
( VDT_CLP_FPO * (
( ( SYC_ANA | DEF_DIGITIZER_MASTER ) * ( VDT_HTOTAL - DEF_HCLAMP_MARGIN ) ) +
( SYC_DIG * SYC_CAM_GEN * ( VDT_HTOTAL - VDT_HSYNC - DEF_HCLAMP_MARGIN - SYC_CAM_LATENCY ) ) - 1
)
) +
( DEF_DIGITIZER_MASTER * SYC_DIG * SYC_CAM_LATENCY )
)
) &
(
( VDC_DIG * 0xFFFFFF ) +
( VDC_ANA * 0xFFFF )
)
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_HCTL
Horizontal Control
eo_information
8
// --------------------------------------
hldsel regular
Horizontal Load Select
eo_information
0 4 unsigned flag_overflow
//
value = (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) +
( VDC_ANA * VDC_ANA * ( ! DEF_DIGITIZER_MASTER ) * 2 )
) ;
//
define_value
External line valid
External horizontal reference (DVI on Analog Connector)
Noise-gated horizontal reference
External Horizontal Reference from Analog Auxiliairy Connector
External Frame Valid for Camera Link
External Vertical Reference for Analog
reserved
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
Exposure 0 output
Exposure 1 output
Exposure 0 output from lower of two adjacent ACs
Exposure 0 output from lower of four adjacent ACs
// --------------------------------------
hldpol regular
Horizontal Load Polarity
eo_information
0 1 unsigned flag_overflow
// Default 1. Resetting on second edge sync. to prevent HEVAL overlapp Htotal => missing first line.
value = ( ( VDC_ANA | ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) ) ) * SYC_DIG * SYC_H_INEG ) ;
//
define_value
Rising edge
Falling edge
// --------------------------------------
hlden regular
Horizontal Load Enable
eo_information
0 1 unsigned flag_overflow
// Synchronize with HS of camera
//
value = (
( CAMERA_LINK_AV * ( SYC_CAM_GEN > 0 ) ) | ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( SYC_CAM_GEN > 0 ) ) |
( ( DEF_HELIOS_ANA | DEF_ODYSSEY_ANA | DEF_SOLIOS_ANA ) * PCK_CAM_GEN * ( ! PCK_USE_OUT ) * ( ! DEF_DIGITIZER_MASTER ) )
) ;
//
define_value
Disabled
Enabled
// --------------------------------------
hldbps regular
Horizontal Load ByPass Synchronisation
eo_information
0 1 unsigned flag_overflow
//
value = ( CAMERA_LINK_AV | PCK_CAM_REC | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) ;
//
define_value
Loaded signal resynchronized
Loaded signal not resynchronized
//
// --------------------------------------
hcnten regular
Horizontal Counter Enable
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
honesht regular
Horizontal One Shot Mode
eo_information
0 1 unsigned flag_overflow
//
value = (
( CT_LS * SYC_CAM_GEN ) |
( ( DEF_HELIOS_ANA | DEF_ODYSSEY_ANA | DEF_SOLIOS_ANA ) * SYC_DIG * SYC_H_IN * SYC_V_IN * PCK_CAM_GEN * ( ! PCK_USE_OUT ) ) |
( CAMERA_LINK_AV * ( SYC_CAM_GEN > 0 ) ) | ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( SYC_CAM_GEN > 0 ) )
) ;
define_value
Disabled
Enabled
// --------------------------------------
hsyncpol regular
Horizontal Sync Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active Low
Active High
//
// --------------------------------------
reserved protected
eo_information
0 22 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VCNT
Vertical Count
eo_information
2
// --------------------------------------
vcnt protected
Vertical Count
eo_information
1 20 unsigned flag_overflow
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VTOTAL
Vertical Total Count
eo_information
2
// --------------------------------------
vtotal regular
Vertical Total Count
eo_information
1 20 unsigned flag_overflow
//
// Fix of New Feature Line Scan Variable Frame Line Count
value = (
(
(
CT_FS * ( VDT_VTOTAL > 0 ) *
(
VDT_VTOTAL - 1 + ( TM_ENABLE * CT_FS * CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID > 0 ) )
)
) +
( CT_LS * ( VDT_VACTIVE - 1 + ( CT_LS * CAMERA_LINK_AV * TM_ENABLE ) ) )
) &
(
( VDC_DIG * 0x00FFFFFF ) +
( VDC_ANA * 0x0000FFFF )
)
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VSCNT
Vertical Set Count
eo_information
2
// --------------------------------------
vscnt regular
Vertical Set Count
eo_information
1 20 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VECNT
Vertical End Count
eo_information
2
// --------------------------------------
vecnt protected
Vertical End Count
eo_information
0 20 unsigned flag_overflow
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VSSYNC
Vertical Start Sync
eo_information
2
// --------------------------------------
vssync regular
Vertical Start Sync
eo_information
1 20 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VESYNC
Vertical End Sync
eo_information
2
// --------------------------------------
vesync regular
Vertical End Sync
eo_information
1 20 unsigned flag_overflow
//
value = (
( VDT_VSYNC > 1 ) * ( VDT_VSYNC - 1 )
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VSVAL
Vertical Start Valid
eo_information
2
// --------------------------------------
vsval regular
Vertical Start Valid
eo_information
1 20 unsigned flag_overflow
//
value = ( CT_FS * ( VDT_VSYNC + VDT_VBPORCH - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VEVAL
Vertical End Valid
eo_information
2
// --------------------------------------
veval regular
Vertical End Valid
eo_information
1 20 unsigned flag_overflow
//
value = (
(
(
CT_FS *
(
(
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) *
( ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) <= ( VDT_VTOTAL - 1 ) )
) +
(
( ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) - VDT_VTOTAL ) *
( ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( ( ( VDT_VSYNC + VDT_VBPORCH ) % 2 ) * VDT_INTERL ) ) * ( ! CT_LS ) ) > ( VDT_VTOTAL - 1 ) )
)
)
) +
(
CT_LS *
(
(
(
GRB_LS_FREE_RUN | GRB_LS_FIXED_LINE | GRB_LS_VARIABLE_LINE | GRB_LS_FRMFIX_LINEFIX |
GRB_LS_FRMFIX_LINEVAR
) * ( TM_ENABLE == 0 ) * 0xFFFFF
) +
( CAMERA_LINK_AV * TM_ENABLE * ( VDT_VACTIVE - 1 ) )
)
)
) &
(
( VDC_DIG * 0x00FFFFFF ) +
( VDC_ANA * 0x0000FFFF )
)
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VSCLM
Vertical Start Clamping
eo_information
2
// --------------------------------------
vsclm regular
Vertical Start Clamping
eo_information
1 20 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDT_VSYNC > 0 ) * ( VDT_VSYNC + ( 0.25 * VDT_VBPORCH ) ) ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VECLM
Vertical End Clamping
eo_information
2
// --------------------------------------
veclm regular
Vertical End Clamping
eo_information
1 20 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + ( 0.75 * VDT_VFPORCH ) - 1 ) ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_VCTL
Vertical Control
eo_information
10
// --------------------------------------
vldsel regular
Vertical Load Select
eo_information
0 4 unsigned flag_overflow
//
value = (
(
VDC_ANA *
(
( SYC_DIG * SYC_V_IN ) +
(
(
( SYC_ANA * SYC_MD_CSYN * ( ! DEF_DIGITIZER_MASTER ) ) |
( DEF_DIGITIZER_MASTER * ( GRB_MD_CONT | GRB_ACT_NXT_FRM | GRB_TRG_VS_PSG ) )
) * 2
) +
(
( ( DEF_DIGITIZER_MASTER * CT_FS ) | CT_LS ) * GRB_MD_HW_TRG * ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) *
(
( GRB_TRG_TIMER0 * 12 ) +
( GRB_TRG_TIMER1 * 13 )
)
) +
(
(
( DEF_DIGITIZER_MASTER * SYC_DIG * GRB_MD_HW_TRG * ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) ) |
( CT_LS * ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) )
) *
(
(
(
GRB_TRG_0_AC0_TTL_ANA | GRB_TRG_0_AC1_TTL_ANA | GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC3_TTL_ANA
) * 8
) +
(
(
GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_1_AC1_OPTO_ANA | GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_1_AC3_OPTO_ANA
) * 9
) +
(
(
GRB_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX6_TTL_ANA |
GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA
) * 10
) +
(
(
GRB_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX7_TTL_ANA |
GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA
) * 11
)
)
)
)
) +
(
CAMERA_LINK_AV *
(
CT_LS * ( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR | GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR ) *
(
( ( GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_0_AC1_TTL_CL ) * 8 ) +
( ( GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC1_TTL_CL ) * 9 ) +
( ( GRB_TRG_2_AC01_OPTO_CL | GRB_TRG_2_AC01_TTL_CL | GRB_TRG_2_AC01_LVDS_CL ) * 10 ) +
( ( GRB_TRG_3_AC01_OPTO_CL | GRB_TRG_3_AC01_TTL_CL | GRB_TRG_3_AC01_LVDS_CL ) * 11 ) +
( GRB_TRG_TIMER0 * 12 ) + ( GRB_TRG_TIMER1 * 13 )
)
)
) +
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( SYC_CAM_GEN * CT_FS ) | ( ( SYC_CAM_GEN == 0 ) * CT_FS * ( ! GRB_ACT_IMMEDIATE ) ) |
( CT_LS * ( GRB_LS_FREE_RUN | GRB_LS_FIXED_LINE | GRB_LS_VARIABLE_LINE ) )
) +
(
(
( ( SYC_CAM_GEN == 0 ) * CT_FS * GRB_ACT_IMMEDIATE ) |
( CT_LS *
( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR | GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR )
)
) *
(
(
(
GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_0_AC3_OPTO_DIG |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG
) * 8
) +
(
(
GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG |
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
) * 9
) +
(
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG
) * 10
) +
(
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG
) * 11
) + ( GRB_TRG_TIMER0 * 12 ) + ( GRB_TRG_TIMER1 * 13 )
)
)
)
)
) ;
//
define_value
External frame valid synchronization
External vertical reference ( DVI Analog Connector )
Noise-gated vertical reference
Other External Vertical Reference from Auxiliairy Connector
reserved
reserved
reserved
Capture Ignore
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
Exposure 0 output
Exposure 1 output
Exposure output from other AC
Exposure 1 output from lower of two adjacent ACs
// --------------------------------------
vldpol regular
Vertical Load Polarity
eo_information
0 1 unsigned flag_overflow
//
value = (
( SYC_V_INEG * SYC_DIG * ( VDC_ANA | DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) ) |
(
VDC_ANA * DEF_DIGITIZER_MASTER *
( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) * GRB_TRG_NEG
) |
(
CAMERA_LINK_AV * CT_LS * GRB_TRG_NEG *
( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR | GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR )
)
) ;
//
define_value
Rising edge
Falling edge
// --------------------------------------
vlden regular
Vertical Load Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( ! (
( TM_ENABLE * DEF_DIGITIZER_MASTER ) |
( CT_LS * GRB_MD_CONT ) |
( DEF_DIGITIZER_MASTER * ( GRB_MD_CONT | GRB_ACT_NXT_FRM | GRB_TRG_VS_PSG ) )
)
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
vldbps regular
Vertical Load ByPass Synchronisation
eo_information
0 1 unsigned flag_overflow
//
value = (
(
CAMERA_LINK_AV *
(
CT_FS |
( CT_LS * ( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR | GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR ) )
)
) |
( VDC_ANA * CT_LS * PCK_CAM_GEN ) |
DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG
) ;
//
define_value
Vert load signal resynchronised
Vert load signal not resynchronised
// --------------------------------------
vldal regular
Vertical Load Alignment
eo_information
0 3 unsigned flag_overflow
//
value = (
VDT_INTERL +
( VDT_NINTRL * 2 )
) ;
//
define_value
Not aligned
Aligned to Htotal or Htotal/2
Aligned with horizontal load signal or HTOTAL
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
vnbfrm regular
Vertical Number of Frames
eo_information
0 3 unsigned flag_overflow
//
value = GRB_ACT_IMM_SKP_NFR ;
//
//value = (
// GRB_ACT_IMMEDIATE *
// (
// GRB_ACT_IMM_SKP_NFR +
// ( GRB_ACT_IMM_SKP_N2FR * 2 ) +
// ( GRB_ACT_IMM_SKP_N3FR * 3 ) +
// ( GRB_ACT_IMM_SKP_N4FR * 4 ) +
// ( GRB_ACT_IMM_SKP_N5FR * 5 ) +
// ( GRB_ACT_IMM_SKP_N6FR * 6 ) +
// ( GRB_ACT_IMM_SKP_N7FR * 7 )
// )
// ) ;
//
define_value
No effect
1 frame
2 frames
3 frames
4 frames
5 frames
6 frames
7 frames
//
// --------------------------------------
vcnten regular
Vertical Counter Enable
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
vonesht regular
Vertical One Shot Mode
eo_information
0 1 unsigned flag_overflow
// Soft or Hard
value = (
(
VDC_ANA * ( ! (
(
DEF_DIGITIZER_MASTER * ( GRB_MD_CONT | GRB_MD_SW_TRG | ( GRB_MD_HW_TRG * GRB_TRG_VS_PSG ) )
) |
( CT_LS * GRB_MD_CONT )
)
)
) +
(
SYC_DIG * ( CLC_MODE_CH0 > 0 ) * SYC_CAM_GEN *
(
CT_FS |
( CT_LS *
(
GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR |
GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR
)
)
)
) +
(
VDC_DIG * ( CLC_MODE_CH0 == 0 ) *
( ( CT_LS * ( ! GRB_MD_CONT ) ) | ( CT_FS * ( ! GRB_TRG_VS_PSG ) * ( ! ( ( SYC_CAM_GEN == 0 ) * GRB_MD_CONT ) ) ) )
)
) ;
//
// (
// VDC_ANA * ( ! ( DEF_DIGITIZER_MASTER | ( CT_LS * GRB_MD_CONT ) ) )
// ) +
define_value
One-shot mode disabled
One-shot mode enabled
// --------------------------------------
vsyncpol regular
Vertical Sync Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Active Low
Active High
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// T0SCNT |
// | EXP_OUT_T0 Delay 0
// T0S0PUL |____
// |
// | EXP_OUT_T1 Pulse 0
// |
// T0E0PUL |----
// | EXP_OUT_T2 Delay 1
// |
// T0S1PUL |____
// | EXP_OUT_T3 Pulse 1
// T0CNT=0 |----
//
DIG_T0CNT
Timer 0 Counter
eo_information
1
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_T0SCNT
Timer 0 Start Count
eo_information
1
0 24 unsigned flag_overflow
//
value = ( ( EXP_OUT_T0 + EXP_OUT_T1 + EXP_OUT_T2 + EXP_OUT_T3 - DEF_TIMER0_TRIGGERS_PIPE_DELAY ) & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T0S0PUL
Timer 0 Start 1st pulse
eo_information
1
0 24 unsigned flag_overflow
//
value = ( ( EXP_OUT_T3 + EXP_OUT_T2 + EXP_OUT_T1 ) & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T0E0PUL
Timer 0 End 1st pulse
eo_information
1
0 24 unsigned flag_overflow
//
value = ( ( EXP_OUT_T3 + EXP_OUT_T2 ) & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T0S1PUL
Timer 0 Start 2nd pulse
eo_information
1
0 24 unsigned flag_overflow
//
value = ( EXP_OUT_T3 & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T0CTLL
Timer 0 Control Low
eo_information
19
// --------------------------------------
t0sts protected
Timer 0 Status
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//Timer0 Inactive
//Timer0 Active
//
// --------------------------------------
t0armsts protected
Timer 0 Arming Circuit Status
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//Timer0 arming Inactive
//Timer0 arming Active
//
// --------------------------------------
t0out protected
Timer 0 Output Status
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//Timer0 Output is Low
//Timer0 Output is High
//
// --------------------------------------
t0outpol regular
Timer 0 Output Polarity
eo_information
0 1 unsigned flag_overflow
//
value = EXP_OUT_NEG ;
//
define_value
Timer 0 output High
Timer 0 output Low
//
// --------------------------------------
t0outen regular
Timer 0 Output Enable
eo_information
0 1 unsigned flag_overflow
//
value = DEF_TIMER0_ENABLED ;
//
define_value
Timer 0 output Disabled
Timer 0 output Enabled
//
// --------------------------------------
t0cnten regular
Timer 0 Counter Enable
eo_information
0 1 unsigned flag_overflow
//
value = DEF_TIMER0_ENABLED ;
//
define_value
Timer 0 counter Disabled
Timer 0 counter Enabled
//
// --------------------------------------
t0onesht regular
Timer 0 One-shot Mode
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_MD_W_TRG * ( ! EXP_MD_PERD ) ) ;
//
define_value
One-shot mode Disabled
One-shot mode Enabled
//
// --------------------------------------
t0cont regular
Timer 0 Continuous
eo_information
0 1 unsigned flag_overflow
//
value = EXP_MD_PERD ;
//
define_value
Continuous mode Disabled
Continuous mode Enabled
//
// --------------------------------------
t0armsel regular
Timer 0 Arming Circuit Selection
eo_information
0 4 unsigned flag_overflow
//
// Select Soft Arm if Used by Grab, if not, set to 0 to mask Trigger Events
//
value = (
EXP_ARM_ENABLE *
(
ARM_EXP_0_SOFTWARE +
( DEF_TIMER1_ENABLED * ARM_EXP_0_TIMER1 * 2 ) +
(
EXP_MD_W_TRG * 3 *
(
ARM_EXP_0_TRG_TIMER0_AC0 + ARM_EXP_0_TRG_TIMER0_AC1 + ARM_EXP_0_TRG_TIMER0_AC2 +
ARM_EXP_0_TRG_TIMER0_AC3
)
) +
( ARM_EXP_0_HS_PSG * 4 ) +
( ARM_EXP_0_VS_PSG * 5 ) +
(
(
ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
) * 6
) +
(
(
ARM_EXP_0_TRG_0_AC0_OPTO_CL | ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL |
ARM_EXP_0_TRG_0_AC1_OPTO_CL | ARM_EXP_0_TRG_0_AC1_LVDS_CL |
ARM_EXP_0_TRG_0_AC0_TTL_ANA | ARM_EXP_0_TRG_0_AC1_TTL_ANA | ARM_EXP_0_TRG_0_AC2_TTL_ANA | ARM_EXP_0_TRG_0_AC3_TTL_ANA |
ARM_EXP_0_TRG_0_AC0_OPTO_DIG | ARM_EXP_0_TRG_0_AC1_OPTO_DIG | ARM_EXP_0_TRG_0_AC2_OPTO_DIG | ARM_EXP_0_TRG_0_AC3_OPTO_DIG |
ARM_EXP_0_TRG_0_AC0_LVDS_DIG | ARM_EXP_0_TRG_0_AC1_LVDS_DIG | ARM_EXP_0_TRG_0_AC2_LVDS_DIG | ARM_EXP_0_TRG_0_AC3_LVDS_DIG |
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG | ARM_EXP_0_TRG_1_AC3_TTL_DIG
) * 8
) +
(
(
ARM_EXP_0_TRG_1_AC0_OPTO_CL | ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL |
ARM_EXP_0_TRG_1_AC1_OPTO_CL | ARM_EXP_0_TRG_1_AC1_LVDS_CL |
ARM_EXP_0_TRG_1_AC0_OPTO_ANA | ARM_EXP_0_TRG_1_AC1_OPTO_ANA | ARM_EXP_0_TRG_1_AC2_OPTO_ANA | ARM_EXP_0_TRG_1_AC3_OPTO_ANA |
ARM_EXP_0_TRG_1_AC0_OPTO_DIG | ARM_EXP_0_TRG_1_AC1_OPTO_DIG | ARM_EXP_0_TRG_1_AC2_OPTO_DIG | ARM_EXP_0_TRG_1_AC3_OPTO_DIG
) * 9
) +
(
(
ARM_EXP_0_TRG_2_AC01_OPTO_CL | ARM_EXP_0_TRG_2_AC01_TTL_CL | ARM_EXP_0_TRG_2_AC01_LVDS_CL | ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG
) * 10
) +
(
(
ARM_EXP_0_TRG_3_AC01_OPTO_CL | ARM_EXP_0_TRG_3_AC01_TTL_CL | ARM_EXP_0_TRG_3_AC01_LVDS_CL | ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA |
ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
) * 11
)
)
) & 0xf ;
//
define_value
Timer0 = 0
Timer0 software arm
Other timer 1 output
Same timer0 output from other AC
Horizontal synchronisation from horizontal counter
Vertical synchronization from vertical counter
Rotary Encoder Timer 1 ARM Trigger
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
reserved
reserved
reserved
reserved
// --------------------------------------
t0armpol regular
Timer 0 Arming Circuit Polarity
eo_information
0 1 unsigned flag_overflow
//
value = EXP_ARM_NEG ;
//
define_value
Rising edge
Falling edge
//
// --------------------------------------
t0armen regular
Timer 0 Arming Circuit Enable
eo_information
1 1 unsigned flag_overflow
//
value = EXP_ARM_ENABLE ;
//
define_value
Arming circuit Disabled
Arming circuit Enabled
//
// --------------------------------------
t0trgsel regular
Timer 0 Trigger Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_TIMER0_ENABLED * ( ! EXP_MD_PERD ) *
(
EXP_MD_SW +
( DEF_TIMER1_ENABLED * EXP_TRG_TIMER1 * 2 ) +
(
EXP_MD_W_TRG * 3 *
( EXP_0_TRG_TIMER0_AC0 + EXP_0_TRG_TIMER0_AC1 + EXP_0_TRG_TIMER0_AC2 + EXP_0_TRG_TIMER0_AC3 )
) +
( EXP_MD_HSY * 4 ) +
( EXP_MD_VSY * 5 ) +
(
(
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
) * 6
) +
(
(
EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_0_AC1_TTL_CL |
EXP_0_TRG_0_AC1_OPTO_CL | EXP_0_TRG_0_AC1_LVDS_CL |
EXP_0_TRG_0_AC0_TTL_ANA | EXP_0_TRG_0_AC1_TTL_ANA | EXP_0_TRG_0_AC2_TTL_ANA | EXP_0_TRG_0_AC3_TTL_ANA |
EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG | EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG |
EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG | EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC3_LVDS_DIG |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
) * 8
) +
(
(
EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_1_AC1_TTL_CL |
EXP_0_TRG_1_AC1_OPTO_CL | EXP_0_TRG_1_AC1_LVDS_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG
) * 9
) +
(
(
EXP_0_TRG_2_AC01_OPTO_CL | EXP_0_TRG_2_AC01_TTL_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
EXP_0_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_2_AC0_AUX1_TTL_DIG |
EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG
) * 10
) +
(
(
EXP_0_TRG_3_AC01_OPTO_CL | EXP_0_TRG_3_AC01_TTL_CL | EXP_0_TRG_3_AC01_LVDS_CL | EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
EXP_0_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_0_TRG_3_AC0_AUX2_TTL_DIG |
EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG
) * 11
)
)
) & 0xf ;
//
define_value
Timer 0 = 0
Timer 0 software trigger
Other timer 1 output
Same timer output from other AC
Horizontal synchronisation from horizontal counter
Vertical synchronisation from vertical counter
Rotary Encoder Timer 1 Trigger
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
reserved
reserved
reserved
reserved
// --------------------------------------
t0trgpol regular
Timer 0 Trigger Polarity
eo_information
0 1 unsigned flag_overflow
//
value = (
( EXP_TRG_NEG * ( ! DEF_TIMER0_TRIG_INVERTED_POL ) ) |
( EXP_TRG_POS * DEF_TIMER0_TRIG_INVERTED_POL )
) ;
//
define_value
Rising edge
Falling edge
//
// --------------------------------------
t0trgpssel regular
Timer 0 Trigger Pre-scaler Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
EXP_PRESCALE1_4 +
( EXP_PRESCALE1_8 * 2 ) +
( EXP_PRESCALE1_16 * 3 )
) ;
//
define_value
Trigger event every 2 triggers
Trigger event every 4 triggers
Trigger event every 8 triggers
Trigger event every 16 triggers
reserved
reserved
reserved
reserved
//
// --------------------------------------
t0trgpsen regular
Timer 0 Trigger Pre-scaler Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_PRESCALE1_2 | EXP_PRESCALE1_4 | EXP_PRESCALE1_8 | EXP_PRESCALE1_16 ) ;
//
define_value
Pre-scaler Disabled
Pre-scaler Enabled
//
// --------------------------------------
t0clksel regular
Timer 0 Clock Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
EXP_CLK_CLKGEN +
( EXP_CLK_TIMER1 * 2 ) +
( EXP_CLK_HS * 4 ) +
( EXP_CLK_VS * 5 ) +
(
(
EXP_CLK_AUXIN1_AC0_CL | EXP_CLK_AUXIN3_AC1_CL | EXP_CLK_AUXIN1_AC0_ANA | EXP_CLK_AUXIN3_AC1_ANA |
EXP_CLK_AUXIN5_AC2_ANA | EXP_CLK_AUXIN7_AC3_ANA | EXP_CLK_AUXIN2_AC0_DIG | EXP_CLK_AUXIN2_AC1_DIG |
EXP_CLK_AUXIN2_AC2_DIG | EXP_CLK_AUXIN2_AC3_DIG
) * 6
)
) ;
//
define_value
Pixel clock
Clock Generator
Timer 0 output
reserved
HS from horizontal counter
VS from vertical counter
Aux 1 input LVDS format
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
t0clkpol regular
Timer 0 Clock Polarity
eo_information
0 1 unsigned flag_overflow
// Default Rising Edge
value = 0 ;
//
define_value
Clock input Rising edge
Clock input Falling edge
//
// --------------------------------------
t0clkpssel regular
Timer 0 Clock Pre-scaler Selection
eo_information
0 3 unsigned flag_overflow
//
value = ( ( EXP_CLK_DIVF > 0 ) * ( EXP_CLK_DIVF - 1 ) ) ;
//
define_value
1 clock pulse out every 2 clocks input
1 clock pulse out every 4 clocks input
1 clock pulse out every 8 clocks input
1 clock pulse out every 16 clocks input
reserved
reserved
reserved
reserved
//
// --------------------------------------
t0clkpsen regular
Timer 0 Clock Pre-scaler Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_CLK_DIVF > 0 ) ;
//
define_value
Pre-scaler timer clock Disabled
Pre-scaler timer clock Enabled
//
// =============================================
//
DIG_T0CTLH
Timer 0 Control High
eo_information
4
// --------------------------------------
t0clrsel regular
Timer 0 Clear Selection
eo_information
0 3 unsigned flag_overflow
//
value = 1 ;
//
define_value
reserved
Timer 0 software clear
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
t0clrpol regular
Timer 0 Clear Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clear active High
Clear active Low
//
// --------------------------------------
t0clren regular
Timer 0 Clear Enable
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Timer 0 software clear Disabled
Timer 0 software clear Enabled
//
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_T1CNT
Timer 1 Counter
eo_information
1
0 24 unsigned flag_overflow
//
value = ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) & 0x00FFFFFF ;
//
//value = ( EXP_OUT_T0_2 + EXP_OUT_T1_2 + EXP_OUT_T2_2 + EXP_OUT_T3_2 ) & 0x00FFFFFF ;
//
no_define_value
//
// =============================================
//
DIG_T1SCNT
Timer 1 Start Count
eo_information
1
0 24 unsigned flag_overflow
//
value = ( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 + EXP_OUT_T2_2 + EXP_OUT_T3_2 - DEF_TIMER1_TRIGGERS_PIPE_DELAY ) & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T1S0PUL
Timer 1 Start 1st pulse
eo_information
1
0 24 unsigned flag_overflow
//
value = ( ( EXP_OUT_T3_2 + EXP_OUT_T2_2 + EXP_OUT_T1_2 ) & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T1E0PUL
Timer 1 End 1st pulse
eo_information
1
0 24 unsigned flag_overflow
//
value = ( ( EXP_OUT_T3_2 + EXP_OUT_T2_2 ) & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T1S1PUL
Timer 1 Start 2nd pulse
eo_information
1
0 24 unsigned flag_overflow
//
value = ( EXP_OUT_T3_2 & 0x00FFFFFF ) ;
//
no_define_value
//
// =============================================
//
DIG_T1CTLL
Timer 1 Control Low
eo_information
19
// --------------------------------------
t1sts protected
Timer 1 Status
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//Timer 1 Inactive
//Timer 1 Active
//
// --------------------------------------
t1armsts protected
Timer 1 Arming Circuit Status
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//Timer 1 arming circuit Inactive
//Timer 1 arming circuit Active
//
// --------------------------------------
t1out protected
Timer 1 Output
eo_information
0 1 unsigned flag_overflow
//
no_define_value
//Timer 1 is Low
//Timer 1 is High
//
// --------------------------------------
t1outpol regular
Timer 1 Output Polarity
eo_information
0 1 unsigned flag_overflow
//
value = EXP_OUT_NEG_2 ;
//
define_value
Timer 1 output High
Timer 1 output Low
//
// --------------------------------------
t1outen regular
Timer 1 Output Enable
eo_information
0 1 unsigned flag_overflow
//
value = DEF_TIMER1_ENABLED ;
//
define_value
Timer 1 output Disabled
Timer 1 output Enabled
//
// --------------------------------------
t1cnten regular
Timer 1 Counter Enable
eo_information
0 1 unsigned flag_overflow
//
value = DEF_TIMER1_ENABLED ;
//
define_value
Timer 1 counter Disabled
Timer 1 counter Enabled
//
// --------------------------------------
t1onesht regular
Timer 1 One-shot Mode
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_MD_W_TRG_2 * ( ! EXP_MD_PERD_2 ) ) ;
//
define_value
One-shot mode Disabled
One-shot mode Enabled
//
// --------------------------------------
t1cont regular
Timer 1 Continuous
eo_information
0 1 unsigned flag_overflow
//
value = EXP_MD_PERD_2 ;
//
define_value
Continuous mode Disabled
Continuous mode Enabled
//
// --------------------------------------
t1armsel regular
Timer 1 Arming Circuit Selection
eo_information
0 4 unsigned flag_overflow
//
// Select Soft Arm if Used by Grab, if not, set to 0 to mask Trigger Events
//
// Set value to 0 with Hardware TRIG ONLY to bypass Bug in FPGA => Timer as long as Exposure time + Vert. Refresh.
// Helios Softarm = OK Odyssey = Bad!
value = (
EXP_ARM_ENABLE_2 *
(
ARM_EXP_1_SOFTWARE +
( DEF_TIMER0_ENABLED * ARM_EXP_1_TIMER0 * 2 ) +
(
EXP_MD_W_TRG_2 * 3 *
(
ARM_EXP_1_TRG_TIMER1_AC0 + ARM_EXP_1_TRG_TIMER1_AC1 + ARM_EXP_1_TRG_TIMER1_AC2 +
ARM_EXP_1_TRG_TIMER1_AC3
)
) +
( ARM_EXP_1_HS_PSG * 4 ) +
( ARM_EXP_1_VS_PSG * 5 ) +
(
(
ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
) * 6
) +
(
(
ARM_EXP_1_TRG_0_AC0_OPTO_CL | ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC0_LVDS_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL |
ARM_EXP_1_TRG_0_AC1_OPTO_CL | ARM_EXP_1_TRG_0_AC1_LVDS_CL |
ARM_EXP_1_TRG_0_AC0_TTL_ANA | ARM_EXP_1_TRG_0_AC1_TTL_ANA | ARM_EXP_1_TRG_0_AC2_TTL_ANA | ARM_EXP_1_TRG_0_AC3_TTL_ANA |
ARM_EXP_1_TRG_0_AC0_OPTO_DIG | ARM_EXP_1_TRG_0_AC1_OPTO_DIG | ARM_EXP_1_TRG_0_AC2_OPTO_DIG | ARM_EXP_1_TRG_0_AC3_OPTO_DIG |
ARM_EXP_1_TRG_0_AC0_LVDS_DIG | ARM_EXP_1_TRG_0_AC1_LVDS_DIG | ARM_EXP_1_TRG_0_AC2_LVDS_DIG | ARM_EXP_1_TRG_0_AC3_LVDS_DIG |
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG | ARM_EXP_1_TRG_1_AC3_TTL_DIG
) * 8
) +
(
(
ARM_EXP_1_TRG_1_AC0_OPTO_CL | ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL |
ARM_EXP_1_TRG_1_AC1_OPTO_CL | ARM_EXP_1_TRG_1_AC1_LVDS_CL |
ARM_EXP_1_TRG_1_AC0_OPTO_ANA | ARM_EXP_1_TRG_1_AC1_OPTO_ANA | ARM_EXP_1_TRG_1_AC2_OPTO_ANA | ARM_EXP_1_TRG_1_AC3_OPTO_ANA |
ARM_EXP_1_TRG_1_AC0_OPTO_DIG | ARM_EXP_1_TRG_1_AC1_OPTO_DIG | ARM_EXP_1_TRG_1_AC2_OPTO_DIG | ARM_EXP_1_TRG_1_AC3_OPTO_DIG
) * 9
) +
(
(
ARM_EXP_1_TRG_2_AC01_OPTO_CL | ARM_EXP_1_TRG_2_AC01_TTL_CL | ARM_EXP_1_TRG_2_AC01_LVDS_CL | ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA |
ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG |
ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
) * 10
) +
(
(
ARM_EXP_1_TRG_3_AC01_OPTO_CL | ARM_EXP_1_TRG_3_AC01_TTL_CL | ARM_EXP_1_TRG_3_AC01_LVDS_CL | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA |
ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
) * 11
)
)
) & 0xf ;
//
define_value
Timer 1 = 0
Timer 1 software arm
Other timer 0 output
Same timer 1 output from other AC
Horizontal synchronisation from horizontal counter
Vertical synchronization from vertical counter
Rotary Encoder Timer 2 ARM Trigger
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
reserved
reserved
reserved
reserved
// --------------------------------------
t1armpol regular
Timer 1 Arming Circuit Polarity
eo_information
0 1 unsigned flag_overflow
//
value = EXP_ARM_NEG_2 ;
//
define_value
Rising edge
Falling edge
//
// --------------------------------------
t1armen regular
Timer 1 Arming Circuit Enable
eo_information
1 1 unsigned flag_overflow
//
value = EXP_ARM_ENABLE_2 ;
//
define_value
Arming circuit Disabled
Arming circuit Enabled
//
// --------------------------------------
t1trgsel regular
Timer 1 Trigger Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_TIMER1_ENABLED * ( ! EXP_MD_PERD_2 ) *
(
EXP_MD_SW_2 +
( DEF_TIMER0_ENABLED * EXP_TRG_TIMER0_2 * 2 ) +
(
EXP_MD_W_TRG_2 * 3 *
( EXP_1_TRG_TIMER1_AC0 + EXP_1_TRG_TIMER1_AC1 + EXP_1_TRG_TIMER1_AC2 + EXP_1_TRG_TIMER1_AC3 )
) +
( EXP_MD_HSY_2 * 4 ) +
( EXP_MD_VSY_2 * 5 ) +
(
(
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
) * 6
) +
(
(
EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_0_AC1_TTL_CL |
EXP_1_TRG_0_AC1_OPTO_CL | EXP_1_TRG_0_AC1_LVDS_CL |
EXP_1_TRG_0_AC0_TTL_ANA | EXP_1_TRG_0_AC1_TTL_ANA | EXP_1_TRG_0_AC2_TTL_ANA | EXP_1_TRG_0_AC3_TTL_ANA |
EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG | EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG |
EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG | EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC3_LVDS_DIG |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
) * 8
) +
(
(
EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_1_AC1_TTL_CL |
EXP_1_TRG_1_AC1_OPTO_CL | EXP_1_TRG_1_AC1_LVDS_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG
) * 9
) +
(
(
EXP_1_TRG_2_AC01_OPTO_CL | EXP_1_TRG_2_AC01_TTL_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_2_4AC_AUX0_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_TTL_ANA | EXP_1_TRG_2_4AC_AUX4_TTL_ANA | EXP_1_TRG_2_4AC_AUX6_TTL_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_AC0_AUX1_TTL_DIG |
EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
) * 10
) +
(
(
EXP_1_TRG_3_AC01_OPTO_CL | EXP_1_TRG_3_AC01_TTL_CL | EXP_1_TRG_3_AC01_LVDS_CL | EXP_1_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_TTL_ANA | EXP_1_TRG_3_4AC_AUX5_TTL_ANA | EXP_1_TRG_3_4AC_AUX7_TTL_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_1_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_3_AC0_AUX2_TTL_DIG |
EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
) * 11
)
)
) ;
//
define_value
Timer 1 = 0
Timer 1 software trigger
Other timer 0 output
Same timer output from other AC
Horizontal synchronisation from horizontal counter
Vertical synchronisation from vertical counter
Rotary Encoder Timer 2 Trigger
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
reserved
reserved
reserved
reserved
// --------------------------------------
t1trgpol regular
Timer 1 Trigger Polarity
eo_information
0 1 unsigned flag_overflow
//
value = (
( EXP_TRG_NEG_2 * ( ! DEF_TIMER1_TRIG_INVERTED_POL ) ) |
( EXP_TRG_POS_2 * DEF_TIMER1_TRIG_INVERTED_POL )
) ;
//
define_value
Rising edge
Falling edge
//
// --------------------------------------
t1trgpssel regular
Timer 1 Trigger Pre-scaler Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
EXP_PRESCALE2_4 +
( EXP_PRESCALE2_8 * 2 ) +
( EXP_PRESCALE2_16 * 3 )
) ;
//
define_value
Trigger event every 2 triggers
Trigger event every 4 triggers
Trigger event every 8 triggers
Trigger event every 16 triggers
reserved
reserved
reserved
reserved
//
// --------------------------------------
t1trgpsen regular
Timer 1 Trigger Pre-scaler Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_PRESCALE2_2 | EXP_PRESCALE2_4 | EXP_PRESCALE2_8 | EXP_PRESCALE2_16 ) ;
//
define_value
Pre-scaler Disabled
Pre-scaler Enabled
//
// --------------------------------------
t1clksel regular
Timer 1 Clock Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
EXP_CLK_2_CLKGEN +
( EXP_CLK_2_TIMER0 * 2 ) +
( EXP_CLK_2_HS * 4 ) +
( EXP_CLK_2_VS * 5 ) +
( EXP_CLK_2_AUXIN1_LVDS * 6 )
) ;
//
define_value
Pixel clock
Clock Generator
Timer 0 output
reserved
HS from horizontal counter
VS from vertical counter
AUX 1 input LVDS format
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
t1clkpol regular
Timer 1 Clock Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clock input Rising edge
Clock input Falling edge
//
// --------------------------------------
t1clkpssel regular
Timer 1 Clock Pre-scaler Selection
eo_information
0 3 unsigned flag_overflow
//
value = ( ( EXP_CLK_DVED_2 > 0 ) * ( EXP_CLK_DVED_2 - 1 ) ) ;
//value = ( ( EXP_CLK_DIVF_2 > 0 ) * ( EXP_CLK_DIVF_2 - 1 ) ) ;
//
define_value
1 clock pulse out every 2 clocks input
1 clock pulse out every 4 clocks input
1 clock pulse out every 8 clocks input
1 clock pulse out every 16 clocks input
reserved
reserved
reserved
reserved
//
// --------------------------------------
t1clkpsen regular
Timer 1 Clock Pre-scaler Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_CLK_DVED_2 > 0 ) ;
//value = ( EXP_CLK_DIVF_2 > 0 ) ;
//
define_value
Pre-scaler timer clock Disabled
Pre-scaler timer clock Enabled
//
// =============================================
//
DIG_T1CTLH
Timer 1 Control High
eo_information
4
//
// --------------------------------------
t1clrsel regular
Timer 1 Clear Selection
eo_information
0 3 unsigned flag_overflow
//
value = 1 ;
//
define_value
reserved
Timer 1 software clear
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
t1clrpol regular
Timer 1 Clear Polarity
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clear active High
Clear active Low
//
// --------------------------------------
t1clren regular
Timer 1 Clear Enable
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Timer software clear Disabled
Timer software clear Enabled
//
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_QUADCTL
Quadrature Control
eo_information
7
// --------------------------------------
quadtcnt regular
Quadrature Trigger Count
eo_information
0 16 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
quadrstsel regular
Quadrature Reset Selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
//
define_value
No Reset
Automatic Clear when Internal Count = QUADTCNT
Input 2 in TTL Format
Input 1 in Opto-Coupled Format
Automatic Set when Internal Count is Positive and Counter goes Backward
reserved
reserved
reserved
//
// --------------------------------------
quadsetsel regular
Quadrature Set Selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
//
define_value
No Set
Automatic Clear when Internal Count = QUADTCNT
Input 2 in TTL Format
Input 1 in Opto-Coupled Format
Automatic Set when Internal Count is Positive and Counter goes Backward
reserved
reserved
reserved
//
// --------------------------------------
quaddir regular
Quadrature direction
eo_information
0 1 unsigned flag_overflow
value = 0 ;
//
define_value
An Increment of External 2-bit Gray Code Increments Internal Counter
An Increment of External 2-bit Gray Code Decrements Internal Counter
//
// --------------------------------------
quadcptsel regular
Quadrature Capture Selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
//
define_value
Internal Count = QUADTCNT (Interrrupt Condition)
Every Quad Input Transition
Every Positive Quad Input Transition
Every Quad Input Transition where the Count is Positive
Every Positive Quad Input Transition where the Count is Positive
reserved
reserved
reserved
//
// --------------------------------------
quadtssel regular
Quadrature Timer Start Selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
//
define_value
Internal Count = QUADTCNT (Interrrupt Condition)
Every Quad Input Transition
Every Positive Quad Input Transition
Every Quad Input Transition where the Count is Positive
Every Positive Quad Input Transition where the Count is Positive
reserved
reserved
reserved
//
// --------------------------------------
quadlvalsel regular
Quadrature Line Valid Selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
//
define_value
Disabled : All Lines are Valids
Valid Lines when Positive Quad Input Transition
Valid Lines when Count is Positive
Valid Lines when Positive Quad Input Transition when Positive Count
Valid Lines when Internal Count = QUADTCNT (Interrupt Condition)
reserved
reserved
reserved
//
// =============================================
//
DIG_CLKCTL
Clock Control
eo_information
5
// --------------------------------------
acclksel regular
Acquisition Controler Clock Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
(
CAMERA_LINK_AV *
( DEF_DIGITIZER_MASTER * ( ! PCK_CAM_GEN ) )
) |
(
VDC_ANA *
(
( DEF_DIGITIZER_MASTER * ( ! PCK_CAM_GEN ) ) +
( ( ! DEF_DIGITIZER_MASTER ) * ( ! PCK_CAM_GEN ) * 2 ) +
( ( ! DEF_DIGITIZER_MASTER ) * ( PCK_CAM_GEN * PCK_ITTL ) * 3 )
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * ( SYC_CAM_GEN == 0 )
)
) ;
//
define_value
External clock CL/DIG DVI Connector/ANA
Clock generator
PLL clock
Other external clock (Input Auxiliary Connector) Analog / 8ns Delay Dig. mod.
External clock with 12ns Digital module
External clock with 16ns Digital module
External clock with 20ns Digital module
reserved
//
// --------------------------------------
acclkpol regular
Acquisition Controler Clock Input Polarity
eo_information
0 1 unsigned flag_overflow
//
// Positive edge if PLL
value = PCK_INEG ;
//
define_value
Rising edge
Falling edge
//
// --------------------------------------
dtclksel regular
Data Clock Selection
eo_information
0 2 unsigned flag_overflow
//
value = DEF_DIGITIZER_MASTER ;
//
define_value
External clock
Clock generator
reserved
reserved
//
// --------------------------------------
othcnlclksel regular
Other Channel Clock Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
SYC_IN_CH +
( ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) * SYC_SEP * 3 )
)
) ;
//
define_value
Clock from Channel 0
Clock from Channel 1
Clock from Channel 2
Clock from Channel 3
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 22 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_GRBCTL
Grab Control
eo_information
17
// --------------------------------------
intcptsel regular
Internal Capture Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
(
( ! TM_ENABLE ) * 2 *
(
GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) +
( GRB_TRG_HS_PSG * ( ! TM_ENABLE ) * 4 ) +
( ( GRB_TRG_VS_PSG | ( TM_ENABLE * DEF_DIGITIZER_MASTER * GRB_MD_CONT ) ) * 5 ) +
( GRB_MD_SW_TRG * ( ! TM_ENABLE ) ) +
(
(
GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC1_OPTO_CL | GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL |
GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_0_AC1_LVDS_CL |
GRB_TRG_0_AC0_TTL_ANA | GRB_TRG_0_AC1_TTL_ANA | GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC3_TTL_ANA |
GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_0_AC3_OPTO_DIG |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG |
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
) * ( ! TM_ENABLE ) * 8
) +
(
(
GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_1_AC1_OPTO_CL | GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL |
GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL |
GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_1_AC1_OPTO_ANA | GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_1_AC3_OPTO_ANA |
GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG
) * ( ! TM_ENABLE ) * 9
) +
(
(
GRB_TRG_2_AC01_OPTO_CL | GRB_TRG_2_AC01_TTL_CL | GRB_TRG_2_AC01_LVDS_CL | GRB_TRG_2_4AC_AUX0_TTL_ANA |
GRB_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_2_AC0_AUX1_TTL_DIG |
GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG |
GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG
) * ( ! TM_ENABLE ) * 10
) +
(
(
GRB_TRG_3_AC01_OPTO_CL | GRB_TRG_3_AC01_TTL_CL | GRB_TRG_3_AC01_LVDS_CL | GRB_TRG_3_4AC_AUX1_TTL_ANA |
GRB_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
GRB_TRG_3_4AC_AUX3_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA | GRB_TRG_3_AC0_AUX2_TTL_DIG |
GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG |
GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG
) * ( ! TM_ENABLE ) * 11
) +
( GRB_TRG_TIMER0 * 12 ) +
(
CAMERA_LINK_AV * CT_LS * DEF_TIMER0_ENABLED *
(
( GRB_LS_FIXED_LINE * EXP_MD_PERD ) |
( GRB_LS_VARIABLE_LINE * EXP_MD_W_TRG )
) * 12
) +
( GRB_TRG_TIMER1 * 13 ) +
(
CAMERA_LINK_AV * CT_LS * DEF_TIMER1_ENABLED *
(
( GRB_LS_FIXED_LINE * EXP_MD_PERD_2 * ( ! EXP_MD_PERD ) ) |
( GRB_LS_VARIABLE_LINE * EXP_MD_W_TRG_2 * ( ! EXP_MD_W_TRG ) )
) * 13
)
) ;
//
define_value
reserved
Software capture
Rotary Encoder Grab Trigger
reserved
HS from horizontal counter
VS from vertical counter
reserved
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input
Trigger 3 input
Exposure 0 output
Exposure 1 output
Exposure 2 output
Exposure 3 output
// --------------------------------------
cptsel regular
Capture Selection
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
define_value
Internal Capture Selection register
AC1out=AC0 AC0out=AC1 AC3out=AC2 AC2out=AC3
AC2out=AC0 AC2out=AC1 AC0out=AC2 AC0out=AC3
AC3out=AC0 AC3out=AC1 AC1out=AC2 AC1out=AC3
//
// --------------------------------------
cptpol regular
Capture Polarity
eo_information
1 1 unsigned flag_overflow
//
value = (
GRB_TRG_NEG |
(
CAMERA_LINK_AV * CT_LS *
(
( GRB_LS_FIXED_LINE * (
( DEF_TIMER0_ENABLED * EXP_MD_PERD * EXP_OUT_NEG ) |
( DEF_TIMER1_ENABLED * EXP_MD_PERD_2 * ( ! EXP_MD_PERD ) * EXP_OUT_NEG_2 )
)
) |
( GRB_LS_VARIABLE_LINE * (
( DEF_TIMER0_ENABLED * EXP_MD_W_TRG * EXP_OUT_NEG ) |
( DEF_TIMER1_ENABLED * EXP_MD_W_TRG_2 * ( ! EXP_MD_W_TRG ) * EXP_OUT_NEG_2 )
)
)
)
)
) ;
//
define_value
Capture active High
Capture active Low
//
// --------------------------------------
cpten regular
Capture Enable
eo_information
1 1 unsigned flag_overflow
//
value = ( ( ! GRB_MD_CONT ) * ( CT_FS | ( CT_LS * ( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR ) ) ) ) ;
//
//value = (
// ( ! GRB_MD_CONT ) |
// ( CAMERA_LINK_AV * CT_LS *
// ( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR | GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR )
// )
// ) ;
define_value
Capture Disabled
Capture Enabled
//
// --------------------------------------
cptmd regular
Capture Mode
eo_information
0 2 unsigned flag_overflow
//
value = GRB_MD_SW_TRG ;
//
define_value
Capture Edge sensitive
Capture Level sensitive
Capture Level and ends immediately when inactive
reserved
//
// --------------------------------------
gsbsen regular
Grab Synchronous Enable
eo_information
1 1 unsigned flag_overflow
// Always 0
//
value = 0 ;
//
define_value
Continuous Grab is reset
Continuous Grab is set
//
// --------------------------------------
snpsht regular
Snap Shot
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No effect
Grab single pending signal is set
//
// --------------------------------------
snpshtclr regular
Snap Shot Clear
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No effect
Grab single pending is cleared
//
// --------------------------------------
grbadis regular
Grab Asynchronous Disable
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No effect
Grab active signal De-asserted
//
// --------------------------------------
sogsel regular
Start of Grab Selection Event
eo_information
0 4 unsigned flag_overflow
//
value = VDT_INTERL ;
//
define_value
Next Field/Frame
Next 2 Fields starting with ODD Field
Next 2 Fields starting with EVEN Field
Next 2 Fields
Next ODD Field
Next EVEN Field
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
scnmd regular
Scan Mode
eo_information
0 1 unsigned flag_overflow
//
value = VDT_INTERL ;
//
define_value
Progressive
Interlaced
//
// --------------------------------------
cptsoft regular
Capture Software
eo_information
0 1 unsigned flag_overflow
//
value = GRB_MD_SW_TRG ;
//
define_value
Harware Grab Trigger
Software Grab Trigger
//
// --------------------------------------
othchlsynsel regular
Other Channel Sync. Select of AP
eo_information
0 2 unsigned flag_overflow
//
value = (
VDC_ANA *
(
( SYC_IN_CH * ( ! ( ( VDC_RGB_COL | VDC_RGB_PACK ) * SYC_SEP ) ) ) +
( ( VDC_RGB_COL | VDC_RGB_PACK ) * SYC_SEP * 3 )
)
) ;
define_value
Sync. on Channel 0
Sync. on Channel 1
Sync. on Channel 2
Sync. on Channel 3
//
// --------------------------------------
cptarmsel regular
Capture Arm Selection
eo_information
0 2 unsigned flag_overflow
//
//value = (
// VDC_DIG * ( ( CAMERA_LINK_AV == 0 ) | ( CLC_MODE_CH0 == 0 ) ) * CT_LS *
// ( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR )
// ) ;
//
define_value
Internal Hardware Arm
Software Arm SOFTCTL:CPTSOFTARM
reserved
reserved
//
// --------------------------------------
cptarmpol regular
Capture Arm Selection
eo_information
0 1 unsigned flag_overflow
//
define_value
Arm Active High/Rising Edge
Arm Active LOW/Falling Edge
//
// --------------------------------------
cptarmen regular
Capture Arm Enable
eo_information
0 1 unsigned flag_overflow
//
define_value
Capture Arm Desactive
Capture Arm Active
//
// --------------------------------------
reserved protected
eo_information
0 6 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// N.B. Hor or Vert Counter used in case where no Hor or Vert blanking
// Internal used in conjonction with internal Line/frame selection
// ( INTLVALSEL,INTFVALSEL,INTDVALSEL )
//
DIG_VALCTL
Valid Control
eo_information
15
// --------------------------------------
eolsel regular
End of Line Selection
eo_information
0 2 unsigned flag_overflow
//
//
// No Horizontal Blank => counter
//
value = (
(
(
( ( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) ) * CAMERA_LINK_AV
) |
( ! CAMERA_LINK_AV )
) * ( DEF_HEVAL_EQUA_HTOTAL | ( DEF_ADD_HTOTAL_EQUA_HEVAL > 0 ) )
) ;
//
//value = (
// (
// (
// ( ( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) ) * CAMERA_LINK_AV
// ) |
// (
// ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) * CAMERA_LINK_AV *
// TM_ENABLE
// ) |
// ( ! CAMERA_LINK_AV )
// ) * ( DEF_HEVAL_EQUA_HTOTAL | ( DEF_ADD_HTOTAL_EQUA_HEVAL > 0 ) )
// ) ;
//
define_value
Internal line valid signal falling edge
Horizontal counter = Htotal field value
reserved
reserved
//
// --------------------------------------
solsel regular
Start of Line Selection
eo_information
0 2 unsigned flag_overflow
//
value = (
(
(
( ( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) ) * CAMERA_LINK_AV
) |
( ! CAMERA_LINK_AV )
) *
(
( 2 * DEF_HSVAL_EQUA_ZERO * ( ! DEF_DIGITIZER_MASTER ) ) +
( 3 * DEF_HSVAL_EQUA_ZERO * DEF_DIGITIZER_MASTER )
)
) ;
//
define_value
Internal line valid signal rising edge
Horizontal counter load or reset
Horizontal counter load (hldsel)
Horizontal counter reset (htotal)
//
// --------------------------------------
eofsel regular
End of Frame Selection
eo_information
0 2 unsigned flag_overflow
//
// No Vertical Blank => counter
//
value = (
(
(
CAMERA_LINK_AV *
(
( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) |
( CT_FS * TM_ENABLE * ( VDT_CL_USE_CAMERA_VALID == 0 ) ) |
( CT_LS * ( VDT_CL_USE_CAMERA_VALID != 3 ) * ( TM_ENABLE == 0 ) )
)
) |
( ! CAMERA_LINK_AV )
) *
(
DEF_VEVAL_EQUA_VTOTAL |
( CT_LS * ( ! GRB_LS_FRMVAR_LINEFIX ) * ( ! GRB_LS_FRMVAR_LINEVAR ) )
)
) ;
//
//value = (
// (
// (
// CAMERA_LINK_AV *
// (
// ( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) | ( CT_FS * TM_ENABLE ) |
// ( CT_LS * ( VDT_CL_USE_CAMERA_VALID != 3 ) * ( TM_ENABLE == 0 ) )
// )
// ) |
// ( ! CAMERA_LINK_AV )
// ) *
// (
// DEF_VEVAL_EQUA_VTOTAL |
// ( CT_LS * ( ! GRB_LS_FRMVAR_LINEFIX ) * ( ! GRB_LS_FRMVAR_LINEVAR ) )
// )
// ) ;
//
define_value
Internal frame valid signal falling edge
Vertical counter = Vtotal field value
reserved
reserved
//
// --------------------------------------
sofsel regular
Start of Frame Selection
eo_information
0 2 unsigned flag_overflow
//
value = (
(
(
CAMERA_LINK_AV *
(
( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) |
( CT_LS * ( VDT_CL_USE_CAMERA_VALID != 3 ) )
)
) |
( ! CAMERA_LINK_AV )
) *
(
( DEF_VSVAL_EQUA_ZERO * CT_LS * ( GRB_LS_FREE_RUN | GRB_LS_FIXED_LINE | GRB_LS_VARIABLE_LINE ) ) +
( 2 * DEF_VSVAL_EQUA_ZERO *
(
( ! (
( DEF_DIGITIZER_MASTER * ( GRB_MD_CONT | GRB_ACT_NXT_FRM ) ) |
( CT_LS * ( GRB_LS_FREE_RUN | GRB_LS_FIXED_LINE | GRB_LS_VARIABLE_LINE | GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR ) )
)
) |
( DEF_DIGITIZER_MASTER * ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) ) |
( VDC_DIG * CT_LS * ( GRB_LS_FRMFIX_LINEFIX | GRB_LS_FRMFIX_LINEVAR ) )
)
) +
( 2 * VDC_ANA * ( ! DEF_VSVAL_EQUA_ZERO ) * ( ! DEF_DIGITIZER_MASTER ) ) +
( 3 * DEF_VSVAL_EQUA_ZERO * DEF_DIGITIZER_MASTER * CT_FS * ( GRB_MD_CONT | GRB_ACT_NXT_FRM ) )
)
) ;
//
define_value
Internal frame valid signal rising edge
Vertical counter load or reset
Vertical counter load (vldsel)
Rising Edge of VSync
//
// --------------------------------------
intdvalsel regular
Internal Data Valid Selection
eo_information
0 3 unsigned flag_overflow
//
// External Data valid = Camera Link ONLY!
//
// Default : Internal Cause: Most cameras with no data valid
value = (
( VDT_CL_USE_CAMERA_VALID < 2 ) |
( ( VDT_CL_USE_CAMERA_VALID > 2 ) * ( VDT_CL_USE_CAMERA_VALID < 5 ) )
) ;
//
define_value
External Data valid
INTFVAL & INTLVAL registers
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
dvalpol regular
Data Valid Polarity
eo_information
1 1 unsigned flag_overflow
//
// STD Valid Active High
value = 1 ;
//
define_value
Active Low
Active High
//
// --------------------------------------
lvaldpsel regular
Line Valid Double Pulse Selection
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
define_value
External HS (Analog ONLY)
reserved
reserved
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input (Camera Link ONLY)
Trigger 3 input (Camera Link ONLY)
//
// --------------------------------------
lvaldppol regular
Line Valid Double Pulse Polarity
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Falling edge
Rising edge
//
// --------------------------------------
intlvalsel regular
Internal Line Valid Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
(
VDC_ANA |
( VDC_DIG * ( ( CAMERA_LINK_AV * ( ( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) | ( SYC_CAM_GEN == 0 ) ) ) | ( ! CAMERA_LINK_AV ) ) ) |
TM_ENABLE
) +
( CAMERA_LINK_AV * ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) * SYC_CAM_GEN * ( ! TM_ENABLE ) * 3 )
) ;
//
define_value
External line valid signal (Camera Link ONLY)
Horizontal valid form PSG
Double pulse input selected by LVALDPSEL Register
External Line Valid Re-Aligned
reserved
reserved
reserved
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input (Camera Link ONLY)
Trigger 3 input (Camera Link ONLY)
reserved
reserved
reserved
reserved
// --------------------------------------
lvalpol regular
Line Valid Polarity
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Active Low
Active High
//
// --------------------------------------
fvaldpsel regular
Frame Valid Double Pulse Selection
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
define_value
External VS (Analog ONLY)
reserved
reserved
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input (Camera Link ONLY)
Trigger 3 input (Camera Link ONLY)
//
// --------------------------------------
fvaldppol regular
Frame Valid Double Pulse Polarity
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Falling edge
Rising edge
//
// --------------------------------------
intfvalsel regular
Internal Frame Valid Selection
eo_information
0 4 unsigned flag_overflow
//
// External Frame valid = Camera Link ONLY!
//
value = (
(
VDC_ANA |
(
VDC_DIG *
(
(
CAMERA_LINK_AV *
(
( VDT_CL_USE_CAMERA_VALID == 0 ) | ( VDT_CL_USE_CAMERA_VALID == 3 ) |
( CT_LS * ( VDT_CL_USE_CAMERA_VALID != 3 ) ) | ( SYC_CAM_GEN == 0 )
)
) |
( ! CAMERA_LINK_AV )
)
) |
TM_ENABLE
) +
( CAMERA_LINK_AV * CT_FS * ( ! TM_ENABLE ) * SYC_CAM_GEN * ( VDT_CL_USE_CAMERA_VALID != 0 ) * ( VDT_CL_USE_CAMERA_VALID != 3 ) * 3 ) +
(
CAMERA_LINK_AV * CT_LS * ( ! TM_ENABLE ) * ( GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR ) *
(
(
(
GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC1_OPTO_CL | GRB_TRG_0_AC0_TTL_CL |
GRB_TRG_0_AC1_TTL_CL | GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_0_AC1_LVDS_CL
) * 7
) +
(
(
GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_1_AC1_OPTO_CL | GRB_TRG_1_AC0_TTL_CL |
GRB_TRG_1_AC1_TTL_CL | GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL
) * 8
) +
( ( GRB_TRG_2_AC01_OPTO_CL | GRB_TRG_2_AC01_TTL_CL | GRB_TRG_2_AC01_LVDS_CL ) * 9 ) +
( ( GRB_TRG_3_AC01_OPTO_CL | GRB_TRG_3_AC01_TTL_CL | GRB_TRG_3_AC01_LVDS_CL ) * 10 )
)
) +
(
VDC_ANA * CT_LS * ( GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR ) *
(
(
(
GRB_TRG_0_AC0_TTL_ANA | GRB_TRG_0_AC1_TTL_ANA | GRB_TRG_0_AC2_TTL_ANA | GRB_TRG_0_AC3_TTL_ANA
) * 7
) +
(
(
GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_1_AC1_OPTO_ANA | GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_1_AC3_OPTO_ANA
) * 8
) +
(
(
GRB_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA
) * 9
) +
(
(
GRB_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
GRB_TRG_3_4AC_AUX3_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA
) * 10
)
)
) +
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * CT_LS * ( GRB_LS_FRMVAR_LINEFIX | GRB_LS_FRMVAR_LINEVAR ) *
(
(
(
GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG | GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_0_AC3_OPTO_DIG |
GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG | GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG
) * 7
) +
(
(
GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG | GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG |
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
) * 8
) +
(
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG |
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG
) * 9
) +
(
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG |
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG
) * 10
)
)
)
) ;
//
define_value
External frame valid (Camera Link ONLY)
Vertical valid from PSG
Double pulse input selected by FVALDPSEL register
External Frame Valid Re-Aligned
reserved
reserved
reserved
reserved
Trigger 0 input
Trigger 1 input
Trigger 2 input (Camera Link ONLY)
Trigger 3 input (Camera Link ONLY)
reserved
reserved
reserved
reserved
// --------------------------------------
fvalpol regular
Frame Valid Polarity
eo_information
1 1 unsigned flag_overflow
//
value = 1 ;
//
define_value
Active Low
Active High
//
// --------------------------------------
reserved protected
eo_information
0 2 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_FLDCTL
Field Control
eo_information
4
// --------------------------------------
fldsel regular
Field Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
(
VDC_ANA *
(
( SYC_ANA * SYC_MD_CSYN ) +
( DEF_DIGITIZER_MASTER * 3 ) +
( SYC_DIG * ( ! DEF_DIGITIZER_MASTER ) * ( SYC_CAM_GEN > 0 ) * 4 )
)
) +
( CAMERA_LINK_AV * 2 )
) ;
//
define_value
Horizontal reference with vertical reference
Noise gated detected field
External Field Input
Internal Half-line signal with VSync. from PSG
Internal Half-line signal with Vertical reference
reserved
reserved
reserved
//
//value = (
// (
// VDC_ANA *
// (
// ( ( SYC_ANA * SYC_MD_CSYN ) | DEF_DIGITIZER_MASTER ) +
// ( SYC_DIG * ( ! DEF_DIGITIZER_MASTER ) * 4 )
// )
// ) +
// ( CAMERA_LINK_AV * 2 )
// ) ;
//
// --------------------------------------
fldpol regular
Field Polarity
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA | ( CAMERA_LINK_AV * VDT_INTERL ) ) ;
//
define_value
EVEN Field Active Low
EVEN Field Active High
//
// --------------------------------------
flden regular
Field Enable
eo_information
0 1 unsigned flag_overflow
//
value = VDT_INTERL ;
//
define_value
Field output Disabled
Field output Enabled
//
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_SYNCOUT
Synchronization Output
eo_information
5
// --------------------------------------
hsoutsel regular
Horizontal Synchronization Output Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
(
VDC_ANA *
( 2 * ( SYC_MD_CSYN | DEF_DIGITIZER_MASTER ) )
) +
( VDC_DIG * ( SYC_H_OUT | SYC_V_OUT ) * 2 )
) ;
//
define_value
External Line Valid Signal (Camera Link ONLY)
External HS Reference (Analog ONLY)
PSG HSync
reserved
reserved
PSG Horizontal Valid signal
Start of Line signal from PSG
End of Line signal from PSG
//
// --------------------------------------
hsoutpol regular
Horizontal Synchronization Output Polarity
eo_information
1 1 unsigned flag_overflow
//
value = ( SYC_H_OPOS | ( ( ! SYC_H_OPOS ) & ( ! SYC_H_ONEG ) ) ) ;
//
define_value
HS Active Low
HS Active High
//
// --------------------------------------
vsoutsel regular
Vertical Synchronization Output Selection
eo_information
0 3 unsigned flag_overflow
//
value = (
(
VDC_ANA *
( ( SYC_DIG * ( ! DEF_DIGITIZER_MASTER ) ) + ( 2 * ( SYC_MD_CSYN | DEF_DIGITIZER_MASTER ) ) )
) +
( VDC_DIG * ( SYC_H_OUT | SYC_V_OUT ) * 2 )
) ;
//
define_value
External Frame Valid Signal (Camera Link ONLY)
External Vertical Reference (Analog ONLY)
PSG VS
reserved
reserved
PSG Vertical Valid Signal
Start of frame signal from PSG
End of frame signal from PSG
//
// --------------------------------------
vsoutpol regular
Vertical Synchronization Output Polarity
eo_information
1 1 unsigned flag_overflow
//
value = ( SYC_V_OPOS | ( ( ! SYC_V_OPOS ) & ( ! SYC_V_ONEG ) ) ) ;
//
define_value
VS Active Low
VS Active High
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// CL : TRGIN Sel + ENCTL0 TTL IN/OUT En + IOCTL0 OUTSEL + CLCTL LVDS IN/OUT EN
// ANA : TRGIN SEL + IOCTL1 FMT TTL/LVDS
//
DIG_TRGIN
Trigger Input
eo_information
5
// --------------------------------------
trg0sel regular
Trigger 0 Input Selection
eo_information
0 4 unsigned flag_overflow
//
// ADD OPTO TRG when Available in Intellicam
value = (
(
VDC_DIG *
(
GRB_TRG_0_AC0_OPTO_CL | GRB_TRG_0_AC1_OPTO_CL | EXP_0_TRG_0_AC0_OPTO_CL | EXP_0_TRG_0_AC1_OPTO_CL |
ARM_EXP_0_TRG_0_AC0_OPTO_CL | ARM_EXP_0_TRG_0_AC1_OPTO_CL | EXP_1_TRG_0_AC0_OPTO_CL | EXP_1_TRG_0_AC1_OPTO_CL |
ARM_EXP_1_TRG_0_AC0_OPTO_CL | ARM_EXP_1_TRG_0_AC1_OPTO_CL | GRB_TRG_0_AC0_OPTO_DIG | GRB_TRG_0_AC1_OPTO_DIG |
GRB_TRG_0_AC2_OPTO_DIG | GRB_TRG_0_AC3_OPTO_DIG | EXP_0_TRG_0_AC0_OPTO_DIG | EXP_0_TRG_0_AC1_OPTO_DIG |
EXP_0_TRG_0_AC2_OPTO_DIG | EXP_0_TRG_0_AC3_OPTO_DIG | ARM_EXP_0_TRG_0_AC0_OPTO_DIG | ARM_EXP_0_TRG_0_AC1_OPTO_DIG |
ARM_EXP_0_TRG_0_AC2_OPTO_DIG | ARM_EXP_0_TRG_0_AC3_OPTO_DIG | EXP_1_TRG_0_AC0_OPTO_DIG | EXP_1_TRG_0_AC1_OPTO_DIG |
EXP_1_TRG_0_AC2_OPTO_DIG | EXP_1_TRG_0_AC3_OPTO_DIG | ARM_EXP_1_TRG_0_AC0_OPTO_DIG | ARM_EXP_1_TRG_0_AC1_OPTO_DIG |
ARM_EXP_1_TRG_0_AC2_OPTO_DIG | ARM_EXP_1_TRG_0_AC3_OPTO_DIG
)
) +
(
VDC_DIG *
(
GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_0_AC1_LVDS_CL | EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_0_AC1_LVDS_CL |
ARM_EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_0_AC1_LVDS_CL | EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_0_AC1_LVDS_CL |
ARM_EXP_1_TRG_0_AC0_LVDS_CL | ARM_EXP_1_TRG_0_AC1_LVDS_CL | GRB_TRG_0_AC0_LVDS_DIG | GRB_TRG_0_AC1_LVDS_DIG |
GRB_TRG_0_AC2_LVDS_DIG | GRB_TRG_0_AC3_LVDS_DIG | EXP_0_TRG_0_AC0_LVDS_DIG | EXP_0_TRG_0_AC1_LVDS_DIG |
EXP_0_TRG_0_AC2_LVDS_DIG | EXP_0_TRG_0_AC3_LVDS_DIG | ARM_EXP_0_TRG_0_AC0_LVDS_DIG | ARM_EXP_0_TRG_0_AC1_LVDS_DIG |
ARM_EXP_0_TRG_0_AC2_LVDS_DIG | ARM_EXP_0_TRG_0_AC3_LVDS_DIG | EXP_1_TRG_0_AC0_LVDS_DIG | EXP_1_TRG_0_AC1_LVDS_DIG |
EXP_1_TRG_0_AC2_LVDS_DIG | EXP_1_TRG_0_AC3_LVDS_DIG | ARM_EXP_1_TRG_0_AC0_LVDS_DIG | ARM_EXP_1_TRG_0_AC1_LVDS_DIG |
ARM_EXP_1_TRG_0_AC2_LVDS_DIG | ARM_EXP_1_TRG_0_AC3_LVDS_DIG
) * 2
)
) ;
//
define_value
AUX Input 0 = TTL format ( CL & ANA )
AUX Input 0 = Opto-coupled format ( CL & DIG )
AUX Input 0 = LVDS format ( CL & DIG )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
Vertical synchronization from other channel (Internal use)
// --------------------------------------
trg1sel regular
Trigger 1 Input Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
(
GRB_TRG_1_AC0_OPTO_CL | GRB_TRG_1_AC1_OPTO_CL | GRB_TRG_1_AC0_OPTO_ANA | GRB_TRG_1_AC1_OPTO_ANA |
GRB_TRG_1_AC2_OPTO_ANA | GRB_TRG_1_AC3_OPTO_ANA | GRB_TRG_1_AC0_OPTO_DIG | GRB_TRG_1_AC1_OPTO_DIG |
GRB_TRG_1_AC2_OPTO_DIG | GRB_TRG_1_AC3_OPTO_DIG | EXP_0_TRG_1_AC0_OPTO_CL | EXP_0_TRG_1_AC1_OPTO_CL |
EXP_0_TRG_1_AC0_OPTO_ANA | EXP_0_TRG_1_AC1_OPTO_ANA | EXP_0_TRG_1_AC2_OPTO_ANA | EXP_0_TRG_1_AC3_OPTO_ANA |
EXP_0_TRG_1_AC0_OPTO_DIG | EXP_0_TRG_1_AC1_OPTO_DIG | EXP_0_TRG_1_AC2_OPTO_DIG | EXP_0_TRG_1_AC3_OPTO_DIG |
ARM_EXP_0_TRG_1_AC0_OPTO_CL | ARM_EXP_0_TRG_1_AC1_OPTO_CL | ARM_EXP_0_TRG_1_AC0_OPTO_ANA | ARM_EXP_0_TRG_1_AC1_OPTO_ANA |
ARM_EXP_0_TRG_1_AC2_OPTO_ANA | ARM_EXP_0_TRG_1_AC3_OPTO_ANA | ARM_EXP_0_TRG_1_AC0_OPTO_DIG | ARM_EXP_0_TRG_1_AC1_OPTO_DIG |
ARM_EXP_0_TRG_1_AC2_OPTO_DIG | ARM_EXP_0_TRG_1_AC3_OPTO_DIG | EXP_1_TRG_1_AC0_OPTO_CL | EXP_1_TRG_1_AC1_OPTO_CL |
EXP_1_TRG_1_AC0_OPTO_ANA | EXP_1_TRG_1_AC1_OPTO_ANA | EXP_1_TRG_1_AC2_OPTO_ANA | EXP_1_TRG_1_AC3_OPTO_ANA |
EXP_1_TRG_1_AC0_OPTO_DIG | EXP_1_TRG_1_AC1_OPTO_DIG | EXP_1_TRG_1_AC2_OPTO_DIG | EXP_1_TRG_1_AC3_OPTO_DIG |
ARM_EXP_1_TRG_1_AC0_OPTO_CL | ARM_EXP_1_TRG_1_AC1_OPTO_CL | ARM_EXP_1_TRG_1_AC0_OPTO_ANA | ARM_EXP_1_TRG_1_AC1_OPTO_ANA |
ARM_EXP_1_TRG_1_AC2_OPTO_ANA | ARM_EXP_1_TRG_1_AC3_OPTO_ANA | ARM_EXP_1_TRG_1_AC0_OPTO_DIG | ARM_EXP_1_TRG_1_AC1_OPTO_DIG |
ARM_EXP_1_TRG_1_AC2_OPTO_DIG | ARM_EXP_1_TRG_1_AC3_OPTO_DIG
) +
(
(
CAMERA_LINK_AV *
(
GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL | EXP_0_TRG_1_AC1_LVDS_CL |
ARM_EXP_0_TRG_1_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC1_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL | EXP_1_TRG_1_AC1_LVDS_CL |
ARM_EXP_1_TRG_1_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC1_LVDS_CL
)
) * 2
) +
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG |
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG |
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG | ARM_EXP_0_TRG_1_AC3_TTL_DIG |
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG |
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG | ARM_EXP_1_TRG_1_AC3_TTL_DIG
) * 3
)
) ;
//
define_value
AUX Input 1 = TTL format ( CL ONLY )
AUX Input 1 = Opto-coupled format ( ALL )
AUX Input 1 = LVDS format ( CL ONLY )
AUX Input 3 = TTL format ( DIG ONLY )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
trg2sel regular
Trigger 2 Input Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
(
CAMERA_LINK_AV *
(
GRB_TRG_2_AC01_OPTO_CL | EXP_0_TRG_2_AC01_OPTO_CL | ARM_EXP_0_TRG_2_AC01_OPTO_CL | EXP_1_TRG_2_AC01_OPTO_CL |
ARM_EXP_1_TRG_2_AC01_OPTO_CL
)
) +
(
(
(
CAMERA_LINK_AV *
(
GRB_TRG_2_AC01_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | ARM_EXP_0_TRG_2_AC01_LVDS_CL |
EXP_1_TRG_2_AC01_LVDS_CL | ARM_EXP_1_TRG_2_AC01_LVDS_CL
)
) |
(
VDC_ANA *
(
GRB_TRG_2_4AC_AUX0_TTL_ANA | EXP_0_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_TTL_ANA |
EXP_1_TRG_2_4AC_AUX0_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX0_TTL_ANA | GRB_TRG_2_4AC_AUX0_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC0_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC0_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG
)
)
) * 2
) +
(
(
(
VDC_ANA *
(
GRB_TRG_2_4AC_AUX2_TTL_ANA | EXP_0_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_TTL_ANA |
EXP_1_TRG_2_4AC_AUX2_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_TTL_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG
)
)
) * 6
) +
(
(
(
VDC_ANA *
(
GRB_TRG_2_4AC_AUX4_TTL_ANA | EXP_0_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_TTL_ANA |
EXP_1_TRG_2_4AC_AUX4_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX4_TTL_ANA | GRB_TRG_2_4AC_AUX4_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG
)
)
) * 10
) +
(
(
(
VDC_ANA *
(
GRB_TRG_2_4AC_AUX6_TTL_ANA | EXP_0_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_TTL_ANA |
EXP_1_TRG_2_4AC_AUX6_TTL_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_TTL_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_2_AC3_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG
)
)
) * 14
)
) ;
//
define_value
AUX Input 2 = TTL format (CL)
AUX Input 0 = Opto-coupled format (CL)
AUX Input 0(CL,ANA) 1(DIG) = TTL or LVDS ( CL(LVDS ONLY)/DIG & ANA PSG0)
reserved
reserved
reserved
AUX Input 2(ANA) 2(DIG) = TTL or LVDS format (DIG & ANA PSG1 )
reserved
reserved
reserved
AUX Input 4(ANA) 1(DIG) = TTL or LVDS format (DIG & ANA PSG2 )
reserved
reserved
reserved
AUX Input 6(ANA) 2(DIG) = TTL or LVDS format (DIG & ANA PSG3 )
reserved
//
// --------------------------------------
trg3sel regular
Trigger 3 Input Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
(
CAMERA_LINK_AV *
(
GRB_TRG_3_AC01_OPTO_CL | EXP_0_TRG_3_AC01_OPTO_CL | ARM_EXP_0_TRG_3_AC01_OPTO_CL |
EXP_1_TRG_3_AC01_OPTO_CL | ARM_EXP_1_TRG_3_AC01_OPTO_CL
)
) +
(
(
(
CAMERA_LINK_AV *
(
GRB_TRG_3_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL | ARM_EXP_0_TRG_3_AC01_LVDS_CL |
EXP_1_TRG_3_AC01_LVDS_CL | ARM_EXP_1_TRG_3_AC01_LVDS_CL
)
) |
(
VDC_ANA *
(
GRB_TRG_3_4AC_AUX1_TTL_ANA | EXP_0_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_TTL_ANA |
EXP_1_TRG_3_4AC_AUX1_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_TTL_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA |
EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC0_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC0_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG
)
)
) * 2
) +
(
(
(
VDC_ANA *
(
GRB_TRG_3_4AC_AUX3_TTL_ANA | EXP_0_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_TTL_ANA |
EXP_1_TRG_3_4AC_AUX3_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_TTL_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG
)
)
) * 6
) +
(
(
(
VDC_ANA *
(
GRB_TRG_3_4AC_AUX5_TTL_ANA | EXP_0_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_TTL_ANA |
EXP_1_TRG_3_4AC_AUX5_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_TTL_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA |
EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG
)
)
) * 10
) +
(
(
(
VDC_ANA *
(
GRB_TRG_3_4AC_AUX7_TTL_ANA | EXP_0_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_TTL_ANA |
EXP_1_TRG_3_4AC_AUX7_TTL_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_TTL_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
)
) |
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
GRB_TRG_3_AC3_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG
)
)
) * 14
)
) ;
//
define_value
AUX Input 2 = TTL format (CL)
AUX Input 1 = Opto-coupled format (CL)
AUX Input 1(CL,ANA) 2(DIG) = TTL or LVDS (CL (LVDS ONLY)/DIG & ANA PSG0)
reserved
reserved
reserved
AUX Input 1(CL,ANA) 2(DIG) = TTL or LVDS format (DIG & ANA PSG1)
reserved
reserved
reserved
AUX Input 1(CL,ANA) 2(DIG) = TTL or LVDS format (DIG & ANA PSG2)
reserved
reserved
reserved
AUX Input 1(CL,ANA) 2(DIG) = TTL or LVDS format (DIG & ANA PSG3)
reserved
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_EXPOUT
Exposure Output
eo_information
5
// --------------------------------------
exp0sel regular
Exposure 0 Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
EXP_COMBINE_XOR_T1 +
( EXP_COMBINE_XOR_T0AC1 * 10 ) +
( EXP_COMBINE_T1 * 4 )
) ;
//
define_value
Timer 0 Output
Timer 0 Output XORED with Timer 1 Output
Timer 0 Output XORED with Timer 2 Output
Timer 0 Output XORED with Timer 3 Output
Timer 1 Output
Timer 1 Output XORED with Timer 2 Output
Timer 1 Output XORED with Timer 3 Output
Timer 2 Output
Timer 2 Output XORED with Timer 3 Output
Timer 3 Output
Timer 0 Output XORED with Exposure 1 Output of other AC
Timer 0 Output XORED with Exposure 1 Output of other AC
Timer 0 Output XORED with Exposure 1 Output of other AC
reserved
Data Valid signal to FIFO (Internal use)
Field signal to FIFO (Internal use)
// --------------------------------------
exp1sel regular
Exposure 1 Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = (
EXP_COMBINE_2_XOR_T0 +
( EXP_COMBINE_2_XOR_T1AC1 * 10 ) +
( EXP_COMBINE_2_T0 * 4 )
) ;
//
define_value
Timer 1 Output
Timer 1 Output XORED with Timer 0 Output
Timer 1 Output XORED with Timer 2 Output
Timer 1 Output XORED with Timer 3 Output
Timer 0 Output
Timer 0 Output XORED with Timer 2 Output
Timer 0 Output XORED with Timer 3 Output
Timer 3 Output
Timer 3 Output XORED with Timer 2 Output
Timer 2 Output
Timer 1 Output XORED with Exposure 1 Output of other AC
Timer 1 Output XORED with Exposure 1 Output of other AC
Timer 1 Output XORED with Exposure 1 Output of other AC
reserved
Data Valid signal to FIFO (Internal use)
Field signal to FIFO (Internal use)
// --------------------------------------
exp2sel regular
Exposure 2 Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Timer 2 Output
Timer 2 Output XORED with Timer 3 Output
Timer 2 Output XORED with Timer 0 Output
Timer 2 Output XORED with Timer 1 Output
Timer 3 Output
Timer 3 Output XORED with Timer 0 Output
Timer 3 Output XORED with Timer 1 Output
Timer 0 Output
Timer 0 Output XORED with Timer 1 Output
Timer 1 Output
Timer 2 Output XORED with Exposure 2 Output of other AC
Timer 2 Output XORED with Exposure 2 Output of other AC
Timer 2 Output XORED with Exposure 2 Output of other AC
reserved
reserved
reserved
// --------------------------------------
exp3sel regular
Exposure 3 Output Selection
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Timer 3 Output
Timer 3 Output XORED with Timer 2 Output
Timer 3 Output XORED with Timer 0 Output
Timer 3 Output XORED with Timer 1 Output
Timer 2 Output
Timer 2 Output XORED with Timer 0 Output
Timer 2 Output XORED with Timer 1 Output
Timer 1 Output
Timer 1 Output XORED with Timer 0 Output
Timer 0 Output
Timer 3 Output XORED with Exposure 3 Output of other AC
Timer 3 Output XORED with Exposure 3 Output of other AC
Timer 3 Output XORED with Exposure 3 Output of other AC
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// =============================================
//
DIG_USROUT
Users Bits Output for AP0
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_0_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
)
) ;
//
define_value
User 0 Output Setted Low
User 0 Output Setted High
//
// --------------------------------------
usr1out regular
User 1 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_1_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
)
) ;
//
define_value
User 1 Output Setted Low
User 1 Output Setted High
//
// --------------------------------------
usr2out regular
User 2 Output
eo_information
0 1 unsigned flag_overflow
//
value = USR_BIT_2_OTH0 ;
//
define_value
User 2 Output Setted Low
User 2 Output Setted High
//
// --------------------------------------
usr3out regular
User 3 Output
eo_information
0 1 unsigned flag_overflow
//
value = USR_BIT_3_OTH0 ;
//
define_value
User 3 Output Setted Low
User 3 Output Setted High
//
// --------------------------------------
usr4out regular
User 4 Output
eo_information
0 1 unsigned flag_overflow
//
value = USR_BIT_4_OTH0 ;
//
define_value
User 4 Output Setted Low
User 4 Output Setted High
//
// --------------------------------------
usr5out regular
User 5 Output
eo_information
0 1 unsigned flag_overflow
//
value = USR_BIT_5_OTH0 ;
//
define_value
User 5 Output Setted Low
User 5 Output Setted High
//
// --------------------------------------
usr6out regular
User 6 Output
eo_information
0 1 unsigned flag_overflow
//
value = USR_BIT_6_OTH0 ;
//
define_value
User 6 Output Setted Low
User 6 Output Setted High
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
// =============================================
//
DIG_USROUT0
Users Bits Output for AP0
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_0_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC0_PROGRAMMED *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
)
) ;
//
define_value
User 0 Output Setted Low
User 0 Output Setted High
//
// --------------------------------------
usr1out regular
User 1 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_1_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC0_PROGRAMMED *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
)
) ;
//
define_value
User 1 Output Setted Low
User 1 Output Setted High
//
// --------------------------------------
usr2out regular
User 2 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * USR_BIT_2_OTH0 ) ;
//
define_value
User 2 Output Setted Low
User 2 Output Setted High
//
// --------------------------------------
usr3out regular
User 3 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * USR_BIT_3_OTH0 ) ;
//
define_value
User 3 Output Setted Low
User 3 Output Setted High
//
// --------------------------------------
usr4out regular
User 4 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * USR_BIT_4_OTH0 ) ;
//
define_value
User 4 Output Setted Low
User 4 Output Setted High
//
// --------------------------------------
usr5out regular
User 5 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * USR_BIT_5_OTH0 ) ;
//
define_value
User 5 Output Setted Low
User 5 Output Setted High
//
// --------------------------------------
usr6out regular
User 6 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * USR_BIT_6_OTH0 ) ;
//
define_value
User 6 Output Setted Low
User 6 Output Setted High
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_USROUT1
Users Bits Output for AP1
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_0_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC1_PROGRAMMED *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
)
) ;
//
define_value
User 0 Output Setted Low
User 0 Output Setted High
//
// --------------------------------------
usr1out regular
User 1 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_1_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC1_PROGRAMMED *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
)
) ;
//
define_value
User 1 Output Setted Low
User 1 Output Setted High
//
// --------------------------------------
usr2out regular
User 2 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * USR_BIT_2_OTH0 ) ;
//
define_value
User 2 Output Setted Low
User 2 Output Setted High
//
// --------------------------------------
usr3out regular
User 3 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * USR_BIT_3_OTH0 ) ;
//
define_value
User 3 Output Setted Low
User 3 Output Setted High
//
// --------------------------------------
usr4out regular
User 4 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * USR_BIT_4_OTH0 ) ;
//
define_value
User 4 Output Setted Low
User 4 Output Setted High
//
// --------------------------------------
usr5out regular
User 5 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * USR_BIT_5_OTH0 ) ;
//
define_value
User 5 Output Setted Low
User 5 Output Setted High
//
// --------------------------------------
usr6out regular
User 6 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * USR_BIT_6_OTH0 ) ;
//
define_value
User 6 Output Setted Low
User 6 Output Setted High
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_USROUT2
Users Bits Output for AP2
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_0_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC2_PROGRAMMED *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
)
) ;
//
define_value
User 0 Output Setted Low
User 0 Output Setted High
//
// --------------------------------------
usr1out regular
User 1 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_1_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC2_PROGRAMMED *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
)
) ;
//
define_value
User 1 Output Setted Low
User 1 Output Setted High
//
// --------------------------------------
usr2out regular
User 2 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * USR_BIT_2_OTH0 ) ;
//
define_value
User 2 Output Setted Low
User 2 Output Setted High
//
// --------------------------------------
usr3out regular
User 3 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * USR_BIT_3_OTH0 ) ;
//
define_value
User 3 Output Setted Low
User 3 Output Setted High
//
// --------------------------------------
usr4out regular
User 4 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * USR_BIT_4_OTH0 ) ;
//
define_value
User 4 Output Setted Low
User 4 Output Setted High
//
// --------------------------------------
usr5out regular
User 5 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * USR_BIT_5_OTH0 ) ;
//
define_value
User 5 Output Setted Low
User 5 Output Setted High
//
// --------------------------------------
usr6out regular
User 6 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * USR_BIT_6_OTH0 ) ;
//
define_value
User 6 Output Setted Low
User 6 Output Setted High
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_USROUT3
Users Bits Output for AP3
eo_information
8
// --------------------------------------
usr0out regular
User 0 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_0_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC3_PROGRAMMED *
( ( CLB_CC1 == 3 ) | ( CLB_CC2 == 3 ) | ( CLB_CC3 == 3 ) | ( CLB_CC4 == 3 ) )
)
) ;
//
define_value
User 0 Output Setted Low
User 0 Output Setted High
//
// --------------------------------------
usr1out regular
User 1 Output
eo_information
0 1 unsigned flag_overflow
//
value = (
USR_BIT_1_OTH0 |
(
CAMERA_LINK_AV * CLB_CCOUTEN1 * DEF_AC3_PROGRAMMED *
( ( CLB_CC1 == 5 ) | ( CLB_CC2 == 5 ) | ( CLB_CC3 == 5 ) | ( CLB_CC4 == 5 ) )
)
) ;
//
define_value
User 1 Output Setted Low
User 1 Output Setted High
//
// --------------------------------------
usr2out regular
User 2 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * USR_BIT_2_OTH0 ) ;
//
define_value
User 2 Output Setted Low
User 2 Output Setted High
//
// --------------------------------------
usr3out regular
User 3 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * USR_BIT_3_OTH0 ) ;
//
define_value
User 3 Output Setted Low
User 3 Output Setted High
//
// --------------------------------------
usr4out regular
User 4 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * USR_BIT_4_OTH0 ) ;
//
define_value
User 4 Output Setted Low
User 4 Output Setted High
//
// --------------------------------------
usr5out regular
User 5 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * USR_BIT_5_OTH0 ) ;
//
define_value
User 5 Output Setted Low
User 5 Output Setted High
//
// --------------------------------------
usr6out regular
User 6 Output
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * USR_BIT_6_OTH0 ) ;
//
define_value
User 6 Output Setted Low
User 6 Output Setted High
//
// --------------------------------------
reserved protected
eo_information
0 25 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_CLCTL
Camera Link Control ***** Camera Link Module ONLY *****
eo_information
6
// --------------------------------------
lvdsin regular
Lvds Input Enable
eo_information
0 1 unsigned flag_overflow
//
value = (
GRB_TRG_0_AC0_LVDS_CL | GRB_TRG_1_AC0_LVDS_CL | GRB_TRG_0_AC1_LVDS_CL | GRB_TRG_1_AC1_LVDS_CL |
GRB_TRG_2_AC01_LVDS_CL | GRB_TRG_3_AC01_LVDS_CL | EXP_0_TRG_0_AC0_LVDS_CL | EXP_0_TRG_1_AC0_LVDS_CL |
EXP_0_TRG_0_AC1_LVDS_CL | EXP_0_TRG_1_AC1_LVDS_CL | EXP_0_TRG_2_AC01_LVDS_CL | EXP_0_TRG_3_AC01_LVDS_CL |
ARM_EXP_0_TRG_0_AC0_LVDS_CL | ARM_EXP_0_TRG_1_AC0_LVDS_CL | ARM_EXP_0_TRG_0_AC1_LVDS_CL | ARM_EXP_0_TRG_1_AC1_LVDS_CL |
ARM_EXP_0_TRG_2_AC01_LVDS_CL | ARM_EXP_0_TRG_3_AC01_LVDS_CL | EXP_1_TRG_0_AC0_LVDS_CL | EXP_1_TRG_1_AC0_LVDS_CL |
EXP_1_TRG_0_AC1_LVDS_CL | EXP_1_TRG_1_AC1_LVDS_CL | EXP_1_TRG_2_AC01_LVDS_CL | EXP_1_TRG_3_AC01_LVDS_CL |
ARM_EXP_1_TRG_0_AC0_LVDS_CL | ARM_EXP_1_TRG_1_AC0_LVDS_CL | ARM_EXP_1_TRG_0_AC1_LVDS_CL | ARM_EXP_1_TRG_1_AC1_LVDS_CL |
ARM_EXP_1_TRG_2_AC01_LVDS_CL | ARM_EXP_1_TRG_3_AC01_LVDS_CL | GRB_TRG_AC0_LVDS_CL_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_CL_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC0_LVDS_CL_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_CL_ROTARY_ENCODER
) ;
//
define_value
Auxiliairy Inputs LVDS Disable
Auxiliairy Inputs LVDS Enable
// --------------------------------------
lvdsout regular
Lvds Output Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( EXP_OUT_LVDS | EXP_OUT_LVDS_2 ) ;
//
define_value
Auxiliairy Outputs LVDS Disable
Auxiliairy Outputs LVDS Enable
// --------------------------------------
cltrans0 regular
Camera Link Transmetter 0 Enable
eo_information
0 1 unsigned flag_overflow
//
value = CAMERA_LINK_AV ;
//
define_value
Camera Link Transmetter 0 Power Down
Camera Link Transmetter 0 Enable
// --------------------------------------
cltrans1 regular
Camera Link Transmetter 1 Enable
eo_information
0 1 unsigned flag_overflow
//
value = CAMERA_LINK_AV ;
//
define_value
Camera Link Transmetter 1 Power Down
Camera Link Transmetter 1 Enable
// --------------------------------------
cltrans2 regular
Camera Link Transmetter 2 Enable
eo_information
0 1 unsigned flag_overflow
//
value = ( CAMERA_LINK_AV * ( DEF_ODYSSEY_CL_DUAL | DEF_HELIOS_CL_DUAL | DEF_SOLIOS_CL_DUAL ) ) ;
//
define_value
Camera Link Transmetter 2 Power Down
Camera Link Transmetter 2 Enable
// --------------------------------------
reserved protected
eo_information
0 27 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL0L
Input/Output Control CL Low ***** Camera Link Module ONLY *****
eo_information
8
// --------------------------------------
clcc0sel regular
Camera Link Camera Control 0 Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV * CLB_CCOUTEN1 *
// (
// ( CLB_CC1 == 2 ) +
// ( ( ( CLB_CC1 == 3 ) | ( CLB_CC1 == 4 ) ) * 2 ) +
// ( ( ( CLB_CC1 == 5 ) | ( CLB_CC1 == 6 ) ) * 3 ) +
// ( ( CLB_CC1 == 7 ) * 4 ) +
// ( ( CLB_CC1 == 8 ) * 5 ) +
// ( ( CLB_CC1 == 9 ) * 6 )
// )
// ) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc1sel regular
Camera Link Camera Control 1 Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV * CLB_CCOUTEN1 *
// (
// ( CLB_CC2 == 2 ) +
// ( ( ( CLB_CC2 == 3 ) | ( CLB_CC2 == 4 ) ) * 2 ) +
// ( ( ( CLB_CC2 == 5 ) | ( CLB_CC2 == 6 ) ) * 3 ) +
// ( ( CLB_CC2 == 7 ) * 4 ) +
// ( ( CLB_CC2 == 8 ) * 5 ) +
// ( ( CLB_CC2 == 9 ) * 6 )
// )
// ) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc2sel regular
Camera Link Camera Control 2 Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV * CLB_CCOUTEN1 *
// (
// ( CLB_CC3 == 2 ) +
// ( ( ( CLB_CC3 == 3 ) | ( CLB_CC3 == 4 ) ) * 2 ) +
// ( ( ( CLB_CC3 == 5 ) | ( CLB_CC3 == 6 ) ) * 3 ) +
// ( ( CLB_CC3 == 7 ) * 4 ) +
// ( ( CLB_CC3 == 8 ) * 5 ) +
// ( ( CLB_CC3 == 9 ) * 6 )
// )
// ) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc3sel regular
Camera Link Camera Control 3 Output Selection
eo_information
0 4 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV * CLB_CCOUTEN1 *
// (
// ( CLB_CC4 == 2 ) +
// ( ( ( CLB_CC4 == 3 ) | ( CLB_CC4 == 4 ) ) * 2 ) +
// ( ( ( CLB_CC4 == 5 ) | ( CLB_CC4 == 6 ) ) * 3 ) +
// ( ( CLB_CC4 == 7 ) * 4 ) +
// ( ( CLB_CC4 == 8 ) * 5 ) +
// ( ( CLB_CC4 == 9 ) * 6 )
// )
// ) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
io0sel regular
Input/Output 0 Selection in TTL Format << AP0:DB9-1 / AP1:HD44-35 >>
eo_information
0 4 unsigned flag_overflow
// Select always User USR1
value = 0 ;
//
define_value
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
io1sel regular
Input/Output 1 Selection in TTL Format << AP0:HD44-13 / AP1:HD44-1 >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
usr3out from USROUT Reg. to Aux 3 TTL Output
Exposure 0 to Aux 3 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
io2sel regular
Input/Output 2 Selection in TTL Format << AP0:HD44-43 / AP1:HD44-15 >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 ) ;
//
define_value
usr4out from USROUT Reg. to Aux 4 TTL Output ( AP0:HD44-43 / AP1:HD44-15 )
Exposure 1 to Aux 4 TTL Output ( AP0:HD44-43 / AP1:HD44-15 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
out0sel regular
Output 0 Selection in LVDS Format << AP0:HD44(20+4-) / AP1:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
usr5out from USROUT Reg. to Aux 5 LVDS Output
Exposure 0 to Aux 5 LVDS Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// =============================================
//
DIG_IOCTL0H
Input Output Control CL APO High ***** Camera Link Module ONLY *****
eo_information
3
// --------------------------------------
out1sel regular
Output 1 Selection in LVDS Format << AP0:HD44(19+3-) / AP1:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
usr6out from USROUT Reg. to Aux 6 LVDS Output
Exposure 1 to Aux 6 LVDS Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection
eo_information
0 4 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * VDT_INTERL * 3 ) ;
//
define_value
Aux Input 0 in Opto-coupled format
Aux Input 0 in LVDS format
Aux Input/Output 0 in TTL format
Spare input of Camera Link
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTLCL0L
Input/Output Control CL AP0 Low ***** Camera Link Module ONLY *****
eo_information
8
// --------------------------------------
clcc0sel regular
Camera Link Camera Control 0 Output Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC1 == 2 ) +
( ( ( CLB_CC1 == 3 ) | ( CLB_CC1 == 4 ) ) * 2 ) +
( ( ( CLB_CC1 == 5 ) | ( CLB_CC1 == 6 ) ) * 3 ) +
( ( CLB_CC1 == 7 ) * 4 ) +
( ( CLB_CC1 == 8 ) * 5 ) +
( ( CLB_CC1 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc1sel regular
Camera Link Camera Control 1 Output Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC2 == 2 ) +
( ( ( CLB_CC2 == 3 ) | ( CLB_CC2 == 4 ) ) * 2 ) +
( ( ( CLB_CC2 == 5 ) | ( CLB_CC2 == 6 ) ) * 3 ) +
( ( CLB_CC2 == 7 ) * 4 ) +
( ( CLB_CC2 == 8 ) * 5 ) +
( ( CLB_CC2 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc2sel regular
Camera Link Camera Control 2 Output Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC3 == 2 ) +
( ( ( CLB_CC3 == 3 ) | ( CLB_CC3 == 4 ) ) * 2 ) +
( ( ( CLB_CC3 == 5 ) | ( CLB_CC3 == 6 ) ) * 3 ) +
( ( CLB_CC3 == 7 ) * 4 ) +
( ( CLB_CC3 == 8 ) * 5 ) +
( ( CLB_CC3 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc3sel regular
Camera Link Camera Control 3 Output Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC4 == 2 ) +
( ( ( CLB_CC4 == 3 ) | ( CLB_CC4 == 4 ) ) * 2 ) +
( ( ( CLB_CC4 == 5 ) | ( CLB_CC4 == 6 ) ) * 3 ) +
( ( CLB_CC4 == 7 ) * 4 ) +
( ( CLB_CC4 == 8 ) * 5 ) +
( ( CLB_CC4 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
io0sel regular
Input/Output 0 Selection in TTL Format of AP0 << AP0:DB9-1 >>
eo_information
0 4 unsigned flag_overflow
// Select always User USR1
value = 0 ;
//
define_value
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
io1sel regular
Input/Output 1 Selection in TTL Format of AP0 << AP0:HD44-13 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
usr3out from USROUT Reg. to Aux 3 TTL Output
Exposure 0 to Aux 3 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
io2sel regular
Input/Output 2 Selection in TTL Format of AP0 << AP0:HD44-43 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 ) ;
//
define_value
usr4out from USROUT Reg. to Aux 4 TTL Output ( AP0:HD44-43 / AP1:HD44-15 )
Exposure 1 to Aux 4 TTL Output ( AP0:HD44-43 / AP1:HD44-15 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
out0sel regular
Output 0 Selection in LVDS Format of AP0 << AP0:HD44(20+4-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
usr5out from USROUT Reg. to Aux 5 LVDS Output
Exposure 0 to Aux 5 LVDS Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// =============================================
//
DIG_IOCTLCL0H
Input Output Control CL APO High ***** Camera Link Module ONLY *****
eo_information
3
// --------------------------------------
out1sel regular
Output 1 Selection in LVDS Format of AP0 << AP0:HD44(19+3-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
usr6out from USROUT Reg. to Aux 6 LVDS Output
Exposure 1 to Aux 6 LVDS Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * VDT_INTERL * 3 ) ;
//
define_value
Aux Input 0 in Opto-coupled format
Aux Input 0 in LVDS format
Aux Input/Output 0 in TTL format
Spare input of Camera Link
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTLCL1L
Input/Output Control CL AP1 Low ***** Camera Link Module ONLY *****
eo_information
8
// --------------------------------------
clcc0sel regular
Camera Link Camera Control 0 Output Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC1 == 2 ) +
( ( ( CLB_CC1 == 3 ) | ( CLB_CC1 == 4 ) ) * 2 ) +
( ( ( CLB_CC1 == 5 ) | ( CLB_CC1 == 6 ) ) * 3 ) +
( ( CLB_CC1 == 7 ) * 4 ) +
( ( CLB_CC1 == 8 ) * 5 ) +
( ( CLB_CC1 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc1sel regular
Camera Link Camera Control 1 Output Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC2 == 2 ) +
( ( ( CLB_CC2 == 3 ) | ( CLB_CC2 == 4 ) ) * 2 ) +
( ( ( CLB_CC2 == 5 ) | ( CLB_CC2 == 6 ) ) * 3 ) +
( ( CLB_CC2 == 7 ) * 4 ) +
( ( CLB_CC2 == 8 ) * 5 ) +
( ( CLB_CC2 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc2sel regular
Camera Link Camera Control 2 Output Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC3 == 2 ) +
( ( ( CLB_CC3 == 3 ) | ( CLB_CC3 == 4 ) ) * 2 ) +
( ( ( CLB_CC3 == 5 ) | ( CLB_CC3 == 6 ) ) * 3 ) +
( ( CLB_CC3 == 7 ) * 4 ) +
( ( CLB_CC3 == 8 ) * 5 ) +
( ( CLB_CC3 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
clcc3sel regular
Camera Link Camera Control 3 Output Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 *
(
( CLB_CC4 == 2 ) +
( ( ( CLB_CC4 == 3 ) | ( CLB_CC4 == 4 ) ) * 2 ) +
( ( ( CLB_CC4 == 5 ) | ( CLB_CC4 == 6 ) ) * 3 ) +
( ( CLB_CC4 == 7 ) * 4 ) +
( ( CLB_CC4 == 8 ) * 5 ) +
( ( CLB_CC4 == 9 ) * 6 )
)
) ;
//
define_value
Exposure 0 Output
Exposure 1 Output
User 0 Output
User 1 Output
PSG Vsync
PSG Hsync
Pixel Clock
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
io0sel regular
Input/Output 0 Selection in TTL Format of AP1 << AP1:HD44-35 >>
eo_information
0 4 unsigned flag_overflow
// Select always User USR1
value = 0 ;
//
define_value
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
io1sel regular
Input/Output 1 Selection in TTL Format of AP1 << AP1:HD44-1 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
usr3out from USROUT Reg. to Aux 3 TTL Output
Exposure 0 to Aux 3 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
io2sel regular
Input/Output 2 Selection in TTL Format of AP1 << AP1:HD44-15 >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 ) ;
//
define_value
usr4out from USROUT Reg. to Aux 4 TTL Output ( AP0:HD44-43 / AP1:HD44-15 )
Exposure 1 to Aux 4 TTL Output ( AP0:HD44-43 / AP1:HD44-15 )
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
out0sel regular
Output 0 Selection in LVDS Format of AP1 << AP1:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
usr5out from USROUT Reg. to Aux 5 LVDS Output
Exposure 0 to Aux 5 LVDS Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// =============================================
//
DIG_IOCTLCL1H
Input Output Control CL AP1 High ***** Camera Link Module ONLY *****
eo_information
3
// --------------------------------------
out1sel regular
Output 1 Selection in LVDS Format of AP1 << AP1:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
usr6out from USROUT Reg. to Aux 6 LVDS Output
Exposure 1 to Aux 6 LVDS Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * VDT_INTERL * 3 ) ;
//
define_value
Aux Input 0 in Opto-coupled format
Aux Input 0 in LVDS format
Aux Input/Output 0 in TTL format
Spare input of Camera Link
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
DIG_IOCTL1
Input/Output Control Analog AP ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output User2/Exp0 << AP0:DVI0(23) / AP1:DVI0(6) / AP2:DVI1(23) / AP3:DVI1(6) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( ( ! DEF_TIMER0_ENABLED ) | EXP_OUT_LVDS ) ;
//
define_value
Exposure 0 to Aux 2 TTL Output
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out0sel regular
Out0 Sel << AP0:HD44(15+30-) / AP1:HD44(43+42-) / AP2:HD44(40+25-) / AP3:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) +
( SYC_H_OUT * ( EXP_OUT_DEFAULT | ( ! DEF_TIMER0_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr0out from USROUT Reg. to Aux 0 LVDS/TTL Output
Exposure 0 to Aux 0 LVDS/TTL Output
Horizontal sync. to Aux 0 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out1sel regular
Out1 Sel << AP0:HD44(44+29-) / AP1:HD44(11+27-) / AP2:HD44(20+4-) / AP3:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
VDC_ANA *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) +
( SYC_V_OUT * ( EXP_OUT_DEFAULT_2 | ( ! DEF_TIMER1_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr1out from USROUT Reg. to Aux 1 LVDS/TTL Output
Exposure 1 to Aux 1 LVDS/TTL Output
Vertical sync. to Aux 1 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
auxinfmt regular
Auxiliary Input Format
eo_information
0 2 unsigned flag_overflow
//
value = (
VDC_ANA *
(
GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER
)
) ;
//
define_value
Aux Input in TTL Format
Aux Input in LVDS Format
reserved
reserved
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format
eo_information
0 2 unsigned flag_overflow
//
// EXP & HS/VS on HD44
//
value = (
VDC_ANA *
(
EXP_OUT_LVDS | EXP_OUT_LVDS_2 | ( EXP_OUT_DEFAULT * SYC_H_OLVDS ) |
( EXP_OUT_DEFAULT_2 * SYC_V_OLVDS ) |
( ( SYC_H_OLVDS | SYC_V_OLVDS ) * ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) ) )
)
) ;
//
define_value
Aux Output in TTL Format
Aux Output in LVDS Format
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Trigger 0 Input in TTL Format
Aux 0 Input in TTL/LVDS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
DIG_IOCTLAN0
Input/Output Control Analog AP0 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output User2/Exp0 of AP0 << AP0:DVI0(23) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( ( ! DEF_TIMER0_ENABLED ) | EXP_OUT_LVDS ) ) ;
//
define_value
Exposure 0 to Aux 2 TTL Output
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out0sel regular
Out0 Sel of AP0 << AP0:HD44(15+30-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) +
( SYC_H_OUT * ( EXP_OUT_DEFAULT | ( ! DEF_TIMER0_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr0out from USROUT Reg. to Aux 0 LVDS/TTL Output
Exposure 0 to Aux 0 LVDS/TTL Output
Horizontal sync. to Aux 0 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out1sel regular
Out1 Sel of AP0 << AP0:HD44(44+29-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) +
( SYC_V_OUT * ( EXP_OUT_DEFAULT_2 | ( ! DEF_TIMER1_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr1out from USROUT Reg. to Aux 1 LVDS/TTL Output
Exposure 1 to Aux 1 LVDS/TTL Output
Vertical sync. to Aux 1 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
auxinfmt regular
Auxiliary Input Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA *
(
GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
GRB_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC0_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC0_LVDS_ANA_ROTARY_ENCODER
)
) ;
//
// (
// GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
//
define_value
Aux Input in TTL Format
Aux Input in LVDS Format
reserved
reserved
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format of AP0
eo_information
0 2 unsigned flag_overflow
//
// EXP & HS/VS on HD44
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA *
(
EXP_OUT_LVDS | EXP_OUT_LVDS_2 | ( EXP_OUT_DEFAULT * SYC_H_OLVDS ) |
( EXP_OUT_DEFAULT_2 * SYC_V_OLVDS ) |
( ( SYC_H_OLVDS | SYC_V_OLVDS ) * ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) ) )
)
) ;
//
define_value
Aux Output in TTL Format
Aux Output in LVDS Format
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Trigger 0 Input in TTL Format
Aux 0 Input in TTL/LVDS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
DIG_IOCTLAN1
Input/Output Control Analog AP1 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output User2/Exp0 of AP1 << AP1:DVI0(6) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( ( ! DEF_TIMER0_ENABLED ) | EXP_OUT_LVDS ) ) ;
//
define_value
Exposure 0 to Aux 2 TTL Output
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out0sel regular
Out0 Sel of AP1 << AP1:HD44(43+42-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) +
( SYC_H_OUT * ( EXP_OUT_DEFAULT | ( ! DEF_TIMER0_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr0out from USROUT Reg. to Aux 0 LVDS/TTL Output
Exposure 0 to Aux 0 LVDS/TTL Output
Horizontal sync. to Aux 0 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out1sel regular
Out1 Sel of AP1 << AP1:HD44(11+27-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) +
( SYC_V_OUT * ( EXP_OUT_DEFAULT_2 | ( ! DEF_TIMER1_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr1out from USROUT Reg. to Aux 1 LVDS/TTL Output
Exposure 1 to Aux 1 LVDS/TTL Output
Vertical sync. to Aux 1 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
auxinfmt regular
Auxiliary Input Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA *
(
GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA |
GRB_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC1_LVDS_ANA_ROTARY_ENCODER
)
) ;
//
// (
// GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
//
define_value
Aux Input in TTL Format
Aux Input in LVDS Format
reserved
reserved
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format of AP1
eo_information
0 2 unsigned flag_overflow
//
// EXP & HS/VS on HD44
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA *
(
EXP_OUT_LVDS | EXP_OUT_LVDS_2 | ( EXP_OUT_DEFAULT * SYC_H_OLVDS ) |
( EXP_OUT_DEFAULT_2 * SYC_V_OLVDS ) |
( ( SYC_H_OLVDS | SYC_V_OLVDS ) * ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) ) )
)
) ;
//
define_value
Aux Output in TTL Format
Aux Output in LVDS Format
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Trigger 0 Input in TTL Format
Aux 0 Input in TTL/LVDS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
DIG_IOCTLAN2
Input/Output Control Analog AP2 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output User2/Exp0 of AP2 << AP2:DVI1(23) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( ( ! DEF_TIMER0_ENABLED ) | EXP_OUT_LVDS ) ) ;
//
define_value
Exposure 0 to Aux 2 TTL Output
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out0sel regular
Out0 Sel of AP2 << AP2:HD44(40+25-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) +
( SYC_H_OUT * ( EXP_OUT_DEFAULT | ( ! DEF_TIMER0_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr0out from USROUT Reg. to Aux 0 LVDS/TTL Output
Exposure 0 to Aux 0 LVDS/TTL Output
Horizontal sync. to Aux 0 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out1sel regular
Out1 Sel of AP2 << AP2:HD44(20+4-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) +
( SYC_V_OUT * ( EXP_OUT_DEFAULT_2 | ( ! DEF_TIMER1_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr1out from USROUT Reg. to Aux 1 LVDS/TTL Output
Exposure 1 to Aux 1 LVDS/TTL Output
Vertical sync. to Aux 1 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
auxinfmt regular
Auxiliary Input Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA *
(
GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
GRB_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC2_LVDS_ANA_ROTARY_ENCODER
)
) ;
//
// (
// GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
//
define_value
Aux Input in TTL Format
Aux Input in LVDS Format
reserved
reserved
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format of AP2
eo_information
0 2 unsigned flag_overflow
//
// EXP & HS/VS on HD44
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA *
(
EXP_OUT_LVDS | EXP_OUT_LVDS_2 | ( EXP_OUT_DEFAULT * SYC_H_OLVDS ) |
( EXP_OUT_DEFAULT_2 * SYC_V_OLVDS ) |
( ( SYC_H_OLVDS | SYC_V_OLVDS ) * ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) ) )
)
) ;
//
define_value
Aux Output in TTL Format
Aux Output in LVDS Format
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection of AP2
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Trigger 0 Input in TTL Format
Aux 0 Input in TTL/LVDS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// For Analog Grab Module
//
DIG_IOCTLAN3
Input/Output Control Analog AP3 ***** Analog Module ONLY *****
eo_information
7
// --------------------------------------
ttl0sel regular
DVI TTL Output User2/Exp0 of AP3 << AP3:DVI1(6) >>
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( ( ! DEF_TIMER0_ENABLED ) | EXP_OUT_LVDS ) ) ;
//
define_value
Exposure 0 to Aux 2 TTL Output
usr2out from USROUT Reg. to Aux 2 TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out0sel regular
Out0 Sel of AP3 << AP3:HD44(33+18-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER0_ENABLED * ( EXP_OUT_TTL | EXP_OUT_LVDS ) ) +
( SYC_H_OUT * ( EXP_OUT_DEFAULT | ( ! DEF_TIMER0_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr0out from USROUT Reg. to Aux 0 LVDS/TTL Output
Exposure 0 to Aux 0 LVDS/TTL Output
Horizontal sync. to Aux 0 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
out1sel regular
Out1 Sel of AP3 << AP3:HD44(2+17-) >>
eo_information
0 4 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
(
( DEF_TIMER1_ENABLED * ( EXP_OUT_TTL_2 | EXP_OUT_LVDS_2 ) ) +
( SYC_V_OUT * ( EXP_OUT_DEFAULT_2 | ( ! DEF_TIMER1_ENABLED ) ) * 2 )
)
) ;
//
define_value
usr1out from USROUT Reg. to Aux 1 LVDS/TTL Output
Exposure 1 to Aux 1 LVDS/TTL Output
Vertical sync. to Aux 1 LVDS/TTL Output
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
auxinfmt regular
Auxiliary Input Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
(
GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA |
ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA |
GRB_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_ANA_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC3_LVDS_ANA_ROTARY_ENCODER
)
) ;
//
// (
// GRB_TRG_2_4AC_AUX0_LVDS_ANA | GRB_TRG_3_4AC_AUX1_LVDS_ANA | GRB_TRG_2_4AC_AUX2_LVDS_ANA | GRB_TRG_3_4AC_AUX3_LVDS_ANA |
// GRB_TRG_2_4AC_AUX4_LVDS_ANA | GRB_TRG_3_4AC_AUX5_LVDS_ANA | GRB_TRG_2_4AC_AUX6_LVDS_ANA | GRB_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_0_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_0_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_0_TRG_3_4AC_AUX7_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | EXP_1_TRG_3_4AC_AUX7_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX0_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX1_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX2_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX3_LVDS_ANA |
// ARM_EXP_1_TRG_2_4AC_AUX4_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX5_LVDS_ANA | ARM_EXP_1_TRG_2_4AC_AUX6_LVDS_ANA | ARM_EXP_1_TRG_3_4AC_AUX7_LVDS_ANA
// )
//
define_value
Aux Input in TTL Format
Aux Input in LVDS Format
reserved
reserved
// --------------------------------------
auxoutfmt regular
Auxiliary Output Format of AP3
eo_information
0 2 unsigned flag_overflow
//
// EXP & HS/VS on HD44
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
(
EXP_OUT_LVDS | EXP_OUT_LVDS_2 | ( EXP_OUT_DEFAULT * SYC_H_OLVDS ) |
( EXP_OUT_DEFAULT_2 * SYC_V_OLVDS ) |
( ( SYC_H_OLVDS | SYC_V_OLVDS ) * ( ( ! DEF_TIMER0_ENABLED ) * ( ! DEF_TIMER1_ENABLED ) ) )
)
) ;
//
define_value
Aux Output in TTL Format
Aux Output in LVDS Format
reserved
reserved
// --------------------------------------
fldinsel regular
Field Input Selection of AP3
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
define_value
Trigger 0 Input in TTL Format
Aux 0 Input in TTL/LVDS
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL2
Input/Output Control Digital ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * PCK_USE_OUT ) ;
//
define_value
User 0 Output
Clock Output
reserved
reserved
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
User 1 Output
PSG HSYNC
reserved
reserved
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
User 2 Output
PSG VSYNC
reserved
reserved
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
User 3 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
User 4 Output
Exposure 1 Output
reserved
reserved
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
User 6 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
in1fmt regular
Input 1 Format
eo_information
0 2 unsigned flag_overflow
//
value = (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER |
EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Auxiliary input 1 TTL Format
Auxiliary input 1 LVDS Format
reserved
reserved
//
// --------------------------------------
in2fmt regular
Input 2 Format
eo_information
0 2 unsigned flag_overflow
//
value = (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Auxiliary input 2 TTL Format
Auxiliary input 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out1fmt regular
Output 1 Format
eo_information
0 2 unsigned flag_overflow
//
value = ( SYC_H_OUT * SYC_H_OLVDS ) ;
//
define_value
Auxiliary output 1 TTL Format
Auxiliary output 1 LVDS Format
reserved
reserved
//
// --------------------------------------
out2fmt regular
Output 2 Format
eo_information
0 2 unsigned flag_overflow
//
value = ( SYC_V_OUT * SYC_V_OLVDS ) ;
//
define_value
Auxiliary output 2 TTL Format
Auxiliary output 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out3fmt regular
Output 3 Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
Auxiliary output 3 TTL Format
Auxiliary output 3 LVDS Format
reserved
reserved
//
// --------------------------------------
out4fmt regular
Output 4 Format
eo_information
0 2 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
Auxiliary output 4 TTL Format
Auxiliary output 4 LVDS Format
reserved
reserved
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Auxiliary input 3 is in input
Auxiliary output 5 is in output
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTLDI0
Input/Output Control Digital AP0 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * PCK_USE_OUT ) ;
//
define_value
User 0 Output
Clock Output
reserved
reserved
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
User 1 Output
PSG HSYNC
reserved
reserved
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
User 2 Output
PSG VSYNC
reserved
reserved
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
User 3 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
User 4 Output
Exposure 1 Output
reserved
reserved
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
User 6 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
in1fmt regular
Input 1 Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
( ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * ( GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * ( EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * ( ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * ( EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * ( ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER ) )
)
) ;
//
//value = (
// ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
// (
// (
// GRB_TRG_LVDS *
// ( GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS *
// ( EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS *
// ( ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS_2 *
// ( EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS_2 *
// ( ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// )
// )
// ) ;
//
define_value
Auxiliary input 1 TTL Format
Auxiliary input 1 LVDS Format
reserved
reserved
//
// --------------------------------------
in2fmt regular
Input 2 Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG |
GRB_TRG_3_AC3_AUX2_LVDS_DIG | GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Auxiliary input 2 TTL Format
Auxiliary input 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out1fmt regular
Output 1 Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * SYC_H_OUT * SYC_H_OLVDS ) ;
//
define_value
Auxiliary output 1 TTL Format
Auxiliary output 1 LVDS Format
reserved
reserved
//
// --------------------------------------
out2fmt regular
Output 2 Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * SYC_V_OUT * SYC_V_OLVDS ) ;
//
define_value
Auxiliary output 2 TTL Format
Auxiliary output 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out3fmt regular
Output 3 Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
Auxiliary output 3 TTL Format
Auxiliary output 3 LVDS Format
reserved
reserved
//
// --------------------------------------
out4fmt regular
Output 4 Format of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
Auxiliary output 4 TTL Format
Auxiliary output 4 LVDS Format
reserved
reserved
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Auxiliary input 3 is in input
Auxiliary output 5 is in output
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTLDI1
Input/Output Control Digital AP1 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * PCK_USE_OUT ) ;
//
define_value
User 0 Output
Clock Output
reserved
reserved
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
User 1 Output
PSG HSYNC
reserved
reserved
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
User 2 Output
PSG VSYNC
reserved
reserved
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
User 3 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
User 4 Output
Exposure 1 Output
reserved
reserved
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
User 6 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
in1fmt regular
Input 1 Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
( ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * ( GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * ( EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * ( ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * ( EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * ( ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER ) )
)
) ;
//value = (
// ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG ) *
// (
// (
// GRB_TRG_LVDS *
// ( GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS *
// ( EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS *
// ( ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS_2 *
// ( EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS_2 *
// ( ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// )
// )
// ) ;
//
define_value
Auxiliary input 1 TTL Format
Auxiliary input 1 LVDS Format
reserved
reserved
//
// --------------------------------------
in2fmt regular
Input 2 Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG |
GRB_TRG_3_AC3_AUX2_LVDS_DIG | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Auxiliary input 2 TTL Format
Auxiliary input 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out1fmt regular
Output 1 Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * SYC_H_OUT * SYC_H_OLVDS ) ;
//
define_value
Auxiliary output 1 TTL Format
Auxiliary output 1 LVDS Format
reserved
reserved
//
// --------------------------------------
out2fmt regular
Output 2 Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * SYC_V_OUT * SYC_V_OLVDS ) ;
//
define_value
Auxiliary output 2 TTL Format
Auxiliary output 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out3fmt regular
Output 3 Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
Auxiliary output 3 TTL Format
Auxiliary output 3 LVDS Format
reserved
reserved
//
// --------------------------------------
out4fmt regular
Output 4 Format of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
Auxiliary output 4 TTL Format
Auxiliary output 4 LVDS Format
reserved
reserved
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Auxiliary input 3 is in input
Auxiliary output 5 is in output
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTLDI2
Input/Output Control Digital AP2 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * PCK_USE_OUT ) ;
//
define_value
User 0 Output
Clock Output
reserved
reserved
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
User 1 Output
PSG HSYNC
reserved
reserved
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
User 2 Output
PSG VSYNC
reserved
reserved
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
User 3 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
User 4 Output
Exposure 1 Output
reserved
reserved
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
User 6 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
in1fmt regular
Input 1 Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
( ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * ( GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * ( EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * ( ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * ( EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * ( ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER ) )
)
) ;
//value = (
// ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG ) *
// (
// (
// GRB_TRG_LVDS *
// ( GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS *
// ( EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS *
// ( ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS_2 *
// ( EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS_2 *
// ( ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// )
// )
// ) ;
//
define_value
Auxiliary input 1 TTL Format
Auxiliary input 1 LVDS Format
reserved
reserved
//
// --------------------------------------
in2fmt regular
Input 2 Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG |
GRB_TRG_3_AC3_AUX2_LVDS_DIG | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Auxiliary input 2 TTL Format
Auxiliary input 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out1fmt regular
Output 1 Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * SYC_H_OUT * SYC_H_OLVDS ) ;
//
define_value
Auxiliary output 1 TTL Format
Auxiliary output 1 LVDS Format
reserved
reserved
//
// --------------------------------------
out2fmt regular
Output 2 Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * SYC_V_OUT * SYC_V_OLVDS ) ;
//
define_value
Auxiliary output 2 TTL Format
Auxiliary output 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out3fmt regular
Output 3 Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
Auxiliary output 3 TTL Format
Auxiliary output 3 LVDS Format
reserved
reserved
//
// --------------------------------------
out4fmt regular
Output 4 Format of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
Auxiliary output 4 TTL Format
Auxiliary output 4 LVDS Format
reserved
reserved
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Auxiliary input 3 is in input
Auxiliary output 5 is in output
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTLDI3
Input/Output Control Digital AP3 ***** Digital Module ONLY *****
eo_information
14
// --------------------------------------
out0sel regular
Output 0 Selection LVDS Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * PCK_USE_OUT ) ;
//
define_value
User 0 Output
Clock Output
reserved
reserved
//
// --------------------------------------
out1sel regular
Output 1 Selection TTL/LVDS Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
User 1 Output
PSG HSYNC
reserved
reserved
//
// --------------------------------------
out2sel regular
Output 2 Selection TTL/LVDS Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
User 2 Output
PSG VSYNC
reserved
reserved
//
// --------------------------------------
out3sel regular
Output 3 Selection TTL/LVDS Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
User 3 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
out4sel regular
Output 4 Selection TTL/LVDS Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
User 4 Output
Exposure 1 Output
reserved
reserved
//
// --------------------------------------
out6sel regular
Output 6 Selection TTL Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
User 6 Output
Exposure 0 Output
reserved
reserved
//
// --------------------------------------
in1fmt regular
Input 1 Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
( ( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) * ( GRB_TRG_2_AC3_AUX1_LVDS_DIG | GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) * ( EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) * ( ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) * ( EXP_1_TRG_2_AC3_AUX1_LVDS_DIG | EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ) ) |
( ( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) * ( ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER ) )
)
) ;
//value = (
// ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG ) *
// (
// (
// GRB_TRG_LVDS *
// ( GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS *
// ( EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS *
// ( ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_TRG_LVDS_2 *
// ( EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// ) |
// (
// EXP_ARM_LVDS_2 *
// ( ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG )
// )
// )
// ) ;
//
define_value
Auxiliary input 1 TTL Format
Auxiliary input 1 LVDS Format
reserved
reserved
//
// --------------------------------------
in2fmt regular
Input 2 Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG |
GRB_TRG_3_AC3_AUX2_LVDS_DIG | GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Auxiliary input 2 TTL Format
Auxiliary input 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out1fmt regular
Output 1 Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * SYC_H_OUT * SYC_H_OLVDS ) ;
//
define_value
Auxiliary output 1 TTL Format
Auxiliary output 1 LVDS Format
reserved
reserved
//
// --------------------------------------
out2fmt regular
Output 2 Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * SYC_V_OUT * SYC_V_OLVDS ) ;
//
define_value
Auxiliary output 2 TTL Format
Auxiliary output 2 LVDS Format
reserved
reserved
//
// --------------------------------------
out3fmt regular
Output 3 Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED * EXP_OUT_LVDS ) ;
//
define_value
Auxiliary output 3 TTL Format
Auxiliary output 3 LVDS Format
reserved
reserved
//
// --------------------------------------
out4fmt regular
Output 4 Format of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED * EXP_OUT_LVDS_2 ) ;
//
define_value
Auxiliary output 4 TTL Format
Auxiliary output 4 LVDS Format
reserved
reserved
//
// --------------------------------------
i3o5dir regular
Input 3 / Output 5 Direction of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Auxiliary input 3 is in input
Auxiliary output 5 is in output
//
// --------------------------------------
reserved protected
eo_information
0 7 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTL0
Enable Control CL ***** Camera Link Module ONLY *****
eo_information
9
// --------------------------------------
syncout0 regular
<< HS : AP0:HD44(41+26-)/AP1:HD44(6+5-) VS : AP0:HD44(40+25-)/AP1:HD44(36+21-) >>
eo_information
0 1 unsigned flag_overflow
//
//value = ( SYC_H_OUT | SYC_V_OUT ) ;
//
define_value
Synchronization Output Disabled
Synchronization Output Enabled
//
// --------------------------------------
ttl0in regular
TTL User 0 Input Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV *
// (
// ( GRB_TRG_TTL * ( GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL * ( EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL * ( ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL_2 * ( EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL ) )
// )
// ) ;
//
define_value
TTL AUX 0 input Disabled
TTL AUX 0 input Enabled
//
// --------------------------------------
ttl1in regular
TTL User 1 Input Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV *
// (
// ( GRB_TRG_TTL * ( GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL * ( EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL * ( ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_TRG_TTL_2 * ( EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL ) ) |
// ( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL ) )
// )
// ) ;
//
define_value
TTL AUX 1 input Disabled
TTL AUX 1 input Enabled
//
// --------------------------------------
ttl2in regular
TTL User 2 Input Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = (
// CAMERA_LINK_AV *
// (
// ( GRB_TRG_TTL * GRB_TRG_2_AC01_TTL_CL ) |
// ( EXP_TRG_TTL * EXP_0_TRG_2_AC01_TTL_CL ) |
// ( EXP_ARM_TTL * ARM_EXP_0_TRG_2_AC01_TTL_CL ) |
// ( EXP_TRG_TTL_2 * EXP_1_TRG_2_AC01_TTL_CL ) |
// ( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_2_AC01_TTL_CL )
// )
// ) ;
//
define_value
TTL AUX 2 input Disabled
TTL AUX 2 input Enabled
//
// --------------------------------------
ttl0out regular
TTL User 0 Output Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = ( USR_OTTL * USR_BIT_0_OTH0 ) ;
//
define_value
TTL AUX 0 Output Disabled
TTL AUX 0 Output Enabled
//
// --------------------------------------
ttl1out regular
TTL User 1 Output Enable << AP0:HD44-13 / AP1:HD44-1 >>
eo_information
0 1 unsigned flag_overflow
//
//value = (
// ( USR_OTTL * USR_BIT_1_OTH0 ) |
// ( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL )
// ) ;
define_value
TTL AUX 1 Output Disabled
TTL AUX 1 Output Enabled
//
// --------------------------------------
ttl2out regular
TTL User 2 Output Enable << AP0:HD44-43 / AP1:HD44-15 >>
eo_information
0 1 unsigned flag_overflow
//
//value = (
// ( USR_OTTL * USR_BIT_2_OTH0 ) |
// ( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 )
// ) ;
define_value
TTL AUX 2 Output Disabled
TTL AUX 2 Output Enabled
//
// --------------------------------------
cl0cc regular
Camera Link 0 Camera Controls Enable of AP
eo_information
0 1 unsigned flag_overflow
//
//value = ( CAMERA_LINK_AV * CLB_CCOUTEN1 ) ;
//
define_value
Camera Link 0 Camera Controls Disabled
Camera Link 0 Camera Controls Enabled
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLCL0
Enable Control CL AP0 ***** Camera Link Module ONLY *****
eo_information
9
// --------------------------------------
syncout0 regular
Synchronisation Output of AP0 << HS : AP0:HD44(41+26-) VS : AP0:HD44(40+25-) >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
Synchronization Output Disabled
Synchronization Output Enabled
//
// --------------------------------------
ttl0in regular
TTL User 0 Input Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 0 input Disabled
TTL AUX 0 input Enabled
//
// --------------------------------------
ttl1in regular
TTL User 1 Input Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 1 input Disabled
TTL AUX 1 input Enabled
//
// --------------------------------------
ttl2in regular
TTL User 2 Input Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC0_PROGRAMMED | DEF_AC0_CL_TRG2_TTL_ACTIF ) * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * GRB_TRG_2_AC01_TTL_CL ) |
( EXP_TRG_TTL * EXP_0_TRG_2_AC01_TTL_CL ) |
( EXP_ARM_TTL * ARM_EXP_0_TRG_2_AC01_TTL_CL ) |
( EXP_TRG_TTL_2 * EXP_1_TRG_2_AC01_TTL_CL ) |
( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_2_AC01_TTL_CL )
)
) ;
//
define_value
TTL AUX 2 input Disabled
TTL AUX 2 input Enabled
//
// --------------------------------------
ttl0out regular
TTL User 0 Output Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( USR_OTTL * USR_BIT_0_OTH0 ) ) ;
//
define_value
TTL AUX 0 Output Disabled
TTL AUX 0 Output Enabled
//
// --------------------------------------
ttl1out regular
TTL User 1 Output Enable of AP0 << AP0:HD44-13 >>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED *
(
( USR_OTTL * USR_BIT_1_OTH0 ) |
( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL )
)
) ;
define_value
TTL AUX 1 Output Disabled
TTL AUX 1 Output Enabled
//
// --------------------------------------
ttl2out regular
TTL User 2 Output Enable of AP0 << AP0:HD44-43 >>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED *
(
( USR_OTTL * USR_BIT_2_OTH0 ) |
( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 )
)
) ;
define_value
TTL AUX 2 Output Disabled
TTL AUX 2 Output Enabled
//
// --------------------------------------
cl0cc regular
Camera Link 0 Camera Controls Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 ) ;
//
define_value
Camera Link 0 Camera Controls Disabled
Camera Link 0 Camera Controls Enabled
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLCL1
Enable Control CL AP1 ***** Camera Link Module ONLY *****
eo_information
9
// --------------------------------------
syncout0 regular
Synchronisation Output of AP1 << HS : AP1:HD44(6+5-) VS : AP1:HD44(36+21-) >>
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( SYC_H_OUT | SYC_V_OUT ) ) ;
//
define_value
Synchronization Output Disabled
Synchronization Output Enabled
//
// --------------------------------------
ttl0in regular
TTL User 0 Input Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_0_AC0_TTL_CL | GRB_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_0_AC0_TTL_CL | EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_0_AC0_TTL_CL | ARM_EXP_0_TRG_0_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_0_AC0_TTL_CL | EXP_1_TRG_0_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_0_AC0_TTL_CL | ARM_EXP_1_TRG_0_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 0 input Disabled
TTL AUX 0 input Enabled
//
// --------------------------------------
ttl1in regular
TTL User 1 Input Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * ( GRB_TRG_1_AC0_TTL_CL | GRB_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL * ( EXP_0_TRG_1_AC0_TTL_CL | EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL * ( ARM_EXP_0_TRG_1_AC0_TTL_CL | ARM_EXP_0_TRG_1_AC1_TTL_CL ) ) |
( EXP_TRG_TTL_2 * ( EXP_1_TRG_1_AC0_TTL_CL | EXP_1_TRG_1_AC1_TTL_CL ) ) |
( EXP_ARM_TTL_2 * ( ARM_EXP_1_TRG_1_AC0_TTL_CL | ARM_EXP_1_TRG_1_AC1_TTL_CL ) )
)
) ;
//
define_value
TTL AUX 1 input Disabled
TTL AUX 1 input Enabled
//
// --------------------------------------
ttl2in regular
TTL User 2 Input Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC1_PROGRAMMED | DEF_AC1_CL_TRG3_TTL_ACTIF ) * CAMERA_LINK_AV *
(
( GRB_TRG_TTL * GRB_TRG_3_AC01_TTL_CL ) |
( EXP_TRG_TTL * EXP_0_TRG_3_AC01_TTL_CL ) |
( EXP_ARM_TTL * ARM_EXP_0_TRG_3_AC01_TTL_CL ) |
( EXP_TRG_TTL_2 * EXP_1_TRG_3_AC01_TTL_CL ) |
( EXP_ARM_TTL_2 * ARM_EXP_1_TRG_3_AC01_TTL_CL )
)
) ;
//
define_value
TTL AUX 2 input Disabled
TTL AUX 2 input Enabled
//
// --------------------------------------
ttl0out regular
TTL User 0 Output Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( USR_OTTL * USR_BIT_0_OTH0 ) ) ;
//
define_value
TTL AUX 0 Output Disabled
TTL AUX 0 Output Enabled
//
// --------------------------------------
ttl1out regular
TTL User 1 Output Enable of AP1 << AP0:HD44-1 >>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED *
(
( USR_OTTL * USR_BIT_1_OTH0 ) |
( CAMERA_LINK_AV * DEF_TIMER0_ENABLED * EXP_OUT_TTL )
)
) ;
define_value
TTL AUX 1 Output Disabled
TTL AUX 1 Output Enabled
//
// --------------------------------------
ttl2out regular
TTL User 2 Output Enable of AP1 << AP0:HD44-15 >>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED *
(
( USR_OTTL * USR_BIT_2_OTH0 ) |
( CAMERA_LINK_AV * DEF_TIMER1_ENABLED * EXP_OUT_TTL_2 )
)
) ;
define_value
TTL AUX 2 Output Disabled
TTL AUX 2 Output Enabled
//
// --------------------------------------
cl0cc regular
Camera Link 0 Camera Controls Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * CAMERA_LINK_AV * CLB_CCOUTEN1 ) ;
//
define_value
Camera Link 0 Camera Controls Disabled
Camera Link 0 Camera Controls Enabled
//
// --------------------------------------
reserved protected
eo_information
0 24 unsigned flag_overflow
//
no_define_value
//INPUT
//<< HS : AP0:DVI_0(13+12-)/HD44(35+34-)/AP1:DVI_0(10+9-)/HD44(8+24-) /AP2:DVI_1(13+12-)/HD44(7+22-)/AP3:DVI_1(10+9-)/HD44(32+31-) >>
//<< VS : AP0:DVI_0(5+4-) /HD44(12+28-)/AP1:DVI_0(2+1-) /HD44(39+38-)/AP2:DVI_1(5+4-) /HD44(6+5-) /AP3:DVI_1(2+1-) /HD44(1+16-) >>
//
//
//
//
//OUTPUT
//<< HS : AP0:DVI_0(13+12-)/HD44(15+30-)/AP1:DVI_0(10+9-)/HD44(43+42-)/AP2:DVI_1(13+12-)/HD44(40+25-)/AP3:DVI_1(10+9-)/HD44(33+18-) >>
//<< VS : AP0:DVI_0(5+4-) /HD44(44+29-)/AP1:DVI_0(2+1-)/HD44(11+27-)/AP2:DVI_1(5+4-)/HD44(20+4-)/AP3:DVI_1(2+1-)/HD44(2+17-) >>
//
// =============================================
//
DIG_ENCTL1
Enable Control 1 DVI HSync/VSync/PCLK ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
Input/Output Synchronization Enable
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = (
VDC_ANA *
( SYC_H_OUT | SYC_V_OUT )
) ;
//
define_value
Synchronization HS/VS & PCLK Input Enabled
Synchronization HS/VS & PCLK Output Enabled
//
// --------------------------------------
ttllvdsen regular
TTL/LVDS Synchronization Enable
eo_information
0 1 unsigned flag_overflow
//
value = (
VDC_ANA *
( SYC_H_ILVDS | SYC_H_OLVDS | SYC_V_ILVDS | SYC_V_OLVDS )
) ;
//
define_value
TTL Synchronization HS/VS & PCLK Enabled
LVDS Synchronization HS/VS & PCLK Enabled
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
//Enable Control Analog AP0 ***** Analog Module ONLY *****
DIG_ENCTLAN0
Enable Control Analog AP0 DVI HSync/VSync/PCLK ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
//Input/Output Synchronization Enable of AP0
inouten regular
<<IN= HS : AP0:DVI_0(13+12-) / HD44(35+34-) || VS : AP0:DVI_0(5+4-) / HD44(12+28-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA *
( SYC_H_OUT | SYC_V_OUT )
) ;
//
define_value
Synchronization HS/VS & PCLK Input Enabled
Synchronization HS/VS & PCLK Output Enabled
//
// --------------------------------------
//TTL/LVDS Synchronization Enable of AP0
ttllvdsen regular
<<OUT= HS : AP0:DVI_0(13+12-) / HD44(15+30-) || VS : AP0:DVI_0(5+4-) / HD44(44+29-)>>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * VDC_ANA *
( SYC_H_ILVDS | SYC_H_OLVDS | SYC_V_ILVDS | SYC_V_OLVDS )
) ;
//
define_value
TTL Synchronization HS/VS & PCLK Enabled
LVDS Synchronization HS/VS & PCLK Enabled
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLAN1
Enable Control Analog AP1 DVI HSync/VSync/PCLK ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
<<IN= HS : AP1:DVI_0(10+9-) / HD44(8+24-) || VS : AP1:DVI_0(2+1-) / HD44(39+38-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA *
( SYC_H_OUT | SYC_V_OUT )
) ;
//
define_value
Synchronization HS/VS & PCLK Input Enabled
Synchronization HS/VS & PCLK Output Enabled
//
// --------------------------------------
ttllvdsen regular
<<OUT= HS : AP1:DVI_0(10+9-) / HD44(43+42-) || VS : AP1:DVI_0(2+1-) / HD44(11+27-)>>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * VDC_ANA *
( SYC_H_ILVDS | SYC_H_OLVDS | SYC_V_ILVDS | SYC_V_OLVDS )
) ;
//
define_value
TTL Synchronization HS/VS & PCLK Enabled
LVDS Synchronization HS/VS & PCLK Enabled
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLAN2
Enable Control Analog AP2 DVI HSync/VSync/PCLK ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
<<IN= HS : AP1:DVI_1(13+12-) / HD44(7+22-) || VS : AP1:DVI_1(5+4-) / HD44(6+5-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA *
( SYC_H_OUT | SYC_V_OUT )
) ;
//
define_value
Synchronization HS/VS & PCLK Input Enabled
Synchronization HS/VS & PCLK Output Enabled
//
// --------------------------------------
ttllvdsen regular
<<OUT= HS : AP1:DVI_1(13+12-) / HD44(40+25-) || VS : AP1:DVI_1(5+4-) / HD44(20+4-)>>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * VDC_ANA *
( SYC_H_ILVDS | SYC_H_OLVDS | SYC_V_ILVDS | SYC_V_OLVDS )
) ;
//
define_value
TTL Synchronization HS/VS & PCLK Enabled
LVDS Synchronization HS/VS & PCLK Enabled
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLAN3
Enable Control Analog AP3 DVI HSync/VSync/PCLK ***** Analog Module ONLY *****
eo_information
3
// --------------------------------------
inouten regular
<<IN= HS : AP1:DVI_1(10+9-) / HD44(32+31-) || VS : AP1:DVI_1(2+1-) / HD44(1+16-)>>
eo_information
0 1 unsigned flag_overflow
//
// On DVI connector ONLY
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
( SYC_H_OUT | SYC_V_OUT )
) ;
//
define_value
Synchronization HS/VS & PCLK Input Enabled
Synchronization HS/VS & PCLK Output Enabled
//
// --------------------------------------
ttllvdsen regular
<<OUT= HS : AP1:DVI_1(10+9-) / HD44(33+18-) || VS : AP1:DVI_1(2+1-) / HD44(2+17-)>>
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
( SYC_H_ILVDS | SYC_H_OLVDS | SYC_V_ILVDS | SYC_V_OLVDS )
) ;
//
define_value
TTL Synchronization HS/VS & PCLK Enabled
LVDS Synchronization HS/VS & PCLK Enabled
//
// --------------------------------------
reserved protected
eo_information
0 30 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTL2
Enable Control Digital ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Disable
Aux1 TTL/LVDS input Enable
//
// --------------------------------------
in2en regular
Input 2 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER |
ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux2 TTL/LVDS input Disable
Aux2 TTL/LVDS input Enable
//
// --------------------------------------
in3en regular
Input 3 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Disable
Aux3 TTL input Enable
//
// --------------------------------------
out1en regular
Output 1 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Disable
Aux1 TTL/LVDS output Enable
//
// --------------------------------------
out2en regular
Output 2 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Disable
Aux2 TTL/LVDS output Enable
//
// --------------------------------------
out3en regular
Output 3 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Disable
Aux3 TTL/LVDS output Enable
//
// --------------------------------------
out4en regular
Output 4 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Disable
Aux4 TTL/LVDS output Enable
//
// --------------------------------------
out5en regular
Output 5 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Disable
Aux5 TTL/LVDS output Enable
//
// --------------------------------------
out6en regular
Output 6 Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Disable
Aux6 TTL/LVDS output Enable
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLDI0
Enable Control Digital AP0 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Disable
Aux1 TTL/LVDS input Enable
//
// --------------------------------------
in2en regular
Input 2 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG |
GRB_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_AC0_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux2 TTL/LVDS input Disable
Aux2 TTL/LVDS input Enable
//
// --------------------------------------
in3en regular
Input 3 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Disable
Aux3 TTL input Enable
//
// --------------------------------------
out1en regular
Output 1 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Disable
Aux1 TTL/LVDS output Enable
//
// --------------------------------------
out2en regular
Output 2 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Disable
Aux2 TTL/LVDS output Enable
//
// --------------------------------------
out3en regular
Output 3 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Disable
Aux3 TTL/LVDS output Enable
//
// --------------------------------------
out4en regular
Output 4 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Disable
Aux4 TTL/LVDS output Enable
//
// --------------------------------------
out5en regular
Output 5 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Disable
Aux5 TTL/LVDS output Enable
//
// --------------------------------------
out6en regular
Output 6 Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC0_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Disable
Aux6 TTL/LVDS output Enable
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLDI1
Enable Control Digital AP1 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG |
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Disable
Aux1 TTL/LVDS input Enable
//
// --------------------------------------
in2en regular
Input 2 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG |
GRB_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_AC1_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux2 TTL/LVDS input Disable
Aux2 TTL/LVDS input Enable
//
// --------------------------------------
in3en regular
Input 3 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Disable
Aux3 TTL input Enable
//
// --------------------------------------
out1en regular
Output 1 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Disable
Aux1 TTL/LVDS output Enable
//
// --------------------------------------
out2en regular
Output 2 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Disable
Aux2 TTL/LVDS output Enable
//
// --------------------------------------
out3en regular
Output 3 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Disable
Aux3 TTL/LVDS output Enable
//
// --------------------------------------
out4en regular
Output 4 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Disable
Aux4 TTL/LVDS output Enable
//
// --------------------------------------
out5en regular
Output 5 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Disable
Aux5 TTL/LVDS output Enable
//
// --------------------------------------
out6en regular
Output 6 Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC1_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Disable
Aux6 TTL/LVDS output Enable
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLDI2
Enable Control Digital AP2 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG |
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Disable
Aux1 TTL/LVDS input Enable
//
// --------------------------------------
in2en regular
Input 2 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG |
GRB_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_AC2_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux2 TTL/LVDS input Disable
Aux2 TTL/LVDS input Enable
//
// --------------------------------------
in3en regular
Input 3 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Disable
Aux3 TTL input Enable
//
// --------------------------------------
out1en regular
Output 1 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Disable
Aux1 TTL/LVDS output Enable
//
// --------------------------------------
out2en regular
Output 2 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Disable
Aux2 TTL/LVDS output Enable
//
// --------------------------------------
out3en regular
Output 3 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Disable
Aux3 TTL/LVDS output Enable
//
// --------------------------------------
out4en regular
Output 4 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Disable
Aux4 TTL/LVDS output Enable
//
// --------------------------------------
out5en regular
Output 5 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Disable
Aux5 TTL/LVDS output Enable
//
// --------------------------------------
out6en regular
Output 6 Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC2_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Disable
Aux6 TTL/LVDS output Enable
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTLDI3
Enable Control Digital AP3 ***** Digital Module ONLY *****
eo_information
10
// --------------------------------------
in1en regular
Input 1 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_2_AC0_AUX1_LVDS_DIG | GRB_TRG_2_AC1_AUX1_LVDS_DIG | GRB_TRG_2_AC2_AUX1_LVDS_DIG | GRB_TRG_2_AC3_AUX1_LVDS_DIG |
GRB_TRG_2_AC0_AUX1_TTL_DIG | GRB_TRG_2_AC1_AUX1_TTL_DIG | GRB_TRG_2_AC2_AUX1_TTL_DIG | GRB_TRG_2_AC3_AUX1_TTL_DIG |
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_0_TRG_2_AC0_AUX1_TTL_DIG | EXP_0_TRG_2_AC1_AUX1_TTL_DIG | EXP_0_TRG_2_AC2_AUX1_TTL_DIG | EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_0_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_0_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
EXP_1_TRG_2_AC0_AUX1_TTL_DIG | EXP_1_TRG_2_AC1_AUX1_TTL_DIG | EXP_1_TRG_2_AC2_AUX1_TTL_DIG | EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_2_AC0_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_LVDS_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_LVDS_DIG |
ARM_EXP_1_TRG_2_AC0_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC1_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC2_AUX1_TTL_DIG | ARM_EXP_1_TRG_2_AC3_AUX1_TTL_DIG |
ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux1 TTL/LVDS input Disable
Aux1 TTL/LVDS input Enable
//
// --------------------------------------
in2en regular
Input 2 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
( GRB_TRG_TTL | GRB_TRG_LVDS | GRB_TRG_DEFAULT ) *
(
GRB_TRG_3_AC0_AUX2_LVDS_DIG | GRB_TRG_3_AC1_AUX2_LVDS_DIG | GRB_TRG_3_AC2_AUX2_LVDS_DIG | GRB_TRG_3_AC3_AUX2_LVDS_DIG |
GRB_TRG_3_AC0_AUX2_TTL_DIG | GRB_TRG_3_AC1_AUX2_TTL_DIG | GRB_TRG_3_AC2_AUX2_TTL_DIG | GRB_TRG_3_AC3_AUX2_TTL_DIG |
GRB_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL | EXP_TRG_LVDS | EXP_TRG_DEFAULT ) *
(
EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | EXP_0_TRG_3_AC2_AUX2_LVDS_DIG | EXP_0_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_0_TRG_3_AC0_AUX2_TTL_DIG | EXP_0_TRG_3_AC1_AUX2_TTL_DIG | EXP_0_TRG_3_AC2_AUX2_TTL_DIG | EXP_0_TRG_3_AC3_AUX2_TTL_DIG
EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL | EXP_ARM_LVDS | EXP_ARM_DEFAULT ) *
(
ARM_EXP_0_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_0_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_0_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_0_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_0_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_0_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_TRG_TTL_2 | EXP_TRG_LVDS_2 | EXP_TRG_DEFAULT_2 ) *
(
EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | EXP_1_TRG_3_AC2_AUX2_LVDS_DIG | EXP_1_TRG_3_AC3_AUX2_LVDS_DIG |
EXP_1_TRG_3_AC0_AUX2_TTL_DIG | EXP_1_TRG_3_AC1_AUX2_TTL_DIG | EXP_1_TRG_3_AC2_AUX2_TTL_DIG | EXP_1_TRG_3_AC3_AUX2_TTL_DIG
EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
) |
(
( EXP_ARM_TTL_2 | EXP_ARM_LVDS_2 | EXP_ARM_DEFAULT_2 ) *
(
ARM_EXP_1_TRG_3_AC0_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC2_AUX2_LVDS_DIG |
ARM_EXP_1_TRG_3_AC3_AUX2_LVDS_DIG | ARM_EXP_1_TRG_3_AC0_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC1_AUX2_TTL_DIG |
ARM_EXP_1_TRG_3_AC2_AUX2_TTL_DIG | ARM_EXP_1_TRG_3_AC3_AUX2_TTL_DIG | ARM_EXP_1_TRG_AC3_LVDS_DIG_ROTARY_ENCODER
)
)
)
) ;
//
define_value
Aux2 TTL/LVDS input Disable
Aux2 TTL/LVDS input Enable
//
// --------------------------------------
in3en regular
Input 3 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) *
(
(
GRB_TRG_TTL *
(
GRB_TRG_1_AC0_TTL_DIG | GRB_TRG_1_AC1_TTL_DIG | GRB_TRG_1_AC2_TTL_DIG | GRB_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL *
(
EXP_0_TRG_1_AC0_TTL_DIG | EXP_0_TRG_1_AC1_TTL_DIG | EXP_0_TRG_1_AC2_TTL_DIG | EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL *
(
ARM_EXP_0_TRG_1_AC0_TTL_DIG | ARM_EXP_0_TRG_1_AC1_TTL_DIG | ARM_EXP_0_TRG_1_AC2_TTL_DIG |
ARM_EXP_0_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_TRG_TTL_2 *
(
EXP_1_TRG_1_AC0_TTL_DIG | EXP_1_TRG_1_AC1_TTL_DIG | EXP_1_TRG_1_AC2_TTL_DIG | EXP_1_TRG_1_AC3_TTL_DIG
)
) |
(
EXP_ARM_TTL_2 *
(
ARM_EXP_1_TRG_1_AC0_TTL_DIG | ARM_EXP_1_TRG_1_AC1_TTL_DIG | ARM_EXP_1_TRG_1_AC2_TTL_DIG |
ARM_EXP_1_TRG_1_AC3_TTL_DIG
)
)
)
) ;
//
define_value
Aux3 TTL input Disable
Aux3 TTL input Enable
//
// --------------------------------------
out1en regular
Output 1 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_H_OUT ) ;
//
define_value
Aux1 TTL/LVDS output Disable
Aux1 TTL/LVDS output Enable
//
// --------------------------------------
out2en regular
Output 2 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * SYC_V_OUT ) ;
//
define_value
Aux2 TTL/LVDS output Disable
Aux2 TTL/LVDS output Enable
//
// --------------------------------------
out3en regular
Output 3 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER0_ENABLED ) ;
//
define_value
Aux3 TTL/LVDS output Disable
Aux3 TTL/LVDS output Enable
//
// --------------------------------------
out4en regular
Output 4 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * ( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * DEF_TIMER1_ENABLED ) ;
//
define_value
Aux4 TTL/LVDS output Disable
Aux4 TTL/LVDS output Enable
//
// --------------------------------------
out5en regular
Output 5 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Aux5 TTL/LVDS output Disable
Aux5 TTL/LVDS output Enable
//
// --------------------------------------
out6en regular
Output 6 Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_DIG * ( CAMERA_LINK_AV == 0 ) * DEF_TIMER0_ENABLED * EXP_OUT_TTL ) ;
//
define_value
Aux6 TTL/LVDS output Disable
Aux6 TTL/LVDS output Enable
//
// --------------------------------------
reserved protected
eo_information
0 23 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ANACTL
Analog Control For AP (Dynamic Setting) ***** Analog Module ONLY *****
eo_information
15
// --------------------------------------
insel regular
Input Selection of AP
eo_information
1 3 unsigned flag_overflow
//
value = (
VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) * VDC_MIL_CHANNEL * 2
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
)
)
) ;
//
define_value
DC-coupled input A
AC-coupled input A
DC-coupled input B
AC-coupled input B
Filtered input of other channel (AC2, AC4 ONLY)
Non-filtered input of other channel (AC2, AC4 ONLY)
reserved
reserved
//
// --------------------------------------
inen regular
Input Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = VDC_ANA ;
//
define_value
Data input Disabled
Data input Enabled
//
// --------------------------------------
fltsel regular
Filter Selection of AP
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) ) ;
//
define_value
Analog input No-Filter or 40 Mhz (Low Pass 1)
Analog input 50 Mhz or 7.5 Mhz (Low Pass 0)
reserved
reserved
//
// --------------------------------------
atnen regular
Attenuator Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDL_AMPL > 1200 ) ) ;
//
define_value
Attenuator Disabled
Attenuator Enabled
//
// --------------------------------------
clmpol regular
Clamping Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clamping Active Low
Clamping Active High
//
// --------------------------------------
clmen regular
Clamping Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = (
VDC_ANA *
( ! ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC ) )
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
clmve regular
Clamping Vertical End of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vertical Clampnig De-Asserted by NGVECNT register
Vertical Clampnig De-Asserted by Vertical Reset signal
//
// --------------------------------------
clmlvl regular
Clamping Level of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * VDL_NEG_SWG ) ;
//
define_value
Clamping Level = 0 Volt
Clamping Level = 1 Volt
//
// --------------------------------------
ngldsel regular
Noise Gating Load Selection of AP
eo_information
0 4 unsigned flag_overflow
//
value = ( VDC_ANA * SYC_DIG * SYC_H_IN ) ;
//
define_value
Video Decoder Composite Synchronization
External Composite Synchronization from DVI connector
External Composite Synchronization from Auxxiliary connector
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
External Comp. Sync. from DVI connector of Other Channel
// --------------------------------------
ngldpol regular
Noise Gating Load Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * SYC_DIG * SYC_H_IN * SYC_CAM_GEN * ( TM_ENABLE == 0 ) * SYC_H_INEG ) ;
//
//value = ( VDC_ANA * SYC_DIG * SYC_H_IN * SYC_H_IPOS ) ;
//
define_value
Composite Synchronisation Active Low
Composite Synchronisation Active High
// --------------------------------------
ngoutpol regular
Noise Gating Output Signal Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Signal Active Low
Output Signal Active High
//
// --------------------------------------
ngfbkpol regular
Noise Gating Phase-locked Loop Feedback Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Feedback signal Active Low
Feedback signal Active High
//
// --------------------------------------
adofrclr regular
Analog to Digital Converter Out-of-range Error Clear of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
ADOFR field of Status register is cleared
//
// --------------------------------------
adpwrdn regular
Analog to Digital Converter Power Down Mode of AP
eo_information
1 1 unsigned flag_overflow
//
value = VDC_ANA ;
//
define_value
A/D converter is Power Down Mode
A/D converter is Active
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ANCTL
Analog Control For AP (Specific ACQ Path) ***** Analog Module ONLY *****
eo_information
15
// --------------------------------------
insel regular
Input Selection of AP
eo_information
1 3 unsigned flag_overflow
//
value = (
VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) * VDC_MIL_CHANNEL * 2
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
)
)
) ;
//
define_value
DC-coupled input A
AC-coupled input A
DC-coupled input B
AC-coupled input B
Filtered input of other channel (AC2, AC4 ONLY)
Non-filtered input of other channel (AC2, AC4 ONLY)
reserved
reserved
//
// --------------------------------------
inen regular
Input Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = VDC_ANA ;
//
define_value
Data input Disabled
Data input Enabled
//
// --------------------------------------
fltsel regular
Filter Selection of AP
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) ) ;
//
define_value
Analog input No-Filter or 40 Mhz (Low Pass 1)
Analog input 50 Mhz or 7.5 Mhz (Low Pass 0)
reserved
reserved
//
// --------------------------------------
atnen regular
Attenuator Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDL_AMPL > 1200 ) ) ;
//
define_value
Attenuator Disabled
Attenuator Enabled
//
// --------------------------------------
clmpol regular
Clamping Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clamping Active Low
Clamping Active High
//
// --------------------------------------
clmen regular
Clamping Enable of AP
eo_information
0 1 unsigned flag_overflow
//
value = (
VDC_ANA *
( ! ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC ) )
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
clmve regular
Clamping Vertical End of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vertical Clampnig De-Asserted by NGVECNT register
Vertical Clampnig De-Asserted by Vertical Reset signal
//
// --------------------------------------
clmlvl regular
Clamping Level of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * VDL_NEG_SWG ) ;
//
define_value
Clamping Level = 0 Volt
Clamping Level = 1 Volt
//
// --------------------------------------
ngldsel regular
Noise Gating Load Selection of AP
eo_information
0 4 unsigned flag_overflow
//
value = ( VDC_ANA * SYC_DIG * SYC_H_IN ) ;
//
define_value
Video Decoder Composite Synchronization
External Composite Synchronization from DVI connector
External Composite Synchronization from Auxiliary connector
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
External Comp. Sync. from DVI connector of Other Channel
// --------------------------------------
ngldpol regular
Noise Gating Load Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * SYC_DIG * SYC_H_IN * SYC_H_IPOS ) ;
//
define_value
Composite Synchronisation Active Low
Composite Synchronisation Active High
// --------------------------------------
ngoutpol regular
Noise Gating Output Signal Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Signal Active Low
Output Signal Active High
//
// --------------------------------------
ngfbkpol regular
Noise Gating Phase-locked Loop Feedback Polarity of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Feedback signal Active Low
Feedback signal Active High
//
// --------------------------------------
adofrclr regular
Analog to Digital Converter Out-of-range Error Clear of AP
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
ADOFR field of Status register is cleared
//
// --------------------------------------
adpwrdn regular
Analog to Digital Converter Power Down Mode of AP
eo_information
1 1 unsigned flag_overflow
//
value = VDC_ANA ;
//
define_value
A/D converter is Power Down Mode
A/D converter is Active
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ANCTL0
Analog Control for AC0 ***** Analog Module ONLY *****
eo_information
15
// --------------------------------------
insel regular
Input Selection of AP0
eo_information
1 3 unsigned flag_overflow
//
value = (
( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) * VDC_MIL_CHANNEL * 2
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
)
)
) ;
//
define_value
DC-coupled input A
AC-coupled input A
DC-coupled input B
AC-coupled input B
Filtered input of other channel (AC2, AC4 ONLY)
Non-filtered input of other channel (AC2, AC4 ONLY)
reserved
reserved
//
// --------------------------------------
inen regular
Input Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA ) ;
//
define_value
Data input Disabled
Data input Enabled
//
// --------------------------------------
fltsel regular
Filter Selection of AP0
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) ) ;
//
define_value
Analog input No-Filter or 40 Mhz (Low Pass 1)
Analog input 50 Mhz or 7.5 Mhz (Low Pass 0)
reserved
reserved
//
// --------------------------------------
atnen regular
Attenuator Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * ( VDL_AMPL > 1200 ) ) ;
//
define_value
Attenuator Disabled
Attenuator Enabled
//
// --------------------------------------
clmpol regular
Clamping Polarity of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clamping Active Low
Clamping Active High
//
// --------------------------------------
clmen regular
Clamping Enable of AP0
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA *
( ! ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC ) )
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
clmve regular
Clamping Vertical End of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vertical Clampnig De-Asserted by NGVECNT register
Vertical Clampnig De-Asserted by Vertical Reset signal
//
// --------------------------------------
clmlvl regular
Clamping Level of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * VDL_NEG_SWG ) ;
//
define_value
Clamping Level = 0 Volt
Clamping Level = 1 Volt
//
// --------------------------------------
ngldsel regular
Noise Gating Load Selection of AP0
eo_information
0 4 unsigned flag_overflow
//
value = ( ( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * SYC_DIG * SYC_H_IN ) ;
//
define_value
Video Decoder Composite Synchronization
External Composite Synchronization from DVI connector
External Composite Synchronization from Auxiliary connector
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
External Comp. Sync. from DVI connector of Other Channel
// --------------------------------------
ngldpol regular
Noise Gating Load Polarity of AP0
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * SYC_DIG * SYC_H_IN * SYC_H_IPOS ) ;
//
define_value
Composite Synchronisation Active Low
Composite Synchronisation Active High
// --------------------------------------
ngoutpol regular
Noise Gating Output Signal Polarity of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Signal Active Low
Output Signal Active High
//
// --------------------------------------
ngfbkpol regular
Noise Gating Phase-locked Loop Feedback Polarity of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Feedback signal Active Low
Feedback signal Active High
//
// --------------------------------------
adofrclr regular
Analog to Digital Converter Out-of-range Error Clear of AP0
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
ADOFR field of Status register is cleared
//
// --------------------------------------
adpwrdn regular
Analog to Digital Converter Power Down Mode of AP0
eo_information
1 1 unsigned flag_overflow
//
value = ( ( DEF_AC0_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA ) ;
//
define_value
A/D converter is Power Down Mode
A/D converter is Active
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ANCTL1
Analog Control for AC1 ***** Analog Module ONLY *****
eo_information
15
// --------------------------------------
insel regular
Input Selection of AP1
eo_information
1 3 unsigned flag_overflow
//
value = (
( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) * VDC_MIL_CHANNEL * 2
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
)
)
) ;
//
define_value
DC-coupled input A
AC-coupled input A
DC-coupled input B
AC-coupled input B
Filtered input of other channel (AC2, AC4 ONLY)
Non-filtered input of other channel (AC2, AC4 ONLY)
reserved
reserved
//
// --------------------------------------
inen regular
Input Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA ) ;
//
define_value
Data input Disabled
Data input Enabled
//
// --------------------------------------
fltsel regular
Filter Selection of AP1
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) ) ;
//
define_value
Analog input No-Filter or 40 Mhz (Low Pass 1)
Analog input 50 Mhz or 7.5 Mhz (Low Pass 0)
reserved
reserved
//
// --------------------------------------
atnen regular
Attenuator Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * ( VDL_AMPL > 1200 ) ) ;
//
define_value
Attenuator Disabled
Attenuator Enabled
//
// --------------------------------------
clmpol regular
Clamping Polarity of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clamping Active Low
Clamping Active High
//
// --------------------------------------
clmen regular
Clamping Enable of AP1
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA *
( ! ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC ) )
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
clmve regular
Clamping Vertical End of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vertical Clampnig De-Asserted by NGVECNT register
Vertical Clampnig De-Asserted by Vertical Reset signal
//
// --------------------------------------
clmlvl regular
Clamping Level of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * VDL_NEG_SWG ) ;
//
define_value
Clamping Level = 0 Volt
Clamping Level = 1 Volt
//
// --------------------------------------
ngldsel regular
Noise Gating Load Selection of AP1
eo_information
0 4 unsigned flag_overflow
//
value = ( ( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * SYC_DIG * SYC_H_IN ) ;
//
define_value
Video Decoder Composite Synchronization
External Composite Synchronization from DVI connector
External Composite Synchronization from Auxiliary connector
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
External Comp. Sync. from DVI connector of Other Channel
// --------------------------------------
ngldpol regular
Noise Gating Load Polarity of AP1
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * SYC_DIG * SYC_H_IN * SYC_H_IPOS ) ;
//
define_value
Composite Synchronisation Active Low
Composite Synchronisation Active High
// --------------------------------------
ngoutpol regular
Noise Gating Output Signal Polarity of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Signal Active Low
Output Signal Active High
//
// --------------------------------------
ngfbkpol regular
Noise Gating Phase-locked Loop Feedback Polarity of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Feedback signal Active Low
Feedback signal Active High
//
// --------------------------------------
adofrclr regular
Analog to Digital Converter Out-of-range Error Clear of AP1
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
ADOFR field of Status register is cleared
//
// --------------------------------------
adpwrdn regular
Analog to Digital Converter Power Down Mode of AP1
eo_information
1 1 unsigned flag_overflow
//
value = ( ( DEF_AC1_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA ) ;
//
define_value
A/D converter is Power Down Mode
A/D converter is Active
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ANCTL2
Analog Control for AC2 ***** Analog Module ONLY *****
eo_information
15
// --------------------------------------
insel regular
Input Selection of AP2
eo_information
1 3 unsigned flag_overflow
//
value = (
( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) * VDC_MIL_CHANNEL * 2
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
)
)
) ;
//
define_value
DC-coupled input A
AC-coupled input A
DC-coupled input B
AC-coupled input B
Filtered input of other channel (AC2, AC4 ONLY)
Non-filtered input of other channel (AC2, AC4 ONLY)
reserved
reserved
//
// --------------------------------------
inen regular
Input Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA ) ;
//
define_value
Data input Disabled
Data input Enabled
//
// --------------------------------------
fltsel regular
Filter Selection of AP2
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) ) ;
//
define_value
Analog input No-Filter or 40 Mhz (Low Pass 1)
Analog input 50 Mhz or 7.5 Mhz (Low Pass 0)
reserved
reserved
//
// --------------------------------------
atnen regular
Attenuator Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * ( VDL_AMPL > 1200 ) ) ;
//
define_value
Attenuator Disabled
Attenuator Enabled
//
// --------------------------------------
clmpol regular
Clamping Polarity of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clamping Active Low
Clamping Active High
//
// --------------------------------------
clmen regular
Clamping Enable of AP2
eo_information
0 1 unsigned flag_overflow
//
value = (
( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA *
( ! ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC ) )
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
clmve regular
Clamping Vertical End of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vertical Clampnig De-Asserted by NGVECNT register
Vertical Clampnig De-Asserted by Vertical Reset signal
//
// --------------------------------------
clmlvl regular
Clamping Level of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * VDL_NEG_SWG ) ;
//
define_value
Clamping Level = 0 Volt
Clamping Level = 1 Volt
//
// --------------------------------------
ngldsel regular
Noise Gating Load Selection of AP2
eo_information
0 4 unsigned flag_overflow
//
value = ( ( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * SYC_DIG * SYC_H_IN ) ;
//
define_value
Video Decoder Composite Synchronization
External Composite Synchronization from DVI connector
External Composite Synchronization from Auxiliary connector
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
External Comp. Sync. from DVI connector of Other Channel
// --------------------------------------
ngldpol regular
Noise Gating Load Polarity of AP2
eo_information
0 1 unsigned flag_overflow
//
value = ( ( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA * SYC_DIG * SYC_H_IN * SYC_H_IPOS ) ;
//
define_value
Composite Synchronisation Active Low
Composite Synchronisation Active High
// --------------------------------------
ngoutpol regular
Noise Gating Output Signal Polarity of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Signal Active Low
Output Signal Active High
//
// --------------------------------------
ngfbkpol regular
Noise Gating Phase-locked Loop Feedback Polarity of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Feedback signal Active Low
Feedback signal Active High
//
// --------------------------------------
adofrclr regular
Analog to Digital Converter Out-of-range Error Clear of AP2
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
ADOFR field of Status register is cleared
//
// --------------------------------------
adpwrdn regular
Analog to Digital Converter Power Down Mode of AP2
eo_information
1 1 unsigned flag_overflow
//
value = ( ( DEF_AC2_PROGRAMMED | VDC_RGB_COL ) * VDC_ANA ) ;
//
define_value
A/D converter is Power Down Mode
A/D converter is Active
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ANCTL3
Analog Control for AC3 ***** Analog Module ONLY *****
eo_information
15
// --------------------------------------
insel regular
Input Selection of AP3
eo_information
1 3 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
(
(
(
VDC_0_DC_WITH_DC | VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITH_DC | VDC_1_DC_WITHOUT_DC |
VDC_2_DC_WITH_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITH_DC | VDC_3_DC_WITHOUT_DC
) * VDC_MIL_CHANNEL * 2
) +
(
( VDC_0_AC_WITH_DC | VDC_1_AC_WITH_DC | VDC_2_AC_WITH_DC | VDC_3_AC_WITH_DC ) *
(
( ! VDC_MIL_CHANNEL ) +
( VDC_MIL_CHANNEL * 3 )
)
)
)
) ;
//
define_value
DC-coupled input A
AC-coupled input A
DC-coupled input B
AC-coupled input B
Filtered input of other channel (AC2, AC4 ONLY)
Non-filtered input of other channel (AC2, AC4 ONLY)
reserved
reserved
//
// --------------------------------------
inen regular
Input Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA ) ;
//
define_value
Data input Disabled
Data input Enabled
//
// --------------------------------------
fltsel regular
Filter Selection of AP3
eo_information
0 2 unsigned flag_overflow
//
value = ( VDC_ANA * ( VDC_0_FILTER_0 | VDC_1_FILTER_0 | VDC_2_FILTER_0 | VDC_3_FILTER_0 ) ) ;
//
define_value
Analog input No-Filter or 40 Mhz (Low Pass 1)
Analog input 50 Mhz or 7.5 Mhz (Low Pass 0)
reserved
reserved
//
// --------------------------------------
atnen regular
Attenuator Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA * ( VDL_AMPL > 1200 ) ) ;
//
define_value
Attenuator Disabled
Attenuator Enabled
//
// --------------------------------------
clmpol regular
Clamping Polarity of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Clamping Active Low
Clamping Active High
//
// --------------------------------------
clmen regular
Clamping Enable of AP3
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_AC3_PROGRAMMED * VDC_ANA *
( ! ( VDC_0_DC_WITHOUT_DC | VDC_1_DC_WITHOUT_DC | VDC_2_DC_WITHOUT_DC | VDC_3_DC_WITHOUT_DC ) )
) ;
//
define_value
Disabled
Enabled
//
// --------------------------------------
clmve regular
Clamping Vertical End of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Vertical Clampnig De-Asserted by NGVECNT register
Vertical Clampnig De-Asserted by Vertical Reset signal
//
// --------------------------------------
clmlvl regular
Clamping Level of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA * VDL_NEG_SWG ) ;
//
define_value
Clamping Level = 0 Volt
Clamping Level = 1 Volt
//
// --------------------------------------
ngldsel regular
Noise Gating Load Selection of AP3
eo_information
0 4 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA * SYC_DIG * SYC_H_IN ) ;
//
define_value
Video Decoder Composite Synchronization
External Composite Synchronization from DVI connector
External Composite Synchronization from Auxiliary connector
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
External Comp. Sync. from DVI connector of Other Channel
// --------------------------------------
ngldpol regular
Noise Gating Load Polarity of AP3
eo_information
0 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA * SYC_DIG * SYC_H_IN * SYC_H_IPOS ) ;
//
define_value
Composite Synchronisation Active Low
Composite Synchronisation Active High
// --------------------------------------
ngoutpol regular
Noise Gating Output Signal Polarity of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Output Signal Active Low
Output Signal Active High
//
// --------------------------------------
ngfbkpol regular
Noise Gating Phase-locked Loop Feedback Polarity of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
Feedback signal Active Low
Feedback signal Active High
//
// --------------------------------------
adofrclr regular
Analog to Digital Converter Out-of-range Error Clear of AP3
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
ADOFR field of Status register is cleared
//
// --------------------------------------
adpwrdn regular
Analog to Digital Converter Power Down Mode of AP3
eo_information
1 1 unsigned flag_overflow
//
value = ( DEF_AC3_PROGRAMMED * VDC_ANA ) ;
//
define_value
A/D converter is Power Down Mode
A/D converter is Active
//
// --------------------------------------
reserved protected
eo_information
0 12 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_PLLCTL
PLL Control ***** Analog Module ONLY *****
eo_information
10
// --------------------------------------
pllsel regular
Phase-locked Loop Selection
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_ANA * ( PCK_FREQ > 25000000 ) * ( ! PCK_CAM_GEN ) ) ;
//
//value = 0 ;
define_value
Range 0.25 to 25 Mhz
Range 1 to 100 Mhz
// --------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
//
no_define_value
// --------------------------------------
pllrefsel regular
Phase-locked Loop Reference Selection
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
define_value
Noise_Gating_HREF Active
Noise_Gating_SEL Divided by 1 (NG bypass)
Noise_Gating_SEL Divided by 2 (NG bypass)
Noise_Gating_SEL Divided by 4 (NG bypass)
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
pllfbksel regular
Phase-locked Loop Feedback Selection
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
define_value
INT_HALF_LINE
INT_HALF_PIXEL
reserved
reserved
reserved
reserved
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
pllunlckarm regular
PLL Unlock Arming Circuit
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
PLL Unlocked Interrupt Enabled
// --------------------------------------
plllckarm regular
PLL Lock Arming Circuit
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
No Effect
PLL Locked Interrupt Enabled
// --------------------------------------
pllunlckcnt regular
PLL Unlock Counts
eo_information
0 2 unsigned flag_overflow
//
value = VDC_ANA ;
//
define_value
Standard (1 Line)
VCR (32 Lines)
reserved
reserved
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_NGHECNT
Noise Gating Horizontal End Count ***** Analog Module ONLY *****
eo_information
2
// --------------------------------------
nghecnt regular
Noise Gating Horizontal End Count
eo_information
0 16 unsigned flag_overflow
//
// New value compatible with old values STD DCFs & TM9701
// Added new setting for VGA. Old manner got problem in noise gating.
// Same compute like Genesis adapted with Odyssey SYS CLK Noise Gating 25Mhz.
//
value = (
VDC_ANA * ( TM_ENABLE == 0 ) *
(
(
( ( ( 25000000 / VDT_HSYNC_FREQ ) - 26 + 0.5 ) <= 0xffff ) *
( ( 25000000 / VDT_HSYNC_FREQ ) - 26 + 0.5 )
) +
(
( ( ( 25000000 / VDT_HSYNC_FREQ ) - 26 + 0.5 ) > 0xffff ) * 0xffff
)
)
) ;
//
// Ref Clk = 25.0000 Mhz from HS 388 Hz - 65 Khz
// Time (Ref) = 0.983323 * Time HTotal
//value = (
// (
// (
// ( VDT_HTOTAL * 0.983323 * 25000000 ) / PCK_FREQ
// ) + 0.5
// ) & 0xFFFF
// ) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_NGVECNT
Noise Gating Vertical End Count ***** Analog Module ONLY *****
eo_information
2
// --------------------------------------
ngvecnt regular
Noise Gating Vertical End Count
eo_information
0 16 unsigned flag_overflow
//
//Sampling ~= 10.5 uS NTSC Htotal = 63.56 uS / 780 Cnts
//
value = (
VDC_ANA *
(
(
(
( VDT_HTOTAL * 0.165198 * 25000000 ) / PCK_FREQ
) + 0.5
) & 0xFFFF
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_NGFECNT
Noise Gating Field End Count ***** Analog Module ONLY *****
eo_information
2
// --------------------------------------
ngfecnt regular
Noise Gating Field End Count
eo_information
0 16 unsigned flag_overflow
//
// REF_CK = 25 Mhz => Time 1 Line / 2
//
value = (
VDC_ANA *
(
(
(
( VDT_HTOTAL * 25000000 ) / ( 2 * PCK_FREQ )
) + 0.5
) & 0xFFFF
)
) ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
//
// =============================================
//
// *********************************************
// FPGA Chip VIDEO(END) ACQ. CTRL
// *********************************************
//
// =============================================
//
//
// =============================================
//
// *********************************************
// FPGA Chip GRAB(BEGIN) ODYSSEY GRAB MODULE
// *********************************************
//
// =============================================
//
//
// =============================================
//
DIG_GRABCTRL
Grab Control Register
eo_information
5
// --------------------------------------
chnl0cb regular
Channel 0 Combination with other channels
eo_information
0 2 unsigned flag_overflow
//
value = (
(
VDC_ANA * ( TM_ENABLE == 0 ) *
(
( ( VDC_MONO * VDC_WD8 * ( ( 2 ^ CT_TAPS ) / 4 ) ) + ( CT_TAPS == 3 ) ) +
(
( VDC_MONO * ( ! VDC_WD8 ) * ( 2 ^ CT_TAPS ) ) -
( VDC_MONO * ( ! VDC_WD8 ) )
) +
( ( VDC_RGB_PACK | VDC_RGB_COL ) * VDC_WD8 * 2 ) +
( ( VDC_RGB_PACK | VDC_RGB_COL ) * ( ! VDC_WD8 ) * 2 )
)
) +
( VDC_ANA * TM_ENABLE * VDC_MONO * ( ( 2 ^ CT_TAPS ) - 1 ) ) +
(
CAMERA_LINK_AV *
(
( CLC_MODE == 1 ) +
( ( CLC_MODE == 2 ) * 2 )
)
) +
(
VDC_DIG * ( ( CAMERA_LINK_AV == 0 ) | ( CLC_MODE_CH0 == 0 ) ) * TM_ENABLE *
(
( VDC_MONO * ( ( 2 ^ CT_TAPS ) - 1 ) ) +
( VDC_RGB_COL * 2 )
)
)
) ;
//
define_value
Channel 0 is not combined with any other Channels
Channel 0 is combined with Channel 1
Channel 0 is combined with Channel 1 & 2
Channel 0 is combined with Channel 1 & 2 & 3
//
// --------------------------------------
chnl2cb regular
Channel 2 Combination with other channels
eo_information
0 1 unsigned flag_overflow
//
// 2 Asynchronous Grabs simultanous
value = 0 ;
//
define_value
Channel 2 is not combined with Channel 3
Channel 2 is combined with Channel 3
//
// --------------------------------------
muxresh regular
Mux Selection Control for Reshuffler (CL)
eo_information
0 11 unsigned flag_overflow
//
value = (
(
CAMERA_LINK_AV *
(
( ( ( CLC_MODE_CH0 == 9 ) | ( CLC_MODE_CH0 == 12 ) | ( CLC_MODE_CH0 == 15 ) ) * 2 ) +
( ( CLC_MODE_CH0 == 10 ) * 5 ) +
( ( ( CLC_MODE_CH0 < 9 ) | ( CLC_MODE_CH0 == 11 ) ) * 0xA8 ) +
( ( CLC_MODE_CH0 == 13 ) * 0x250 ) +
( ( CLC_MODE_CH0 == 14 ) * 0x65 ) +
( ( CLC_MODE_CH0 == 16 ) * 0x552 )
)
) +
(
VDC_ANA * 0
)
) ;
//
no_define_value
//
// --------------------------------------
maskint protected
Mask Interrupt
eo_information
1 1 unsigned flag_overflow
//
define_value
No Interrupt generated
Interrupt generated
//
// --------------------------------------
reserved protected
eo_information
0 17 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_GTM
Grab Test Module
eo_information
12
// --------------------------------------
tmntap regular
Test module Number of TAP ( Camera Link / Digital )
eo_information
0 3 unsigned flag_overflow
//
// Test Module multiply Taps in RGB ? T.B.D.
value = (
(
TAP_REGIONSX * TAP_REGIONSY * TAP_PIXADJX * TAP_PIXADJY *
(
VDC_MONO +
( ( VDC_RGB_COL | VDC_RGB_PACK ) * 3 ) +
( VDC_RGB_ALPHA * 4 )
)
) - 1 - ( 2 * ( CT_TAPS == 3 ) )
) & 0x00000007 ;
//
define_value
1 Tap
2 Taps
3 Taps
4 Taps
6 Taps
8 Taps
reserved
reserved
//
// --------------------------------------
tmpxd regular
Test module Pixel Depth ( Camera Link / Digital )
eo_information
0 3 unsigned flag_overflow
//
value = (
VDC_VID_WIDTH_10 +
( VDC_VID_WIDTH_12 * 2 ) +
( VDC_VID_WIDTH_14 * 3 ) +
( ( VDC_VID_WIDTH_16 | VDC_WD16 ) * 4 )
) ;
//
define_value
8 Bits
10 Bits
12 Bits
14 Bits
16 Bits
reserved
reserved
reserved
//
// --------------------------------------
tmpxm regular
Test module Pixel Mode
eo_information
0 2 unsigned flag_overflow
//
value = (
( ( ( TM_PIXELMODE == 3 ) * ( TAP_PIXADJX == 1 ) ) | ( TAP_PIXADJX > 1 ) ) +
( ( TM_PIXELMODE == 2 ) * ( TAP_PIXADJX == 1 ) * 2 ) +
( ( TM_PIXELMODE == 4 ) * ( TAP_PIXADJX == 1 ) * 3 )
) ;
//
define_value
Consecutive pixels from 0 to 2n-1 & Resetted start line
Byte aligned pixels & resetted start line
Consecutive pixels from 0 to 2n-1 & not resetted
Byte aligned pixels & not resetted start line
//
// --------------------------------------
tmtmx regular
Test module Time Multiplexed (Camera Link ONLY)
eo_information
0 1 unsigned flag_overflow
//
value = (
( CL_MODE_BITMAP == 5 ) |
( ( CL_MODE_BITMAP > 6 ) * ( CL_MODE_BITMAP < 11 ) ) |
( CL_MODE_BITMAP == 17 )
) ;
//
define_value
No Time Multiplexing
Time Multiplexing
//
// --------------------------------------
tmln regular
Test module Line Number
eo_information
0 1 unsigned flag_overflow
//
value = TM_LINENUMBER ;
//
define_value
No Line Number
First pixels contain Line Number
//
// --------------------------------------
tmtmd regular
Test module Test Mode
eo_information
0 4 unsigned flag_overflow
//
value = (
(
CAMERA_LINK_AV * TM_ENABLE *
(
( CLC_MODE == 0 ) +
( ( CLC_MODE == 1 ) * 3 ) +
( ( CLC_MODE == 2 ) * 4 )
)
) +
( VDC_ANA * TM_ENABLE *
(
( VDC_MONO * VDC_USE_PSG_0 * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) ) +
( VDC_MONO * ( ! VDC_USE_PSG_0 ) * VDC_USE_PSG_1 * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) * 2 ) +
( VDC_MONO * VDC_USE_PSG_0 * VDC_USE_PSG_1 * ( ! VDC_USE_PSG_2 ) * ( ! VDC_USE_PSG_3 ) * 3 ) +
( (
VDC_RGB_COL | VDC_RGB_PACK |
( VDC_MONO * VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * ( ! VDC_USE_PSG_3 ) )
) * 4
) +
( VDC_MONO * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * VDC_USE_PSG_2 * ( ! VDC_USE_PSG_3 ) * 5 ) +
( VDC_MONO * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * ( ! VDC_USE_PSG_2 ) * VDC_USE_PSG_3 * 6 ) +
( VDC_MONO * ( ! VDC_USE_PSG_0 ) * ( ! VDC_USE_PSG_1 ) * VDC_USE_PSG_2 * VDC_USE_PSG_3 * 7 ) +
( VDC_MONO * VDC_USE_PSG_0 * VDC_USE_PSG_1 * VDC_USE_PSG_2 * VDC_USE_PSG_3 * 8 )
)
) +
(
( DEF_ODYSSEY_DIG | DEF_HELIOS_DIG | DEF_SOLIOS_DIG ) * TM_ENABLE *
(
( VDC_MONO * ( ( 2 * ( 2 ^ CT_TAPS ) ) - ( CT_TAPS < 2 ) ) ) +
( VDC_RGB_COL * 3 )
)
)
) ;
//
define_value
Not in test mode
Channel 0 is in test mode (Base Config CL or ANA or DIG)
Channel 1 is in test mode (Base Config CL or ANA)
Channel 0 & 1 are in test mode (Medium Config CL or ANA or DIG)
Channel 0,1 & 2 are in test mode (Full Config CL or ANA or DIG)
Channel 2 is in test mode (Analog)
Channel 3 is in test mode (Analog)
Channel 2 & 3 are in test mode (Analog)
Channel 0,1,2 & 3 are in test mode (Analog or Digital)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
//
// --------------------------------------
tmrgb regular
Test module RGB ( Camera Link / Digital )
eo_information
0 1 unsigned flag_overflow
//
value = ( SYC_DIG * ( VDC_RGB_COL | VDC_RGB_PACK | VDC_RGB_ALPHA ) ) ;
//
define_value
Not RGB
RGB
//
// --------------------------------------
tmprtm regular
Test module Port Mode
eo_information
0 2 unsigned flag_overflow
//
value = (
( CAMERA_LINK_AV *
(
( ( CLC_MODE_CH0 == 1 ) | ( CLC_MODE_CH0 == 4 ) | ( CLC_MODE_CH0 == 9 ) | ( CLC_MODE_CH0 == 14 ) ) +
( ( ( CLC_MODE_CH0 == 10 ) | ( CLC_MODE_CH0 == 13 ) ) * 2 ) +
(
(
( CLC_MODE_CH0 == 2 ) | ( ( CLC_MODE_CH0 > 4 ) & ( CLC_MODE_CH0 < 8 ) ) |
( CLC_MODE_CH0 == 11 ) | ( CLC_MODE_CH0 == 12 ) | ( CLC_MODE_CH0 == 15 ) | ( CLC_MODE_CH0 == 16 )
) * 3
)
)
) +
( VDC_ANA * 0 )
) ;
//
define_value
Port Mode 0
Port Mode 1
Port Mode 2
Port Mode 3
//
// --------------------------------------
tmnolnbrst regular
Test module NO Line Number Reset
eo_information
0 1 unsigned flag_overflow
//
value = TM_ENABLE ;
//
define_value
Line Number is Reset on a Start of Frame
Line Number is NOT Reset on a Start of Frame
//
// --------------------------------------
tmfrmcnt regular
Test module Frame Count Offset
eo_information
0 1 unsigned flag_overflow
//
value = ( TM_ENABLE * ( TM_PIXELMODE == 0 ) ) ;
//
define_value
No Frame Count
The 1st pixel replaced by Frame Count Value
//
// --------------------------------------
tmfrmcntofs regular
Test module Frame Count Offset
eo_information
0 1 unsigned flag_overflow
//
value = ( TM_ENABLE * ( TM_PIXELMODE == 0 ) ) ;
//
define_value
No Offset
Moving Pattern
//
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_GCTRLCHNL
Grab Control Register
eo_information
5
// --------------------------------------
gbitinchnl0 regular
Grab number of Bits Input for Channel 0
eo_information
0 3 unsigned flag_overflow
//
value = (
VDC_VID_WIDTH_10 +
( VDC_VID_WIDTH_12 * 2 ) +
( VDC_VID_WIDTH_14 * 3 ) +
( ( VDC_VID_WIDTH_16 | VDC_WD16 ) * 4 )
) ;
//
define_value
Channel 0 receives 8 bits data
Channel 0 receives 10 bits data
Channel 0 receives 12 bits data
Channel 0 receives 14 bits data
Channel 0 receives 16 bits data
reserved
reserved
reserved
//
// --------------------------------------
demuxcfg regular
Demultiplexing Configuration on channel 0
eo_information
0 2 unsigned flag_overflow
//
// Dual base Option = 0,1 Only else always 0
value = (
CAMERA_LINK_AV *
(
( ( CLC_MODE_CH0 == 4 ) | ( CLC_MODE_CH0 == 7 ) ) +
(
( ( CLC_MODE_CH0 == 6 ) | ( CLC_MODE_CH0 == 8 ) |
( CLC_MODE_CH0 == 0xF )
) * 2
)
)
) ;
//
define_value
Bypass. Data is not time multiplexed
2 taps (14-16 bits) or 4 taps (8 bits)
2 RGB (8 bits) or 4 taps (10-12 bits) or 8 taps (8 bits)
reserved
//
// --------------------------------------
lutout regular
LUT Output mode on Channel 0
eo_information
0 2 unsigned flag_overflow
//
// Default LUT bypass FOR NOW
value = 2 ;
//
define_value
LUT outputs 8 bits
LUT outputs 16 bits
LUT is bypass
reserved
//
// --------------------------------------
palette regular
Palette Selection for LUTs on Channel 0
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// --------------------------------------
reserved protected
eo_information
0 6 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
// *********************************************
// FPGA Chip GRAB(END) ODYSSEY GRAB MODULE
// *********************************************
//
// =============================================
//
//
// =============================================
//
// REGISTERS NOT USED ANYMORE : COMPATIBILITY DCFs LOAD
//
// =============================================
//
//
// =============================================
//
DIG_T0CTL_L
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_T0CTL_H
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_T1CTL_L
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_T1CTL_H
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL0_L
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL0_H
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL1_L
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL1_H
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL1L
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL1H
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_IOCTL0_L
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
DIG_ENCTL
OLD Register NOT USED anymore
eo_information
2
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
[EOF]
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Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
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