1. DD_DCCLMXRTWIN_100.zip Driver
2. Intelcam.inf File Contents

Intelcam.inf Driver File Contents (DD_DCCLMXRTWIN_100.zip)

[INFO_FILE]
///////////////////////////////////////////////////////////////////////////////
//
// REVISION HISTORY: 
//
// 0002.0000.0000 - initial version.
// 0002.0000.0001 - fixed problem with blob sync enabling on output only.
//
///////////////////////////////////////////////////////////////////////////////
//
///////////////////////////////////////////////////////////////////////////////
//
// SECTION #1: HEADER
//
///////////////////////////////////////////////////////////////////////////////
60BF     0002.0000.0001
INTELCAM
"Intellicam Digitizer Configuration Software"
Information file for INTELLICAM
//
///////////////////////////////////////////////////////////////////////////////
//
// SECTION #2: NEW GENERAL PARAMETERS|MEMBERS
//
///////////////////////////////////////////////////////////////////////////////
[NEW_GPARAM]
//
GVDT_TYPE
autocorrect = ( DAT_ERROR == 3076 ) ? 
              ( UNDO + VDT_NOVERT.SETVALUE[1] +
                       VDT_NINTRL.SETVALUE[1] +
                       VDT_INTERL.SETVALUE[0] ) ;
eo_param
//
GSYC_BLOC_SYNC
enable = ENABLE[SYC_CAM_GEN ? SYC_BLK_IN_AV : SYC_BLK_OUT_AV] ;
eo_param
//
///////////////////////////////////////////////////////////////////////////////
//
// SECTION #3: MEMBER COMPATIBILITY
//
///////////////////////////////////////////////////////////////////////////////
[COMPATIBILITY]
//
// Translate general parameters from v1.09
//
// input video channel indicator was a unique parameter
VDC_IN_CH
filter = ( ( DAT_VALUE_READ == 0 ) ? VDC_IN_CH0.SETVALUE[1] ) ||
		 ( ( DAT_VALUE_READ == 1 ) ? VDC_IN_CH1.SETVALUE[1] ) ||
		 ( ( DAT_VALUE_READ == 2 ) ? VDC_IN_CH2.SETVALUE[1] ) ||
		 ( ( DAT_VALUE_READ == 3 ) ? VDC_IN_CH3.SETVALUE[1] ) ;
//
// the first 5 VDC_D_WDx become VDC_WDn, the rest are dynamic ones
VDC_D_WD0
filter = VDC_WD8.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD1
filter = VDC_WD16.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD2
filter = VDC_WD24.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD3
filter = VDC_WD32.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD4
filter = VDC_WD64.SETVALUE[DAT_VALUE_READ] ;
//
// CT_AS and CT_OT are now the same as CT_FS
CT_AS
filter = DAT_VALUE_READ ? CT_FS.SETVALUE[1] ;
CT_OT
filter = DAT_VALUE_READ ? CT_FS.SETVALUE[1] ;
//
// there was a typo in intellicam 2.0 betas
CT_CONV_INVERT
filter = CT_CONV_INVERTED.SETVALUE[DAT_VALUE_READ] ;
//
// CT_CONV_ODD_EV is now CT_CONV_INVERTED=1
CT_CONV_ODD_EV
filter = DAT_VALUE_READ ? CT_CONV_INVERTED.SETVALUE[1] ;
//
// CT_CONV_EVEN_ODD and CT_CONV_ANY are now GP_CT_CONV_INVERTED=0
CT_CONV_EV_ODD
filter = DAT_VALUE_READ ? CT_CONV_INVERTED.SETVALUE[0] ;
CT_CONV_ANY
filter = DAT_VALUE_READ ? CT_CONV_INVERTED.SETVALUE[0] ;
//
// GRB_MD_W_TRG is now GRB_MD_CONT and its meaning is reversed
GRB_MD_W_TRG
filter = GRB_MD_CONT.SETVALUE[( ! DAT_VALUE_READ )] ;
//
//
// Initialize members not found in old DCFs
//
// set a correct value for VDT_HSYNC_FREQ
VDT_HSYNC_FREQ
filter = ( ! DAT_IS_INIT ) ? 
		 VDT_HSYNC_FREQ.SETVALUE[PCK_FREQ / VDT_HTOTAL] ;
//
// set a correct value for VDT_VSYNC_FREQ
VDT_VSYNC_FREQ
filter = ( ! DAT_IS_INIT ) ? 
		 VDT_VSYNC_FREQ.SETVALUE[( 1 + VDT_INTERL ) * VDT_HSYNC_FREQ / VDT_VTOTAL] ;
//
// video signal - we no longuer rely on the VDC_MONO to determine
// if a signal is digital or analog
VDC_ANA
filter = ( ! DAT_IS_INIT ) ? 
           (
		     ( ( ! VDC_DIG ) & ( ! VDC_ANA ) ) ? ( 
             VDC_MONO ? ( VDC_ANA.SETVALUE[1] + VDC_WD8.SETVALUE[1] ) 
                      : ( VDC_DIG.SETVALUE[1] ) ) 
           : ( ( VDC_DIG ) ? ( VDC_MONO.SETVALUE[1] + VDC_ANA.SETVALUE[0] ) ) 
           ) ;
[EOF]

GGRB_ACTIVATION

///////////////////////////////////////////////////////////////////////////////
// error messages
// 
error_message
ERR_INVALID_VALUE, "GGRB_ACTIVATION: Internal error, invalid value."
ERR_TOOMANY_VALUE, "GGRB_ACTIVATION: Internal error, too many values selected."
ERR_HW_TRG_NSUP,   "Hardware trigger, not supported by digitizer."
eo_error_message

///////////////////////////////////////////////////////////////////////////////
// valid - 
// 
valid = ( ( GRB_MD_CONT > 1 ) ? 
          GRB_MD_CONT.ADDERROR[ERR_INVALID_VALUE] ) : (

        ( ( ( GRB_MD_CONT + GRB_MD_HW_TRG + GP_GRB_MD_SW_TRG ) > 1 ) ? 
          GRB_MD_CONT.ADDERROR[ERR_TOOMANY_VALUE] ) : (

        ( ( ( ! GRB_MD_HW_TRG_AV ) & GRB_MD_HW_TRG ) ?
          GRB_MD_CONT.ADDERROR[ERR_HW_TRG_NS] ) ) ) ;

///////////////////////////////////////////////////////////////////////////////
// enable - if triggered, forceoff non imm. modes in line scan
// 
enable = ( ! GRB_MD_CONT ) ? 
         ( 1 | ( CT_LS ? 
               ( FORCEOFF[GRB_ACT_NXT_FRM] +
                 FORCEOFF[GRB_ACT_IMM_SKP_NFRM]
               )
               )
         ) ;
eo_param
//
GGRB_STARTON
///////////////////////////////////////////////////////////////////////////////
// enable - if triggered and interlaced
// 
enable = ( ( ! GRB_MD_CONT ) & ( VDT_INTERL ) ) ;
eo_param
//
GGRB_TRG_SIGNAL
///////////////////////////////////////////////////////////////////////////////
// enable - if hw triggered
// 
enable = ( GRB_MD_HW_TRG ) ;
eo_param
//
GGRB_TRG_FORMAT
///////////////////////////////////////////////////////////////////////////////
// enable - if hw triggered
// 
enable = ( GRB_MD_HW_TRG ) ;
eo_param
//
GGRB_TRG_POL
///////////////////////////////////////////////////////////////////////////////
// enable - if hw triggered
// 
enable = ( GRB_MD_HW_TRG ) ;
eo_param
//