[INFO_FILE]
60BF 0002.0000.0047
GENESIS_GRAB_0
"Matrox Genesis"
Information file for the GENESIS board.
[NEW_GPARAM]
GCT_CAMERA_NUMBER
valid = DAT_ERROR ||
( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) & ( CT_CAMERA > 0 ) ) ? ADDERROR[ERR_TOOMANYCAM] ) ;
error_message
ERR_TOOMANYCAM, "Cannot have more than 1 camera in analog if the bus width is larger than 8 bits"
eo_error_message
eo_param
GVDT_CL_USE_CAMERA_VALID MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
enable = ENABLE[0] ;
eo_param
GCT_CAMERA_TAPS
valid = DAT_ERROR ||
( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) & ( CT_TAPS > 0 ) ) ? ADDERROR[ERR_TOOMANYTAPS] ) ;
error_message
ERR_TOOMANYTAPS, "Cannot have more than 1 tap in analog if the bus width is larger than 8 bits"
eo_error_message
eo_param
GTAP_CONFIGURATION NUM_PAR|ED_FLD_STRING|BRD_OPT_ON
param_info
Tap Configuration
Tap Destination(s)
eo_param_info
board_specific_value
NO_STRING M_DEFAULT TAP_CONFIG M_DEFAULT yes 1
eo_board_specific_value
valid = ( ( ! DEF_TAP_VALID ) & ( TAP_CONFIG != 0 ) ) ? ADDERROR[ERR_INVTAP] ;
enable = ENABLE[1] ;
error_message
ERR_INVTAP, "Invalid tap destinations selected"
eo_error_message
eo_param
GVDC_VID_WIDTH
board_specific_value
"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV yes|M_ARRAY_TWO
"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV yes|M_ARRAY_TWO
"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV yes|M_ARRAY_TWO
eo_board_specific_value
valid = DAT_ERROR ||
( ( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) &
( CT_CAMERA > 0 ) ) ? ADDERROR[ERR_TOOMANYCAM] ) +
( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) &
( CT_TAPS > 0 ) ) ? ADDERROR[ERR_TOOMANYTAPS] ) ) ;
error_message
ERR_TOOMANYCAM, "Cannot have more than 1 camera in analog if the bus width is larger than 8 bits"
ERR_TOOMANYTAPS, "Cannot have more than 1 tap in analog if the bus width is larger than 8 bits"
eo_error_message
eo_param
GEXP_GEN_MODE
valid = DAT_ERROR ||
( ( ( EXP_CLOCK_2_TIMER1 | ( EXP_TRG_SIGNAL_2_TIMER1 & EXP_MD_W_TRG_2 ) |
EXP_COMBINE_2_XOR | EXP_COMBINE_2_AND |
EXP_COMBINE_2_OR | GRB_TRG_SIGNAL_TIMER1 ) &
( ! DEF_TIMER1_ENABLE ) ) ? ADDERROR[ERR_T1NOTSET] ) ;
error_message
ERR_T1NOTSET, "The exposure timer 1 signal must be set."
eo_error_message
eo_param
GEXP_CLOCK
board_specific_value
"hsync clock" M_DEFAULT EXP_CLOCK_HSYNC EXP_CLOCK_HSYNC_AV yes
"vsync clock" M_DEFAULT EXP_CLOCK_VSYNC EXP_CLOCK_VSYNC_AV yes
"crystal clock" M_DEFAULT EXP_CLOCK_CRYSTAL EXP_CLOCK_CRYSTAL_AV yes
"digital port trigger" M_DEFAULT EXP_CLOCK_DITRIG EXP_CLOCK_DITRIG_AV yes
"analog port trigger" M_DEFAULT EXP_CLOCK_VTRIG EXP_CLOCK_VTRIG_AV yes
"timer 2 output" M_DEFAULT EXP_CLOCK_TIMER2 EXP_CLOCK_TIMER2_AV yes
eo_board_specific_value
pagelinks = EXP_CLOCK_TIMER2 ? GEXP_GEN_MODE_2.VALID ;
eo_param
GEXP_FREQUENCY
enable = DAT_ENABLED ||
( ( EXP_ASY_CLK * ( ! DEF_MASTER ) * ( ! PCK_ODIVF ) ) ? ENABLE[1] ) ||
ENABLE[EXP_CLOCK_DITRIG | EXP_CLOCK_VTRIG | EXP_CLOCK_TIMER2] ;
eo_param
GEXP_TRG_SIGNAL
board_specific_value
"digital port" M_DEFAULT EXP_TRG_SIGNAL_DPORT EXP_TRG_EXT_OTH1_AV yes
"analog port" M_DEFAULT EXP_TRG_SIGNAL_APORT EXP_TRG_EXT_OTH2_AV yes
"timer 2 output" M_DEFAULT EXP_TRG_SIGNAL_TIMER2 EXP_TRG_EXT_OTH4_AV yes
eo_board_specific_value
pagelinks = EXP_TRG_SIGNAL_TIMER2 ? GEXP_GEN_MODE_2.VALID ;
eo_param
GEXP_TRG_FORMAT
enable = ENABLE[EXP_TRG_SIGNAL_DPORT] ;
eo_param
GEXP_TRG_POL
enable = ENABLE[EXP_MD_W_TRG] ;
eo_param
GEXP_COMBINE ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 1 Combination
eo_param_info
board_specific_value
"timer 1" M_DEFAULT DUMMY_PAR NO_BOPTION yes
"timer 1 XOR timer 2" M_DEFAULT EXP_COMBINE_XOR M_DEFAULT yes
"timer 1 AND timer 2" M_DEFAULT EXP_COMBINE_AND M_DEFAULT yes
"timer 1 OR timer 2" M_DEFAULT EXP_COMBINE_OR M_DEFAULT yes
eo_board_specific_value
pagelinks = GEXP_GEN_MODE_2.VALID ;
enable = ENABLE[DEF_TIMER1_ENABLE] ;
eo_param
GEXP_PRESCALE1 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 1 Prescale
eo_param_info
board_specific_value
1 M_DEFAULT EXP_PRESCALE1_1 M_DEFAULT yes 1
2 M_DEFAULT EXP_PRESCALE1_2 M_DEFAULT yes
4 M_DEFAULT EXP_PRESCALE1_4 M_DEFAULT yes
8 M_DEFAULT EXP_PRESCALE1_8 M_DEFAULT yes
16 M_DEFAULT EXP_PRESCALE1_16 M_DEFAULT yes
eo_board_specific_value
enable = ENABLE[EXP_MD_W_TRG] ;
eo_param
GEXP_GEN_MODE_2
valid = DAT_ERROR ||
( ( ( EXP_CLOCK_TIMER2 | ( EXP_TRG_SIGNAL_TIMER2 & EXP_MD_W_TRG ) |
EXP_COMBINE_XOR | EXP_COMBINE_AND |
EXP_COMBINE_OR | GRB_TRG_SIGNAL_TIMER2 ) &
( ! DEF_TIMER2_ENABLE ) ) ? ADDERROR[ERR_T2NOTSET] ) ;
error_message
ERR_T2NOTSET, "The exposure timer 2 signal must be set."
eo_error_message
eo_param
GEXP_CLOCK_2
board_specific_value
"hsync clock" M_DEFAULT EXP_CLOCK_2_HSYNC EXP_CLOCK_2_HSYNC_AV yes
"vsync clock" M_DEFAULT EXP_CLOCK_2_VSYNC EXP_CLOCK_2_VSYNC_AV yes
"crystal clock" M_DEFAULT EXP_CLOCK_2_CRYSTAL EXP_CLOCK_2_CRYSTAL_AV yes
"digital port trigger" M_DEFAULT EXP_CLOCK_2_DITRIG EXP_CLOCK_2_DITRIG_AV yes
"analog port trigger" M_DEFAULT EXP_CLOCK_2_VTRIG EXP_CLOCK_2_VTRIG_AV yes
"timer 1 output" M_DEFAULT EXP_CLOCK_2_TIMER1 EXP_CLOCK_2_TIMER1_AV yes
eo_board_specific_value
pagelinks = EXP_CLOCK_2_TIMER1 ? GEXP_GEN_MODE.VALID ;
eo_param
GEXP_FREQUENCY_2
enable = DAT_ENABLED ||
( ( EXP_ASY_CLK_2 & ( ! EXP_ASY_CLK ) & ( ! DEF_MASTER ) & ( ! PCK_ODIVF ) )
? ENABLE[1] ) ||
ENABLE[EXP_CLOCK_2_DITRIG | EXP_CLOCK_2_VTRIG | EXP_CLOCK_2_TIMER1] ;
eo_param
GEXP_TRG_SIGNAL_2
board_specific_value
"digital port" M_DEFAULT EXP_TRG_SIGNAL_2_DPORT EXP_TRG_EXT_2_OTH0_AV yes
"analog port" M_DEFAULT EXP_TRG_SIGNAL_2_APORT EXP_TRG_EXT_2_OTH3_AV yes
"timer 1 output" M_DEFAULT EXP_TRG_SIGNAL_2_TIMER1 EXP_TRG_EXT_2_OTH2_AV yes
eo_board_specific_value
pagelinks = EXP_TRG_SIGNAL_2_TIMER1 ? GEXP_GEN_MODE.VALID ;
eo_param
GEXP_TRG_FORMAT_2
enable = ENABLE[EXP_TRG_SIGNAL_2_DPORT] ;
eo_param
GEXP_TRG_POL_2
enable = ENABLE[EXP_MD_W_TRG_2] ;
eo_param
GEXP_COMBINE_2 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 2 Combination
eo_param_info
board_specific_value
"timer 2" M_DEFAULT DUMMY_PAR NO_BOPTION yes
"timer 2 XOR timer 1" M_DEFAULT EXP_COMBINE_2_XOR M_DEFAULT yes
"timer 2 AND timer 1" M_DEFAULT EXP_COMBINE_2_AND M_DEFAULT yes
"timer 2 OR timer 1" M_DEFAULT EXP_COMBINE_2_OR M_DEFAULT yes
eo_board_specific_value
pagelinks = GEXP_GEN_MODE.VALID ;
enable = ENABLE[DEF_TIMER2_ENABLE] ;
eo_param
GEXP_PRESCALE2 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 2 Prescale
eo_param_info
board_specific_value
1 M_DEFAULT EXP_PRESCALE2_1 M_DEFAULT yes 1
2 M_DEFAULT EXP_PRESCALE2_2 M_DEFAULT yes
4 M_DEFAULT EXP_PRESCALE2_4 M_DEFAULT yes
8 M_DEFAULT EXP_PRESCALE2_8 M_DEFAULT yes
16 M_DEFAULT EXP_PRESCALE2_16 M_DEFAULT yes
eo_board_specific_value
enable = ENABLE[EXP_MD_W_TRG_2] ;
eo_param
GGRB_TRG_SIGNAL
board_specific_value
"digital port trigger" M_DEFAULT GRB_TRG_SIGNAL_DPORT GRB_TRG_SIGNAL_DPORT_AV yes
"analog port trigger" M_DEFAULT GRB_TRG_SIGNAL_APORT GRB_TRG_SIGNAL_APORT_AV yes
"timer 1 output" M_DEFAULT GRB_TRG_SIGNAL_TIMER1 GRB_TRG_SIGNAL_TIMER1_AV yes
"timer 2 output" M_DEFAULT GRB_TRG_SIGNAL_TIMER2 GRB_TRG_SIGNAL_TIMER2_AV yes
eo_board_specific_value
pagelinks = ( GRB_TRG_SIGNAL_TIMER1 ? GEXP_GEN_MODE.VALID ) ||
( GRB_TRG_SIGNAL_TIMER2 ? GEXP_GEN_MODE_2.VALID ) ;
eo_param
GGRB_TRG_FORMAT
valid = 0 ;
eo_param
GUSR_IN_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Input Enable
eo_param_info
board_specific_value
no M_DEFAULT USR_IENABLE M_DEFAULT yes
yes M_DEFAULT USR_IENABLE M_DEFAULT yes
eo_board_specific_value
enable = ENABLE[1] ;
eo_param
GUSR_IN_FORMAT ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Input Format
eo_param_info
board_specific_value
TTL M_DEFAULT USR_ITTL M_DEFAULT yes 1
RS-422 M_DEFAULT USR_I422 M_DEFAULT yes
eo_board_specific_value
enable = ENABLE[USR_IENABLE] ;
eo_param
GUSR_OUT_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Output Enable
eo_param_info
board_specific_value
no M_DEFAULT USR_OENABLE M_DEFAULT yes
yes M_DEFAULT USR_OENABLE M_DEFAULT yes
eo_board_specific_value
eo_param
GUSR_OUT_FORMAT ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Output Format
eo_param_info
board_specific_value
TTL M_DEFAULT USR_OTTL M_DEFAULT yes 1
RS-422 M_DEFAULT USR_O422 M_DEFAULT yes
eo_board_specific_value
enable = ENABLE[USR_OENABLE] ;
eo_param
GUSR_BIT_0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
User Bit 0
eo_param_info
board_specific_value
no M_DEFAULT USR_BIT_1_OTH0 USR_BIT_1_AV yes
yes M_DEFAULT USR_BIT_1_OTH0 NO_BOPTION
eo_board_specific_value
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
eo_param
GUSR_BIT_1 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
User Bit 1
eo_param_info
board_specific_value
no M_DEFAULT USR_BIT_2_OTH0 USR_BIT_2_AV yes
yes M_DEFAULT USR_BIT_2_OTH0 NO_BOPTION
eo_board_specific_value
enable = ENABLE[DAT_ENABLED * USR_OENABLE] ;
eo_param
GUSR_CAMERA_BIT_0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Camera Control 0
eo_param_info
board_specific_value
no M_DEFAULT USR_BIT_3_OTH0 USR_BIT_3_AV yes
yes M_DEFAULT USR_BIT_3_OTH0 NO_BOPTION
eo_board_specific_value
eo_param
GUSR_CAMERA_BIT_1 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Camera Control 1
eo_param_info
board_specific_value
no M_DEFAULT USR_BIT_4_OTH0 USR_BIT_4_AV yes
yes M_DEFAULT USR_BIT_4_OTH0 NO_BOPTION
eo_board_specific_value
eo_param
GUSR_CAMERA_BIT_2 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Bits
Camera Control 2
eo_param_info
board_specific_value
no M_DEFAULT USR_BIT_5_OTH0 USR_BIT_5_AV yes
yes M_DEFAULT USR_BIT_5_OTH0 NO_BOPTION
eo_board_specific_value
eo_param
GCL_CONFIG_MODE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Configuration mode
eo_param_info
board_specific_value
base M_DEFAULT CLC_MODE CL_CONFIG_BASE_AV yes 0
medium M_DEFAULT CLC_MODE CL_CONFIG_MEDIUM_AV yes
full M_DEFAULT CLC_MODE CL_CONFIG_FULL_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
pagelinks = GCL_MODE_CH0.VALID ;
eo_param
GCL_ACTIVE_CH0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Activate Channel 0
eo_param_info
board_specific_value
no M_DEFAULT CLC_ACTIVE_CH0 CAMERA_LINK_AV yes
yes M_DEFAULT CLC_ACTIVE_CH0 CL_CHANNEL0_AV yes 1
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
pagelinks = GCL_MODE_CH0.VALID ;
eo_param
GCL_ACTIVE_CH1 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Activate Channel 1
eo_param_info
board_specific_value
no M_DEFAULT CLC_ACTIVE_CH1 CAMERA_LINK_AV yes 0
yes M_DEFAULT CLC_ACTIVE_CH1 CL_CHANNEL1_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
pagelinks = GCL_MODE_CH0.VALID ;
eo_param
GCL_MODE_CH0 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Channel 0 mode
eo_param_info
board_specific_value
"B1 1 tap 8 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_BASE yes
"B2 1 tap 10...16 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_BASE yes
"B3 2 taps 8 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_BASE yes
"B4 2 taps 10/12 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_BASE yes
"B5 3 taps 8 bit (RGB)" M_DEFAULT CLC_MODE_CH0 CLC_MODE_BASE yes
"M1 2 taps 8 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_MEDIUM yes
"M2 2 taps 10...16 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_MEDIUM yes
"M3 2 taps 10...16 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_MEDIUM yes
"M4 4 taps 8 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_MEDIUM yes
"M5 4 taps 8 bits" M_DEFAULT CLC_MODE_CH0 CLC_MODE_MEDIUM yes
eo_board_specific_value
enable = ENABLE[CL_CHANNEL0_AV] ;
valid = DAT_ERROR || CAMERA_LINK_AV *
(
( ( CLC_MODE == 0 ) & ( ( CLC_MODE_CH0 < 0 ) | ( CLC_MODE_CH0 > 4 ) ) ? ADDERROR[ERR_BASE] ) ||
( ( CLC_MODE == 1 ) & ( ( CLC_MODE_CH0 < 5 ) | ( CLC_MODE_CH0 > 9 ) ) ? ADDERROR[ERR_MEDIUM] ) ||
( ( DEF_CL_BITS == 8 ) & ( DEF_CL_BUS_BITS != 8 ) ? ADDERROR[ERR_8BITS] ) ||
( ( DEF_CL_BITS == 12 ) & ( ( DEF_CL_BUS_BITS <= 8 ) | ( DEF_CL_BUS_BITS > 12 ) ) ? ADDERROR[ERR_12BITS] ) ||
( ( DEF_CL_BITS == 16 ) & ( ( DEF_CL_BUS_BITS <= 8 ) | ( DEF_CL_BUS_BITS > 16 ) ) ? ADDERROR[ERR_16BITS] ) ||
( ( DEF_CL_TAPS < DEF_CL_BUS_TAPS ) ? ADDERROR[ERR_LESSTAPS] ) ||
( ( DEF_CL_TAPS > DEF_CL_BUS_TAPS ) ? ADDERROR[ERR_MORETAPS] )
) ;
pagelinks = GVDC_VID_WIDTH.VALID ;
error_message
ERR_BASE, "Invalid base mode selected for channel 0."
ERR_MEDIUM, "Invalid medium mode selected for channel 0."
ERR_8BITS, "The data bus width must be adjusted to 8 bits."
ERR_12BITS, "The data bus width must be adjusted to 10/12 bits."
ERR_16BITS, "The data bus width must be adjusted to 10/12/14/16 bits."
ERR_LESSTAPS, "The camera mode specified uses less taps than required by the data bus."
ERR_MORETAPS, "The camera mode specified uses more taps than required by the data bus."
eo_error_message
eo_param
GCL_MODE_CH1 MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Channel 1 mode
eo_param_info
board_specific_value
"B1 1 tap 8 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_BASE yes
"B2 1 tap 10...16 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_BASE yes
"B3 2 taps 8 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_BASE yes
"B4 2 taps 10/12 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_BASE yes
"B5 3 taps 8 bit (RGB)" M_DEFAULT CLC_MODE_CH1 CLC_MODE_BASE yes
"M1 2 taps 8 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_MEDIUM yes
"M2 2 taps 10...16 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_MEDIUM yes
"M3 2 taps 10...16 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_MEDIUM yes
"M4 4 taps 8 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_MEDIUM yes
"M5 4 taps 8 bits" M_DEFAULT CLC_MODE_CH1 CLC_MODE_MEDIUM yes
eo_board_specific_value
enable = ENABLE[CL_CHANNEL1_AV] ;
valid = DAT_ERROR || CAMERA_LINK_AV *
( ( CLC_MODE == 0 ) & ( ( CLC_MODE_CH0 < 0 ) | ( CLC_MODE_CH0 > 4 ) ) ? ADDERROR[ERR_BASE] ) ;
pagelinks = GCL_MODE_CH0.VALID ;
error_message
ERR_BASE, "Invalid base mode selected for channel 1."
eo_error_message
eo_param
GCL_SYNC_SOURCE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Synchronization source selection
eo_param_info
board_specific_value
"grab channel" M_DEFAULT CLC_SYNC_SOURCE CAMERA_LINK_AV yes 0
"channel 0" M_DEFAULT CLC_SYNC_SOURCE CL_CHANNEL0_AV yes
"channel 1" M_DEFAULT CLC_SYNC_SOURCE CL_CHANNEL1_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_VSYNC_SEL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Vertical synchronization selection
eo_param_info
board_specific_value
"HSYNC selected (edge sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes 0
"LVDS trigger (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"Opto-coupled trigger (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"TTL trigger (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"User bit 0 (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
"FVAL selected (level sensitive)" M_DEFAULT CLC_VSYNC_SEL CAMERA_LINK_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_VSYNC_POL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Vertical synchronization polarity
eo_param_info
board_specific_value
"active high" M_DEFAULT CLC_VSYNC_POL CAMERA_LINK_AV yes 0
"active low" M_DEFAULT CLC_VSYNC_POL CAMERA_LINK_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_HSYNC_SEL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Horizontal synchronization selection
eo_param_info
board_specific_value
"HSYNC selected (edge sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes 0
"LVDS trigger (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"Opto-coupled trigger (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"TTL trigger (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"User bit 1 (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
"LVAL selected (level sensitive)" M_DEFAULT CLC_HSYNC_SEL CAMERA_LINK_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_HSYNC_POL MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Configuration
Horizontal synchronization polarity
eo_param_info
board_specific_value
"active high" M_DEFAULT CLC_HSYNC_POL CAMERA_LINK_AV yes 0
"active low" M_DEFAULT CLC_HSYNC_POL CAMERA_LINK_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_CC1_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Control Bits
Camera Control bit 1 input source
eo_param_info
board_specific_value
disabled M_DEFAULT CLB_CC1 CL_CC1_DISABLE_AV no
"timer 1" M_DEFAULT CLB_CC1 CL_CC1_TIMER_1_AV yes 1
"timer 2" M_DEFAULT CLB_CC1 CL_CC1_TIMER_2_AV yes
"user output 0" M_DEFAULT CLB_CC1 CL_CC1_USROUT_0_AV yes
"user output 1" M_DEFAULT CLB_CC1 CL_CC1_USROUT_1_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_CC2_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Control Bits
Camera Control bit 2 input source
eo_param_info
board_specific_value
disabled M_DEFAULT CLB_CC2 CL_CC2_DISABLE_AV no
"timer 1" M_DEFAULT CLB_CC2 CL_CC2_TIMER_1_AV yes
"timer 2" M_DEFAULT CLB_CC2 CL_CC2_TIMER_2_AV yes 2
"user output 0" M_DEFAULT CLB_CC2 CL_CC2_USROUT_0_AV yes
"user output 1" M_DEFAULT CLB_CC2 CL_CC2_USROUT_1_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_CC3_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Control Bits
Camera Control bit 3 input source
eo_param_info
board_specific_value
disabled M_DEFAULT CLB_CC3 CL_CC3_DISABLE_AV no
"timer 1" M_DEFAULT CLB_CC3 CL_CC3_TIMER_1_AV yes
"timer 2" M_DEFAULT CLB_CC3 CL_CC3_TIMER_2_AV yes
"user output 0" M_DEFAULT CLB_CC3 CL_CC3_USROUT_0_AV yes 3
"user output 1" M_DEFAULT CLB_CC3 CL_CC3_USROUT_1_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_CC4_SRC MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Control Bits
Camera Control bit 4 input source
eo_param_info
board_specific_value
disabled M_DEFAULT CLB_CC4 CL_CC4_DISABLE_AV no
"timer 1" M_DEFAULT CLB_CC4 CL_CC4_TIMER_1_AV yes
"timer 2" M_DEFAULT CLB_CC4 CL_CC4_TIMER_2_AV yes
"user output 0" M_DEFAULT CLB_CC4 CL_CC4_USROUT_0_AV yes
"user output 1" M_DEFAULT CLB_CC4 CL_CC4_USROUT_1_AV yes 4
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_CCOUT1_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Control Bits
Enable CC bits on the first connector
eo_param_info
board_specific_value
no M_DEFAULT CLB_CCOUTEN1 CAMERA_LINK_AV yes
yes M_DEFAULT CLB_CCOUTEN1 CAMERA_LINK_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
GCL_CCOUT2_ENABLE MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Camera Link Control Bits
Enable CC bits on the second connector
eo_param_info
board_specific_value
no M_DEFAULT CLB_CCOUTEN2 CAMERA_LINK_AV yes
yes M_DEFAULT CLB_CCOUTEN2 CAMERA_LINK_AV yes
eo_board_specific_value
enable = ENABLE[CAMERA_LINK_AV] ;
eo_param
[COMPATIBILITY]
EXP_MD_EXT
filter = DAT_VALUE_READ ?
( GRB_MD_HW_TRG
? ( EXP_TRG_SIGNAL_DPORT.SETVALUE[GRB_TRG_SIGNAL_DPORT] +
EXP_TRG_SIGNAL_APORT.SETVALUE[GRB_TRG_SIGNAL_APORT] )
: ( EXP_TRG_SIGNAL_DPORT.SETVALUE[VDC_DIG] +
EXP_TRG_SIGNAL_APORT.SETVALUE[VDC_ANA] ) +
EXP_MD_EXT.SETVALUE[0] ) ;
USR_CLOCK_VALUE
filter = 0 ;
USR_CLK_VALUE_OTH0
filter = 0 ;
VDC_VID_WIDTH_OTH0
filter = VDC_VID_WIDTH_10.SETVALUE[DAT_VALUE_READ] ;
VDC_VID_WIDTH_OTH1
filter = VDC_VID_WIDTH_12.SETVALUE[DAT_VALUE_READ] ;
VDC_VID_WIDTH_OTH2
filter = VDC_VID_WIDTH_14.SETVALUE[DAT_VALUE_READ] ;
GRB_TRG_SIGNAL_OTH0
filter = GRB_TRG_SIGNAL_DPORT.SETVALUE[DAT_VALUE_READ] ;
GRB_TRG_SIGNAL_OTH1
filter = GRB_TRG_SIGNAL_APORT.SETVALUE[DAT_VALUE_READ] ;
GRB_TRG_SIGNAL_OTH2
filter = 0 ;
GRB_TRG_SIGNAL_OTH3
filter = 0 ;
GRB_TRG_SIGNAL_OTH4
filter = GRB_TRG_SIGNAL_TIMER1.SETVALUE[DAT_VALUE_READ] ;
GRB_TRG_SIGNAL_OTH5
filter = GRB_TRG_SIGNAL_TIMER2.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_OTH0
filter = EXP_CLOCK_HSYNC.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_OTH1
filter = EXP_CLOCK_VSYNC.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_OTH2
filter = EXP_CLOCK_CRYSTAL.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_OTH3
filter = EXP_CLOCK_DITRIG.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_OTH4
filter = EXP_CLOCK_VTRIG.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_OTH5
filter = EXP_CLOCK_TIMER2.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_2_OTH0
filter = EXP_CLOCK_2_HSYNC.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_2_OTH1
filter = EXP_CLOCK_2_VSYNC.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_2_OTH2
filter = EXP_CLOCK_2_CRYSTAL.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_2_OTH3
filter = EXP_CLOCK_2_DITRIG.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_2_OTH4
filter = EXP_CLOCK_2_VTRIG.SETVALUE[DAT_VALUE_READ] ;
EXP_CLOCK_2_OTH5
filter = EXP_CLOCK_2_TIMER1.SETVALUE[DAT_VALUE_READ] ;
EXP_TRG_SIGNAL_OTH1
filter = EXP_TRG_SIGNAL_DPORT.SETVALUE[DAT_VALUE_READ] ;
EXP_TRG_SIGNAL_OTH2
filter = EXP_TRG_SIGNAL_APORT.SETVALUE[DAT_VALUE_READ] ;
EXP_TRG_SIGNAL_OTH3
filter = EXP_TRG_SIGNAL_TIMER2.SETVALUE[DAT_VALUE_READ] ;
EXP_TRG_SIGNAL_2_OTH0
filter = EXP_TRG_SIGNAL_2_DPORT.SETVALUE[DAT_VALUE_READ] ;
EXP_TRG_SIGNAL_2_OTH1
filter = EXP_TRG_SIGNAL_2_APORT.SETVALUE[DAT_VALUE_READ] ;
EXP_TRG_SIGNAL_2_OTH2
filter = EXP_TRG_SIGNAL_2_TIMER1.SETVALUE[DAT_VALUE_READ] ;
EXP_MD_EXT_OTH0
filter = EXP_TRG_SIGNAL_DPORT.SETVALUE[DAT_VALUE_READ] ;
EXP_MD_EXT_OTH1
filter = EXP_TRG_SIGNAL_APORT.SETVALUE[DAT_VALUE_READ] ;
EXP_MD_EXT_OTH2
filter = EXP_TRG_SIGNAL_TIMER2.SETVALUE[DAT_VALUE_READ] ;
EXP_MD_EXT_2_OTH0
filter = EXP_TRG_SIGNAL_2_DPORT.SETVALUE[DAT_VALUE_READ] ;
EXP_MD_EXT_2_OTH1
filter = EXP_TRG_SIGNAL_2_APORT.SETVALUE[DAT_VALUE_READ] ;
EXP_MD_EXT_2_OTH2
filter = EXP_TRG_SIGNAL_2_TIMER1.SETVALUE[DAT_VALUE_READ] ;
PCK_EXT_SIGNAL_CUSTOM
filter = 0 ;
PCK_EXT_SIGNAL_OTH0
filter = 0 ;
PCK_IN_CONT
filter = 0 ;
CLK_OUT_SELECT_USER
filter = 0 ;
CLK_OUT_SELECT_EXT
filter = 0 ;
CLK_OUT_SELECT_EXP1
filter = 0 ;
CLK_OUT_SELECT_EXP2
filter = 0 ;
EXP_COMBINE_1_NONE
filter = 0 ;
EXP_COMBINE_1_OTH0
filter = EXP_COMBINE_XOR.SETVALUE[DAT_VALUE_READ] ;
EXP_COMBINE_1_OTH1
filter = EXP_COMBINE_AND.SETVALUE[DAT_VALUE_READ] ;
EXP_COMBINE_1_OTH2
filter = EXP_COMBINE_OR.SETVALUE[DAT_VALUE_READ] ;
EXP_COMBINE_2_NONE
filter = 0 ;
EXP_COMBINE_2_OTH0
filter = EXP_COMBINE_2_XOR.SETVALUE[DAT_VALUE_READ] ;
EXP_COMBINE_2_OTH1
filter = EXP_COMBINE_2_AND.SETVALUE[DAT_VALUE_READ] ;
EXP_COMBINE_2_OTH2
filter = EXP_COMBINE_2_OR.SETVALUE[DAT_VALUE_READ] ;
USR_IN_ENABLE_OTH0
filter = USR_IENABLE.SETVALUE[DAT_VALUE_READ] ;
USR_OUT_ENABLE_OTH0
filter = USR_OENABLE.SETVALUE[DAT_VALUE_READ] ;
GRB_HWTRG_OTH0
filter = GRB_TRG_SIGNAL_DPORT.SETVALUE[DAT_VALUE_READ] ;
GRB_HWTRG_OTH1
filter = GRB_TRG_SIGNAL_APORT.SETVALUE[DAT_VALUE_READ] ;
GRB_HWTRG_OTH4
filter = GRB_TRG_SIGNAL_TIMER1.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD5
filter = VDC_VID_WIDTH_10.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD6
filter = VDC_VID_WIDTH_12.SETVALUE[DAT_VALUE_READ] ;
VDC_D_WD6
filter = VDC_VID_WIDTH_14.SETVALUE[DAT_VALUE_READ] ;
[COMMON_OPTIONS]
CT_LINE_SCAN_AVAIL yes
CT_FRAM_SCAN_AVAIL yes
ANA_VID_AVAIL yes
MONO_VID_AVAIL array 1 1
C_COL_VID_AVAIL array 0 0
RGB_COL_VID_AVAIL array 1 1
RGB_PACK_VID_AVAIL array 0 1
RGB_ALPHA_VID_AVAIL array 1 1
SVID_AVAIL array 0 0
YUVVID_AVAIL array 0 0
VID_STD_RS170_PCLK 12272700
VID_STD_RS170_HORZ array 58 58 24 640
VID_STD_RS170_VERT array 6 31 8 480
VID_STD_CCIR_PCLK 14750000
VID_STD_CCIR_HORZ array 69 85 22 768
VID_STD_CCIR_VERT array 5 39 5 576
VID_8BITS array 1 1
VID_16BITS array 0 1
VID_24BITS array 0 1
VID_32BITS array 0 1
VID_64BITS array 0 0
VDC_VID_WIDTH_10_AV equ
value = VDC_MONO ;
VDC_VID_WIDTH_12_AV equ
value = VDC_MONO & VDC_DIG ;
VDC_VID_WIDTH_14_AV equ
value = VDC_MONO & VDC_DIG ;
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL no
YUV_INPUT_AVAIL no
CHROMI_IN_AVAIL no
MONO_DIG_INPUT_AVAIL array 0 1 2 3
RGB_DIG_INPUT_AVAIL array 0
DIG_VID_TTL no
HIGH_SPEED_GRAB yes
SYC_ANA_IN_CH_AV array 1 1 1 1
RS_330_SUPPORTED no
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 0
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCLK_FREQ_LIMIT array 1000 20000000 20000000 140000000
PLL_FREQ_LIMIT array 4000000 140000000
PCK_FRQ_LM_SP_MONO array 500000 140000000 1000 45000000
PCK_FRQ_LM_SP_CCOL array 500000 45000000 1000 45000000
PCK_FRQ_LM_SP_RGB array 500000 45000000 1000 45000000
PCK_FRQLIM_ON_RGB_ALPHA array 500000 45000000 1000 45000000
PCK_FRQLIM_ON_RGB_PACK array 500000 45000000 1000 45000000
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_OUTPUT_DIVD_AV yes
PCK_OMAX_DIV_FACT 8
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV yes
PCK_CAM_RG_OMAX_DIVF 8
PCLK_OUT_HFREQ_AV yes
PCLK_OUT_HF_MAX_MULF 8
PCLK_OUT_HF_MAXVAL 120000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 1 1
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV yes
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV yes
VACTIVE_INTERL_EVEN no
VDT_HORIZ_MAX_VAL 0xfff0
VDT_VERT_MAX_VAL 0xfff0
VDT_HSY_CNT_MIN 0
VDT_HBP_CNT_MIN 0
VDT_HACT_CNT_MIN 0
VDT_HFP_CNT_MIN 0
VDT_HSY+HBP_CNT_MIN 0
VDT_VSY_CNT_MIN 0
VDT_VBP_CNT_MIN 0
VDT_VACT_CNT_MIN 0
VDT_VFP_CNT_MIN 0
VDT_VSY+VBP_CNT_MIN 0
VACT_MULTV_ON_DIG 1
VACT_MULTV_ON_MONO array 1 1
VACT_MULTV_ON_MONOHI array 1 1
HACT_MULTV_ON_DIG 1
HACT_MULTV_ON_MONO array 1 1
HACT_MULTV_ON_MONOHI array 1 1
VTOT_ARR_ON_MONO no
VTOT_ARR_ON_CCOL no
VTOT_ARR_ON_RGB no
VTOT_ARR_ON_SVID no
VTOT_ARR_ON_YUV no
VTOT_ARR_ON_MONOHI no
VDT_SERRATION_AVAIL no
VDT_EQUALIZAT_AVAIL no
CLAMP_SYNC_AVAIL yes
CLAMP_BPORCH_AVAIL yes
CLAMP_FPORCH_AVAIL yes
CLAMP_TIMING_MIN array 250 750 275
SYC_REC&GEN_BY_CAM no
SYC_ANAL_O_DIGVID_AV yes
SYC_HS&VS_MUST_SDIR yes
SYC_HS&CS_MUST_SDIR yes
SYC_VS&CS_MUST_SDIR yes
SYC_HSY_MAY_I&O no
SYC_VSY_MAY_I&O no
SYC_CSY_MAY_I&O no
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
SYC_DIG_C_IN_AV yes
SYC_DIG_C_OUT_AV yes
SYC_HVC_SAME_FORMAT yes
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
SYC_CAM_LATMAX_HTF 100
SYC_DIG_ON_MONO_AV yes
SYC_DIG_ON_MONOHI_AV yes
SYC_ASEP_O_MONO_AV yes
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
CSYN_IN_TTL_AV yes
CSYN_IN_RS422_AV yes
CSYN_OUT_TTL_AV yes
CSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
CSYN_IN_POS_POL_AV yes
CSYN_IN_NEG_POL_AV yes
CSYN_OUT_NEG_POL_AV yes
CSYN_OUT_POS_POL_AV yes
ANA_VID_AMPL_LIMIT array 0 700
ANA_VID_GAIN_AVAIL array 350 470 700 980 1400
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV yes
GRAB_NXT_EXPCKDV_AV yes
GRAB_IMM_EXPCKDV_AV yes
GRAB_ISK_EXPCKDV_AV yes
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
EXP_ASY_CLK_AV yes
EXP_ASY_CLK_FREQ equ
value = ( DEF_MASTER * DEF_PCK_FREQ ) ||
( ( PCK_ODIVF != 0 ) * ( PCK_OFREQDV ) ) ||
( EXP_ASY_CLK * EXP_CLK_FREQ ) ||
10000000 ;
EXP_SYN_CLK_MAX_FREQ 50000000
EXP_CLK_DVED_AV no
EXP_CLK_MAXDIV_FACT 1
EXP_DELYED_FR_TRG_AV yes
EXP_TIMER_MAX_VALUE 0xfffd
EXP_TIMER_MIN_VALUE 8
EXP_CHK_MAXSUM_PERD yes
EXP_CHK_MAXSUM_DEL yes
EXP_CHK_MAXSUM_NDEL yes
EXP_NDEL_TRG_TTL_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_TTL_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_TTL_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_TTL_AV yes
EXP_DEL_OUT_422_AV yes
EXP_MD_PERD_AV yes
EXP_PERD_CLKDVED_AV yes
EXP_DEL_CLKDVED_AV yes
EXP_NDEL_CLKDVED_AV yes
EXP_TEX_CLKDVED_AV yes
EXP_THSY_CLKDVED_AV yes
EXP_TVSY_CLKDVED_AV yes
EXP_TSW_CLKDVED_AV yes
EXP_ASY_CLK_AV_2 yes
EXP_ASY_CLK_FREQ_2 equ
value = ( DEF_MASTER * DEF_PCK_FREQ ) ||
( ( PCK_ODIVF != 0 ) * ( PCK_OFREQDV ) ) ||
( EXP_ASY_CLK * EXP_CLK_FREQ ) ||
( EXP_ASY_CLK_2 * EXP_CLK_FREQ_2 ) ||
10000000 ;
EXP_SYN_CLK_MAX_FREQ_2 30000000
EXP_CLK_DVED_AV_2 no
EXP_CLK_MAXDIV_FACT_2 1
EXP_DELYED_FR_TRG_AV_2 yes
EXP_TIMER_MAX_VALUE_2 0xfffd
EXP_TIMER_MIN_VALUE_2 8
EXP_CHK_MAXSUM_PERD_2 yes
EXP_CHK_MAXSUM_DEL_2 yes
EXP_CHK_MAXSUM_NDEL_2 yes
EXP_NDEL_TRG_TTL_AV_2 yes
EXP_NDEL_TRG_422_AV_2 yes
EXP_DEL_TRG_TTL_AV_2 yes
EXP_DEL_TRG_422_AV_2 yes
EXP_NDEL_OUT_TTL_AV_2 yes
EXP_NDEL_OUT_422_AV_2 yes
EXP_DEL_OUT_TTL_AV_2 yes
EXP_DEL_OUT_422_AV_2 yes
EXP_MD_PERD_AV_2 yes
EXP_TRG_ON_EXT_AV_2 no
EXP_PERD_CLKDVED_AV_2 yes
EXP_DEL_CLKDVED_AV_2 yes
EXP_NDEL_CLKDVED_AV_2 yes
EXP_TEX_CLKDVED_AV_2 yes
EXP_THSY_CLKDVED_AV_2 yes
EXP_TVSY_CLKDVED_AV_2 yes
EXP_TSW_CLKDVED_AV_2 yes
EXP_CLOCK_HSYNC_AV equ
value = VDT_HSYNC_FREQ ;
EXP_CLOCK_VSYNC_AV equ
value = VDT_VSYNC_FREQ ;
EXP_CLOCK_DITRIG_AV equ
value = ( EXP_CLOCK_DITRIG * EXP_CLK_FREQ ) || 1 ;
EXP_CLOCK_VTRIG_AV equ
value = ( EXP_CLOCK_VTRIG * EXP_CLK_FREQ ) || 1 ;
EXP_CLOCK_CRYSTAL_AV equ
value = DEF_GRBSYSCLK ;
EXP_CLOCK_TIMER2_AV equ
value = ( EXP_CLOCK_TIMER2 * EXP_CLK_FREQ ) || 1 ;
EXP_CLOCK_2_HSYNC_AV equ
value = VDT_HSYNC_FREQ ;
EXP_CLOCK_2_VSYNC_AV equ
value = VDT_VSYNC_FREQ ;
EXP_CLOCK_2_DITRIG_AV equ
value = ( EXP_CLOCK_2_DITRIG * EXP_CLK_FREQ ) || 1 ;
EXP_CLOCK_2_VTRIG_AV equ
value = ( EXP_CLOCK_2_VTRIG * EXP_CLK_FREQ ) || 1 ;
EXP_CLOCK_2_CRYSTAL_AV equ
value = DEF_GRBSYSCLK ;
EXP_CLOCK_2_TIMER1_AV equ
value = ( EXP_CLOCK_2_TIMER1 * EXP_CLK_FREQ ) || 1 ;
HACT_MULTV_ON_CCOL 1 1
HACT_MULTV_ON_RGB 1 1 1 1 1 1
HACT_MULTV_ON_SVID 1 1
HACT_MULTV_ON_YUV 1 1
VACT_MULTV_ON_CCOL 1 1
VACT_MULTV_ON_RGB 1 1 1 1 1 1
VACT_MULTV_ON_SVID 1 1
VACT_MULTV_ON_YUV 1 1
SYC_DIG_ON_CCOL_AV no
SYC_DIG_ON_RGB_AV yes
SYC_DIG_ON_SVID_AV no
SYC_DIG_ON_YUV_AV no
EXP_MD_WITH_TRG_AV yes
EXP_MD_WITH_TRG_AV_2 yes
EXP_TRG_ON_EXT_AV no
EXP_TRG_ON_HSY_AV yes
EXP_TRG_ON_VSY_AV yes
EXP_TRG_ON_SW_AV yes
EXP_TRG_ON_HSY_AV_2 yes
EXP_TRG_ON_VSY_AV_2 yes
EXP_TRG_ON_SW_AV_2 yes
EXP_NDEL_TRG_PPOL_AV yes
EXP_NDEL_TRG_NPOL_AV yes
EXP_DEL_TRG_PPOL_AV yes
EXP_DEL_TRG_NPOL_AV yes
EXP_NDEL_OUT_PPOL_AV yes
EXP_NDEL_OUT_NPOL_AV yes
EXP_DEL_OUT_PPOL_AV yes
EXP_DEL_OUT_NPOL_AV yes
EXP_NDEL_TRG_PPOL_AV_2 yes
EXP_NDEL_TRG_NPOL_AV_2 yes
EXP_DEL_TRG_PPOL_AV_2 yes
EXP_DEL_TRG_NPOL_AV_2 yes
EXP_NDEL_OUT_PPOL_AV_2 yes
EXP_NDEL_OUT_NPOL_AV_2 yes
EXP_DEL_OUT_PPOL_AV_2 yes
EXP_DEL_OUT_NPOL_AV_2 yes
GRAB_ON_TRG_EVNT yes
GRAB_HW_TRG_POS_AV yes
GRAB_HW_TRG_NEG_AV yes
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
CT_MAX_TAPS array 4 1 1 1 1 0
CT_MAX_CAMERA array 4 1 1 1 1 0
CT_MAX_CONNECTORS array 4 4
CAMERA_LINK_AV no
CL_CONFIG_BASE_AV no
CL_CONFIG_MEDIUM_AV no
CL_CONFIG_FULL_AV no
CLC_MODE_BASE equ
value = ( CLC_MODE == 0 ) ;
CLC_MODE_MEDIUM equ
value = ( CLC_MODE == 1 ) ;
CL_CHANNEL0_AV no
CL_CHANNEL1_AV no
CL_CC1_DISABLE_AV no
CL_CC1_TIMER_1_AV no
CL_CC1_TIMER_2_AV no
CL_CC1_USROUT_0_AV no
CL_CC1_USROUT_1_AV no
CL_CC2_DISABLE_AV no
CL_CC2_TIMER_1_AV no
CL_CC2_TIMER_2_AV no
CL_CC2_USROUT_0_AV no
CL_CC2_USROUT_1_AV no
CL_CC3_DISABLE_AV no
CL_CC3_TIMER_1_AV no
CL_CC3_TIMER_2_AV no
CL_CC3_USROUT_0_AV no
CL_CC3_USROUT_1_AV no
CL_CC4_DISABLE_AV no
CL_CC4_TIMER_1_AV no
CL_CC4_TIMER_2_AV no
CL_CC4_USROUT_0_AV no
CL_CC4_USROUT_1_AV no
[OPTION]
GENESIS
DIG_VID_422 no
DIG_VID_AVAIL no
[OPTION1]
GENESIS/DIG/MOD
DIG_VID_422 yes
DIG_VID_AVAIL yes
[OPTION2]
GENESIS/GRABPORT
DIG_VID_AVAIL yes
DIG_VID_TTL yes
DIG_VID_422 no
ANA_VID_AVAIL no
USR_IENABLE_AV no
PCK_IN_DELAY_AV no
PCK_INT_DIVD_AV no
PCK_OUTPUT_DIVD_AV no
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_OUTDIV_AV no
PCLK_OUT_HFREQ_AV no
PCLK_OUT_AV_O_MONO array 0 0
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 0 0
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 0 0
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
PCLK_OUT_POS_POL_AV no
PCLK_OUT_NEG_POL_AV no
SYC_REC&GEN_BY_CAM no
SYC_ANAL_O_DIGVID_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_OUT_AV no
SYC_DIG_C_IN_AV no
SYC_DIG_C_OUT_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
CSYN_OUT_TTL_AV no
CSYN_OUT_RS422_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
CSYN_OUT_NEG_POL_AV no
CSYN_OUT_POS_POL_AV no
GRAB_ON_SW_TRG_AV no
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
EXP_ASY_CLK_AV no
EXP_DELYED_FR_TRG_AV no
EXP_TIMER_MAX_VALUE 0
EXP_TIMER_MIN_VALUE 0
EXP_DEL_TRG_422_AV no
EXP_MD_PERD_AV no
EXP_TIMER_MAX_VALUE_2 0
EXP_TIMER_MIN_VALUE_2 0
EXP_MD_PERD_AV_2 no
SYC_DIG_ON_CCOL_AV no
SYC_DIG_ON_RGB_AV yes
SYC_DIG_ON_SVID_AV no
SYC_DIG_ON_YUV_AV no
EXP_MD_WITH_TRG_AV no
EXP_MD_WITH_TRG_AV_2 no
GRAB_ON_TRG_EVNT no
GRAB_HW_TRG_POS_AV yes
GRAB_HW_TRG_NEG_AV yes
[OPTION3]
GENESIS/GRABPORT/DIG
DIG_VID_AVAIL yes
DIG_VID_422 yes
DIG_VID_TTL yes
ANA_VID_AVAIL no
USR_IENABLE_AV no
PCK_IN_DELAY_AV no
PCK_INT_DIVD_AV no
PCK_OUTPUT_DIVD_AV no
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_OUTDIV_AV no
PCLK_OUT_HFREQ_AV no
PCLK_OUT_AV_O_MONO array 0 0
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 0 0
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 0 0
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
PCLK_OUT_POS_POL_AV no
PCLK_OUT_NEG_POL_AV no
SYC_REC&GEN_BY_CAM no
SYC_ANAL_O_DIGVID_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_OUT_AV no
SYC_DIG_C_IN_AV no
SYC_DIG_C_OUT_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
CSYN_OUT_TTL_AV no
CSYN_OUT_RS422_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
CSYN_OUT_NEG_POL_AV no
CSYN_OUT_POS_POL_AV no
GRAB_ON_SW_TRG_AV no
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
GRB_TRG_SIGNAL_TIMER2_AV no
EXP_ASY_CLK_AV no
EXP_DELYED_FR_TRG_AV no
EXP_TIMER_MAX_VALUE 0
EXP_TIMER_MIN_VALUE 0
EXP_DEL_TRG_422_AV no
EXP_MD_PERD_AV no
EXP_TIMER_MAX_VALUE_2 0
EXP_TIMER_MIN_VALUE_2 0
EXP_MD_PERD_AV_2 no
SYC_DIG_ON_CCOL_AV no
SYC_DIG_ON_RGB_AV yes
SYC_DIG_ON_SVID_AV no
SYC_DIG_ON_YUV_AV no
EXP_MD_WITH_TRG_AV no
EXP_MD_WITH_TRG_AV_2 no
GRAB_ON_TRG_EVNT no
GRAB_HW_TRG_POS_AV yes
GRAB_HW_TRG_NEG_AV yes
[OPTION4]
METEOR-II/DIG
DIG_VID_AVAIL yes
DIG_VID_422 yes
DIG_VID_TTL no
ANA_VID_AVAIL no
PCLK_FREQ_LIMIT array 1000 20000000 20000000 40000000
SYC_ANAL_O_DIGVID_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
PCLK_IN_TTL_AV no
PCLK_OUT_TTL_AV no
HSYN_IN_TTL_AV no
HSYN_OUT_TTL_AV no
VSYN_IN_TTL_AV no
VSYN_OUT_TTL_AV no
CSYN_IN_TTL_AV no
CSYN_OUT_TTL_AV no
[OPTION5]
METEOR-II/DIG/JPEG
DIG_VID_AVAIL yes
DIG_VID_422 yes
DIG_VID_TTL no
ANA_VID_AVAIL no
PCLK_FREQ_LIMIT array 1000 20000000 20000000 40000000
SYC_ANAL_O_DIGVID_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
PCLK_IN_TTL_AV no
PCLK_OUT_TTL_AV no
HSYN_IN_TTL_AV no
HSYN_OUT_TTL_AV no
VSYN_IN_TTL_AV no
VSYN_OUT_TTL_AV no
CSYN_IN_TTL_AV no
CSYN_OUT_TTL_AV no
[OPTION6]
METEOR-II/CL
DIG_VID_AVAIL yes
DIG_VID_422 yes
DIG_VID_TTL no
ANA_VID_AVAIL no
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 0
PCK_IN_DELAY_MAXVAL 3
PCK_IN_DELAY_STEP 3
PCLK_FREQ_LIMIT array 1000 50000000 1000 50000000
PCK_FRQ_LM_SP_MONO array 500000 50000000 1000 50000000
PCK_FRQ_LM_SP_RGB array 500000 50000000 1000 50000000
PCK_FRQLIM_ON_RGB_ALPHA array 500000 50000000 1000 50000000
PCK_FRQLIM_ON_RGB_PACK array 500000 50000000 1000 50000000
SYC_ANAL_O_DIGVID_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_DIG_C_IN_AV no
SYC_DIG_C_OUT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
PCLK_IN_TTL_AV no
PCLK_OUT_TTL_AV no
HSYN_IN_TTL_AV no
HSYN_OUT_TTL_AV no
VSYN_IN_TTL_AV no
VSYN_OUT_TTL_AV no
CSYN_IN_TTL_AV no
CSYN_OUT_TTL_AV no
CT_MAX_TAPS array 4 0 1 1 1 0
CT_MAX_CAMERA array 4 0 1 1 1 0
CAMERA_LINK_AV yes
CL_CONFIG_BASE_AV yes
CL_CONFIG_MEDIUM_AV yes
CL_CHANNEL0_AV yes
CL_CHANNEL1_AV yes
CL_CC1_TIMER_1_AV yes
CL_CC1_TIMER_2_AV yes
CL_CC1_USROUT_0_AV yes
CL_CC1_USROUT_1_AV yes
CL_CC2_TIMER_1_AV yes
CL_CC2_TIMER_2_AV yes
CL_CC2_USROUT_0_AV yes
CL_CC2_USROUT_1_AV yes
CL_CC3_TIMER_1_AV yes
CL_CC3_TIMER_2_AV yes
CL_CC3_USROUT_0_AV yes
CL_CC3_USROUT_1_AV yes
CL_CC4_TIMER_1_AV yes
CL_CC4_TIMER_2_AV yes
CL_CC4_USROUT_0_AV yes
CL_CC4_USROUT_1_AV yes
[DEFINE_VALUE]
DEF_VAL0
value = ( ( VDC_MONO * SYC_ANA ) | SYC_DIG ) ;
DEF_MASTER
value = SYC_DIG & SYC_H_OUT & ( ! ( SYC_ANA | ( SYC_DIG &
( SYC_H_IN | SYC_C_IN ) ) ) ) ;
DEF_VAL5
value = ( ( ! PCK_CAM_XCHG ) & SYC_CAM_GEN & DEF_VAL0 ) ;
DEF_CLAMP_MARGIN
value = ( VDT_CLP_BPO * ( ( DEF_HBPORCH <= 16 ) ? ( ( DEF_HBPORCH <= 10 ) ? 0 : 5 ) : 8 ) ) ||
( VDT_CLP_FPO * ( ( DEF_HFPORCH <= 16 ) ? ( ( DEF_HFPORCH <= 10 ) ? 0 : 5 ) : 8 ) ) ||
( VDT_CLP_SYN * ( ( DEF_HSYNC <= 16 ) ? ( ( DEF_HSYNC <= 10 ) ? 0 : 5 ) : 8 ) ) ;
DEF_TAP_VALID
value = ( ( CT_TAPS == 0 ) & ( TAP_CONFIG == 1 ) & ( GVDC_VID_WIDTH <= 32 ) &
( CT_CAMERA <= 3 ) ) |
( ( CT_TAPS == 1 ) & ( ( TAP_CONFIG == 3 ) | ( TAP_CONFIG == 17 ) |
( TAP_CONFIG == 129 ) | ( TAP_CONFIG == 1025 ) ) & ( GVDC_VID_WIDTH <= 16 ) &
( CT_CAMERA <= 1 ) ) |
( ( CT_TAPS == 2 ) & ( ( TAP_CONFIG == 15 ) | ( TAP_CONFIG == 85 ) |
( TAP_CONFIG == 897 ) | ( TAP_CONFIG == 9473 ) | ( TAP_CONFIG == 51 ) |
( TAP_CONFIG == 3075 ) | ( TAP_CONFIG == 5137 ) ) & ( GVDC_VID_WIDTH <= 8 ) &
( CT_CAMERA == 0 ) ) ;
DEF_TIMER1_ENABLE
value = ( EXP_MD_PERD | EXP_MD_W_TRG ) ;
DEF_TIMER2_ENABLE
value = ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) ;
DEF_XTAPS
value = ( 1 + ( ( TAP_CONFIG == 17 ) | ( TAP_CONFIG == 51 ) | ( TAP_CONFIG == 5137 ) ) + ( ( TAP_CONFIG == 85 ) * 3 ) ) *
( 1 + ( ( TAP_CONFIG == 3 ) | ( TAP_CONFIG == 51 ) | ( TAP_CONFIG == 3075 ) ) + ( ( TAP_CONFIG == 15 ) * 3 ) ) ;
DEF_YTAPS
value = ( 1 + ( ( TAP_CONFIG == 1025 ) | ( TAP_CONFIG == 3075 ) | ( TAP_CONFIG == 5137 ) ) + ( ( TAP_CONFIG == 9473 ) * 3 ) ) *
( 1 + ( TAP_CONFIG == 129 ) + ( ( TAP_CONFIG == 897 ) * 3 ) ) ;
DEF_CASE_1
value = ( VDC_ANA & ( SYC_ANA | ( SYC_DIG & ( SYC_H_IN | SYC_C_IN ) ) ) & ( ! PCK_CAM_GEN ) & ( GRB_MD_CONT | GRB_ACT_NXT_FRM ) ) ;
DEF_CASE_2
value = VDC_ANA & PCK_CAM_GEN & SYC_DIG & ( SYC_H_IN | SYC_C_IN ) & ( GRB_MD_CONT | GRB_ACT_NXT_FRM ) ;
DEF_CASE_3
value = ( VDC_ANA & DEF_MASTER ) ;
DEF_CASE_4
value = VDC_DIG & SYC_DIG & SYC_H_IN ;
DEF_CASE_5
value = VDC_DIG & DEF_MASTER ;
DEF_CASE_6
value = ( VDC_ANA & ( SYC_ANA | ( SYC_DIG & SYC_H_IN ) ) & ( ! ( GRB_MD_CONT | GRB_ACT_NXT_FRM ) ) ) ;
DEF_FRAMESCAN
value = CT_FS & GRB_MD_HW_TRG & ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) ;
DEF_LATENCY_FPORCH
value = ( DEF_CASE_3 * ( ( SYC_CAM_LATENCY + 7 ) > VDT_HFPORCH ) ) ||
( DEF_CASE_5 * ( SYC_CAM_LATENCY > VDT_HFPORCH ) ) ;
DEF_NON_CONT_VIDEO
value = ( ! GRB_MD_CONT ) & ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) ;
DEF_GRBSYSCLK
value = 28636000 ;
DEF_NTSC
value = VDT_STD_NTSC & VDC_C_COLOR ;
DEF_DMODE
value =
( ( VDC_ANA & VDC_WD8 & ( 35000000 <= PCK_FREQ ) & ( PCK_FREQ < 70000000 ) ) * 2 ) +
( ( VDC_ANA & VDC_WD8 & ( 70000000 <= PCK_FREQ ) & ( PCK_FREQ < 140000000 ) ) * 4 ) +
( ( VDC_ANA & VDC_VID_WIDTH_10 ) * 6 ) +
( ( ( VDC_ANA & ( VDC_WD8 & ( ( 1000 <= PCK_FREQ ) & ( PCK_FREQ < 35000000 ) ) ) )
| ( VDC_DIG | ( VDC_RGB_COL | VDC_RGB_ALPHA ) ) ) * 1 ) ;
DEF_HTOTAL
value = ( VDT_HTOTAL / ( DEF_DMODE % 5 ) ) ;
DEF_HSYNC
value = ( VDT_HSYNC / ( DEF_DMODE % 5 ) ) ;
DEF_HFPORCH
value = ( VDT_HFPORCH / ( DEF_DMODE % 5 ) ) ;
DEF_HBPORCH
value = ( VDT_HBPORCH / ( DEF_DMODE % 5 ) ) ;
DEF_HACTIVE
value = ( VDT_HACTIVE / ( DEF_DMODE % 5 ) ) ;
DEF_PCK_FREQ
value = ( PCK_FREQ / ( DEF_DMODE % 5 ) ) ;
DEF_VIAHMULTIPLY
value = 1 + ( TAP_CONFIG == 3 ) + ( TAP_CONFIG == 51 ) + ( TAP_CONFIG == 3075 ) + ( ( TAP_CONFIG == 15 ) * 3 ) ;
DEF_GRABPORT_ACTIVE
value = ! ANA_VID_AVAIL ;
DEF_DELAY_TIMER1
value = EXP_OUT_T0 < 6 ? 6 : EXP_OUT_T0;
DEF_DELAY_TIMER2
value = EXP_OUT_T0_2 < 6 ? 6 : EXP_OUT_T0_2;
DEF_CL_MODE_CH0
value = CAMERA_LINK_AV * (
( ( CLC_MODE == 0 ) * ( CL_CHANNEL0_AV * CLC_MODE_CH0 ) ) +
( ( CLC_MODE == 1 ) * ( CL_CHANNEL0_AV * CLC_MODE_CH0 ) ) +
( ( CLC_MODE == 2 ) * ( CL_CHANNEL0_AV * 0 ) ) ) ;
DEF_CL_MODE_CH1
value = CAMERA_LINK_AV * (
( ( CLC_MODE == 0 ) * ( CL_CHANNEL1_AV * CLC_MODE_CH1 ) ) +
( ( CLC_MODE == 1 ) * ( CL_CHANNEL0_AV * CLC_MODE_CH0 ) ) +
( ( CLC_MODE == 2 ) * ( CL_CHANNEL0_AV * 0 ) ) ) ;
DEF_CL_TAPS
value = CAMERA_LINK_AV * (
( ( CLC_MODE == 0 ) * (
( ( ( CLC_ACTIVE_CH0 == 1 ) & ( CLC_ACTIVE_CH1 == 0 ) ) * (
( ( ( DEF_CL_MODE_CH0 == 0 ) | ( DEF_CL_MODE_CH0 == 1 ) ) * 1 ) +
( ( ( DEF_CL_MODE_CH0 == 2 ) | ( DEF_CL_MODE_CH0 == 3 ) ) * 2 ) +
( ( DEF_CL_MODE_CH0 == 4 ) * 3 ) ) ) +
( ( ( CLC_ACTIVE_CH0 == 0 ) & ( CLC_ACTIVE_CH1 == 1 ) ) * (
( ( ( DEF_CL_MODE_CH1 == 0 ) | ( DEF_CL_MODE_CH1 == 1 ) ) * 1 ) +
( ( ( DEF_CL_MODE_CH1 == 2 ) | ( DEF_CL_MODE_CH1 == 3 ) ) * 2 ) +
( ( DEF_CL_MODE_CH1 == 4 ) * 3 ) ) ) +
( ( ( CLC_ACTIVE_CH0 == 1 ) & ( CLC_ACTIVE_CH1 == 1 ) ) * (
( ( ( ( DEF_CL_MODE_CH0 == 0 ) & ( DEF_CL_MODE_CH1 == 0 ) ) |
( ( DEF_CL_MODE_CH0 == 1 ) & ( DEF_CL_MODE_CH1 == 1 ) ) ) * 2 ) +
( ( ( ( DEF_CL_MODE_CH0 == 0 ) & ( DEF_CL_MODE_CH1 == 2 ) ) |
( ( DEF_CL_MODE_CH0 == 2 ) & ( DEF_CL_MODE_CH1 == 0 ) ) ) * 3 ) +
( ( ( ( DEF_CL_MODE_CH0 == 0 ) & ( DEF_CL_MODE_CH1 == 4 ) ) |
( ( DEF_CL_MODE_CH0 == 2 ) & ( DEF_CL_MODE_CH1 == 2 ) ) |
( ( DEF_CL_MODE_CH0 == 4 ) & ( DEF_CL_MODE_CH1 == 0 ) ) ) * 4 ) ) ) ) ) +
( ( CLC_MODE == 1 ) *
( ( CLC_ACTIVE_CH0 == 1 ) * (
( ( ( DEF_CL_MODE_CH0 == 5 ) | ( DEF_CL_MODE_CH0 == 6 ) | ( DEF_CL_MODE_CH0 == 7 ) ) * 2 ) +
( ( DEF_CL_MODE_CH0 == 8 ) | ( DEF_CL_MODE_CH0 == 9 ) * 4 ) ) ) ) ) ;
DEF_CL_BITS
value = CAMERA_LINK_AV * (
( ( CLC_MODE == 0 ) * (
( ( ( CLC_ACTIVE_CH0 == 1 ) & ( CLC_ACTIVE_CH1 == 0 ) ) * (
( ( ( DEF_CL_MODE_CH0 == 0 ) | ( DEF_CL_MODE_CH0 == 2 ) | ( DEF_CL_MODE_CH0 == 4 ) ) * 8 ) +
( ( DEF_CL_MODE_CH0 == 3 ) * 12 ) +
( ( DEF_CL_MODE_CH0 == 1 ) * 16 ) ) ) +
( ( ( CLC_ACTIVE_CH0 == 0 ) & ( CLC_ACTIVE_CH1 == 1 ) ) * (
( ( ( DEF_CL_MODE_CH1 == 0 ) | ( DEF_CL_MODE_CH1 == 2 ) | ( DEF_CL_MODE_CH1 == 4 ) ) * 8 ) +
( ( DEF_CL_MODE_CH1 == 3 ) * 12 ) +
( ( DEF_CL_MODE_CH1 == 1 ) * 16 ) ) ) +
( ( ( CLC_ACTIVE_CH0 == 1 ) & ( CLC_ACTIVE_CH1 == 1 ) ) * (
( ( ( ( DEF_CL_MODE_CH0 == 0 ) & ( DEF_CL_MODE_CH1 == 0 ) ) |
( ( DEF_CL_MODE_CH0 == 0 ) & ( DEF_CL_MODE_CH1 == 2 ) ) |
( ( DEF_CL_MODE_CH0 == 0 ) & ( DEF_CL_MODE_CH1 == 4 ) ) |
( ( DEF_CL_MODE_CH0 == 2 ) & ( DEF_CL_MODE_CH1 == 0 ) ) |
( ( DEF_CL_MODE_CH0 == 2 ) & ( DEF_CL_MODE_CH1 == 2 ) ) |
( ( DEF_CL_MODE_CH0 == 4 ) & ( DEF_CL_MODE_CH1 == 0 ) ) ) * 8 ) +
( ( ( DEF_CL_MODE_CH0 == 1 ) & ( DEF_CL_MODE_CH1 == 1 ) ) * 16 ) ) ) ) ) +
( ( CLC_MODE == 1 ) *
( ( CLC_ACTIVE_CH0 == 1 ) * (
( ( DEF_CL_MODE_CH0 == 5 ) | ( DEF_CL_MODE_CH0 == 8 ) | ( DEF_CL_MODE_CH0 == 9 ) * 8 ) +
( ( DEF_CL_MODE_CH0 == 6 ) | ( DEF_CL_MODE_CH0 == 7 ) * 16 ) ) ) ) ) ;
DEF_CL_BUS_TAPS
value = CAMERA_LINK_AV *
(
( ( ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) & ( VDC_MONO | VDC_C_COLOR ) ) *
( GVDC_VID_WIDTH > 16 ? ( GVDC_VID_WIDTH / 8 ) : ( VDC_IN_CH0 + VDC_IN_CH1 + VDC_IN_CH2 + VDC_IN_CH3 ) ) ) +
( VDC_RGB_COL * 3 ) +
( VDC_RGB_PACK * 3 ) +
( VDC_RGB_ALPHA * 4 ) +
( ( ( CT_CAMERA == 0 ) & ( CT_TAPS == 1 ) & ( VDC_MONO | VDC_C_COLOR ) ) * ( ( VDC_IN_CH0 * 2 ) + ( VDC_IN_CH2 * 2 ) ) ) +
( ( ( CT_CAMERA == 0 ) & ( CT_TAPS == 2 ) & ( VDC_MONO | VDC_C_COLOR ) ) * 4 ) +
( ( ( CT_CAMERA == 1 ) & ( CT_TAPS == 1 ) ) * 4 ) +
( ( ( CT_CAMERA == 1 ) & ( CT_TAPS == 0 ) ) * ( VDC_IN_CH0 + VDC_IN_CH1 + VDC_IN_CH2 + VDC_IN_CH3 ) ) +
( ( CT_CAMERA == 2 ) * 3 ) +
( ( CT_CAMERA == 3 ) * 4 )
) ;
DEF_CL_BUS_BITS
value = CAMERA_LINK_AV * ( GVDC_VID_WIDTH <= 16 ? GVDC_VID_WIDTH : 8 ) ;
[PARAMETER]
DIG_SHCNT
Set horizontal count
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_SVCNT
set vertical count
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_HTOTAL
Horizontal total count
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x303 ) || ( DEF_HTOTAL - 8 - 1 ) ;
no_define_value
DIG_VTOTAL
Vertical total count
eo_information
1
0 16 unsigned flag_overflow
value = VDT_VTOTAL - 1 ;
no_define_value
DIG_HSSYNC
Horizontal start sync
eo_information
1
0 16 unsigned flag_overflow
value = ( ! DEF_NTSC ) * ( ( DEF_CASE_1 * 6 ) || ( DEF_CASE_2 * ( DEF_HTOTAL - 5 ) ) ) ;
no_define_value
DIG_HESYNC
Horizontal end sync
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x3a ) || (
( DEF_CASE_1 * ( 6 + DEF_HSYNC ) ) ||
( DEF_CASE_2 * ( ( DEF_HSYNC < 5 ) ? 0 : ( DEF_HSYNC - 5 ) ) ) ||
( ( DEF_CASE_3 | DEF_CASE_4 | DEF_CASE_5 | DEF_CASE_6 ) * ( DEF_HSYNC ) ) || 11 ) - 1 ;
no_define_value
DIG_VSSYNC
Vertical start sync
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_VESYNC
Vertical end sync
eo_information
1
0 16 unsigned flag_overflow
value = ( ( CT_LS * 2 ) +
( ( ! CT_LS ) * VDT_VSYNC ) ) || 1 ;
no_define_value
DIG_HSBLNK
Horizontal start blank
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x40 ) ||
( DEF_CASE_1 * ( 6 + DEF_HSYNC + DEF_HBPORCH ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( ( ( DEF_HSYNC + DEF_HBPORCH ) < 5 ) ? 0 : ( DEF_HSYNC + DEF_HBPORCH - 5 ) ) ) ||
( DEF_CASE_3 * ( DEF_HSYNC + DEF_HBPORCH + 7 + SYC_CAM_LATENCY ) ) ||
( DEF_CASE_4 * ( ( ( DEF_HSYNC + DEF_HBPORCH ) < 5 ) ? 0 : ( DEF_HSYNC + DEF_HBPORCH - 5 ) ) ) ||
( DEF_CASE_5 * ( DEF_HSYNC + DEF_HBPORCH + SYC_CAM_LATENCY ) ) ;
no_define_value
DIG_HEBLNK
Horizontal end blank
eo_information
1
0 16 unsigned flag_overflow
value =
( DEF_NTSC * 0x300 ) ||
( DEF_CASE_1 * ( 6 + DEF_HTOTAL - DEF_HFPORCH ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( DEF_HTOTAL - DEF_HFPORCH - 5 ) ) ||
( DEF_CASE_3 * ( ( DEF_HTOTAL - DEF_HFPORCH + 7 + SYC_CAM_LATENCY ) % DEF_HTOTAL ) ) ||
( DEF_CASE_4 * ( DEF_HTOTAL - DEF_HFPORCH - 5 ) ) ||
( DEF_CASE_5 * ( ( DEF_HTOTAL - DEF_HFPORCH + SYC_CAM_LATENCY ) % DEF_HTOTAL ) ) ;
no_define_value
DIG_VSBLNK
Vertical start blank
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x1e ) ||
( ( CT_LS *
( 0 ) ) +
( ( ! CT_LS ) *
( VDT_VSYNC + VDT_VBPORCH + ( DEF_MASTER * 3 ) ) ) ) ;
no_define_value
DIG_VEBLNK
Vertical end blank
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x1fe ) ||
( ( ( CT_LS * 0 ) +
( ( ! CT_LS ) *
( VDT_VTOTAL - VDT_VFPORCH + ( DEF_MASTER * 3 ) ) ) ) % VDT_VTOTAL ) ;
no_define_value
DIG_HSCLMP
Horizontal start clamp
eo_information
1
0 16 unsigned flag_overflow
value =
( DEF_NTSC * 0x2fc ) ||
( ( DEF_CLAMP_MARGIN > 0 ) ? (
( VDT_CLP_BPO * (
( DEF_CASE_1 * ( DEF_HSYNC + DEF_CLAMP_MARGIN ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( DEF_HSYNC - 7 + DEF_CLAMP_MARGIN - 5 ) ) ||
( DEF_CASE_3 * ( DEF_HSYNC + DEF_CLAMP_MARGIN + SYC_CAM_LATENCY ) ) ) ) ||
( VDT_CLP_SYN * (
( DEF_CASE_1 * ( DEF_CLAMP_MARGIN ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( ( ( DEF_CLAMP_MARGIN < 7 ) * ( DEF_HTOTAL - 7 + DEF_CLAMP_MARGIN ) ) || ( DEF_CLAMP_MARGIN - 7 ) ) ) ||
( DEF_CASE_3 * ( SYC_CAM_LATENCY + DEF_CLAMP_MARGIN ) ) ) ) ||
( VDT_CLP_FPO * (
( DEF_CASE_1 * ( DEF_HTOTAL - DEF_HFPORCH + DEF_CLAMP_MARGIN ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( DEF_HTOTAL - DEF_HFPORCH - 7 ) ) ||
( DEF_CASE_3 * ( DEF_HTOTAL - DEF_HFPORCH + DEF_CLAMP_MARGIN + SYC_CAM_LATENCY ) ) ) ) ) : 0 ) ;
no_define_value
DIG_HECLMP
Horizontal end clamp
eo_information
1
0 16 unsigned flag_overflow
value =
( DEF_NTSC * 0x30a ) ||
( ( DEF_CLAMP_MARGIN > 0 ) ? (
( VDT_CLP_BPO * (
( DEF_CASE_1 * ( DEF_HSYNC + DEF_HBPORCH - DEF_CLAMP_MARGIN ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( DEF_HSYNC + DEF_HBPORCH - 12 - DEF_CLAMP_MARGIN ) ) ||
( DEF_CASE_3 * ( DEF_HSYNC + DEF_HBPORCH - DEF_CLAMP_MARGIN + SYC_CAM_LATENCY ) ) ) ) ||
( VDT_CLP_FPO * (
( DEF_CASE_1 * ( DEF_HTOTAL - DEF_CLAMP_MARGIN ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( DEF_HTOTAL - DEF_CLAMP_MARGIN - 7 ) ) ||
( DEF_CASE_3 * ( DEF_HTOTAL - DEF_CLAMP_MARGIN + SYC_CAM_LATENCY ) ) ) ) ||
( VDT_CLP_SYN * (
( DEF_CASE_1 * ( DEF_HSYNC - DEF_CLAMP_MARGIN ) ) ||
( ( DEF_CASE_2 | DEF_CASE_6 ) * ( ( ( DEF_HSYNC >= ( 7 + DEF_CLAMP_MARGIN ) ) * ( DEF_HSYNC - 7 - DEF_CLAMP_MARGIN ) ) || ( DEF_HTOTAL - 7 - DEF_CLAMP_MARGIN + DEF_HSYNC ) ) ) ||
( DEF_CASE_3 * ( DEF_HSYNC - DEF_CLAMP_MARGIN + SYC_CAM_LATENCY ) ) ) ) ) : 1 ) ;
no_define_value
DIG_VSCLMP
Vertical start clamp
eo_information
1
0 16 unsigned flag_overflow
value = ( CT_LS & VDC_ANA ) ? 0 : ( DEF_MASTER * 3 ) ;
no_define_value
DIG_VECLMP
Vertical end clamp
eo_information
1
0 16 unsigned flag_overflow
value = ( CT_LS & VDC_ANA ) ? 0 : ( VDT_VSYNC + ( DEF_MASTER * 3 ) + 1 ) ;
no_define_value
DIG_HSPLLF
Horizontal start PLL feedback
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_HEPLLF
Horizontal end PLL feedback
eo_information
1
0 16 unsigned flag_overflow
value = ( SYC_ANA + ( SYC_DIG & SYC_CAM_GEN & ( ! PCK_CAM_GEN ) ) ) * 20 ;
no_define_value
DIG_VSNGVR
Vertical start noise gate vertical reset
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_VENGVR
Vertical end noise gate vertical reset
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_HSCSGT
Horizontal start csync gate
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_HECSGT
Horizontal end csync gate
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_VSPDTC
Vertical start phase detector enable
eo_information
1
0 16 unsigned flag_overflow
value = SYC_BLK * VDT_VSYNC ;
no_define_value
DIG_VEPDTC
Vertical end phase detector enable
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_ECSNGT
End csync noise gate
eo_information
1
0 16 unsigned flag_overflow
value = ( SYC_ANA | ( SYC_DIG & SYC_CAM_GEN & SYC_C_IN ) ) *
( ( DEF_GRBSYSCLK / VDT_HSYNC_FREQ ) - 30 ) ;
no_define_value
DIG_NGCSFM
Noise gated csync found and missed
eo_information
2
ngcsfnd regular
number of noise gated csync found
eo_information
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
ngcsmis regular
Number of noise gated csync missed
eo_information
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
DIG_DTCVSR
Detection vsync sample register
eo_information
2
dtcvs regular
Detection vsync sample register
eo_information
0 12 unsigned flag_overflow
value = ( 1 - CT_LS ) * (
( SYC_ANA | ( SYC_DIG & SYC_CAM_GEN & SYC_C_IN ) ) *
( ( DEF_GRBSYSCLK / VDT_HSYNC_FREQ ) / 4 ) ) ;
no_define_value
reserved protected
eo_information
0 4 unsigned flag_overflow
no_define_value
DIG_FLDSG
Field start gate
eo_information
1
0 16 unsigned flag_overflow
value = ( SYC_ANA | ( SYC_DIG & SYC_CAM_GEN & SYC_C_IN ) ) *
( DEF_GRBSYSCLK / VDT_HSYNC_FREQ / 2 ) ;
no_define_value
DIG_FLDEG
Field end gate
eo_information
1
0 16 unsigned flag_overflow
value = ( SYC_ANA | ( SYC_DIG & SYC_CAM_GEN & SYC_C_IN ) ) *
( DEF_GRBSYSCLK / VDT_HSYNC_FREQ ) ;
no_define_value
DIG_T1SCNT
Timer 1 set count
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_DELAY_TIMER1 + EXP_OUT_T1 - 4 ) * DEF_TIMER1_ENABLE ;
no_define_value
DIG_T2SCNT
Timer 2 set count
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_DELAY_TIMER2 + EXP_OUT_T1_2 - 4 ) * DEF_TIMER2_ENABLE ;
no_define_value
DIG_EXP1S
Exposure 1 start
eo_information
1
0 16 unsigned flag_overflow
value = ( EXP_OUT_T1 + 2 ) * DEF_TIMER1_ENABLE ;
no_define_value
DIG_EXP2S
Exposure 2 start
eo_information
1
0 16 unsigned flag_overflow
value = ( EXP_OUT_T1_2 + 2 ) * DEF_TIMER2_ENABLE ;
no_define_value
DIG_T1CTL
Timer 1 control register
eo_information
10
t1clksel regular
Timer 1 clock source select
eo_information
0 3 unsigned flag_overflow
value =
( 0 * EXP_CLOCK_DITRIG ) +
( 1 * EXP_CLOCK_VTRIG ) +
( 2 * EXP_CLOCK_HSYNC ) +
( 3 * EXP_CLOCK_VSYNC ) +
( 4 * EXP_CLOCK_TIMER2 ) +
( 5 * EXP_ASY_CLK ) +
( 6 * EXP_SYN_CLK ) +
( 7 * EXP_CLOCK_CRYSTAL ) ;
define_value
DI trigger
Video trigger
HSYNC output
VSYNC output
Ouput exposure 2
User clock
Pixel clock
XTALCK
t1clkpol regular
Timer 1 clock polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Rising edge
Falling edge
t1trgsl regular
Timer 1 trigger source select
eo_information
0 3 unsigned flag_overflow
value =
( EXP_MD_W_TRG * (
( EXP_TRG_SIGNAL_APORT * 1 ) +
( EXP_MD_VSY * 3 ) +
( EXP_MD_HSY * 2 ) +
( EXP_MD_SW * 7 ) +
( EXP_TRG_SIGNAL_DPORT * 0 ) +
( EXP_TRG_SIGNAL_TIMER2 * 5 )
) ) ||
( EXP_MD_PERD * 6 ) ;
define_value
DI trigger
Video trigger
HSYNC output
VSYNC output
Field output
Exposure 2
Timer 1 count
T1SOFTRG
t1trgpol regular
Timer 1 trigger polarity
eo_information
0 1 unsigned flag_overflow
value = EXP_TRG_NEG ;
define_value
Rising edge
Falling edge
t1onesht regular
Timer 1 one shot enable
eo_information
0 1 unsigned flag_overflow
value = EXP_MD_W_TRG ;
define_value
Continuous mode
Monoshot
t1tsclr regular
Timer 1 trigger scaler selection
eo_information
0 2 unsigned flag_overflow
value =
( EXP_PRESCALE1_2 * 0 ) +
( EXP_PRESCALE1_4 * 1 ) +
( EXP_PRESCALE1_8 * 2 ) +
( EXP_PRESCALE1_16 * 3 ) ;
define_value
1 every 2
1 every 4
1 every 8
1 every 16
t1tpsclr regular
Timer 1 trigger prescaler
eo_information
0 1 unsigned flag_overflow
value = EXP_PRESCALE1_2 | EXP_PRESCALE1_4 | EXP_PRESCALE1_8 | EXP_PRESCALE1_16 ;
define_value
Not prescaled
Prescaled
t1cmbn regular
Timer 1 combine selection
eo_information
0 2 unsigned flag_overflow
value = ( EXP_COMBINE_XOR * 1 ) ||
( EXP_COMBINE_AND * 2 ) ||
( EXP_COMBINE_OR * 3 ) ;
define_value
Timer 1
T1 XOR T2
T1 AND T2
T1 OR T2
t1pol regular
Timer 1 output polarity
eo_information
0 1 unsigned flag_overflow
value =
EXP_OUT_NEG ;
define_value
High
Low
exp1 regular
Timer 1 exposure output
eo_information
0 1 unsigned flag_overflow
value = EXP_OUT_NEG ;
define_value
Low
High
DIG_T2CTL
Timer 2 control register
eo_information
10
t2clksl regular
Timer 2 clock source select
eo_information
0 3 unsigned flag_overflow
value =
( 0 * EXP_CLOCK_2_DITRIG ) +
( 1 * EXP_CLOCK_2_VTRIG ) +
( 2 * EXP_CLOCK_2_HSYNC ) +
( 3 * EXP_CLOCK_2_VSYNC ) +
( 4 * EXP_CLOCK_2_TIMER1 ) +
( 5 * EXP_ASY_CLK_2 ) +
( 6 * EXP_SYN_CLK_2 ) +
( 7 * EXP_CLOCK_2_CRYSTAL ) ;
define_value
DI trigger
Video trigger
HSYNC output
VSYNC output
Output exposure 1
User clock
Pixel clock
XTALCK
t2clkpol regular
Timer 2 clock polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Rising edge
Falling edge
t2trgsl regular
Timer 2 trigger source select
eo_information
0 3 unsigned flag_overflow
value =
EXP_MD_W_TRG_2 * (
( EXP_TRG_SIGNAL_2_APORT * 1 ) +
( EXP_MD_VSY_2 * 3 ) +
( EXP_MD_HSY_2 * 2 ) +
( EXP_MD_SW_2 * 7 ) +
( EXP_TRG_SIGNAL_2_DPORT * 0 ) +
( EXP_TRG_SIGNAL_2_TIMER1 * 5 )
) ||
( EXP_MD_PERD_2 * 6 ) ;
define_value
DI trigger
Video trigger
HSYNC output
VSYNC output
Field output
Exposure 1
Timer 2 count
T2SOFTRG
t2trgpol regular
Timer 2 trigger input polarity
eo_information
0 1 unsigned flag_overflow
value = EXP_TRG_NEG_2 ;
define_value
Rising edge
Falling edge
t2onesht regular
default: set to continuous, t1cnten is also disabled by default
eo_information
0 1 unsigned flag_overflow
value = EXP_MD_W_TRG_2 ;
define_value
Continuous mode
Monoshot
t2tsclr regular
Timer 2 trigger scaler selection
eo_information
0 2 unsigned flag_overflow
value =
( EXP_PRESCALE2_2 * 0 ) +
( EXP_PRESCALE2_4 * 1 ) +
( EXP_PRESCALE2_8 * 2 ) +
( EXP_PRESCALE2_16 * 3 ) ;
define_value
1 every 2
1 every 4
1 every 8
1 every 16
t2tpsclr regular
Timer 2 trigger prescaler
eo_information
0 1 unsigned flag_overflow
value = EXP_PRESCALE2_2 | EXP_PRESCALE2_4 | EXP_PRESCALE2_8 | EXP_PRESCALE2_16 ;
define_value
Not prescaled
Prescaled
t2cmbn regular
Timer 2 combine selection
eo_information
0 2 unsigned flag_overflow
value = ( EXP_COMBINE_2_XOR * 1 ) ||
( EXP_COMBINE_2_AND * 2 ) ||
( EXP_COMBINE_2_OR * 3 ) ;
define_value
T2
T2 XOR T1
T2 AND T1
T2 OR T1
t2pol regular
Timer 2 output enable
eo_information
0 1 unsigned flag_overflow
value = EXP_OUT_NEG_2 ;
define_value
High
Low
exp2 regular
Timer 2 exposure output
eo_information
0 1 unsigned flag_overflow
value = EXP_OUT_NEG_2 ;
define_value
Low
High
DIG_HVRCTL
Horizontal vertical reset control
eo_information
9
hrstsel regular
Horizontal reset selection
eo_information
0 3 unsigned flag_overflow
value =
( SYC_DIG & SYC_H_IN & PCK_CAM_GEN ) * 2 ;
define_value
Noise gated Csync
BT261 HSYNC
Digital interface
reserved
Digital trigger
Video trigger
Exposure #1 output
Exposure #2 output
hrstpol regular
Horizontal reset polarity
eo_information
0 1 unsigned flag_overflow
value =
( SYC_DIG & SYC_H_IN & PCK_CAM_GEN ) * SYC_H_INEG ;
define_value
No inversion
Polarity inversed
hrsten regular
Horizontal reset enable
eo_information
0 1 unsigned flag_overflow
value = ( SYC_DIG & SYC_H_IN & PCK_CAM_GEN ) ||
( SYC_DIG & SYC_C_IN & PCK_CAM_GEN ) ;
define_value
Hcnt load disabled
Hcnt load enabled
reserved protected
eo_information
0 3 unsigned flag_overflow
no_define_value
vrstsel regular
Vertical reset select
eo_information
0 3 unsigned flag_overflow
value = ( CT_LS * SYC_EXT_VSY * 2 ) ||
( ( DEF_MASTER & GRB_ACT_IMMEDIATE & CT_FS ) * 6 ) ||
( ( ( ! DEF_MASTER ) & GRB_ACT_IMMEDIATE & CT_FS ) * ( ( SYC_ANA * 0 ) + ( SYC_DIG * 2 ) ) ) ||
( ( DEF_MASTER & GRB_ACT_IMM_SKP_NFR & CT_FS ) * 6 ) ||
( ( ( ! DEF_MASTER ) & GRB_ACT_IMM_SKP_NFR & CT_FS ) * ( ( SYC_ANA * 0 ) + ( SYC_DIG * 2 ) ) ) ||
( ( SYC_DIG & SYC_V_IN ) * 2 ) ;
define_value
Detected vsync
BT261 vsync
DI vsync(XVSYNC)
DI hsync(XHSYNC)
Digital trigger
Video trigger
Exposure 1 ouput
Exposure 2 output
vrstpol regular
Vertical reset polarity
eo_information
0 1 unsigned flag_overflow
value = ( ( DEF_MASTER & GRB_ACT_IMMEDIATE & CT_FS ) * ( EXP_OUT_POS ) ) +
( ( ( ! DEF_MASTER ) & GRB_ACT_IMMEDIATE & CT_FS ) * ( SYC_DIG & SYC_V_INEG ) ) +
( ( DEF_MASTER & GRB_ACT_IMM_SKP_NFR & CT_FS ) * ( EXP_OUT_POS ) ) +
( ( ( ! DEF_MASTER ) & GRB_ACT_IMM_SKP_NFR & CT_FS ) * ( SYC_DIG & SYC_V_INEG ) ) +
( GRB_MD_CONT * ( ( ( SYC_ANA | ( SYC_DIG & SYC_CAM_GEN & SYC_C_IN ) ) * 0 ) + ( ( SYC_DIG & SYC_V_IN ) * SYC_V_INEG ) ) ) ;
define_value
No inversion
Polarity inversed
vrsten regular
Vertical reset enable
eo_information
0 1 unsigned flag_overflow
value = ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) & CT_FS || ( CT_LS & SYC_EXT_VSY ) || ( ( ! DEF_MASTER ) & ( ! CT_LS ) ) ;
define_value
Vcnt load disabled
Vcnt load enabled
algvrsl regular
Align vertical counter reset selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
Not realigned
Not realigned
Aligned HTOTAL
Align VRST-HRST
vrstngen regular
Vertical reset noise gate enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
NGating disabled
NGating enabled
DIG_OUTCTL
Output control
eo_information
9
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
fieldpol regular
Field output polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
High
Low
clamppol regular
Clamping output polarity
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
High
Low
blankpol regular
Blanking output polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
High
Low
csyncpol regular
Composite sync output polarity
eo_information
0 1 unsigned flag_overflow
value = SYC_C_OUT * SYC_C_ONEG ;
define_value
High
Low
vsyncpol regular
Vertical sync output polarity
eo_information
0 1 unsigned flag_overflow
value =
( ( SYC_DIG & SYC_V_OUT ) * SYC_V_ONEG )
+ ( ( ! ( SYC_DIG & SYC_V_OUT ) ) * 1 ) ;
define_value
High
Low
hsyncpol regular
Horizontal sync output polarity
eo_information
0 1 unsigned flag_overflow
value =
( ( SYC_DIG & SYC_H_OUT ) * SYC_H_ONEG )
+ ( ( ! ( SYC_DIG & SYC_H_OUT ) ) * 1 ) ;
define_value
High
Low
reserved2 protected
eo_information
0 5 unsigned flag_overflow
no_define_value
fldctl regular
Field control (WARNING: new definition from 2.08)
eo_information
0 3 unsigned flag_overflow
value = VDT_INTERL * 2 ;
define_value
detected field
hrst/vrst
hcnt/VSYNC out
hcnt/vrst
detected field tog
hrst/vrst tog field
hcnt/VSYNC out tog
hcnt/vrst toggle
DIG_CPTCTL
Capture control
eo_information
4
reserved1 protected
eo_information
0 9 unsigned flag_overflow
no_define_value
captpol regular
Capture polarity control
eo_information
0 1 unsigned flag_overflow
value = GRB_TRG_NEG ;
define_value
Not inverted
Inverted
captsel regular
Capture source selection
eo_information
0 3 unsigned flag_overflow
value =
( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_DPORT ) * 0 ) +
( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_APORT ) * 1 ) +
( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_TIMER1 ) * 2 ) +
( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_TIMER2 ) * 3 ) +
( GRB_MD_SW_TRG * 5 ) ;
define_value
DI trigger
Video trigger
Exposure 1
Exposure 2
RESERVED
SOFTCAP
RESERVED
SOFTCAP
reserved2 protected
eo_information
0 3 unsigned flag_overflow
no_define_value
DIG_SRSCTL
Signal reset control. Handled by software.
eo_information
11
vcntrst regular
Vertical count soft reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset vcnt
hcntrst regular
Horizontal counter soft reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset hcnt
pdtcrst regular
Phase detector output reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset PHDTCEN
clamprst regular
Clamping output reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset clamp
blankrst regular
Blanking output reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset clamp
ngvrsrst regular
Noise gate vertical reset signal reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset NGVRT
vsyncrst regular
Vertical sync output reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset vsync
hsyncrst regular
Horizontal sync output reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset hsync
t1sofclr regular
Timer 1 soft clear
eo_information
0 1 unsigned flag_overflow
define_value
No effect
Clear timer 1 counter
t2sofclr regular
Timer 2 soft clear
eo_information
0 1 unsigned flag_overflow
define_value
No effect
Clear timer 2 counter
reserved protected
eo_information
0 6 unsigned flag_overflow
no_define_value
DIG_PLLCTL
Phase lock loop control
eo_information
13
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
pllrfpol regular
PLL reference polarity
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
High
Low
pllfbpol regular
PLL feedback polarity
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
High
Low
pdtcsel regular
PLL phase detector selection
eo_information
0 2 unsigned flag_overflow
value = 2 ;
define_value
Reserved
Reserved
PLLFB PLLRF enable
Reserved
pdtcpol regular
PLL phase detector polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
High
Low
pdtcouen regular
PLL phase detector output enable
eo_information
0 1 unsigned flag_overflow
value = ! SYC_BLK ;
define_value
PHDTCEN disabled
PHDTCEN enabled
lcksts0 regular
PLL lock status bit 0. Handled by software.
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
lcksts1 regular
PLL lock status bit 1. Handled by software.
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
lcksts2 regular
PLL lock status bit 2. Handled by software.
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
lcksts3 regular
PLL lock status bit 3. Handled by software.
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
lksts0rs regular
PLL lock status bit 0 reset. Handled by software.
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
lksts1rs regular
PLL lock status bit 1 reset. Handled by software.
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
reserved2 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
DIG_NGCTL
Noise gating control
eo_information
9
crctnen regular
Noise gated csync correction enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Disabled
Enabled
dlypllrf regular
Delay the PLL reference signal
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No delay
Delay
reserved1 protected
eo_information
0 6 unsigned flag_overflow
no_define_value
xsynsel regular
External sync input selection
eo_information
0 3 unsigned flag_overflow
value =
( ( VDC_ANA & ( ! SYC_DIG ) ) * 0x4 ) ||
( ( SYC_DIG & SYC_H_IN & ( ! PCK_CAM_GEN ) ) * 1 ) || ( ( SYC_DIG & SYC_C_IN )
* 2 ) ;
define_value
DI HSYNC/VSYNC
DI HSYNC
DI CSYNC
BT261
Sync slicer
Sync slicer
Sync slicer
Sync slicer
btsynpol regular
eo_information
0 1 unsigned flag_overflow
value = ( VDC_ANA & ( ! SYC_DIG ) ) * 1 ;
define_value
Not inverted
Inversion
vcsynpol regular
Video csync input polarity control
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
High
Low
xcsynpol regular
External csync input polarity control
eo_information
0 1 unsigned flag_overflow
value = ( SYC_DIG & SYC_C_IN ) * SYC_C_INEG ;
define_value
High
Low
xvsynpol regular
External vsync input polarity control
eo_information
0 1 unsigned flag_overflow
value = ( SYC_DIG & SYC_V_IN ) * SYC_V_INEG ;
define_value
High
Low
xhsynpol regular
External hsync input polarity control
eo_information
0 1 unsigned flag_overflow
value = ( SYC_DIG & SYC_H_IN & ( ! PCK_CAM_GEN ) ) * SYC_H_INEG ;
define_value
High
Low
DIG_PSGCFG
PSG configuration
eo_information
10
intrlace regular
Interlace mode
eo_information
0 1 unsigned flag_overflow
value = VDT_INTERL ;
define_value
Non-interlaced
Interlaced
rmvhlfln regular
Remove half-line
eo_information
0 1 unsigned flag_overflow
value = VDT_INTERL ;
define_value
Display half lines
Remove half line
lnscan regular
Line scan mode
eo_information
0 1 unsigned flag_overflow
value = CT_LS ;
define_value
No effect
Stop hcnt=htotal
frmscan regular
Frame scan mode
eo_information
0 1 unsigned flag_overflow
value = DEF_FRAMESCAN ;
define_value
No effect
Stop vcnt=vtotal
pclktst regular
Pixel clock test
eo_information
0 1 unsigned flag_overflow
define_value
No effect
PCLK test mode
vclpdfn regular
Vertical clamp define
eo_information
1 1 unsigned flag_overflow
value = 1 ;
define_value
S&E as defined
Reversed
vgrstmd regular
Vertical gate reset mode
eo_information
0 1 unsigned flag_overflow
define_value
Not affected by VRST
VRST will reset the gate
reserved1 protected
eo_information
0 1 unsigned flag_overflow
no_define_value
nbfscnd regular
Number of frame scanned
eo_information
0 2 unsigned flag_overflow
value = ( GRB_ACT_IMM_SKP_NFR & CT_FS ) *
( ( VDT_INTERL == 1 ) ? 3 : 1 ) ;
define_value
1 frame scanned
2 frames scanned
3 frames scanned
4 frames scanned
reserved2 protected
eo_information
0 6 unsigned flag_overflow
no_define_value
DIG_SRCCFG
STRC configuration. Handled by software.
eo_information
5
reserved protected
eo_information
0 12 unsigned flag_overflow
no_define_value
dlkprtcn regular
Host interface dead lock protection
eo_information
0 1 unsigned flag_overflow
define_value
Active
Disabled
holdsys regular
Hold system
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Ack immediate
Ack wait
resync regular
Resynchronize data
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Disabled
Enabled
fifofull regular
Fifo full read only
eo_information
0 1 unsigned flag_overflow
no_define_value
DIG_GRABCTL
Grab control
eo_information
10
didir regular
Digital interface output buffers direction selection
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
A/D input
DI input
diouen regular
Digital interface output enable
eo_information
0 1 unsigned flag_overflow
value = VDC_DIG ;
define_value
Buffers disabled
Buffers enabled
adrben regular
A/D red and blue channel enable
eo_information
0 1 unsigned flag_overflow
value = VDC_ANA ;
define_value
A/D tri-stated
Output enable
adgaen regular
A/D green and alpha channel enable
eo_information
0 1 unsigned flag_overflow
value = VDC_ANA ;
define_value
A/D tri-stated
Output enable
vcsel regular
Video csync selection
eo_information
0 2 unsigned flag_overflow
value =
( SYC_IN_CH + 1 ) % 4 ;
define_value
Alpha
Red
Green
Blue
hvsynsel regular
Horizontal and vertical sync selection
eo_information
0 1 unsigned flag_overflow
value = ( ( SYC_DIG & SYC_H_IN & SYC_V_IN & ( PCK_CAM_GEN | PCK_CAM_R&G )
& VDC_DIG ) | ( CT_LS & SYC_H_IN & PCK_CAM_GEN & VDC_DIG ) ) * 1 ;
define_value
STRC hvsync
DI hvsync
validsel regular
Valid source selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
STRC blank
DI XVALID
dmode regular
Digitizer mode selection
eo_information
0 4 unsigned flag_overflow
value =
( ( DEF_DMODE == 6 ) * 4 ) ||
( ( DEF_DMODE == 4 ) * 2 ) ||
( ( DEF_DMODE == 2 ) * 0 ) ||
( ( DEF_DMODE == 1 ) * 12 ) ;
define_value
2 Ch/8bits
2 Ch/8bits
1 Ch/8bits
1 Ch/8bits
1 Ch/10bits 0
1 Ch/10bits 180
1 Ch/10bits 90
1 Ch/10bits 270
2 Ch/8bits
2 Ch/8bits
1 Ch/8bits
1 Ch/8bits
4 Ch/8bits 0
4 Ch/8bits 180
4 Ch/8bits 90
4 Ch/8bits 270
pclksel regular
Pixel clock selection
eo_information
0 3 unsigned flag_overflow
value = ( (
( DEF_MASTER * 1 ) +
( ( SYC_ANA | ( SYC_DIG & ( SYC_H_IN | SYC_C_IN ) ) ) * 2 ) ) * ( ! ( PCK_CAM_GEN | PCK_CAM_R&G ) ) ) +
( ( PCK_CAM_GEN | PCK_CAM_R&G ) * ( ( ( PCK_IDELAY <= 4.5 ) * 0 ) +
( ( ( ( CAMERA_LINK_AV == 1 ) & ( PCK_IDELAY >= 3 ) )
| ( ( CAMERA_LINK_AV == 0 ) & ( PCK_IDELAY > 4.5 ) ) ) * 3 )
) ) ;
define_value
EXTCLK
USERCLK
STRC PLL ref
EXTCLKDL
VTRIG
XTRIG
Timer 1 exp
Timer 2 exp
ck0sl regular
Clock phase 0 selection
eo_information
0 1 unsigned flag_overflow
value = ( SYC_ANA | ( SYC_DIG & ( ! PCK_CAM_GEN ) ) ) * 1 * ( ! DEF_MASTER ) ;
define_value
PLL by-passed
PLL phase 0
DIG_ANACTL
Analog section control
eo_information
9
alfgain regular
Alpha channel gain selection
eo_information
0 2 unsigned flag_overflow
value =
( ! DEF_NTSC ) * (
( ( VDL_AMPL <= 488 ) * 3 ) +
( ( ( 488 < VDL_AMPL ) & ( VDL_AMPL <= 606 ) ) * 2 ) +
( ( ( 606 < VDL_AMPL ) & ( VDL_AMPL <= 740 ) ) * 1 ) +
( ( 740 < VDL_AMPL ) * 0 ) ) ;
define_value
2.0
2.7
3.3
4.1
redgain regular
Red channel gain selection
eo_information
0 2 unsigned flag_overflow
value =
( ! DEF_NTSC ) * (
( ( VDL_AMPL <= 488 ) * 3 ) +
( ( ( 488 < VDL_AMPL ) & ( VDL_AMPL <= 606 ) ) * 2 ) +
( ( ( 606 < VDL_AMPL ) & ( VDL_AMPL <= 740 ) ) * 1 ) +
( ( 740 < VDL_AMPL ) * 0 ) ) ;
define_value
2.0
2.7
3.3
4.1
grngain regular
Green channel gain selection
eo_information
0 2 unsigned flag_overflow
value =
( ! DEF_NTSC ) * (
( ( VDL_AMPL <= 488 ) * 3 ) +
( ( ( 488 < VDL_AMPL ) & ( VDL_AMPL <= 606 ) ) * 2 ) +
( ( ( 606 < VDL_AMPL ) & ( VDL_AMPL <= 740 ) ) * 1 ) +
( ( 740 < VDL_AMPL ) * 0 ) ) ;
define_value
2.0
2.7
3.3
4.1
blugain regular
Blue channel gain selection
eo_information
0 2 unsigned flag_overflow
value =
( ! DEF_NTSC ) * (
( ( VDL_AMPL <= 488 ) * 3 ) +
( ( ( 488 < VDL_AMPL ) & ( VDL_AMPL <= 606 ) ) * 2 ) +
( ( ( 606 < VDL_AMPL ) & ( VDL_AMPL <= 740 ) ) * 1 ) +
( ( 740 < VDL_AMPL ) * 0 ) ) ;
define_value
2.0
2.7
3.3
4.1
afltrsl regular
Alpha channel anti-aliasing filter selection
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
By-passed
Selected
rfltsl regular
Red channel anti-aliasing filter selection
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
By-passed
Selected
gfltrsl regular
Green channel anti-aliasing filter selection
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
By-passed
Selected
bfltrsl regular
Blue channel anti-aliasing filter selection
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
By-passed
Selected
reserved protected
eo_information
0 4 unsigned flag_overflow
no_define_value
DIG_DICTL
Digital interface control
eo_information
14
dimdata regular
Digital interface module data
eo_information
0 1 unsigned flag_overflow
value = USR_BIT_5_OTH0 ;
define_value
Low
High
dimclk regular
Digital interface module clock
eo_information
0 1 unsigned flag_overflow
value = USR_BIT_4_OTH0 ;
define_value
Low
High
dimld regular
Digital interface module load
eo_information
0 1 unsigned flag_overflow
value = USR_BIT_3_OTH0 ;
define_value
Low
High
dimpres regular
Digital interface module present
eo_information
0 1 unsigned flag_overflow
no_define_value
dimprsen regular
Digital interface module present enable
eo_information
0 1 unsigned flag_overflow
define_value
Enable
Disable
iclksel regular
Digital interface clock selection
eo_information
0 3 unsigned flag_overflow
value = 4 ;
define_value
PCLK_0
PCLK_90
PCLK_180
PCLK_270
USERCLK
EXTCLK
Timer 1
Timer 2
synttlin regular
TTL synchronisation in enable
eo_information
0 1 unsigned flag_overflow
value = SYC_H_ITTL | SYC_V_ITTL | SYC_C_ITTL | PCK_ITTL ;
define_value
Disable
Enable
synttlou regular
TTL synchronisation out enable
eo_information
0 1 unsigned flag_overflow
value = SYC_H_OTTL | SYC_V_OTTL | SYC_C_OTTL | PCK_OTTL ;
define_value
Disable
Enable
usrttlin regular
User TTL in enable
eo_information
0 1 unsigned flag_overflow
value = ( USR_ITTL & USR_IENABLE ) |
( USR_ITTL & USR_IENABLE ) | ( GRB_TRG_SIGNAL_DPORT & GRB_TRG_TTL )
| ( EXP_TRG_SIGNAL_DPORT & EXP_TRG_TTL ) |
( EXP_TRG_SIGNAL_2_DPORT & EXP_TRG_TTL_2 ) ;
define_value
Disable
Enable
usrttlou regular
User TTL out enable
eo_information
0 1 unsigned flag_overflow
value = ( USR_OTTL & USR_OENABLE ) |
( DEF_TIMER1_ENABLE & EXP_OUT_TTL ) | ( DEF_TIMER2_ENABLE & EXP_OUT_TTL_2 ) ;
define_value
Disable
Enable
syn422in regular
RS-422 synchronisation in enable
eo_information
0 1 unsigned flag_overflow
value = SYC_H_I422 | SYC_V_I422 | SYC_C_I422 | PCK_I422 ;
define_value
Disable
Enable
syn422ou regular
RS-422 synchronisation out enable
eo_information
0 1 unsigned flag_overflow
value = SYC_H_O422 | SYC_V_O422 | SYC_C_O422 | PCK_O422 ;
define_value
Disable
Enable
usr422in regular
User rs-422 in enable
eo_information
0 1 unsigned flag_overflow
value = ( USR_I422 & USR_IENABLE ) | ( GRB_TRG_SIGNAL_DPORT & GRB_TRG_422 )
| ( EXP_TRG_SIGNAL_DPORT & EXP_TRG_422 ) | ( EXP_TRG_SIGNAL_2_DPORT & EXP_TRG_422_2 ) ;
define_value
Disable
Enable
usr422ou regular
User rs-422 out enable
eo_information
0 1 unsigned flag_overflow
value = ( USR_O422 & USR_OENABLE ) | ( DEF_TIMER1_ENABLE & EXP_OUT_422 ) |
( DEF_TIMER2_ENABLE & EXP_OUT_422_2 ) ;
define_value
Disable
Enable
DIG_DLYLN
Delay line
eo_information
2
dixckdl regular
Digital interface external clock
eo_information
0 4 unsigned flag_overflow
value = ( PCK_IDELAY >= 9 ) * ( ( PCK_IDELAY - 9 ) / 3 ) ;
no_define_value
reserved protected
eo_information
0 12 unsigned flag_overflow
no_define_value
DIG_USRREG
User register
eo_information
9
reserved1 protected
eo_information
0 4 unsigned flag_overflow
no_define_value
userin0 regular
User input 0
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
userin1 regular
User in 1
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
userou0 regular
User out 0
eo_information
0 1 unsigned flag_overflow
value = ( USR_OENABLE & USR_BIT_1_OTH0 ) ;
define_value
Low
High
userou1 regular
User out 1
eo_information
0 1 unsigned flag_overflow
value = ( USR_OENABLE & USR_BIT_2_OTH0 ) ;
define_value
Low
High
cc1 regular
CC Selection
eo_information
0 2 unsigned flag_overflow
value = ( CAMERA_LINK_AV * ( CLB_CC1 - 1 ) ) ;
define_value
Timer 1
Timer 2
User Output #0
User Output #1
cc2 regular
CC Selection
eo_information
0 2 unsigned flag_overflow
value = ( CAMERA_LINK_AV * ( CLB_CC2 - 1 ) ) ;
define_value
Timer 1
Timer 2
User Output #0
User Output #1
cc3 regular
CC Selection
eo_information
0 2 unsigned flag_overflow
value = ( CAMERA_LINK_AV * ( CLB_CC3 - 1 ) ) ;
define_value
Timer 1
Timer 2
User Output #0
User Output #1
cc4 regular
CC Selection
eo_information
0 2 unsigned flag_overflow
value = ( CAMERA_LINK_AV * ( CLB_CC4 - 1 ) ) ;
define_value
Timer 1
Timer 2
User Output #0
User Output #1
DIG_INTCTL
Interrupt control
eo_information
5
reserved1 protected
eo_information
0 8 unsigned flag_overflow
no_define_value
intsl regular
Interrupt source selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
DI trigger
Video trigger
Exposure 1
Exposure 2
DI trigger
Video trigger
Exposure 1
Exposure 2
grabint regular
Grab module interrupt
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
intpol regular
Interrupt input signal polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Rising edge
Falling edge
reserved2 protected
eo_information
0 3 unsigned flag_overflow
no_define_value
DIG_GPCTL
Grab port control
eo_information
6
gbouen regular
grab module's output buffers' enable
eo_information
1 1 unsigned flag_overflow
value = 1 ;
define_value
Disabled
Enabled
gpinen regular
grab port input buffers' enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Input disabled
Input enabled
gpouen regular
grab port output buffers' enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Output disabled
Input enabled
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
bluesel regular
Base board blue channel selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Real blue
Pseudo blue
reserved2 protected
eo_information
0 10 unsigned flag_overflow
no_define_value
DIG_LUTPAL
Lut palette
eo_information
5
lut1pl regular
Lut 1 palette selection
eo_information
0 5 unsigned flag_overflow
value = 0 ;
no_define_value
lut3z regular
Lut palette selection tri-state control
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
12:8 tri stated
11:8 tri stated
10:8 tri stated
9:8 tri stated
8 tri stated
12:8 driving
Reserved
Reserved
lut2pl regular
Lut 2 palette selection
eo_information
0 5 unsigned flag_overflow
value = 0 ;
no_define_value
pixrgb regular
Color index mode selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
Color index mode
RGB 11101
RGB 11110
RGB 11111
reserved protected
eo_information
0 1 unsigned flag_overflow
no_define_value
DIG_MISCTL
Miscellaneous control
eo_information
12
t1setarm regular
Timer 1 set arm
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Next no effect
Next start
t1armen regular
Timer 1 trigger arm enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Monoshot
Continuous
t1softrg regular
Timer 1 software trigger
default: do not send a soft trigger
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
t1cnten regular
Timer 1 counter enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Counter disabled
Counter enabled
t2setarm regular
Timer 2 set arm
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Next no effect
Next start
t2armen regular
Timer 2 trigger arm enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Monoshot
Continuous
t2softrg regular
Timer 2 software trigger
default: do not send a soft trigger
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
t2cnten regular
Timer 2 count enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Counter disabled
Counter enabled
reserved protected
eo_information
0 5 unsigned flag_overflow
no_define_value
softcap regular
Software capture control bit
default: do not send a soft capture
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
capten regular
Capture output enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
CAPTEN disabled
CAPTEN enabled
intclr regular
Interrupt clear
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
GRABINT enabled
GRABINT clr/disbl
DIG_TMRCLR
Timer clear
eo_information
7
t1clrsl regular
Timer 1 clear source select
eo_information
0 3 unsigned flag_overflow
define_value
Digital connector
Video connector
Reserved
Reserved
User bit 0
Output Exp2
Reserved
T1SOFCLR bit
t1clrpol regular
Timer 1 clear polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active high
Active low
t2clrsl regular
Timer 2 clear source select
eo_information
0 3 unsigned flag_overflow
define_value
Digital connector
Video connector
Reserved
Reserved
User bit 1
Output Exp1
Reserved
T2SOFCLR bit
t2clrpol regular
Timer 2 clear polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active high
Active low
t1clren regular
Timer 1 clear enable
eo_information
0 1 unsigned flag_overflow
define_value
Timer clear disabled
Timer clear enabled
t2clren regular
Timer 2 clear enable
eo_information
0 1 unsigned flag_overflow
define_value
Timer clear disabled
Timer clear enabled
reserved protected
eo_information
0 6 unsigned flag_overflow
no_define_value
DIG_PMCCTRL
PMC control
eo_information
13
vidsel regular
Video Selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
Cam1 video
Cam2 video
Cam3 video
Cam4 video
syncsel regular
Sync Selection
eo_information
0 2 unsigned flag_overflow
value = 0;
define_value
Cam1 HD/VD
Cam2 HD/VD
Cam3 HD/VD
Cam4 HD/VD
frsel regular
frame reset selection
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
frame reset 1 selected
frame reset 2 selected
fren regular
frame reset enable
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
frame reset 1 and 2 are tristated
a frane reset is enabled
pxclksel regular
pixel clock select
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
pixclk1 selected
pixclk2 selected
cmtrgsel regular
camtrig selection
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
camtrig0 selected
camtrig1 selected
strbsel regular
strobe select
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
strobe1 selected
strobe2 selected
strben regular
strobe enable
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
strobe 1 and 2 are tristated
a strobe is enabled
strbpol regular
strobe polarity
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
strobe is active low
strobe is active high
enclsel regular
encl select
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
encl0 selected
encl1 selected
boardid regular
Board ID
eo_information
0 2 unsigned flag_overflow
value = 0;
define_value
Default
Reserved
Reserved
Reserved
syndir regular
sync direction
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
Receive sync
Drive sync
tjexpsel regular
test jig exposure select
eo_information
0 1 unsigned flag_overflow
value = 0;
define_value
exp0 is selected
exp1 is selected
DIG_TCTLA
Timer control A
eo_information
10
t1armsel regular
timer #1 arm source select
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
tsetarm
opto-trig
hsync
vsync
field
exp1
ext. trig
soft trig
t1armpol regular
timer #1 arm source polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
high
low
t1armmsk regular
timer #1 arm mask
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
normal
mask
t1trglev regular
timer #1 trig on level
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
rising
falling
fronvs regular
frame reset on vsync
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
vsync
frame reset
reserved protected
eo_information
0 1 unsigned flag_overflow
no_define_value
t2armsel regular
timer #2 arm source select
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
tsetarm
opto-trig
hsync
vsync
field
exp1
ext. trig
soft trig
t2armpol regular
timer #2 arm source polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
high
low
t2armmsk regular
timer #2 arm mask
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
normal
mask
t2trglev regular
timer #2 trig on level
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
rising
falling
DIG_CLNKCTRL
Camera Link control
eo_information
6
rtrctl regular
router control
eo_information
0 4 unsigned flag_overflow
value = 0 ;
define_value
mode 1
mode 2
mode 3
rsvd 1
mode 4
mode 5
mode 6
rsvd 2
mode 1 swapped
rsvd 3
mode 2 swapped
rsvd 4
rsvd 5
rsvd 6
rsvd 7
rsvd 8
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
ccouten2 regular
cc output enable #2
eo_information
0 1 unsigned flag_overflow
value = ( CAMERA_LINK_AV & CLB_CCOUTEN2 ) ;
define_value
CCx disable
CCx enable
ccouten1 regular
cc output enable #1
eo_information
0 1 unsigned flag_overflow
value = ( CAMERA_LINK_AV & CLB_CCOUTEN1 ) ;
define_value
CCx disable
CCx enable
pixclksel regular
pixel clock select
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
CL #1
CL #1 DELAYED
CL #2
CL #2 DELAYED
CL USERCLK
RSVD_1
RSVD_2
RSVD_3
intsyncsel regular
internal synchronization selection
eo_information
0 1 unsigned flag_overflow
value = CAMERA_LINK_AV * (
( ( CLC_SYNC_SOURCE == 0 ) * ( CL_CHANNEL1_AV * CLC_ACTIVE_CH1 * 1 ) ) +
( ( CLC_SYNC_SOURCE == 1 ) * 0 ) +
( ( CLC_SYNC_SOURCE == 2 ) * 1 ) ) ;
define_value
Sync from chip #1
Sync from chip #2
DIG_GRABCTL2
Grab control 2
eo_information
5
vsyncsel regular
vertical synchronization selection
eo_information
0 3 unsigned flag_overflow
value = CLC_VSYNC_SEL ;
define_value
HVSYNSEL (edge sensitive)
LVDS trigger (level sensitive)
Opto-coupled trigger (level sensitive)
TTL trigger (level sensitive)
User bit 0 (level sensitive)
FVAL selected (level sensitive)
Reserved 1
Reserved 2
vsyncpol regular
vertical synchronization polarity
eo_information
0 1 unsigned flag_overflow
value = CLC_VSYNC_POL ;
define_value
Active high
Active low
hsyncsel regular
horizontal synchronization selection
eo_information
0 3 unsigned flag_overflow
value = CLC_HSYNC_SEL ;
define_value
HVSYNSEL (edge sensitive)
LVDS trigger (level sensitive)
Opto-coupled trigger (level sensitive)
TTL trigger (level sensitive)
User bit 1 (level sensitive)
LVAL selected (level sensitive)
Reserved 1
Reserved 2
hsyncpol regular
horizontal synchronization polarity
eo_information
0 1 unsigned flag_overflow
value = CLC_HSYNC_POL ;
define_value
Active high
Active low
reserved protected
eo_information
0 8 unsigned flag_overflow
no_define_value
SDIG_HTOTAL
eo_information
1
0 16 unsigned flag_overflow
value = 0x303 ;
no_define_value
SDIG_HSSYNC
eo_information
1
0 16 unsigned flag_overflow
value = 0xa ;
no_define_value
SDIG_HESYNC
eo_information
1
0 16 unsigned flag_overflow
value = 0x32 ;
no_define_value
SDIG_T2SCNT
eo_information
1
0 16 unsigned flag_overflow
value = 0x718 ;
no_define_value
SDIG_EXP2S
eo_information
1
0 16 unsigned flag_overflow
value = 0xae ;
no_define_value
SDIG_T2CTL
Timer 2 control register
eo_information
10
t2clksl regular
Timer 2 clock source select
eo_information
0 3 unsigned flag_overflow
value = 0x7 ;
define_value
DI trigger
Video trigger
HSYNC output
VSYNC output
Ouput exposure 1
User clock
Pixel clock
XTALCK
t2clkpol regular
Timer 2 clock polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Rising edge
Falling edge
t2trgsl regular
Timer 2 trigger source select
eo_information
0 3 unsigned flag_overflow
value = 0x6 ;
define_value
DI trigger
Video trigger
HSYNC output
VSYNC output
Field output
Exposure 1
Timer 2 count
T2SOFTRG
t2trgpol regular
Timer 2 trigger input polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Rising edge
Falling edge
t2onesht regular
default: set to continuous, t1cnten is also disabled by default
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Continuous mode
Monoshot
t2tsclr regular
Timer 2 trigger scaler selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
1 every 2
1 every 4
1 every 8
1 every 16
t2tpsclr regular
Timer 2 trigger prescaler
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Not prescaled
Prescaled
t2cmbn regular
Timer 2 combine selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
T2
T2 XOR T1
T2 AND T1
T2 OR T1
t2pol regular
Timer 2 output enable
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
High
Low
exp2 regular
Timer 2 exposure output
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
SDIG_GRABCTL
Grab control
eo_information
10
didir regular
Digital interface output buffers direction selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
A/D input
DI input
diouen regular
Digital interface output enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Buf not driving
Buffers enable
adrben regular
A/D red and blue channel enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
A/D tri-stated
Output enable
adgaen regular
A/D green and alpha channel enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
A/D tri-stated
Output enable
vcsel regular
Video csync selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
Alpha
Red
Green
Blue
hvsynsel regular
Horizontal and vertical sync selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
STRC hvsync
DI hvsync
validsel regular
Valid source selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
STRC blank
DI XVALID
dmode regular
Digitizer mode selection
eo_information
0 4 unsigned flag_overflow
value = 0xc ;
no_define_value
pclksel regular
Pixel clock selection
eo_information
0 3 unsigned flag_overflow
value = 0x7 ;
define_value
EXTCLK
USERCLK
STRC PLL ref
EXTCLKDL
VTRIG
XTRIG
Timer 1 exp
Timer 2 exp
ck0sl regular
Clock phase 0 selection
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
PLL by-passed
PLL phase 0
SDIG_GPCTL
Grab port control
eo_information
6
gbouen regular
grab module's output buffers' enable
eo_information
1 1 unsigned flag_overflow
value = 1 ;
define_value
Disabled
Enabled
gpinen regular
grab port input buffers' enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Input disabled
Input enabled
gpouen regular
grab port output buffers' enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Output disabled
Input enabled
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
bluesel regular
Base board blue channel selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Real blue
Pseudo blue
reserved2 protected
eo_information
0 10 unsigned flag_overflow
no_define_value
SDIG_HVRCTL
Horizontal vertical reset control
eo_information
9
hrstsel regular
Horizontal reset selection
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
Noise gated Csync
BT261 HSYNC
Digital interface
reserved
Digital trigger
Video trigger
Exposure #1 output
Exposure #2 output
hrstpol regular
Horizontal reset polarity
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No inversion
Polarity inversed
hrsten regular
Horizontal reset enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Hcnt load disabled
Hcnt load enabled
reserved protected
eo_information
0 3 unsigned flag_overflow
no_define_value
vrstsel regular
Vertical reset select
eo_information
0 3 unsigned flag_overflow
define_value
Detected vsync
BT261 vsync
DI vsync(XVSYNC)
DI hsync(XHSYNC)
Digital trigger
Video trigger
Exposure 1 ouput
Exposure 2 output
vrstpol regular
Vertical reset polarity
eo_information
0 1 unsigned flag_overflow
define_value
No inversion
Polarity inversed
vrsten regular
Vertical reset enable
eo_information
0 1 unsigned flag_overflow
define_value
Vcnt load disabled
Vcnt load enabled
algvrsl regular
Align vertical counter reset selection
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
Not realigned
Not realigned
Aligned HTOTAL
Align VRST-HRST
vrstngen regular
Vertical reset noise gate enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
NGating disabled
NGating enabled
SDIG_HSPLLF
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
SDIG_HEPLLF
eo_information
1
0 16 unsigned flag_overflow
value = 50 ;
no_define_value
SDIG_MISCTL
Miscellaneous control
eo_information
12
t1setarm regular
Timer 1 set arm
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Next no effect
Next start
t1armen regular
Timer 1 trigger arm enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Monoshot
Continuous
t1softrg regular
Timer 1 software trigger
default: do not send a soft trigger
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
t1cnten regular
Timer 1 counter enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Counter disabled
Counter enabled
t2setarm regular
Timer 2 set arm
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Next no effect
Next start
t2armen regular
Timer 2 trigger arm enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
Monoshot
Continuous
t2softrg regular
Timer 2 software trigger
default: do not send a soft trigger
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
t2cnten regular
Timer 2 count enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
Counter disabled
Counter enabled
reserved protected
eo_information
0 5 unsigned flag_overflow
no_define_value
softcap regular
Software capture control bit
default: do not send a soft capture
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
capten regular
Capture output enable
default: disable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
CAPTEN disabled
CAPTEN enabled
intclr regular
Interrupt clear
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
GRABINT enabled
GRABINT clr/disbl
SDIG_PSGCFG
PSG configuration
eo_information
10
intrlace regular
Interlace mode
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Non-interlaced
Interlaced
rmvhlfln regular
Remove half-line
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Display half lines
Remove half line
lnscan regular
Line scan mode
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Stop hcnt=htotal
frmscan regular
Frame scan mode
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Stop vcnt=vtotal
pclktst regular
Pixel clock test
eo_information
0 1 unsigned flag_overflow
define_value
No effect
PCLK test mode
vclpdfn regular
Vertical clamp define
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
S&E as defined
Reversed
vgrstmd regular
Vertical gate reset mode
eo_information
0 1 unsigned flag_overflow
define_value
Not affected by VRST
VRST will reset the gate
reserved1 protected
eo_information
0 1 unsigned flag_overflow
no_define_value
nbfscnd regular
Number of frame scanned
eo_information
0 2 unsigned flag_overflow
define_value
1 frame scanned
2 frames scanned
3 frames scanned
4 frames scanned
reserved2 protected
eo_information
0 6 unsigned flag_overflow
no_define_value
DAC8800LVL_ALPHAC
Alpha coarse level
eo_information
1
0 8 unsigned flag_overflow
value = 50 + ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_REDC
Red coarse level
eo_information
1
0 8 unsigned flag_overflow
value = 50 + ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_GREENC
Green coarse level
eo_information
1
0 8 unsigned flag_overflow
value = 50 + ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_BLUEC
Blue coarse level
eo_information
1
0 8 unsigned flag_overflow
value = 50 + ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_ALPHAF
Alpha fine level
eo_information
1
0 8 unsigned flag_overflow
value = 15 - ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_REDF
Red fine level
eo_information
1
0 8 unsigned flag_overflow
value = 15 - ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_GREENF
Green fine level
eo_information
1
0 8 unsigned flag_overflow
value = 15 - ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800LVL_BLUEF
Blue fine level
eo_information
1
0 8 unsigned flag_overflow
value = 15 - ( 10 * DEF_NTSC ) ;
no_define_value
DAC8800REF_ALPHAR
Alpha positive reference
eo_information
1
0 8 unsigned flag_overflow
value = 255 ;
no_define_value
DAC8800REF_REDR
Red positive reference
eo_information
1
0 8 unsigned flag_overflow
value = 255 ;
no_define_value
DAC8800REF_GREENR
Green positive reference
eo_information
1
0 8 unsigned flag_overflow
value = 255 ;
no_define_value
DAC8800REF_BLUER
Blue positive reference
eo_information
1
0 8 unsigned flag_overflow
value = 255 ;
no_define_value
DAC8800REF_NREF
Negative reference
eo_information
1
0 8 unsigned flag_overflow
value = 51 - ( 31 * DEF_NTSC ) ;
no_define_value
DAC8800REF_EXPFCTL
Used for test purposes
eo_information
1
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
DAC8800REF_EXPGCTL
Used for test purposes
eo_information
1
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
DAC8800REF_PLLFINE
PLL fine adjust voltage
eo_information
1
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
ICS1522REG0
Feedback divider
eo_information
1
0x04F 11 unsigned flag_overflow
value =
( ( PCK_CAM_R&G | PCK_CAM_REC ) *
DEF_PCK_FREQ / DEF_GRBSYSCLK * 182 * 4 * ( 1 +
( ( 1 * ( DEF_PCK_FREQ < 14000000 ) ) +
( 2 * ( DEF_PCK_FREQ < 6000000 ) ) +
( 4 * ( DEF_PCK_FREQ < 3000000 ) ) ) ) ) +
( ( PCK_CAM_GEN * ( ! PCK_CAM_R&G ) * PCK_INTDVED ) * 1024 ) +
( ( ! ( PCK_CAM_R&G | PCK_CAM_REC | ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) & PCK_INTDVED ) ) ) * 0x04F ) ;
no_define_value
ICS1522REG1
Feedback sync pulse
eo_information
1
0 11 unsigned flag_overflow
value = 0x30 ;
no_define_value
ICS1522REG2
Feedback sync pulse
eo_information
1
0 11 unsigned flag_overflow
value = 0x006 ;
no_define_value
ICS1522REG3
Reference register
eo_information
2
refdiv regular
Reference divider
eo_information
0 10 unsigned flag_overflow
value =
( ( PCK_CAM_R&G | PCK_CAM_REC ) * 182 ) +
( ( PCK_CAM_GEN * ( ! PCK_CAM_R&G ) * PCK_INTDVED ) * 256 ) +
( ( ! SYC_CAM_GEN ) * ( DEF_HTOTAL * DEF_GRBSYSCLK / DEF_PCK_FREQ ) & 0x3ff ) ;
no_define_value
refpol regular
Reference polarity
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
Positive egde
Negative edge
ICS1522REG4
Multiple purposes
eo_information
7
vco regular
VCO Gain
eo_information
4 3 unsigned flag_overflow
value = 4 + (
( ( PCK_CAM_R&G | PCK_CAM_REC ) *
( 1 * ( ! ( ( ( DEF_PCK_FREQ - 25000000 ) & 0x80000000 )
/ 0x80000000 ) ) ) ) +
( ( PCK_CAM_GEN * ( ! PCK_CAM_R&G ) * PCK_INTDVED ) *
( 1 * ( ! ( ( ( ( DEF_PCK_FREQ * ( 1 +
( 1 * ( ! ( ( ( PCK_INTDIVF - 1 ) & 0x80000000 ) / 0x80000000 ) ) ) +
( 2 * ( ! ( ( ( PCK_INTDIVF - 2 ) & 0x80000000 ) / 0x80000000 ) ) ) +
( 4 * ( ! ( ( ( PCK_INTDIVF - 3 ) & 0x80000000 ) / 0x80000000 ) ) ) ) )
- 25000000 ) & 0x80000000 ) / 0x80000000 ) ) ) ) +
( ( ! ( PCK_CAM_R&G | PCK_CAM_REC | ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) &
PCK_INTDVED ) ) ) *
( 1 * ( ! ( ( ( DEF_PCK_FREQ - 25000000 ) & 0x80000000 )
/ 0x80000000 ) ) ) ) ) ;
define_value
10 MHz/V
15 MHz/V
20 MHz/V
25 MHz/V
45 MHz/V
60 MHz/V
75 MHz/V
90 MHz/V
pfd regular
Phase frequency detector
eo_information
3 3 unsigned flag_overflow
value = 3 ;
define_value
0.2344 uA
0.9375 uA
3.7500 uA
15.000 uA
1.8750 uA
7.5000 uA
30.000 uA
120.00 uA
pden regular
Phase frequency detector enable
eo_information
1 1 unsigned flag_overflow
define_value
PFD disable
PFD enable
int_flt regular
Loop filter select
eo_information
1 1 unsigned flag_overflow
value = PCK_CAM_XCHG ;
define_value
External loop filter
Internal loop filter
intvco regular
VCO select
eo_information
1 1 unsigned flag_overflow
define_value
External VCO
Internal VCO
clksel regular
Feedback divider clock input select
eo_information
0 1 unsigned flag_overflow
define_value
VCO
Out1
one regular
Always set to 1
eo_information
1 1 unsigned flag_overflow
define_value
Zero
One
ICS1522REG5
Multiple purposes
eo_information
9
fbk_sel regular
Feedback select
eo_information
0 1 unsigned flag_overflow
value = PCK_CAM_XCHG ;
define_value
External feedback
Internal feedback
fbk_pol regular
External feedback polarity
eo_information
1 1 unsigned flag_overflow
value = 1 ;
define_value
Positive edge
Negative edge
add regular
Addition of 1 VCO cycle
eo_information
0 1 unsigned flag_overflow
define_value
No effect
Insert 1 cycle
swlw regular
Removal of 1 VCO cycle
eo_information
0 1 unsigned flag_overflow
define_value
No effect
Remove 1 cycle
pda regular
Output post-scaler
eo_information
3 2 unsigned flag_overflow
value =
( ( ! ( PCK_CAM_GEN * ( ! PCK_CAM_R&G ) ) ) *
( 3 -
( ( ( ( DEF_PCK_FREQ - 14000000 ) & 0x80000000 ) / 0x80000000 ) +
( ( ( DEF_PCK_FREQ - 6000000 ) & 0x80000000 ) / 0x80000000 ) +
( ( ( DEF_PCK_FREQ - 3000000 ) & 0x80000000 ) / 0x80000000 ) ) ) ) +
( ( PCK_CAM_GEN * ( ! PCK_CAM_R&G ) * PCK_INTDVED ) *
( 3 - ( PCK_INTDVED * PCK_INTDIVF ) ) ) ;
define_value
Divide by 8
Divide by 4
Divide by 2
Divide by 1
pdb regular
Feedback post-scaler
eo_information
3 2 unsigned flag_overflow
define_value
Divide by 8
Divide by 4
Divide by 2
Divide by 1
ldlg regular
Fine phase adjust lead/lag
eo_information
1 1 unsigned flag_overflow
define_value
Lag
Lead
fen regular
Fine adjust enable
eo_information
0 1 unsigned flag_overflow
define_value
Disable
Enable
one regular
Always set to 1
eo_information
1 1 unsigned flag_overflow
define_value
Zero
One
ICS1522REG6
Multiple purposes
eo_information
9
ldcnt regular
Load counter
eo_information
0 3 unsigned flag_overflow
define_value
3 1-pos, 0-neg
4 pos edge
4 neg edge
5 1-pos, 0-neg
6 pos edge
8 pos edge
8 neg edge
10 neg edge
omux1 regular
Out1 select
eo_information
1 1 unsigned flag_overflow
define_value
Load counter
Diff out 0
omux2 regular
Out2 select
eo_information
1 1 unsigned flag_overflow
define_value
Internal feedback
Diff out 90
omux3 regular
Out3 select
eo_information
1 1 unsigned flag_overflow
define_value
Feedback Sync lo
Diff out 180
omux4 regular
Out4 select
eo_information
1 1 unsigned flag_overflow
define_value
Feedback Sync hi
Diff out 270
dacrst regular
Output reset
eo_information
0 1 unsigned flag_overflow
define_value
Reset
Normal
auxen regular
Output test mode
eo_information
0 1 unsigned flag_overflow
define_value
Normal mode
Test mode
auxclk regular
Output clock in test mode
eo_information
0 1 unsigned flag_overflow
no_define_value
extref regular
XTAL/EXTREF input buffer
eo_information
1 1 unsigned flag_overflow
define_value
XTAL
EXTREF
SICS1522REG0
eo_information
1
0 16 unsigned flag_overflow
value = 0x4f ;
no_define_value
SICS1522REG1
eo_information
1
0 16 unsigned flag_overflow
value = 0x30 ;
no_define_value
SICS1522REG2
eo_information
1
0 16 unsigned flag_overflow
value = 0x6 ;
no_define_value
SICS1522REG3
eo_information
1
0 16 unsigned flag_overflow
value = 0x400 ;
no_define_value
SICS1522REG4
eo_information
1
0 16 unsigned flag_overflow
value = 0x775 ;
no_define_value
SICS1522REG5
eo_information
1
0 16 unsigned flag_overflow
value = 0x522 ;
no_define_value
SICS1522REG6
eo_information
1
0 16 unsigned flag_overflow
value = 0x4f8 ;
no_define_value
DS1020DLY
eo_information
1
0 8 unsigned flag_overflow
no_define_value
ICD2061PWRDWN
eo_information
1
0 4 unsigned flag_overflow
value = DEF_VAL0 ;
no_define_value
ICD2061CONTROL
eo_information
1
0 9 unsigned flag_overflow
value = DEF_VAL0 ;
no_define_value
INFO_XSIZE
Number of horizontal pixel (column)
eo_information
1
0 32 unsigned flag_overflow
value = ( DEF_NTSC * 0x2c0 ) || ( VDT_HACTIVE * DEF_XTAPS ) ;
no_define_value
INFO_YSIZE
Number of row.
eo_information
1
0 32 unsigned flag_overflow
value = VDT_VACTIVE * DEF_YTAPS ;
no_define_value
INFO_MODE
0 = non-interlaced, 1 = interlaced.
eo_information
2
interl regular
eo_information
0 1 unsigned flag_overflow
value = VDT_INTERL ;
define_value
Non interlaced
Interlaced
reserved protected
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_TYPE
This field tells what kind of camera it is.
1=Linescan, 2=Framescan, 3=Areascan, 4=Other
eo_information
4
camera_type regular
eo_information
0 3 unsigned flag_overflow
value = ( 1 * CT_LS ) || ( 2 * DEF_FRAMESCAN ) || ( 3 * CT_FS ) ;
define_value
Reserved
Linescan
Framescan
Areascan
Other
Reserved
Reserved
reserved
ntsc regular
Selection of NTSC
eo_information
0 1 unsigned flag_overflow
value = VDT_STD_NTSC & VDC_C_COLOR ;
define_value
NTSC inactive
NTSC selected
pal regular
Selection of PAL
eo_information
0 1 unsigned flag_overflow
value = VDT_STD_PAL & VDC_C_COLOR ;
define_value
PAL inactive
PAL selected
reserved protected
eo_information
0 27 unsigned flag_overflow
no_define_value
INFO_INPUT
Analog signal: 0 - 3, indicating the active channel.
Digital signal: 4=TTL signals, 5=RS-422 signals (w/module only).
eo_information
2
input regular
eo_information
0 3 unsigned flag_overflow
value = ( ( ( VDC_MONO | VDC_C_COLOR | VDC_RGB_COL | VDC_YUVVID )
* 0 ) + ( VDC_DIG * ( 4 * VDC_TTL + 5 * VDC_422 ) ) ) ;
define_value
Analog input
Reserved
Reserved
Reserved
Digital TTL
Digital RS-422
Reserved
Reserved
reserved protected
eo_information
0 29 unsigned flag_overflow
no_define_value
INFO_PIXCLK
Pixel clock rate.
eo_information
1
0 32 unsigned flag_overflow
value = DEF_PCK_FREQ ;
no_define_value
INFO_SAMPLEMODE
eo_information
2
mode regular
eo_information
0 2 unsigned flag_overflow
value =
( ( DEF_DMODE == 6 ) * 3 ) ||
( ( DEF_DMODE == 4 ) * 2 ) ||
( ( DEF_DMODE == 2 ) * 1 ) ||
( ( DEF_DMODE == 1 ) * 0 ) ;
define_value
4 channel 8 bit
2 channel 8 bit
1 channel 8 bit
1 channel 10 bit
reserved protected
eo_information
0 30 unsigned flag_overflow
no_define_value
INFO_CHANNEL
Select channel
eo_information
3
reserved protected
eo_information
0 16 unsigned flag_overflow
no_define_value
channel regular
eo_information
0x1 4 unsigned flag_overflow
value = ( ( CAMERA_LINK_AV == 0 ) *
( ( ( ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) & ( VDC_MONO | VDC_C_COLOR ) ) * (
( ( VDC_IN_CH0 == 1 ) * 0x1 ) +
( ( VDC_IN_CH1 == 1 ) * 0x2 ) +
( ( VDC_IN_CH2 == 1 ) * 0x4 ) +
( ( VDC_IN_CH3 == 1 ) * 0x8 ) ) ) +
( VDC_RGB_COL * 0x7 ) +
( VDC_RGB_ALPHA * 0xf ) +
( ( ( CT_CAMERA == 0 ) & ( CT_TAPS == 1 ) & ( VDC_MONO | VDC_C_COLOR ) ) *
( ( VDC_IN_CH0 * 0x1 ) + ( VDC_IN_CH2 * 0x2 ) ) ) +
( ( ( CT_CAMERA == 0 ) & ( CT_TAPS == 2 ) & ( VDC_MONO | VDC_C_COLOR ) ) *
( 0x1 ) ) +
( ( ( CT_CAMERA == 1 ) & ( CT_TAPS == 1 ) ) * 0x3 ) +
( ( ( CT_CAMERA == 1 ) & ( CT_TAPS == 0 ) ) * (
( ( VDC_IN_CH0 == 1 ) * 0x1 ) +
( ( VDC_IN_CH1 == 1 ) * 0x2 ) +
( ( VDC_IN_CH2 == 1 ) * 0x4 ) +
( ( VDC_IN_CH3 == 1 ) * 0x8 ) ) ) +
( ( CT_CAMERA == 2 ) * 0x7 ) +
( ( CT_CAMERA == 3 ) * 0xf ) ) )
+ ( ( CAMERA_LINK_AV == 1 ) *
( ( CL_CHANNEL0_AV * CLC_ACTIVE_CH0 * 0x1 )
+ ( CL_CHANNEL1_AV * CLC_ACTIVE_CH1 * 0x2 ) ) ) ;
define_value
No channel
0
1
0 + 1
2
0 + 2
1 + 2
0 + 1 + 2
3
0 + 3
1 + 3
0 + 1 + 3
2 + 3
0 + 2 + 3
1 + 2 + 3
0 + 1 + 2 + 3
reserved2 protected
eo_information
0 12 unsigned flag_overflow
no_define_value
INFO_BITSPERLOGCH
Width of logical channel
eo_information
1
8 32 unsigned flag_overflow
value = (
( VDC_WD8 * 8 ) +
( VDC_VID_WIDTH_10 * 10 ) +
( VDC_VID_WIDTH_12 * 12 ) +
( VDC_VID_WIDTH_14 * 14 ) +
( VDC_WD16 * 16 ) +
( VDC_WD24 * 24 ) +
( VDC_WD32 * 32 ) +
( VDC_WD64 * 64 )
) ;
no_define_value
INFO_TIMEMULTICH
Total clock cycles before all time-multiplexed channel of a camera are received
eo_information
1
1 32 unsigned flag_overflow
no_define_value
INFO_TIMEMULTIPIX
Total clock cycles before all time-multiplexed bytes of a pixel are received
eo_information
1
1 32 unsigned flag_overflow
no_define_value
INFO_PACKEDPIXELS
Identify packed RGB format
eo_information
2
pack regular
eo_information
0 1 unsigned flag_overflow
value = VDC_RGB_PACK ;
define_value
Not packed
Packed
reserved protected
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_SYNCGRABCHAN
Sync channel must follow the grab channel
eo_information
2
syncgrab regular
eo_information
0 1 unsigned flag_overflow
value = ! SYC_DIG || ( CAMERA_LINK_AV & ( CLC_SYNC_SOURCE == 0 ) ) ;
define_value
Sync don't follow grab
Sync follow grab channel
reserved protected
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_LUTBUFID
Lut buffer ID
eo_information
1
0 32 unsigned flag_overflow
no_define_value
INFO_LUTPROG
Lut to be programmed
eo_information
2
lutprog regular
eo_information
0 1 unsigned flag_overflow
define_value
Don't program LUT
Program LUT
reserved protected
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_T1DELAY
Timer 1 delay
eo_information
1
0 32 unsigned flag_overflow
value = DEF_DELAY_TIMER1 * DEF_TIMER1_ENABLE;
no_define_value
INFO_T2DELAY
Timer 2 delay
eo_information
1
0 32 unsigned flag_overflow
value = DEF_DELAY_TIMER2 * DEF_TIMER2_ENABLE;
no_define_value
INFO_TRIGSRC
Trigger source
eo_information
8
type regular
eo_information
0 3 unsigned flag_overflow
value = ( GRB_MD_SW_TRG * 0 ) + ( ( GRB_MD_HW_TRG & ( GRB_TRG_SIGNAL_DPORT | GRB_TRG_SIGNAL_APORT ) ) * 1 ) +
( ( GRB_MD_HW_TRG & ( GRB_TRG_SIGNAL_TIMER1 | GRB_TRG_SIGNAL_TIMER2 ) ) * 4 ) ;
define_value
Software
Video/Digital connector
Reserved
Reserved
Exposure1/Exposure2
Reserved
Reserved
Reserved
reserved1 protected
eo_information
0 13 unsigned flag_overflow
no_define_value
timer regular
eo_information
0 2 unsigned flag_overflow
value = ( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_TIMER1 ) * 1 ) +
( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_TIMER2 ) * 2 ) ;
define_value
Reserved
Timer 1
Timer 2
Reserved
reserved2 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
trigger regular
eo_information
0 2 unsigned flag_overflow
value = ( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_APORT ) * 1 ) +
( ( GRB_MD_HW_TRG & GRB_TRG_SIGNAL_DPORT ) * 2 ) ;
define_value
Reserved
Video connector
Digital connector
Reserved
reserved3 protected
eo_information
0 7 unsigned flag_overflow
no_define_value
no_capture regular
eo_information
0 1 unsigned flag_overflow
value = GRB_MD_CONT ;
define_value
Use a trigger
Don't use a trigger
reserved4 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
INFO_T1TRGSRC
Timer 1 trigger source
eo_information
8
type regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_W_TRG * (
( EXP_MD_SW * 0 ) +
( ( EXP_TRG_SIGNAL_APORT | EXP_TRG_SIGNAL_DPORT ) * 1 ) +
( EXP_MD_HSY * 2 ) +
( EXP_MD_VSY * 3 )
) ) +
( EXP_MD_PERD * 3 ) ;
define_value
Software
Video/Digital connector
VSync
HSync
reserved1 regular
eo_information
0 14 unsigned flag_overflow
value = EXP_MD_PERD * 0x3fff ;
no_define_value
timer regular
eo_information
0 2 unsigned flag_overflow
value = ( ( EXP_MD_W_TRG & EXP_TRG_SIGNAL_TIMER2 ) * 2 ) +
( EXP_MD_PERD * 3 ) ;
define_value
Reserved
Reserved
Timer 2
Reserved
reserved2 regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_PERD * 3 ) ;
no_define_value
trigger regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_PERD * 0x3 ) +
( EXP_MD_W_TRG * ( ( EXP_TRG_SIGNAL_APORT * 1 ) + ( EXP_TRG_SIGNAL_DPORT * 2 ) ) ) ;
define_value
Reserved
Video connector
Digital connector
Reserved
reserved3 regular
eo_information
0 7 unsigned flag_overflow
value = EXP_MD_PERD * 0x7f ;
no_define_value
no_timer2 regular
eo_information
0 1 unsigned flag_overflow
value = ( ! ( EXP_MD_W_TRG | EXP_MD_PERD ) ) +
( EXP_MD_PERD * 1 ) ;
define_value
Use trigger
No timer1 trigger
reserved4 regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_PERD * 0x3 ) ;
no_define_value
INFO_T2TRGSRC
Timer 2 trigger source
eo_information
8
type regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_W_TRG_2 * (
( EXP_MD_SW_2 * 0 ) +
( ( EXP_TRG_SIGNAL_2_APORT | EXP_TRG_SIGNAL_2_DPORT ) * 1 ) +
( EXP_MD_HSY_2 * 2 ) +
( EXP_MD_VSY_2 * 3 )
) ) +
( EXP_MD_PERD_2 * 3 ) ;
define_value
Software
Video/Digital connector
VSync
HSync
reserved1 regular
eo_information
0 14 unsigned flag_overflow
value = EXP_MD_PERD_2 * 0x3fff ;
no_define_value
timer regular
eo_information
0 2 unsigned flag_overflow
value = ( ( EXP_MD_W_TRG_2 & EXP_TRG_SIGNAL_2_TIMER1 ) * 1 ) +
( EXP_MD_PERD_2 * 3 ) ;
define_value
Reserved
Timer 1
Reserved
Reserved
reserved2 regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_PERD_2 * 3 ) ;
no_define_value
trigger regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_PERD_2 * 0x3 ) +
( EXP_MD_W_TRG_2 * ( ( EXP_TRG_SIGNAL_2_APORT * 1 ) + ( EXP_TRG_SIGNAL_2_DPORT * 2 ) ) ) ;
define_value
Reserved
Video connector
Digital connector
Reserved
reserved3 regular
eo_information
0 7 unsigned flag_overflow
value = EXP_MD_PERD_2 * 0x7f ;
no_define_value
no_timer2 regular
eo_information
0 1 unsigned flag_overflow
value = ( ! ( EXP_MD_W_TRG_2 | EXP_MD_PERD_2 ) ) +
( EXP_MD_PERD_2 * 1 ) ;
define_value
Use trigger
No timer2 trigger
reserved4 regular
eo_information
0 2 unsigned flag_overflow
value = ( EXP_MD_PERD_2 * 0x3 ) ;
no_define_value
INFO_CONTPCLK
Continuous clock
eo_information
2
continuous regular
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
Non-continuous clock
Continuous clock
ExtClkFreq regular
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_USRCLK0
User clock 0 frequency in hertz
eo_information
1
0 32 unsigned flag_overflow
value = ( DEF_MASTER * DEF_PCK_FREQ ) ||
( PCK_USE_OUT * ( PCK_OFREQDV ) ) ||
( ( PCK_ODIVF != 0 ) * ( PCK_OFREQDV ) ) ||
( EXP_ASY_CLK * EXP_CLK_FREQ ) ||
( EXP_ASY_CLK_2 * EXP_CLK_FREQ_2 ) ||
( ( ( DEF_PCK_FREQ % 15564000 ) != 0 ) * 15564000 ) ||
( DEF_PCK_FREQ + ( ( DEF_GRBSYSCLK - DEF_PCK_FREQ ) / 2.2 ) ) ;
no_define_value
INFO_USRCLK1
User clock 1 frequency in hertz
eo_information
1
0 32 unsigned flag_overflow
no_define_value
INFO_USRCLK2
User clock 2 frequency in hertz
eo_information
1
0 32 unsigned flag_overflow
no_define_value
INFO_USRCLKSEL
eo_information
2
select regular
eo_information
0 2 unsigned flag_overflow
value = 1 ;
define_value
Reserved
User clock 0
User clock 1
User clock 2
reserved protected
eo_information
0 30 unsigned flag_overflow
no_define_value
INFO_GRBSYSCLK
eo_information
1
0 32 unsigned flag_overflow
value = DEF_GRBSYSCLK ;
no_define_value
INFO_XTAPSPERCH
Non adjacent pixel on x
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( ( TAP_CONFIG == 17 ) | ( TAP_CONFIG == 51 ) |
( TAP_CONFIG == 5137 ) ) +
( ( TAP_CONFIG == 85 ) * 3 ) ;
no_define_value
INFO_YTAPSPERCH
Non adjacent pixel on y
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( ( TAP_CONFIG == 1025 ) | ( TAP_CONFIG == 3075 ) |
( TAP_CONFIG == 5137 ) ) +
( ( TAP_CONFIG == 9473 ) * 3 ) ;
no_define_value
INFO_XTAPSPERCHADJ
Adjacent pixel on x
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( ( TAP_CONFIG == 3 ) | ( TAP_CONFIG == 51 ) |
( TAP_CONFIG == 3075 ) ) +
( ( TAP_CONFIG == 15 ) * 3 ) ;
no_define_value
INFO_YTAPSPERCHADJ
Adjacent pixel on y
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( TAP_CONFIG == 129 ) +
( ( TAP_CONFIG == 897 ) * 3 ) ;
no_define_value
INFO_CLAMP
Generate clamp signal
eo_information
2
clamp regular
eo_information
0 2 unsigned flag_overflow
value = VDC_DIG | ( DEF_CLAMP_MARGIN == 0 ) ;
define_value
Clamp active
Clamp inactive
Clamp auto
Reserved
reserved protected
eo_information
0 30 unsigned flag_overflow
no_define_value
INFO_T1CLKSRC
The allowed clock source for the timer 1
eo_information
9
ditrig regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_CLOCK_DITRIG ) ) ;
define_value
Cannot select
Can select
vitrig regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_CLOCK_VTRIG ) ) ;
define_value
Cannot select
Can select
ohsync regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_CLOCK_HSYNC ) ) ;
define_value
Cannot select
Can select
ovsync regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_CLOCK_VSYNC ) ) ;
define_value
Cannot select
Can select
oexp2 regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_CLOCK_TIMER2 ) ) ;
define_value
Cannot select
Can select
usrclk regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_ASY_CLK ) ) ;
define_value
Cannot select
Can select
pixclk regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_SYN_CLK ) ) ;
define_value
Cannot select
Can select
xtalclk regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER1_ENABLE & ( ! EXP_CLOCK_CRYSTAL ) ) ;
define_value
Cannot select
Can select
reserved protected
eo_information
0 24 unsigned flag_overflow
no_define_value
INFO_T2CLKSRC
The allowed clock source for the timer 2
eo_information
9
ditrig regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_CLOCK_2_DITRIG ) ) ;
define_value
Cannot select
Can select
vitrig regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_CLOCK_2_VTRIG ) ) ;
define_value
Cannot select
Can select
ohsync regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_CLOCK_2_HSYNC ) ) ;
define_value
Cannot select
Can select
ovsync regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_CLOCK_2_VSYNC ) ) ;
define_value
Cannot select
Can select
oexp1 regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_CLOCK_2_TIMER1 ) ) ;
define_value
Cannot select
Can select
usrclk regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_ASY_CLK_2 ) ) ;
define_value
Cannot select
Can select
pixclk regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_SYN_CLK_2 ) ) ;
define_value
Cannot select
Can select
xtalclk regular
eo_information
0 1 unsigned flag_overflow
value = ! ( DEF_TIMER2_ENABLE & ( ! EXP_CLOCK_2_CRYSTAL ) ) ;
define_value
Cannot select
Can select
reserved protected
eo_information
0 24 unsigned flag_overflow
no_define_value
INFO_T1EXPMOD
Indicates if software can modify the timer 1 output timings
eo_information
2
modif regular
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
FALSE
TRUE
reserved protected
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_T2EXPMOD
Indicates if software can modify the timer 2 output timings
eo_information
2
modif regular
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
FALSE
TRUE
reserved protected
eo_information
0 31 unsigned flag_overflow
no_define_value
INFO_XYSIZEMOD
Indicates if the X and Y size of a frame can be modified
eo_information
2
modify regular
eo_information
0 2 unsigned flag_overflow
value = 1 + 2 ;
define_value
Can't modify X and Y size
Can modify X size
Can modify Y size
Can modify X and Y size
reserved protected
eo_information
0 30 unsigned flag_overflow
no_define_value
INFO_SPIXCLK
Pixel clock in hertz to which the PLL must be locked
eo_information
1
0 32 unsigned flag_overflow
value = 0xbb3d98 ;
no_define_value
INFO_MISC
eo_information
12
grabport regular
eo_information
0 1 unsigned flag_overflow
value = DEF_GRABPORT_ACTIVE ;
define_value
Grabport 2 active
Grabport 1 active
useeeprom regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Do not use EEPROM
Use EEPROM
proglut regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Default LUT
Program specific LUT
palette regular
eo_information
0 5 unsigned flag_overflow
value = 0 ;
no_define_value
pllmethod regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Old PLL procedure
New PLL procedure
swprelock regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No S/W prelock
SW prelock
simultrig regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Default
Use VSYNC
skipdaclimit regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Default
Skip DAC Limit validation
grabresync regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Don't resync grab register
Resync grab register
disablePLLCheck regular
eo_information
0 1 unsigned flag_overflow
value = DEF_TIMER1_ENABLE ;
define_value
enable PLL check
disable PLL check
FastRefLoad regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Disable Fast Reference Load (default)
Enable Fast Reference Load
reserved protected
eo_information
0 17 unsigned flag_overflow
no_define_value
INFO_LINEDELAY
Number of lines of offset between 3 channels of a color line scan
eo_information
4
first_line_delay regular
eo_information
0 14 unsigned flag_overflow
no_define_value
second_line_delay regular
eo_information
0 14 unsigned flag_overflow
no_define_value
channel_order regular
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
RGB
RBG
GRB
GBR
BGR
BRG
reserved
reserved
reserved regular
eo_information
0 1 unsigned flag_overflow
no_define_value
INFO_CLCONFIGMODE
Camera Link configuration mode
eo_information
4
channel0 regular
Channel 0 configuration mode
eo_information
0 4 unsigned flag_overflow
value = DEF_CL_MODE_CH0 ;
define_value
B1 1x8 bits (A)
B2 1x10-16 bits (BA)
B3 2x8 bits (A, B)
B4 2x10-12 bits (BA, BC)
B5 3x8 bits RGB (A, B, C)
M1 2x8 bits (A, D)
M2 2x10-16 bits (BA, ED)
M3 2x10-16 bits (BA, DC)
M4 4x8 bits (A, B, D, E)
M5 4x8 bits (A, B, C, D)
reserved
reserved
reserved
reserved
reserved
reserved
channel1 regular
Channel 1 configuration mode
eo_information
0 4 unsigned flag_overflow
value = DEF_CL_MODE_CH1 ;
define_value
B1 1x8 bits (D)
B2 1x10-16 bits (ED)
B3 2x8 bits (D, E)
B4 2x10-12 bits (ED, EF)
B5 3x8 bits RGB (D, E, F)
M1 2x8 bits (A, D)
M2 2x10-16 bits (BA, ED)
M3 2x10-16 bits (BA, DC)
M4 4x8 bits (A, B, D, E)
M5 4x8 bits (A, B, C, D)
reserved
reserved
reserved
reserved
reserved
reserved
swap_mode regular
Data swapping
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
No swapping
B0 B1 B2 B3 => B1 B0 B3 B2
reserved
reserved
reserved protected
eo_information
0 22 unsigned flag_overflow
no_define_value
VIAGREG_GHCOUNT
To be removed
eo_information
1
0 32 unsigned flag_overflow
no_define_value
VIAGREG_GVCOUNT
To be removed
eo_information
1
0 32 unsigned flag_overflow
no_define_value
VIAGREG_GHSCLNG
Horizontal scaling HANDLE BY SW
eo_information
3
ghsclng_ghsubfac protected
eo_information
0 4 unsigned flag_overflow
no_define_value
ghsclng_ghzoom protected
eo_information
0 2 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 2 unsigned flag_overflow
no_define_value
VIAGREG_GHTOTAL
Horizontal total
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x2c0 ) || ( ( VDT_HTOTAL - 2 ) * DEF_VIAHMULTIPLY ) ;
no_define_value
VIAGREG_GHWSTART
Horizontal window start
eo_information
1
0 16 unsigned flag_overflow
value = ( ! DEF_NTSC ) *
( ( VDT_HSYNC + VDT_HBPORCH ) - ( DEF_LATENCY_FPORCH * VDT_HSYNC ) +
( DEF_CASE_3 * ( 7 + SYC_CAM_LATENCY ) ) + ( DEF_CASE_5 * SYC_CAM_LATENCY ) ) * DEF_VIAHMULTIPLY ;
no_define_value
VIAGREG_GHWSTOP
Horizontal window stop
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x2bf ) ||
( ( ( VDT_HTOTAL - VDT_HFPORCH ) - ( DEF_LATENCY_FPORCH * VDT_HSYNC )
+ ( DEF_CASE_3 * ( 7 + SYC_CAM_LATENCY ) ) + ( DEF_CASE_5 * SYC_CAM_LATENCY ) ) * DEF_VIAHMULTIPLY ) - 1 ;
no_define_value
VIAGREG_GLNINT
Line interrupt HANDLE BY SW
eo_information
1
0 16 unsigned flag_overflow
no_define_value
VIAGREG_GPIXFMT
Pixel formatter HANDLE BY SW
eo_information
8
gpixfmt_gstfmt protected
eo_information
0 3 unsigned flag_overflow
no_define_value
gpixfmt_gtsize protected
eo_information
0 4 unsigned flag_overflow
no_define_value
gpixfmt_gbitchnl protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gpixfmt_gnbchnl protected
eo_information
0 2 unsigned flag_overflow
no_define_value
gpixfmt_gcolor protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gpixfmt_gbtxtrct protected
eo_information
0 2 unsigned flag_overflow
no_define_value
gpixfmt_gfmtcvr protected
eo_information
0 1 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 2 unsigned flag_overflow
no_define_value
VIAGREG_GRABCTRL
Grab control register
eo_information
21
grabctrl_grabadis protected
SW default: grab operation specified by other grabctrl bits
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_grabsen protected
SW default: continuous grab disabled
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_gsnpsht protected
SW default: grab based on grabsen
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_ghrtrg regular
default: ignore /ihsync until GHTOTAL is reached
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
Ignore IHSYNC/
Start a new field/frame on IHSYNC/
grabctrl_gvrtrg regular
default: ignore /ivsync until GVTOTAL is reached
eo_information
0 1 unsigned flag_overflow
value = ! CT_LS ;
define_value
Ignore IVSYNC/
Start a new field/frame on IVSYNC/
grabctrl_igvalid regular
default: consider only iclk cycles with ivalid active
eo_information
0 1 unsigned flag_overflow
value = ! DEF_NTSC ;
define_value
Use IVALID
Ignore IVALID
grabctrl_gcptmd regular
default: ignore icapture line
eo_information
0 2 unsigned flag_overflow
value = ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) * 3 ;
define_value
Ignore ICAPTURE
Rising edge
Grab if high
Rising edge then reset
grabctrl_gscnmd regular
eo_information
0 2 unsigned flag_overflow
value = ( ( 1 * VDT_INTERL ) + ( 2 * CT_LS ) ) ;
define_value
Progressive scan mode
Interlaced video mode
Line grab mode
Reserved
grabctrl_gregudt regular
eo_information
0 3 unsigned flag_overflow
value = ( ( CT_LS | ( VDT_NINTRL & ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) ) ) * 7 ) ||
( ( ( ! CT_LS ) & VDT_NINTRL ) * 6 ) ||
(
( ( VDT_INTERL & CT_FS & ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) & GRB_START_ODD ) * 0 ) +
( ( VDT_INTERL & CT_FS & ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) & GRB_START_EVEN ) * 1 ) +
( ( VDT_INTERL & CT_FS & ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) & GRB_START_ANY ) * 2 )
) ;
define_value
Start odd
Start even
Start any
Grab odd
Grab even
Grab one field
Grab one frame
Grab one frame
grabctrl_gfldpol regular
default: odd fields are identified by ifield low
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Odd fields are low
Odd fields are high
grabctrl_gintlad protected
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_glnrv protected
default: grab from left to right
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_ghsmode regular
default: horizontal reference on rising iclk when /ihsync is low
eo_information
0 2 unsigned flag_overflow
value = ( ( ! DEF_LATENCY_FPORCH ) * ( 1 - ( ( ( SYC_DIG & SYC_H_OUT ) * SYC_H_ONEG )
+ ( ( ! ( SYC_DIG & SYC_H_OUT ) ) * 1 ) ) ) ) +
(
( DEF_LATENCY_FPORCH ) * ( ( ( SYC_DIG & SYC_H_OUT ) * SYC_H_ONEG )
+ ( ( ! ( SYC_DIG & SYC_H_OUT ) ) * 1 ) )
) || ( DEF_CASE_4 * SYC_H_IPOS ) ;
define_value
IHSYNC/ low is reference
IHSYNC/ high is reference
Ignore IHSYNC/
Reserved
grabctrl_gvsmode regular
default: vertical reference on rising iclk when /ivsync is low
eo_information
0 1 unsigned flag_overflow
value = ( ( ! DEF_MASTER ) * ( 1 - ( ( ( SYC_DIG & SYC_V_OUT ) * SYC_V_ONEG )
+ ( ( ! ( SYC_DIG & SYC_V_OUT ) ) * 1 ) ) ) ) +
(
( DEF_MASTER ) * ( ( ( SYC_DIG & SYC_V_OUT ) * SYC_V_ONEG )
+ ( ( ! ( SYC_DIG & SYC_V_OUT ) ) * 1 ) )
) || ( DEF_CASE_4 * SYC_V_IPOS ) ;
define_value
IVSYNC/ low is reference
IVSYNC/ high is reference
grabctrl_gintdst protected
default: the MVP receives the grab interrupts
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_glinten protected
default: disable grab line interrupts
eo_information
0 2 unsigned flag_overflow
no_define_value
grabctrl_soginten protected
default: enable SoG interrupts
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_eoginten protected
default: enable EoG interrupts
eo_information
0 1 unsigned flag_overflow
no_define_value
grabctrl_ivldpol regular
default: use ivalid directly: ivalid is active high
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
IVALID is active high
IVALID is active low
IVALID is active high
IVALID is active low
grabctrl_grbsrc protected
default: source of grab is the grab port
eo_information
0 1 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 5 unsigned flag_overflow
no_define_value
VIAGREG_GVSCLNG
Vertical scaling HANDLE BY SW
eo_information
3
gvsclng_gvsubfac protected
eo_information
0 4 unsigned flag_overflow
no_define_value
gvsclng_gvzoom protected
eo_information
0 2 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 2 unsigned flag_overflow
no_define_value
VIAGREG_GVTOTAL
Vertical total
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x1e0 ) || ( VDT_VTOTAL - 1 ) ;
no_define_value
VIAGREG_GVWSTART
Vertical window start
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 1 ) ||
( ( CT_LS * 0 ) +
( ( ! CT_LS ) * ( VDT_VSYNC + VDT_VBPORCH - ( VDC_ANA & DEF_NON_CONT_VIDEO & ( ! DEF_MASTER ) ) + DEF_MASTER ) ) ) ;
no_define_value
VIAGREG_GVWSTOP
Vertical window stop
eo_information
1
0 16 unsigned flag_overflow
value = ( DEF_NTSC * 0x1e0 ) ||
( ( CT_LS * VDT_VACTIVE ) +
( ( ! CT_LS ) * ( VDT_VTOTAL - VDT_VFPORCH - ( VDC_ANA & DEF_NON_CONT_VIDEO & ( ! DEF_MASTER ) ) + DEF_MASTER ) ) - 1 ) ;
no_define_value
VIAGREG_GARPADDR
ARP list address HANDLE BY SW
eo_information
2
garpaddr_garpaddr protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GARPCTRL
ARP control register HANDLE BY SW
eo_information
4
garpctrl_garpen protected
eo_information
0 1 unsigned flag_overflow
no_define_value
garpctrl_garpwait protected
eo_information
0 1 unsigned flag_overflow
no_define_value
garpctrl_grlhmen protected
default: register list is stored in on-board memory
eo_information
0 1 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 5 unsigned flag_overflow
no_define_value
VIAGREG_GSTATUS
Grab status HANDLE BY SW
eo_information
7
gstatus_goverun protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gstatus_gfield protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gstatus_gcapture protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gstatus_gintovrn protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gstatus_gactive protected
eo_information
0 1 unsigned flag_overflow
no_define_value
gstatus_gpending protected
eo_information
0 1 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 2 unsigned flag_overflow
no_define_value
VIAGREG_GBLENGTH
Burst length HANDLE BY SW
eo_information
2
gblength_gblength protected
default: 0x7 = bytes, largest burst length
eo_information
7 3 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 5 unsigned flag_overflow
no_define_value
VIAGREG_GC1FOFF
Channel 1 frame offset HANDLE BY SW
eo_information
2
gc1foff_gc1foff protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GC1TOFF
Channel 1 tag offset HANDLE BY SW
eo_information
2
gc1toff_gc1toff protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GC2FOFF
Channel 2 frame offset HANDLE BY SW
eo_information
2
gc2foff_gc2foff protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GC2TOFF
Channel 2 tag offset HANDLE BY SW
eo_information
2
gc2toff_gc2toff protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GC3FOFF
Channel 3 frame offset HANDLE BY SW
eo_information
2
gc3foff_gc3foff protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GC3TOFF
Channel 3 tag offset HANDLE BY SW
eo_information
2
gc3toff_gc3toff protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GDWRTMSK
Display write mask HANDLE BY SW
eo_information
1
0 24 unsigned flag_overflow
no_define_value
VIAGREG_GFSTART
Frame start HANDLE BY SW
eo_information
2
gfstart_gfstart protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GLPITCH
Line pitch HANDLE BY SW
eo_information
2
glpitch_glpitch protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
VIAGREG_GTAGCTL
Tag control register HANDLE BY SW
eo_information
4
gtlpitch_gtagaddr protected
eo_information
0 26 unsigned flag_overflow
no_define_value
gtlpitch_gtagen protected
eo_information
0 2 unsigned flag_overflow
no_define_value
gtlpitch_gmcten protected
eo_information
0 1 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 3 unsigned flag_overflow
no_define_value
VIAGREG_GTLPITCH
Tag line pitch HANDLE BY SW
eo_information
2
gtlpitch_gtlpitch protected
eo_information
0 26 unsigned flag_overflow
no_define_value
reserved protected
Unused bits.
eo_information
0 6 unsigned flag_overflow
no_define_value
BT261_CMD_REG0
eo_information
4
clk_input_sel regular
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
TTL comp. OSC1
TTL comp. OSC1*
TTL comp. OSC2
TTL comp. OSC2*
ECL comp. OSC1-1*
ECL comp. OSC2-2*
reserved
reserved
sync_detect_sel regular
eo_information
2 2 unsigned flag_overflow
value = ( 1 * SYC_ANA ) +
( 3 * SYC_DIG ) ;
define_value
25 mV
50 mV
100 mV
125 mV
capture_strobe regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
hor_counter_ctrl regular
eo_information
1 2 unsigned flag_overflow
value = 1 ;
define_value
Reserved
Reset each ngCSYNC
Reset to 0 when HCOUNT
Two above mode
BT261_CMD_REG1
eo_information
8
phase_limit_en regular
eo_information
0 1 unsigned flag_overflow
define_value
inhibit phase limit
enable phase limit
phase_comp_in_sel regular
eo_information
0 1 unsigned flag_overflow
define_value
hsync pin
internal gen. hsync
reset_lock_stat_bit regular
eo_information
0 1 unsigned flag_overflow
define_value
reset status bit
inactive
hsync_out_disable regular
eo_information
1 1 unsigned flag_overflow
value = ( ! DEF_VAL5 ) * ( VDC_FROM_VCR | SYC_ANA | SYC_DIG ) ;
define_value
drive output
three-state output
vsync_out_disable regular
eo_information
0 1 unsigned flag_overflow
define_value
drive output
three-state output
csync_out_disable regular
eo_information
0 1 unsigned flag_overflow
define_value
drive output
three-state output
clock_out_disable regular
eo_information
0 1 unsigned flag_overflow
define_value
drive output
three-state output
interlaced_select regular
eo_information
0 1 unsigned flag_overflow
value = 1 ;
define_value
noninterlaced
interlaced
BT261_CMD_REG2
eo_information
4
pixel_clk_sel regular
eo_information
2 2 unsigned flag_overflow
value = 0 ;
define_value
OSC inputs
ext. pixel clock
OSC drive clock
reserved
lock_override regular
eo_information
0 1 unsigned flag_overflow
define_value
tell phase comp it's lock
Normal operation
pixel_clk_mask_en regular
eo_information
0 1 unsigned flag_overflow
define_value
continuous
stop at hcount
phase_lock_pix_cnt regular
eo_information
0xf 4 unsigned flag_overflow
value = 0 ;
no_define_value
BT261_CMD_REG3
eo_information
1
0x1 8 unsigned flag_overflow
value = 0 ;
no_define_value
BT261_VSYNC_SPL
eo_information
1
0 8 unsigned no_flag_overflow
no_define_value
BT261_OSC_COUNT_L
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_OSC_COUNT_H
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_HSYNC_STAL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_HSYNC_STAH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_HSYNC_STOL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_HSYNC_STOH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_CLAMP_STAL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_CLAMP_STAH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_CLAMP_STOL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_CLAMP_STOH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_ZERO_STAL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_ZERO_STAH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_ZERO_STOL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_ZERO_STOH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_FIELD_GT_STAL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_FIELD_GT_STAH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_FIELD_GT_STOL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_FIELD_GT_STOH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_NOISE_GT_STAL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_NOISE_GT_STAH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_NOISE_GT_STOL
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_NOISE_GT_STOH
eo_information
1
0 8 unsigned flag_overflow
no_define_value
BT261_HCOUNT_STAL
eo_information
1
0xFF 8 unsigned flag_overflow
value = 0 ;
no_define_value
BT261_HCOUNT_STAH
eo_information
1
0x0F 8 unsigned flag_overflow
value = 0 ;
no_define_value
DIMREG0
Digital interface module register
eo_information
4
camctrl2 regular
Camera control bit 2
eo_information
0 1 unsigned flag_overflow
value = USR_BIT_5_OTH0 ;
define_value
Off
On
camctrl1 regular
Camera control bit 1
eo_information
0 1 unsigned flag_overflow
value = USR_BIT_4_OTH0 ;
define_value
Off
On
camctrl0 regular
Camera control bit 0
eo_information
0 1 unsigned flag_overflow
value = USR_BIT_3_OTH0 ;
define_value
Off
On
reserved regular
eo_information
0 5 unsigned flag_overflow
value = 0 ;
no_define_value
[EOF]
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.