[INFO_FILE]
/////////////////////////////////////////////////
//
// MATROX CRONOS Info file
// For more informations refer to INFGUIDE.DOC
//
// REVISION HISTORY:
// 0007.5000.0000 - initial version.
// 0007.5004.0000 - Current PRELIMINARY
//
/////////////////////////////////////////////////
//
// **********************************************
// **********************************************
// SECTION #1: HEADER
// **********************************************
// **********************************************
// Generic product name line (CRONOS) = 47 caracters Max. including space for proper
// loading in Intellicam.
60BF 0007.5004.0000
CRONOS_PLUS
"Matrox CRONOS PLUS"
Information file for the CRONOS board.
//
//
// **********************************************
// **********************************************
// SECTION #2: NEW GENERAL PARAMETERS|MEMBERS
// **********************************************
// **********************************************
//
//
[NEW_GPARAM]
//
// OPTION = CRONOS PLUS
//
// =============================================
// Marc B Modification 99-12-09: Added new internal param.
//
//
GGEN_BOARD_TYPE ONE_VAL_PAR|BRD_OPT_ON|VOLATILE
//
board_specific_value
NO_STRING M_DEFAULT DUMMY_PAR OPTION no
eo_board_specific_value
//
eo_param
// --------------------------------------
// J.McC Modification : Added new param.
//
GGRB_RGB_PATH MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Advanced
RGB Grab Path
eo_param_info
//
board_specific_value
no M_DEFAULT GRB_RGB_PATH_FORCED GRB_RGB_PATH_FORCED_AV no
yes M_DEFAULT GRB_RGB_PATH_FORCED NO_BOPTION
eo_board_specific_value
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
//
GVDT_CL_USE_CAMERA_VALID MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GSYC_ANA_TYPE
//
valid = ( ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) & SYC_SEP ? ADDERROR[ERR_MONOSYNCSEP] ) ;
//
error_message
ERR_MONOSYNCSEP, "Separated sync not available."
eo_error_message
//
eo_param
// --------------------------------------
GSYC_ANA_CHANNEL
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GVDT_STANDARD
//
pagelinks = GVDC_VID_SIGNAL_STD.UPDATE + GVDL_PEDESTAL.UPDATE + GVDL_USE_DEFAULT.UPDATE ;
//
valid = ( ( ( VDL_AMPL != 700 ) | VDL_PEDEST ) ? ADDERROR[ERR_FIXED_PED_AMPL] :
( ( ! VDL_POS_SWG ) ? ADDERROR[ERR_FIXED_VOLTSWG] : 0 )
) ;
//
error_message
ERR_FIXED_PED_AMPL, "Decoder automatically adjusts pedestal and amplitude: Use default setting."
ERR_FIXED_VOLTSWG,"Negative and both voltage swing not available. Use Positive voltage swing."
eo_error_message
//
eo_param
//
//
//..............................
//valid = ( VDL_PEDEST & DEF_NTSC ? ADDERROR[ERR_FIXE_PEDESTAL_AMPL] :
// ( ( VDL_PEDEST & DEF_PAL ) ? ADDERROR[ERR_NO_PEDESTAL_AMPL] :
// ( DEF_VID_DEFAULT_CHANGED ? ADDERROR[ERR_VDL_USE_DEFVAL] :
// 0 ) )
// ) ;
//ERR_FIXE_PEDESTAL_AMPL, "Decoder automatically adjusts pedestal amplitude: Use default setting."
//ERR_NO_PEDESTAL_AMPL, "Pedestal NOT present in Pal & Secam. Use default setting."
//ERR_VDL_USE_DEFVAL, "Control of video voltage swing, amplitude and pedestal: Leave default values."
// --------------------------------------
GVDC_VID_SIGNAL_TYPE
//
pagelinks = GSYC_FORMAT ;
//
eo_param
// --------------------------------------
GVDC_VID_SIGNAL_STD
//
pagelinks = ( GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ) ;
//
eo_param
// --------------------------------------
GVDC_ANA_VID_CH
//
pagelinks = GSYC_ANA_TYPE.UPDATE ;
//
// SVHS avec ? canaux ????
//
valid = ( ( VDC_SVID & VDC_IN_CH0 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( VDC_SVID & VDC_IN_CH1 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( VDC_SVID & VDC_IN_CH2 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[1] ) :
( ( VDC_SVID & VDC_IN_CH3 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[1] ) :
( ( ( VDC_MONO | VDC_C_COLOR ) &
( ( VDC_IN_CH0 & VDC_IN_CH1 ) | ( VDC_IN_CH2 & VDC_IN_CH3 ) )
) ?
( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) : 1
) ) ) ) & ( ( ! VDC_SVID ) & DAT_ERROR )
) ;
//
eo_param
//
//
//..............................
//error_message
//ERR_VIDEO_NOT_AV_CH3, "Video NOT Available on Input Channel 3 in monochrome by RGB Path. Select Input 0-2."
//eo_error_message
// --------------------------------------
//
// Round the PCK_FREQ at 4 Decimals
GPCK_FREQUENCY
//
valid = (
( ( PCK_FREQ != 12272600 ) & ( PCK_FREQ != 14750000 ) )
? ADDERROR[ERR_STD_PCK_FREQ] : 0
) ;
//
error_message
ERR_STD_PCK_FREQ, "Digitizer supports standard pixel clock frequencies only: Use 12.2726Mhz (RS170/NTSC SQ Pixel) or 14.75Mhz (CCIR/PAL SQ Pixel) )."
//ERR_STD_PCK_FREQ, "Digitizer supports standard pixel clock frequencies only: Use 12.2726Mhz (RS170/NTSC SQ Pixel) or 14.75Mhz (CCIR/PAL SQ Pixel) or 13.5 Mhz (RS170/NTSC/CCIR/PAL Ccir601)."
eo_error_message
//
eo_param
//
//
//..............................
//pagelinks = GVDT_HORIZONTAL.UPDATE + GVDT_VERTICAL.UPDATE ;
//valid = (
// ( ( PCK_FREQ != 12272600 ) & ( PCK_FREQ != 14750000 ) & ( PCK_FREQ != 13500000 ) )
// ? ADDERROR[ERR_STD_PCK_FREQ] :
// (
// (
// ( ( DEF_VACTIVE_IN != 480 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 14750000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_VACTIVE] :
// (
// (
// ( ( DEF_VTOTAL_IN != 525 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( PCK_FREQ == 14750000 ) ) |
// ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_VTOTAL_IN != 625 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_VTOTAL] : 0 ) )
// ) ;
//ERR_VTOTAL, "Total vertical line count must be 525 (RS170/Ntsc SQ Pixel,Ccir601) or 625 (Ccir/Pal SQ Pixel,Ccir601)."
//ERR_VACTIVE, "Active vertical line count must be 480 (RS170/Ntsc SQ Pixel,Ccir601) or 576 (Ccir/Pal SQ Pixel,Ccir601)."
// --------------------------------------
GPCK_EXT_SIGNAL
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GVDT_TYPE
//
valid = ( VDT_NINTRL ? ADDERROR[ERR_NO_PROG_VID_AV] : 0 ) ;
//
error_message
ERR_NO_PROG_VID_AV, "Non-interlaced video not supported by the digitizer."
eo_error_message
//
eo_param
//
//
//..............................
//pagelinks = GPCK_FREQUENCY.UPDATE + GVDT_VERTICAL.UPDATE ;
//valid = (
// VDT_NINTRL ? ADDERROR[ERR_NO_PROG_VID_AV] :
// (
// (
// ( ( DEF_VACTIVE_IN != 480 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 14750000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_VACTIVE] :
// (
// (
// ( ( DEF_VTOTAL_IN != 525 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( PCK_FREQ == 14750000 ) ) |
// ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_VTOTAL_IN != 625 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_VTOTAL] : 0 ) )
// ) ;
//
//valid = ( VDT_NINTRL ? ADDERROR[ERR_NO_PROG_VID_AV] : 0 ) ;
// --------------------------------------
GVDC_ANA_VID_C_CH
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GVDL_PEDESTAL
//
pagelinks = GVDT_STANDARD.VALID ;
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GVDL_AMPLITUDE
//
pagelinks = GVDT_STANDARD.VALID ;
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GVDL_SWING
//
pagelinks = GVDT_STANDARD.VALID ;
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GVDL_BRIGHTNESS
//
pagelinks = GVDT_STANDARD.UPDATE ;
//
enable = ENABLE[1] ;
//
eo_param
// --------------------------------------
GVDL_CONTRAST
//
pagelinks = GVDT_STANDARD.UPDATE ;
//
enable = ENABLE[1] ;
//
eo_param
// --------------------------------------
GVDL_SATURATION
//
pagelinks = GVDT_STANDARD.UPDATE ;
//
enable = ENABLE[( VDC_C_COLOR || VDC_SVID )] ;
//
eo_param
//
//
//..............................
//enable = ENABLE[1] ;
// --------------------------------------
GVDL_HUE
//
pagelinks = GVDT_STANDARD.UPDATE ;
//
enable = ENABLE[( VDC_C_COLOR || VDC_SVID )] ;
//
eo_param
//
//
//..............................
//enable = ENABLE[1] ;
// --------------------------------------
GEXP_GEN_MODE
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
GEXP_GEN_MODE_2
//
enable = ENABLE[0] ;
//
eo_param
// --------------------------------------
// Si HEPVAL > HTOTAL => Erreur en cours !
//
GVDT_HORIZONTAL
//
pagelinks = GPCK_FREQUENCY.UPDATE + GVDT_VERTICAL.UPDATE ;
//
valid = (
DEF_MIN_HBP_CROPPING ? ADDERROR[ERR_MIN_HBP_CROPPING] :
( DEF_MAX_HBP_CROPPING ? ADDERROR[ERR_MAX_HBP_CROPPING] :
( DEF_MIN_HFP_CROPPING ? ADDERROR[ERR_MIN_HFP_CROPPING] :
( DEF_MAX_HFP_CROPPING ? ADDERROR[ERR_MAX_HFP_CROPPING] :
(
(
( ( DEF_HACTIVE_IN != 640 ) & ( PCK_FREQ == 12272600 ) ) |
( ( DEF_HACTIVE_IN != 768 ) & ( PCK_FREQ == 14750000 ) )
) ? ADDERROR[ERR_HACTIVE_SQPIX] :
(
(
( ( DEF_HTOTAL_IN != 780 ) & ( PCK_FREQ == 12272600 ) ) |
( ( DEF_HTOTAL_IN != 944 ) & ( PCK_FREQ == 14750000 ) )
) ? ADDERROR[ERR_HTOTAL_SQPIX] : 0 ) ) ) ) )
) ;
//
error_message
ERR_HTOTAL_SQPIX, "Total Horizontal pixels must be 780 (RS170/Ntsc) 944 (Ccir/Pal)."
ERR_HACTIVE_SQPIX, "Active Horizontal pixels must be 640 (RS170/Ntsc) 768 (Ccir/Pal)."
ERR_MIN_HBP_CROPPING, "Minimum horizontal back porch reached. Increase horizontal back porch."
ERR_MAX_HBP_CROPPING, "Maximum horizontal back porch reached. Decrease horizontal back porch."
ERR_MIN_HFP_CROPPING, "Minimum horizontal front porch reached. Increase horizontal front porch."
ERR_MAX_HFP_CROPPING, "Maximum horizontal front porch reached. Decrease horizontal front porch."
eo_error_message
//
eo_param
//
//
//..............................
//valid = (
// (
// ( ( DEF_HACTIVE_IN != 640 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_HACTIVE_IN != 768 ) & ( PCK_FREQ == 14750000 ) )
// ) ? ADDERROR[ERR_HACTIVE_SQPIX] :
// (
// ( ( DEF_HACTIVE_IN != 720 ) & ( PCK_FREQ == 13500000 ) )
// ? ADDERROR[ERR_HACTIVE_CCIR601PIX] :
// (
// (
// ( ( DEF_HTOTAL_IN != 780 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_HTOTAL_IN != 944 ) & ( PCK_FREQ == 14750000 ) )
// ) ? ADDERROR[ERR_HTOTAL_SQPIX] :
// (
// ( ( ( DEF_HTOTAL_IN != 858 ) & ( DEF_HTOTAL_IN != 864 ) ) & ( PCK_FREQ == 13500000 ) )
// ? ADDERROR[ERR_HTOTAL_CCIR601] :
// (
// (
// ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_MIXED_HV_SQCCIR601] : 0 ) ) ) )
// ) ;
// --------------------------------------
GVDT_VERTICAL
//
pagelinks = GPCK_FREQUENCY.UPDATE + GVDT_VERTICAL.UPDATE + GVDT_HORIZONTAL.UPDATE ;
//
valid = (
DEF_MIN_VBP_CROPPING ? ADDERROR[ERR_MIN_VBP_CROPPING] :
( DEF_MAX_VBP_CROPPING ? ADDERROR[ERR_MAX_VBP_CROPPING] :
( DEF_MIN_VFP_CROPPING ? ADDERROR[ERR_MIN_VFP_CROPPING] :
( DEF_MAX_VFP_CROPPING ? ADDERROR[ERR_MAX_VFP_CROPPING] :
(
(
( ( DEF_VACTIVE_IN != 480 ) & ( PCK_FREQ == 12272600 ) ) |
( ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 14750000 ) ) |
( ( DEF_VACTIVE_IN != 480 ) & ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 13500000 ) )
) ? ADDERROR[ERR_VACTIVE] :
(
(
( ( DEF_VTOTAL_IN != 525 ) & ( PCK_FREQ == 12272600 ) ) |
( ( DEF_VTOTAL_IN != 625 ) & ( PCK_FREQ == 14750000 ) ) |
( ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_VTOTAL_IN != 625 ) ) & ( PCK_FREQ == 13500000 ) )
) ? ADDERROR[ERR_VTOTAL] : 0 ) ) ) ) )
) ;
//
error_message
ERR_VTOTAL, "Total Vertical lines must be 525 (RS170/Ntsc) or 625 (Ccir/Pal)."
ERR_VACTIVE, "Active Vertical lines must be 480 (RS170/Ntsc) or 576 (Ccir/Pal)."
ERR_MIN_VBP_CROPPING, "Minimum vertical back porch reached. Increase vertical back porch."
ERR_MAX_VBP_CROPPING, "Maximum vertical back porch reached. Decrease vertical back porch."
ERR_MIN_VFP_CROPPING, "Minimum vertical front porch reached. Increase vertical front porch."
ERR_MAX_VFP_CROPPING, "Maximum vertical front porch reached. Decrease vertical front porch."
eo_error_message
//
eo_param
//
//
//..............................
//pagelinks = GVDC_ANA_VID_CH.VALID + GSYC_ANA_TYPE.VALID +
// GPCK_FREQUENCY.UPDATE + GVDT_VERTICAL.UPDATE + GVDT_HORIZONTAL.UPDATE ;
//valid = (
// (
// ( ( DEF_VACTIVE_IN != 480 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 14750000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_VACTIVE_IN != 576 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 480 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VACTIVE_IN != 576 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_VACTIVE] :
// (
// (
// ( ( DEF_VTOTAL_IN != 525 ) & ( PCK_FREQ == 12272600 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( PCK_FREQ == 14750000 ) ) |
// ( ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_VTOTAL_IN != 625 ) ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 525 ) & ( DEF_HTOTAL_IN == 858 ) & ( PCK_FREQ == 13500000 ) ) |
// ( ( DEF_VTOTAL_IN != 625 ) & ( DEF_HTOTAL_IN == 864 ) & ( PCK_FREQ == 13500000 ) )
// ) ? ADDERROR[ERR_VTOTAL] : 0 )
// ) ;
// --------------------------------------
GVDC_VID_WIDTH
//
board_specific_value
"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV no|M_ARRAY_TWO
//"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV no|M_ARRAY_TWO
//"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV no|M_ARRAY_TWO
//"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV yes|M_ARRAY_TWO
//"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV yes|M_ARRAY_TWO
//"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV yes|M_ARRAY_TWO
eo_board_specific_value
//
enable = ENABLE[1] ;
//
eo_param
//
//
//..............................
//valid = ( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) ) ? ADDERROR[ERR_BAD_BUS_WIDTH] :
// 0 ) ;
//error_message
//ERR_BAD_BUS_WIDTH, "8-bit bus width only with analog video signal."
//eo_error_message
// --------------------------------------
GGRB_TRG_SIGNAL
//
board_specific_value
"digital port trigger ( TTL TRIG )" M_DEFAULT GRB_TRG_SIGNAL_DPORT GRB_TRG_SIGNAL_DPORT_AV yes
eo_board_specific_value
//
pagelinks = GGRB_TRG_FORMAT + GEXP_TRG_SIGNAL ;
//
eo_param
// --------------------------------------
GGRB_TRG_POL
//
enable = ENABLE[( ! GRB_MD_CONT )] ;
//
eo_param
//
//
//
//board_specific_value
//"level high trig" M_DEFAULT GRB_TRG_LEVEL_HIGH GRB_TRG_LEVEL_HIGH_AV yes
//"level low trig" M_DEFAULT GRB_TRG_LEVEL_LOW GRB_TRG_LEVEL_LOW_AV yes
//eo_board_specific_value
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #3: COMMON BOARD LIMITATION
// **********************************************
// **********************************************
//
//
[COMMON_OPTIONS]
//
// =============================================
//
// ******** Camera type ********
//
CT_LINE_SCAN_AVAIL no
CT_FRAM_SCAN_AVAIL yes
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 1 1 0 0 0 1 1
CT_MAX_CAMERA array 1 1 0 0 0 1 1
// ana dig
CT_MAX_CONNECTORS array 4 0
//
// --------------------------------------
//
// ******** Video signal format (analog/digital) ********
//
YUVVID_AVAIL no
YUV_INPUT_AVAIL no
CHROMI_IN_AVAIL no
// ** Information on clamping position available
CLAMP_SYNC_AVAIL no
CLAMP_BPORCH_AVAIL yes
CLAMP_FPORCH_AVAIL no
//
// --------------------------------------
//
// ******** Video timing ********
//
VID_STD_RS170_PCLK 12272600
VID_STD_RS170_HORZ array 58 60 22 640
//Change for start on ODD Field (First field of Frame)
VID_STD_RS170_VERT array 6 33 6 480
VID_STD_CCIR_PCLK 14750000
VID_STD_CCIR_HORZ array 69 85 22 768
VID_STD_CCIR_VERT array 5 42 2 576
//
// --------------------------------------
//
// ******** Pixel clock ********
//
//PCLK_IN_POS_POL_AV no
//PCLK_IN_NEG_POL_AV no
//PCLK_OUT_POS_POL_AV no
//PCLK_OUT_NEG_POL_AV no
//HIGH_SPEED_GRAB no
//
// --------------------------------------
//
// ******** Synchronisation signal ********
//
// ** Serration & equalization available on csync pulse
VDT_SERRATION_AVAIL no
VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_CAM_LATENCY_AV no
SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_C_IN_AV no
SYC_DIG_C_OUT_AV no
//
CSYN_IN_TTL_AV no
CSYN_IN_RS422_AV no
CSYN_OUT_TTL_AV no
CSYN_OUT_RS422_AV no
CSYN_IN_POS_POL_AV no
CSYN_IN_NEG_POL_AV no
CSYN_OUT_NEG_POL_AV no
CSYN_OUT_POS_POL_AV no
//
// ** Info about availability of analog csync separate from video signal,
// based on the video type signal. (to reflect the Bt812 limitation)
//
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//
// ** Information on sync. signal that must have the same direction **
// (both generated or both received, not one received other generated)
SYC_HVC_SAME_FORMAT yes
SYC_HS&VS_MUST_SDIR yes
SYC_HS&CS_MUST_SDIR yes
SYC_VS&CS_MUST_SDIR yes
//
// ** Information if a sync. signal may be in and out at the same time.
//
SYC_HSY_MAY_I&O no
SYC_VSY_MAY_I&O no
SYC_CSY_MAY_I&O no
SYC_ANAL_O_DIGVID_AV no
//
// --------------------------------------
//
// ******** Exposure ********
//
// ** Exposure asynchronous clock signal information **
EXP_ASY_CLK_AV no
//
// ** Asynchr. clock frequency (in Hz) ** USERCLK
EXP_ASY_CLK_FREQ 25000000
//
EXP_ASY_CLK_AV_2 no
//
// ** Asynchr. clock frequency (in Hz) ** USERCLK
EXP_ASY_CLK_FREQ_2 25000000
//
//
//EXP_CLOCK_HSYNC_AV no
//value = VDT_HSYNC_FREQ ;
//EXP_CLOCK_2_HSYNC_AV no
//value = VDT_HSYNC_FREQ ;
//EXP_CLOCK_TIMER2_AV no
//value = ( EXP_CLOCK_TIMER2 * ( 1 / ( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) * ( 1 / EXP_CLK_FREQ_2 ) ) ) ) || 1 ;
//EXP_CLOCK_2_TIMER1_AV equ
//value = ( EXP_CLOCK_2_TIMER1 * ( 1 / ( ( EXP_OUT_T0 + EXP_OUT_T1 ) * ( 1 / EXP_CLK_FREQ ) ) ) ) || 1 ;
//
//EXP_SYN_CLK_MAX_FREQ 30000000
EXP_CLK_DVED_AV no
EXP_CLK_DVED_AV_2 no
EXP_CLK_MAXDIV_FACT 1
//
// --------------------------------------
//
// ******** none classified board options ********
//
SYC_ANA_IN_CH_AV array 1 1 1 1
RS_330_SUPPORTED no
VACTIVE_INTERL_EVEN no
//
// ** horizontal & vertical absolute maximum value **
// (be sure to give an absolute maximum, so keep a margin of safety
// from the maximum value found in the HW registers.)
// (Intellicam absolute maximum of 0xffffffff)
//
VDT_HORIZ_MAX_VAL 0x1000
VDT_VERT_MAX_VAL 0x1000
//
// ** Minimum timings state value (in pixel count)
// (based on HW limitation, pipeline, line buffer etc...)
//
VDT_HSY_CNT_MIN 0
VDT_HBP_CNT_MIN 0
VDT_HACT_CNT_MIN 0
VDT_HFP_CNT_MIN 0
VDT_HSY+HBP_CNT_MIN 0
VDT_VSY_CNT_MIN 0
VDT_VBP_CNT_MIN 0
VDT_VACT_CNT_MIN 0
VDT_VFP_CNT_MIN 0
VDT_VSY+VBP_CNT_MIN 0
//
// ** Vertical active value that must be a multiple value, based on
// the video type signal. analog digital
//--> Where does ON_DIG comes from????
//--> Other signal type as CCOL, RGB, SVID, YUV
VACT_MULTV_ON_DIG 1
VACT_MULTV_ON_MONO array 1 1
VACT_MULTV_ON_MONOHI array 1 1
//
// ** Horizontal active value that must be a multiple value, based on
// the video type signal.
HACT_MULTV_ON_DIG 1
HACT_MULTV_ON_MONO array 1 1
HACT_MULTV_ON_MONOHI array 1 1
//
VTOT_ARR_ON_MONO no
VTOT_ARR_ON_CCOL array 525 625
VTOT_ARR_ON_RGB no
VTOT_ARR_ON_SVID no
VTOT_ARR_ON_YUV no
VTOT_ARR_ON_MONOHI no
CLAMP_TIMING_MIN array 250 750 275
//
// =============================================
//
//
// **********************************************
// **********************************************
// SECTION #4: BOARD LIMITATION DESCRIPTION (A)
// **********************************************
// **********************************************
//
//
[OPTION]
CRONOS_PLUS
//
// Board Type : CRONOS
//
OPTION yes
//
// =============================================
// CRONOS
// ******** Video signal format (analog/digital) ********
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
//
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 0 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
SVID_INPUT_AVAIL array 0 1
RGB_INPUT_AVAIL array 0
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 120 2000
//ANA_VID_AMPL_LIMIT array 300 1999 => 300mV for MET2/MC limit sync detect
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VDC_VID_WIDTH_10_AV array 0 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
// --------------------------------------
// CRONOS
// ******** Pixel clock ********
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB no
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
//PLL_FREQ_LIMIT no
PLL_FREQ_LIMIT array 1000 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
//PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO no
PCLK_OUT_AV_O_CCOL no
PCLK_OUT_AV_O_RGB no
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI no
//
// --------------------------------------
// CRONOS
// ******** Synchronisation signal ********
//
SYC_REC&GEN_BY_CAM no
//SYC_ASEP_O_MONO_AV If value used => must be used in Common Option Section for Intellicam's interperter.
SYC_ASEP_O_CCOL_AV no
//
SYC_ASEP_O_RGB_AV no
//
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_V_OUT_AV no
HSYN_IN_TTL_AV no
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV no
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV no
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV no
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV no
HSYN_IN_NEG_POL_AV no
HSYN_OUT_POS_POL_AV no
HSYN_OUT_NEG_POL_AV no
VSYN_IN_POS_POL_AV no
VSYN_IN_NEG_POL_AV no
VSYN_OUT_POS_POL_AV no
VSYN_OUT_NEG_POL_AV no
//
// --------------------------------------
// CRONOS
// ******** Grab control ********
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV yes
//GRB_TRG_LEVEL_HIGH_AV yes
//GRB_TRG_LEVEL_LOW_AV yes
//GRB_TRG_SIGNAL_APORT_AV yes
//GRB_TRG_SIGNAL_HSDPORT_AV no
//GRB_TRG_SIGNAL_VSDPORT_AV no
//GRB_TRG_SIGNAL_TIMER2_AV no
//GRB_TRG_SIGNAL_TIMER1_AV no
//
// --------------------------------------
// CRONOS
// ******** Exposure control ********
//
EXP_NDEL_TRG_TTL_AV yes
EXP_NDEL_OUT_TTL_AV yes
//
// =============================================
//
//
// **********************************************
// **********************************************
// Section #5 : DEFINE VALUES
// **********************************************
// **********************************************
//
//
// N.B.
// DEFINE using in his equation other DEFINE(S) MUST be placed after these ones.
// Reason: DEFINE value must be updated by intellicam
// DEFINE utilisant dans son equation d'autre(s) DEFINE(s) doit etre toujours place apres ceux-ci.
// Raison : Valeur du DEFINE doit etre update par Intellicam
//
//
[DEFINE_VALUE]
//
// =============================================
// ******** Video Timings entered group ********
//
DEF_HTOTAL_IN
value = ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE + VDT_HFPORCH ) ;
//
// --------------------------------------
DEF_HACTIVE_IN
value = ( DEF_HTOTAL_IN - VDT_HSYNC - VDT_HBPORCH - VDT_HFPORCH ) ;
//
// --------------------------------------
DEF_VTOTAL_IN
value = ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) ;
//
// --------------------------------------
DEF_VACTIVE_IN
value = ( DEF_VTOTAL_IN - VDT_VSYNC - VDT_VBPORCH - VDT_VFPORCH ) ;
//
// --------------------------------------
// ******** Video Format group ********
//
DEF_NTSC
value = (
( ( PCK_FREQ == 12272600 ) * ( VDT_HTOTAL == 780 ) * ( VDT_VTOTAL == 525 ) ) +
( ( PCK_FREQ == 13500000 ) * ( VDT_HTOTAL == 858 ) * ( VDT_VTOTAL == 525 ) )
) ;
//
// --------------------------------------
DEF_PAL
value = (
( ( PCK_FREQ == 14750000 ) * ( VDT_HTOTAL == 944 ) * ( VDT_VTOTAL == 625 ) ) +
( ( PCK_FREQ == 13500000 ) * ( VDT_HTOTAL == 864 ) * ( VDT_VTOTAL == 625 ) )
) ;
//
// --------------------------------------
DEF_CCIR601
value = (
( PCK_FREQ == 13500000 ) *
(
( ( VDT_HTOTAL == 858 ) * ( VDT_VTOTAL == 525 ) ) ||
( ( VDT_HTOTAL == 864 ) * ( VDT_VTOTAL == 625 ) )
)
) ;
//
// --------------------------------------
// ******** Video Type group ********
//
DEF_MONO_CAM
value = VDC_MONO ;
//value = ( VDC_MONO | ( GRB_RGB_PATH_FORCED & VDC_MONO ) ) ;
//
// --------------------------------------
DEF_COLOR_CAM
value = ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID | VDC_RGB_COL ) ;
//
// --------------------------------------
// ******** Hor. Vert. validation group ********
//
DEF_VTOTAL_IN_NOTSTD
value = (
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 525 ) &
( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE + VDT_VFPORCH ) != 625 )
) ;
//
// --------------------------------------
DEF_MIN_HBP_CROPPING
// Don't remove the 1 from equation to patch Intellicam bug equation entries parser
value = (
( 1 ) *
( ( VDT_HSYNC + VDT_HBPORCH ) <= ( 112 + ( DEF_PAL * 31 ) ) )
) ;
//
// --------------------------------------
DEF_MAX_HBP_CROPPING
value = ( ( VDT_HSYNC + VDT_HBPORCH ) >= ( 140 + ( DEF_PAL * 36 ) ) ) ;
//
// --------------------------------------
DEF_MIN_HFP_CROPPING
value = ( VDT_HFPORCH < 1 ) ;
//
// --------------------------------------
DEF_MAX_HFP_CROPPING
// Don't remove the 1 from equation to patch Intellicam bug equation entries parser
value = (
( 1 ) *
( VDT_HFPORCH > ( 27 + ( DEF_PAL * 5 ) ) )
) ;
//
// --------------------------------------
DEF_MIN_VBP_CROPPING
value = ( ( VDT_VSYNC + VDT_VBPORCH ) <= ( 25 + ( DEF_PAL * 5 ) ) ) ;
//
// --------------------------------------
DEF_MAX_VBP_CROPPING
value = ( ( VDT_VSYNC + VDT_VBPORCH ) >= ( 45 + ( DEF_PAL * 4 ) ) ) ;
//
// --------------------------------------
DEF_MIN_VFP_CROPPING
value = ( VDT_VFPORCH < 1 ) ;
//
// --------------------------------------
DEF_MAX_VFP_CROPPING
value = ( VDT_VFPORCH > ( 19 - DEF_PAL ) ) ;
//
// =============================================
//
//
// **********************************************
// **********************************************
// Section #6 : BOARD REGISTER DEFINITION
// **********************************************
// **********************************************
//
//
[PARAMETER]
//
// =============================================
//
INFO_XSIZE
Horizontal image size
eo_information
1
640 12 unsigned flag_overflow
//
value = VDT_HACTIVE ;
//
no_define_value
//
// =============================================
//
INFO_YSIZE
Vertical image size
eo_information
1
480 12 unsigned flag_overflow
//
value = VDT_VACTIVE ;
//
no_define_value
//
// =============================================
//
INFO_MODE
Corona DCF software specification (INFO_MODE)
eo_information
5
// --------------------------------------
MaskInterlaced regular
Interlaced/Progressive Mode
eo_information
0 1 unsigned flag_overflow
//
value = (
VDT_INTERL ? 0 :
( VDT_NINTRL ? 1 :
0 )
) ;
//
define_value
0 : Camera Interlaced
1 : Camera non interlaced
// --------------------------------------
MaskVideo regular
Pulsar Compatibility
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
MaskColor regular
Monochrome/Color Mode
eo_information
0 1 unsigned flag_overflow
//
value = (
DEF_MONO_CAM ? 0 :
( DEF_COLOR_CAM ? 1 :
0 )
) ;
//
define_value
0 : Camera monochrome
1 : Camera color
// --------------------------------------
MaskRGB regular
Hardware Video Path
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
define_value
0 : Decoder path
1 : RGB path
// --------------------------------------
MaskYC regular
SVHS Camera Y/C
eo_information
0 1 unsigned flag_overflow
//
value = VDC_SVID ;
//
define_value
0 : Camera non YC
1 : Camera YC
//
// =============================================
//
INFO_TYPE
Video Scan Mode
eo_information
1
2 8 unsigned flag_overflow
//
value = 2 ;
//
no_define_value
// 1 : Line scan
// 2 : Frame scan
// 3 : Area scan
// 4 : Others
//
// =============================================
//
INFO_DEPTH
Pixel Width Size
eo_information
1
8 8 unsigned flag_overflow
//
value = ( VDC_WD8 ? 8 :
( VDC_VID_WIDTH_10 ? 10 : 8 )
) ;
//
no_define_value
//
// =============================================
//
INFO_BAND
Video Band Size
eo_information
1
1 8 unsigned flag_overflow
//
value = ( VDC_MONO ? 1 :
3
) ;
//
no_define_value
//1 : Mono
//3 : Color
//
// =============================================
//
INFO_INPUT
Input Channel Selected
eo_information
1
0 8 unsigned flag_overflow
//
value = (
( ( ( VDC_IN_CH2 || VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ) ? 1 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ? 2 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
0 ) )
) ;
//
no_define_value
//0 : Analog Channel 0
//1 : Analog Channel 1
//2 : Analog Channel 2
//3 : Analog Channel 3
//4 : Digital TTL
//5 : Digital 422
//
// =============================================
//
INFO_PIXCLK
Pixel clock frequency
eo_information
1
0 32 unsigned flag_overflow
//
value = PCK_FREQ ;
//
no_define_value
//
// =============================================
//
INFO_PIPELINE
?
eo_information
1
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
INFO_MODULE_422
Digital video and sync module
eo_information
1
0 32 unsigned flag_overflow
//
value = ( VDC_DIG ? 0x60f00 :
0 ) ;
//
no_define_value
//
// =============================================
//
INFO_CHANNEL
Corona DCF software specification (INFO_CHANNEL)
eo_information
2
// --------------------------------------
VideoSignal regular
eo_information
0 4 unsigned flag_overflow
//
// Modify also INFO_INPUT
// Channel Software Ex. svid Ch0=0,1 | Ch1=2,3
//
value = (
( ( ( VDC_IN_CH2 | VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ) ? 1 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ? 2 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
0 ) )
) ;
//
no_define_value
// --------------------------------------
VideoSync regular
eo_information
0 4 unsigned flag_overflow
//
value = (
( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ? 1 :
( ( ( ( VDC_IN_CH2 | VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ) ? 2 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
0 ) )
) ;
//
no_define_value
//
// =============================================
INFO_FORMAT
Input Video Type
eo_information
4
// --------------------------------------
Pal regular
eo_information
0 1 unsigned flag_overflow
//
value = DEF_PAL ;
//
no_define_value
// --------------------------------------
Ntsc regular
eo_information
0 1 unsigned flag_overflow
//
value = DEF_NTSC ;
//
no_define_value
// --------------------------------------
CCir601 regular
eo_information
0 1 unsigned flag_overflow
//
value = DEF_CCIR601 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 29 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
INFO_MIL_CHANNEL
Software Video Channel
eo_information
1
0 32 unsigned flag_overflow
//
value = (
( ( ( VDC_IN_CH2 | VDC_IN_CH3 ) & VDC_SVID ) || ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 ) ) ? 1 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 ) ? 2 :
( ( ( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH3 ) ? 3 :
0 ) )
) ;
//
no_define_value
//
// =============================================
//
INFO_MIL_CHANNEL_SYNC
Input Sync. Channel
eo_information
1
0 32 unsigned flag_overflow
//
value = (
( ( VDC_MONO || VDC_C_COLOR ) * VDC_IN_CH1 * SYC_COMP ) +
( ( VDC_MONO || VDC_C_COLOR ) * VDC_IN_CH2 * SYC_COMP * 2 ) +
( ( VDC_MONO || VDC_C_COLOR ) * VDC_IN_CH3 * SYC_COMP * 3 ) +
( ( VDC_SVID & ( VDC_IN_CH2 || VDC_IN_CH3 ) ) * SYC_COMP * 2 )
) ;
//
no_define_value
//
// =============================================
//
INFO_MIL_TRIGGER
Trigger Configuration
eo_information
3
// --------------------------------------
Trigger_Mode regular
eo_information
1 1 unsigned flag_overflow
//
value = ( GRB_MD_HW_TRG | GRB_MD_CONT ) ;
//
define_value
Software
Hardware
//
//
//..............................
//value = GRB_MD_HW_TRG ;
// --------------------------------------
Trigger_Polarity regular
eo_information
1 2 unsigned flag_overflow
//
value = (
( GRB_TRG_POS | GRB_MD_CONT ) +
( GRB_TRG_NEG * 2 )
) ;
//
define_value
Level Low
Rising Edge
Falling Edge
Level High
//
//
//..............................
//value = (
// GRB_TRG_POS +
// ( GRB_TRG_NEG * 2 )
// ) ;
//..............................
//value = (
// GRB_TRG_POS +
// ( GRB_TRG_NEG * 2 ) +
// ( GRB_TRG_LEVEL_HIGH * 3 )
// ) ;
// --------------------------------------
Trigger_Enable regular
eo_information
0 1 unsigned flag_overflow
//
value = ( GRB_MD_SW_TRG | GRB_MD_HW_TRG ) ;
//
define_value
Disabled
Enabled
//
// =============================================
//
// *********************************************
// SAA7130 Chip VIDEO(BEGIN)
// *********************************************
//
// =============================================
//
SAA7130_SRCTIMINGREF
Source Timing Reference
eo_information
5
// --------------------------------------
LineCnter regular
Line Center
eo_information
0 12 unsigned flag_overflow
//
value = ( 4 + ( 3 * DEF_NTSC ) ) ;
//
no_define_value
// --------------------------------------
HorizTrigEvent regular
Horizontal Trig Event
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VertTrigEvent regular
Vertical Trig Event
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
FieldPolaritySwitch regular
Field Polarity Switch
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 17 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_STARTPOINT
Start Point Path RGB
eo_information
4
// --------------------------------------
StartPnt_GreenPath regular
Start Point Green Path
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
StartPnt_BluePath regular
Start Point Blue Path
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
StartPnt_RedPath regular
Start Point Red Path
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_GREENPATH_GAMMA00_37
Green Path Gamma Curve 00-37
eo_information
4
// --------------------------------------
GreenPath_Gamma00_07 regular
Green Gamma Correction 0-7
eo_information
0 8 unsigned flag_overflow
//
value = 0x10 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma10_17 regular
Green Gamma Correction 10-17
eo_information
0 8 unsigned flag_overflow
//
value = 0x20 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma20_27 regular
Green Gamma Correction 20-27
eo_information
0 8 unsigned flag_overflow
//
value = 0x30 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma30_37 regular
Green Gamma Correction 30-37
eo_information
0 8 unsigned flag_overflow
//
value = 0x40 ;
//
no_define_value
//
// =============================================
//
SAA7130_GREENPATH_GAMMA40_77
Green Path Gamma Curve 40-77
eo_information
4
// --------------------------------------
GreenPath_Gamma40_47 regular
Green Gamma Correction 40-47
eo_information
0 8 unsigned flag_overflow
//
value = 0x50 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma50_57 regular
Green Gamma Correction 50-57
eo_information
0 8 unsigned flag_overflow
//
value = 0x60 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma60_67 regular
Green Gamma Correction 60-67
eo_information
0 8 unsigned flag_overflow
//
value = 0x70 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma70_77 regular
Green Gamma Correction 70-77
eo_information
0 8 unsigned flag_overflow
//
value = 0x80 ;
//
no_define_value
//
// =============================================
//
SAA7130_GREENPATH_GAMMA80_B7
Green Path Gamma Curve 80-B7
eo_information
4
// --------------------------------------
GreenPath_Gamma80_87 regular
Green Gamma Correction 80-87
eo_information
0 8 unsigned flag_overflow
//
value = 0x90 ;
//
no_define_value
// --------------------------------------
GreenPath_Gamma90_97 regular
Green Gamma Correction 90-97
eo_information
0 8 unsigned flag_overflow
//
value = 0xA0 ;
//
no_define_value
// --------------------------------------
GreenPath_GammaA0_A7 regular
Green Gamma Correction A0-A7
eo_information
0 8 unsigned flag_overflow
//
value = 0xB0 ;
//
no_define_value
// --------------------------------------
GreenPath_GammaB0_B7 regular
Green Gamma Correction B0-B7
eo_information
0 8 unsigned flag_overflow
//
value = 0xC0 ;
//
no_define_value
//
// =============================================
//
SAA7130_GREENPATH_GAMMAC0_F7
Green Path Gamma Curve C0-F7
eo_information
4
// --------------------------------------
GreenPath_GammaC0_C7 regular
Green Gamma Correction C0-C7
eo_information
0 8 unsigned flag_overflow
//
value = 0xD0 ;
//
no_define_value
// --------------------------------------
GreenPath_GammaD0_D7 regular
Green Gamma Correction D0-D7
eo_information
0 8 unsigned flag_overflow
//
value = 0xE0 ;
//
no_define_value
// --------------------------------------
GreenPath_GammaE0_E7 regular
Green Gamma Correction E0-E7
eo_information
0 8 unsigned flag_overflow
//
value = 0xF0 ;
//
no_define_value
// --------------------------------------
GreenPath_GammaF0_F7 regular
Green Gamma Correction F0-F7
eo_information
0 8 unsigned flag_overflow
//
value = 0xFF ;
//
no_define_value
//
// =============================================
//
SAA7130_BLUEPATH_GAMMA00_37
Green Path Gamma Curve 00-37
eo_information
4
// --------------------------------------
BluePath_Gamma00_07 regular
Blue Gamma Correction 0-7
eo_information
0 8 unsigned flag_overflow
//
value = 0x10 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma10_17 regular
Blue Gamma Correction 10-17
eo_information
0 8 unsigned flag_overflow
//
value = 0x20 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma20_27 regular
Blue Gamma Correction 20-27
eo_information
0 8 unsigned flag_overflow
//
value = 0x30 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma30_37 regular
Blue Gamma Correction 30-37
eo_information
0 8 unsigned flag_overflow
//
value = 0x40 ;
//
no_define_value
//
// =============================================
//
SAA7130_BLUEPATH_GAMMA40_77
Blue Path Gamma Curve 40-77
eo_information
4
// --------------------------------------
BluePath_Gamma40_47 regular
Blue Gamma Correction 40-47
eo_information
0 8 unsigned flag_overflow
//
value = 0x50 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma50_57 regular
Blue Gamma Correction 50-57
eo_information
0 8 unsigned flag_overflow
//
value = 0x60 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma60_67 regular
Blue Gamma Correction 60-67
eo_information
0 8 unsigned flag_overflow
//
value = 0x70 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma70_77 regular
Blue Gamma Correction 70-77
eo_information
0 8 unsigned flag_overflow
//
value = 0x80 ;
//
no_define_value
//
// =============================================
//
SAA7130_BLUEPATH_GAMMA80_B7
Blue Path Gamma Curve 80-B7
eo_information
4
// --------------------------------------
BluePath_Gamma80_87 regular
Blue Gamma Correction 80-87
eo_information
0 8 unsigned flag_overflow
//
value = 0x90 ;
//
no_define_value
// --------------------------------------
BluePath_Gamma90_97 regular
Blue Gamma Correction 90-97
eo_information
0 8 unsigned flag_overflow
//
value = 0xA0 ;
//
no_define_value
// --------------------------------------
BluePath_GammaA0_A7 regular
Blue Gamma Correction A0-A7
eo_information
0 8 unsigned flag_overflow
//
value = 0xB0 ;
//
no_define_value
// --------------------------------------
BluePath_GammaB0_B7 regular
Blue Gamma Correction B0-B7
eo_information
0 8 unsigned flag_overflow
//
value = 0xC0 ;
//
no_define_value
//
// =============================================
//
SAA7130_BLUEPATH_GAMMAC0_F7
Blue Path Gamma Curve C0-F7
eo_information
4
// --------------------------------------
BluePath_GammaC0_C7 regular
Blue Gamma Correction C0-C7
eo_information
0 8 unsigned flag_overflow
//
value = 0xD0 ;
//
no_define_value
// --------------------------------------
BluePath_GammaD0_D7 regular
Blue Gamma Correction D0-D7
eo_information
0 8 unsigned flag_overflow
//
value = 0xE0 ;
//
no_define_value
// --------------------------------------
BluePath_GammaE0_E7 regular
Blue Gamma Correction E0-E7
eo_information
0 8 unsigned flag_overflow
//
value = 0xF0 ;
//
no_define_value
// --------------------------------------
BluePath_GammaF0_F7 regular
Blue Gamma Correction F0-F7
eo_information
0 8 unsigned flag_overflow
//
value = 0xFF ;
//
no_define_value
//
// =============================================
//
SAA7130_REDPATH_GAMMA00_37
Red Path Gamma Curve 00-37
eo_information
4
// --------------------------------------
RedPath_Gamma00_07 regular
Red Gamma Correction 0-7
eo_information
0 8 unsigned flag_overflow
//
value = 0x10 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma10_17 regular
Red Gamma Correction 10-17
eo_information
0 8 unsigned flag_overflow
//
value = 0x20 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma20_27 regular
Red Gamma Correction 20-27
eo_information
0 8 unsigned flag_overflow
//
value = 0x30 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma30_37 regular
Red Gamma Correction 30-37
eo_information
0 8 unsigned flag_overflow
//
value = 0x40 ;
//
no_define_value
//
// =============================================
//
SAA7130_REDPATH_GAMMA40_77
Red Path Gamma Curve 40-77
eo_information
4
// --------------------------------------
RedPath_Gamma40_47 regular
Red Gamma Correction 40-47
eo_information
0 8 unsigned flag_overflow
//
value = 0x50 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma50_57 regular
Red Gamma Correction 50-57
eo_information
0 8 unsigned flag_overflow
//
value = 0x60 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma60_67 regular
Red Gamma Correction 60-67
eo_information
0 8 unsigned flag_overflow
//
value = 0x70 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma70_77 regular
Red Gamma Correction 70-77
eo_information
0 8 unsigned flag_overflow
//
value = 0x80 ;
//
no_define_value
//
// =============================================
//
SAA7130_REDPATH_GAMMA80_B7
Red Path Gamma Curve 80-B7
eo_information
4
// --------------------------------------
RedPath_Gamma80_87 regular
Red Gamma Correction 80-87
eo_information
0 8 unsigned flag_overflow
//
value = 0x90 ;
//
no_define_value
// --------------------------------------
RedPath_Gamma90_97 regular
Red Gamma Correction 90-97
eo_information
0 8 unsigned flag_overflow
//
value = 0xA0 ;
//
no_define_value
// --------------------------------------
RedPath_GammaA0_A7 regular
Red Gamma Correction A0-A7
eo_information
0 8 unsigned flag_overflow
//
value = 0xB0 ;
//
no_define_value
// --------------------------------------
RedPath_GammaB0_B7 regular
Red Gamma Correction B0-B7
eo_information
0 8 unsigned flag_overflow
//
value = 0xC0 ;
//
no_define_value
//
// =============================================
//
SAA7130_REDPATH_GAMMAC0_F7
Red Path Gamma Curve C0-F7
eo_information
4
// --------------------------------------
RedPath_GammaC0_C7 regular
Red Gamma Correction C0-C7
eo_information
0 8 unsigned flag_overflow
//
value = 0xD0 ;
//
no_define_value
// --------------------------------------
RedPath_GammaD0_D7 regular
Red Gamma Correction D0-D7
eo_information
0 8 unsigned flag_overflow
//
value = 0xE0 ;
//
no_define_value
// --------------------------------------
RedPath_GammaE0_E7 regular
Red Gamma Correction E0-E7
eo_information
0 8 unsigned flag_overflow
//
value = 0xF0 ;
//
no_define_value
// --------------------------------------
RedPath_GammaF0_F7 regular
Red Gamma Correction F0-F7
eo_information
0 8 unsigned flag_overflow
//
value = 0xFF ;
//
no_define_value
//
// =============================================
//
SAA7130_VBIHORIZWIN_TA
VBI Horizontal Input Window
eo_information
4
// --------------------------------------
VbiHorizWinStart regular
VBI Horizontal Input Window Start
eo_information
0 12 unsigned flag_overflow
//
value = (
( ( VDT_HSYNC + VDT_HBPORCH - 112 - ( 32 * DEF_PAL ) ) >= 0 ) *
(
VDT_HSYNC + VDT_HBPORCH - 112 - ( 32 * DEF_PAL ) + ( ( VDT_HSYNC + VDT_HBPORCH ) % 2 )
)
) ;
//value = ( 6 + ( DEF_PAL * 4 ) );
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VbiHorizWinStop regular
VBI Horizontal Input Window Stop
eo_information
0 12 unsigned flag_overflow
//
value = (
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - 38 - ( 164 * DEF_PAL ) +
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) % 2 )
) ;
//value = 0x2D0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VBIVERTWIN_TA
VBI Vertical Input Window
eo_information
4
// --------------------------------------
VbiVertWinStart regular
VBI Vertical Input Window Start
eo_information
0 12 unsigned flag_overflow
//
value = ( VDT_VSYNC + VDT_VBPORCH - 18 - ( 8 * DEF_PAL ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VbiVertWinStop regular
VBI Vertical Input Window Stop
eo_information
0 12 unsigned flag_overflow
//
value = ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 497 - ( 104 * DEF_PAL ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VBIHORIZOUT_TA
VBI Output Window
eo_information
4
// --------------------------------------
VbiHorizOutX regular
VBI Horizontal Output Length X
eo_information
0 12 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0x280 ) + ( DEF_PAL * 0x2D0 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VbiHorizOutY regular
VBI Horizontal Output Length Y
eo_information
0 12 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0xC ) + ( DEF_PAL * 0x10 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VIDHORIZWIN_TA
Video Horizontal Input Window
eo_information
4
// --------------------------------------
VidHorizWinStart regular
Video Horizontal Input Window Start
eo_information
0 12 unsigned flag_overflow
//
value = (
( ( VDT_HSYNC + VDT_HBPORCH - 112 - ( 32 * DEF_PAL ) ) >= 0 ) *
(
VDT_HSYNC + VDT_HBPORCH - 112 - ( 32 * DEF_PAL ) + ( ( VDT_HSYNC + VDT_HBPORCH ) % 2 )
)
) ;
//value = ( 6 + ( DEF_PAL * 4 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VidHorizWinStop regular
Video Horizontal Input Window Stop
eo_information
0 12 unsigned flag_overflow
//
value = (
VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - 38 - ( 164 * DEF_PAL ) +
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) % 2 )
) ;
//value = 0x2D0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VIDVERTWIN_TA
Video Vertical Input Window
eo_information
4
// --------------------------------------
VidVertWinStart regular
Video Vertical Input Window Start
eo_information
0 12 unsigned flag_overflow
//
value = ( VDT_VSYNC + VDT_VBPORCH - 16 - ( 8 * DEF_PAL ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VidVertWinStop regular
Video Vertical Input Window Stop
eo_information
0 12 unsigned flag_overflow
//
value = ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 257 - ( 55 * DEF_PAL ) ) ;
//value = ( ( DEF_NTSC * 0x106 ) + ( DEF_PAL * 0x137 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VIDPIXLINESOUT_TA
Video Number Pixels/Lines Output
eo_information
4
// --------------------------------------
VidNbPixelsOut regular
Video Number of Pixels at Output
eo_information
0 12 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0x280 ) + ( DEF_PAL * 0x300 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VidNbLinesOut regular
Video Number of Lines at Output
eo_information
0 12 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0xF0 ) + ( DEF_PAL * 0x120 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_PRESCALE_TA
Horizontal Prescaling
eo_information
11
// --------------------------------------
HorizPreScale regular
Horizontal Prescaling
eo_information
0 5 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
//
no_define_value
// --------------------------------------
PreScaleFilterLength regular
Prescale Filter Length
eo_information
0 5 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
//
no_define_value
// --------------------------------------
DCGainAdjust regular
DC Gain Adjust
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
PreScaleAccWeightFac regular
Prescale Acc Weigh Fac
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 4 unsigned flag_overflow
//
no_define_value
// --------------------------------------
PreFilterY regular
Pre Filter Luma
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
PreFilterC regular
Pre Filter Chroma
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VBIPreFilterY regular
VBI Pre Filter Luma
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VBIPreFilterC regular
VBI Pre Filter Chroma
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
SAA7130_BRIGHT_CONT_SAT_TA
Horizontal Prescaling
eo_information
4
// --------------------------------------
Luma_Brightness regular
Luma Brightness
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0x80 ) +
( ( ! VDL_USE_DEFVAL ) * VDL_BRGHT * 2.55 )
) & 0xFF
) ;
//
no_define_value
// --------------------------------------
Luma_Contrast regular
Luma Contrast
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0x40 ) +
( ( ! VDL_USE_DEFVAL ) * VDL_CONTR * 1.275 )
) & 0xFF
) ;
//
no_define_value
// --------------------------------------
Chroma_Saturation regular
Chroma Saturation
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0x40 ) +
( ( ! VDL_USE_DEFVAL ) * VDL_SATUR * 1.275 )
) & 0xFF
) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 8 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VBISCALE_VBIOFF_TA
VBI Horizontal Prescaling
eo_information
4
// --------------------------------------
VbiHorizScale regular
VBI Horizontal Scaling
eo_information
0 13 unsigned flag_overflow
//
value = 0x400 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
//
no_define_value
// --------------------------------------
VbiPhaseOffLuma regular
VBI Phase Offset Luma
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VbiPhaseOffChroma regular
VBI Phase Offset Chroma
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
SAA7130_SCALE_OFFSET_TA
Horizontal Offset Scaling
eo_information
4
// --------------------------------------
HorizScale regular
Horizontal Scaling
eo_information
0 13 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0x463 ) + ( DEF_PAL * 0x3A8 ) ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
//
no_define_value
// --------------------------------------
PhaseOffLuma regular
Phase Offset Luma
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
PhaseOffChroma regular
Phase Offset Chroma
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
SAA7130_VSCALE_VFILT_TA
Vertical Scaling and Filtering mode
eo_information
3
// --------------------------------------
VertScaleRatio regular
Vertical Scaling Ratio
eo_information
0 16 unsigned flag_overflow
//
value = 0x400 ;
//
no_define_value
// --------------------------------------
VertFilterMode regular
Vertical Filter Mode
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 15 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_VPHASEOFFSET_TA
Vertical Phase Offset
eo_information
2
// --------------------------------------
VertPhaseOffset_L regular
Vertical Phase Offset Low Portion
eo_information
0 16 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VertPhaseOffset_H regular
Vertical Phase Offset High Portion
eo_information
0 16 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
SAA7130_INCDLY_ANINCTL12
Increment Delay & Analog Input Controls 1 & 2
eo_information
16
// --------------------------------------
reserved regular
eo_information
0 8 unsigned flag_overflow
//
value = ( ( DEF_NTSC * 0x10 ) + ( DEF_PAL * 0x50 ) ) ;
//
no_define_value
// --------------------------------------
IncDly_PlineDly regular
Increment Delay PLine Delay
eo_information
0 4 unsigned flag_overflow
//
value = 8 ;
//
no_define_value
// --------------------------------------
IncDly_AgcHyst regular
Increment Delay AGC Hysteresis
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
IncDly_WhitePeak regular
Increment Delay White Peak
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
AnInCtl1_Mode regular
Analog Input Control 1 Mode
eo_information
0 4 unsigned flag_overflow
//
value = ( 8 * VDC_SVID ) ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 2 unsigned flag_overflow
//
no_define_value
// --------------------------------------
AnInCtl1_GainFilter regular
Analog Input Control 1 Gain Filter
eo_information
0 2 unsigned flag_overflow
//
value = 2 ;
//
// Changed for Linearity in test production
//value = 3 ;
no_define_value
// --------------------------------------
AnInCtl2_Gain1MSB regular
Analog Input Control 2 Gain 1 Most Significant Bits
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
AnInCtl2_Gain2MSB regular
Analog Input Control 2 Gain 2 Most Significant Bits
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
AnInCtl2_AGCFix regular
Analog Input Control 2 AGC Fixed
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
AnInCtl2_AGCHold regular
Analog Input Control 2 AGC Hold
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
AnInCtl2_CAGCPeak regular
Analog Input Control 2 CAG Peak
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
AnInCtl2_AVClamp regular
Analog Input Control 2 AV Clamp
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
AnInCtl2_Clamp regular
Analog Input Control 2 Clamping
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
AnInCtl2_Test regular
Analog Input Control 2 Test
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
SAA7130_ANINCTL34_HSYNC
Analog Input Controls 3 & 4 And Hsync
eo_information
4
// --------------------------------------
AnInCtl3_Gain1 regular
Analog Input Control 3 Gain 1
eo_information
0 8 unsigned flag_overflow
//
value = 0x90 ;
//
no_define_value
// --------------------------------------
AnInCtl4_Gain2 regular
Analog Input Control 4 Gain 2
eo_information
0 8 unsigned flag_overflow
//
value = 0x90 ;
//
no_define_value
// --------------------------------------
Hsync_Begin regular
Horizontal Sync Begin
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
Hsync_End regular
Horizontal Sync End
eo_information
0 8 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
//
// =============================================
//
SAA7130_SYNCCTL_LUMACTL
Synchronisation & Luma Controls
eo_information
13
// --------------------------------------
SyncCtl_Vsync regular
Synchronisation Control Vsync
eo_information
0 2 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
SyncCtl_HPll regular
Synchronisation Control PLL
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
SyncCtl_HPllMode regular
Synchronisation Control PLL Mode
eo_information
0 2 unsigned flag_overflow
//
value = 3 ;
//
no_define_value
// --------------------------------------
SyncCtl_FieldGen regular
Synchronisation Control Field Generation
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
SyncCtl_FieldRateSel regular
Synchronisation Control Field rate Selection
eo_information
0 1 unsigned flag_overflow
//
value = DEF_NTSC ;
//
no_define_value
// --------------------------------------
SyncCtl_FieldRateDet regular
Synchronisation Control Field Rate Detection
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
LumaCtl_LumaFilter regular
Luma Control Filter
eo_information
0 4 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
LumaCtl_ChromaNotch regular
Luma Control Chroma Notch Enabled
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
LumaCtl_VertDelay regular
Luma Control Vertical Delay
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
LumaCtl_LumaChroma regular
Luma Control Luma/Chroma Select
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
LumaCtl_Bypass regular
Luma Control Bypass
eo_information
0 1 unsigned flag_overflow
//
value = ( VDC_MONO | VDC_SVID ) ;
//
no_define_value
// --------------------------------------
Luma_Brightness regular
Luma Brightness
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0x80 ) +
( ( ! VDL_USE_DEFVAL ) * VDL_BRGHT * 2.55 )
) & 0xFF
) ;
//
no_define_value
// --------------------------------------
Luma_Contrast regular
Luma Contrast
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0x44 ) +
( ( ! VDL_USE_DEFVAL ) * VDL_CONTR * 1.275 )
) & 0xFF
) ;
//
no_define_value
//
// =============================================
//
SAA7130_CHROMACTL_SAT_HUE
Chroma Saturation & Hue Control
eo_information
10
// --------------------------------------
Saturation regular
SATURATION
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0x40 ) +
( ( ! VDL_USE_DEFVAL ) * VDL_SATUR * 1.275 )
) & 0xFF
) ;
//
no_define_value
// --------------------------------------
Hue regular
HUE
eo_information
0 8 unsigned flag_overflow
//
value = (
(
( VDL_USE_DEFVAL * 0 ) +
( ( ! VDL_USE_DEFVAL ) * ( VDL_HUE < 50 ) * ( ( VDL_HUE * ( 130 / 50 ) ) + 128 ) ) +
( ( ! VDL_USE_DEFVAL ) * ( VDL_HUE > 50 ) * ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) )
) & 0xFF
) ;
//
no_define_value
// --------------------------------------
CCtl1_ChromaComb regular
Chroma Control 1 Chroma Comb
eo_information
0 1 unsigned flag_overflow
//
value = VDC_C_COLOR ;
//
no_define_value
// --------------------------------------
CCtl1_AutoColorStdDet0 regular
Chroma Control 1 Auto Color Standard Detection
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
CCtl1_FastColorDetect regular
Chroma Control 1 Fast Color Detection
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
CCtl1_ChromaVertFilter regular
Chroma Control 1 Chroma Vertical Filter
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
CCtl1_ColorStd regular
Chroma Control 1 Color Standard Select
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
CCtl1_RstColorSubOscil regular
Chroma Control 1 Reset Color Subcarrier Oscillation
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
CGainCtl_ColorGain regular
Chroma Control Color Gain
eo_information
0 7 unsigned flag_overflow
//
value = ( 0x24 * ( ! VDC_MONO ) ) ;
//
no_define_value
// --------------------------------------
CGainCtl_ColorAGC regular
Chroma Control Color AGC
eo_information
0 1 unsigned flag_overflow
//
// To Kill Color in monochrome for the display buffer Mono or Color.
value = VDC_MONO ;
//
no_define_value
//
// =============================================
//
SAA7130_CHROMACTL2_DLYCTL
Chroma Control 2 & Delay Control
eo_information
10
// --------------------------------------
CCtl2_LumaChromaBandW regular
Chroma Control 2 Luma/Chroma Bandwidth Select
eo_information
0 3 unsigned flag_overflow
//
value = 6 ;
//
no_define_value
// --------------------------------------
CCtl2_ChromaBandWidth regular
Chroma Control 2 Chroma Bandwidth
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
CCtl2_ChromaOffsetV regular
Chroma Control 2 Chroma Offset V
eo_information
0 2 unsigned flag_overflow
//
// Changed to 3 unstead 0 for test linearity
value = 3 ;
//
no_define_value
// --------------------------------------
CCtl2_ChromaOffsetU regular
Chroma Control 2 Chroma Offset U
eo_information
0 2 unsigned flag_overflow
//
// Changed to 3 unstead 0 for test linearity
value = 3 ;
//
no_define_value
// --------------------------------------
DlyCtl_YDelay regular
Y Delay Control Select
eo_information
0 3 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
DlyCtl_HgateDelay regular
Horizontal Gate Delay Control
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
DlyCtl_ColorOn regular
Delay Control Color ON
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 16 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_ADC_VGATE
A/D & VGATE
eo_information
13
// --------------------------------------
ADC_ClkPhase regular
A/D Converter Clock Phase
eo_information
0 2 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
ADC_AutoColorStdDet1 regular
A/D Converter Auto Color Standard Detect 1
eo_information
0 1 unsigned flag_overflow
//
value = 1 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
//
no_define_value
// --------------------------------------
ADC_AnalogOutSel regular
A/D Converter Analog Output Select
eo_information
0 2 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
ADC_IncreaseGain regular
A/D Converter Increase Gain
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
ADC_RtcoProtocol regular
A/D Converter RTCO Protocol
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VGate_Begin regular
VGATE Begin
eo_information
0 8 unsigned flag_overflow
//
value = 0x11 ;
//
no_define_value
// --------------------------------------
VGate_End regular
VGATE End
eo_information
0 8 unsigned flag_overflow
//
value = 0xFE ;
//
no_define_value
// --------------------------------------
VGate_Begin8 regular
VGATE Begin Addr8
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VGate_End8 regular
VGATE End Addr8
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VGate_VgatePos2ndField regular
VGATE Positive Second Field
eo_information
0 1 unsigned flag_overflow
//
value = 0 ;
//
no_define_value
// --------------------------------------
VGate_ColorDetSpeed regular
VGATE Color Detection Speed
eo_information
0 3 unsigned flag_overflow
//
value = 3 ;
//
no_define_value
// --------------------------------------
reserved protected
eo_information
0 2 unsigned flag_overflow
//
no_define_value
//
// =============================================
//
SAA7130_RAWDATA
Raw Data Close Caption
eo_information
3
// --------------------------------------
RawData_Gain regular
Raw Data Gain
eo_information
0 8 unsigned flag_overflow
//
value = 0x40 ;
//
no_define_value
// --------------------------------------
RawData_Offset regular
Raw Data Offset
eo_information
0 8 unsigned flag_overflow
//
value = 0x80 ;
//
no_define_value
// --------------------------------------
reserved regular
eo_information
0 16 unsigned flag_overflow
//
value = 0x277 ;
//
no_define_value
//
//
//// ******************************************************************************
//// --------------------------------------
// regular
//
//eo_information
//0 5 unsigned flag_overflow
////
//value = 0 ;
////
//no_define_value
//
//
//// --------------------------------------
//reserved protected
//eo_information
//0 1 unsigned flag_overflow
////
//no_define_value
//
//
//
//SAA7130_STARTPOINT 0x00000000
//SAA7130_GREENPATH_GAMMA00_37 0x40302010
//SAA7130_GREENPATH_GAMMA40_77 0x80706050
//SAA7130_GREENPATH_GAMMA80_B7 0xC0B0A090
//SAA7130_GREENPATH_GAMMAC0_F7 0xFFF0E0D0
//SAA7130_BLUEPATH_GAMMA00_37 0x40302010
//SAA7130_BLUEPATH_GAMMA40_77 0x80706050
//SAA7130_BLUEPATH_GAMMA80_B7 0xC0B0A090
//SAA7130_BLUEPATH_GAMMAC0_F7 0xFFF0E0D0
//SAA7130_REDPATH_GAMMA00_37 0x40302010
//SAA7130_REDPATH_GAMMA40_77 0x80706050
//SAA7130_REDPATH_GAMMA80_B7 0xC0B0A090
//SAA7130_REDPATH_GAMMAC0_F7 0xFFF0E0D0
//SAA7130_VBIHORIZWIN_TA 0x02D00006
//SAA7130_VBIVERTWIN_TA 0x00170016
//SAA7130_VBIHORIZOUT_TA 0x000C0280
//SAA7130_VIDHORIZWIN_TA 0x02D00006
//SAA7130_VIDVERTWIN_TA 0x01070018
//SAA7130_VIDPIXLINESOUT_TA 0x00F00280
//SAA7130_PRESCALE_TA 0x00000001
//SAA7130_BRIGHT_CONT_SAT_TA 0x00404080
//SAA7130_VBISCALE_VBIOFF_TA 0x00000400
//SAA7130_SCALE_OFFSET_TA 0x00000463
//SAA7130_VSCALE_VFILT_TA 0x00000400
//SAA7130_VPHASEOFFSET_TA 0x00000000
//SAA7130_INCDLY_ANINCTL12 0x10C00810
//SAA7130_ANINCTL34_HSYNC 0x00009090
//SAA7130_SYNCCTL_LUMACTL 0x44804059
//SAA7130_CHROMACTL_SAT_HUE 0x33010040
//SAA7130_CHROMACTL2_DLYCTL 0x00000006
//SAA7130_ADC_VGATE 0x18FE1105
//SAA7130_RAWDATA 0x02778040
//// ******************************************************************************
//
// =============================================
//
// *********************************************
// SAA7130 Chip VIDEO(END)
// *********************************************
//
// =============================================
//
[EOF]
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.