[INFO_FILE]
60BF 0008.0000.0000
CORONA
"Matrox CORONA flexible color PCI frame grabber"
Information file for the CORONA board.
[NEW_GPARAM]
//
// FOR COLOUR HIGHLIGHTING, SELECT EDIT|PROPERTIES, AND SET TO C/C++
// AND OBTAIN THE USERTYPE.DAT FILE TO HAVE INFO-FILE KEYWORDS HIGHLIGHTED
//
///////////////////////////////////////////////////////////////////////////////
//
// REVISION HISTORY:
//
// 0002.0000.0000 - initial version.
//
//***********************************************
//***********************************************
// SECTION #1: HEADER
//***********************************************
//***********************************************
// With Digital Option
//
//***********************************************
//***********************************************
// SECTION #2: NEW GENERAL PARAMETERS|MEMBERS
//***********************************************
//***********************************************
//
// OPTION = CORONA
// OPTION_LC = CORONA_LC
// OPTION_DIG = CORONA_DIG
// OPTION_II = CORONA_II
// OPTION_II_DIG = CORONA_II_DIG
// OPTION_M2 = METEOR_II
// OPTION_MC = METEOR_II_MC
// OPTION_MC_DIG = METEOR_II_MC_DIG
// OPTION_M2_JPEG = METEOR_II_JPEG
// OPTION_MC_JPEG = METEOR_II_MC_JPEG
// OPTION_MC_JPEG_DIG = METEOR_II_MC_JPEG_DIG
// -----------------------------------------------
// Marc B Modification 99-12-09: Added new internal param.
//
GGEN_BOARD_TYPE ONE_VAL_PAR|BRD_OPT_ON|VOLATILE
board_specific_value
NO_STRING M_DEFAULT DUMMY_PAR OPTION no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_LC no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_DIG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_II no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_II_DIG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_M2 no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_MC no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_MC_DIG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_M2_JPEG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_MC_JPEG no
NO_STRING M_DEFAULT DUMMY_PAR OPTION_MC_JPEG_DIG no
eo_board_specific_value
eo_param
//
// -----------------------------------------------
// J.McC Modification : Added new param.
//
GGRB_RGB_PATH MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Advanced
RGB Grab Path
eo_param_info
board_specific_value
no M_DEFAULT GRB_RGB_PATH_FORCED GRB_RGB_PATH_FORCED_AV yes
yes M_DEFAULT GRB_RGB_PATH_FORCED NO_BOPTION
eo_board_specific_value
pagelinks = GPCK_EXT_SIGNAL.UPDATE ;
enable = ENABLE[DAT_ENABLED & VDC_MONO & ( OPTION | OPTION_DIG )] ;
//
valid = DAT_ERROR ||
(
( PCK_CAM_R&G & ( ! ( DEF_CORONA_II | OPTION | OPTION_DIG ) ) ) ? ADDERROR[ERR_PCK_R&G_NOTSUPPORTED] :
( ( PCK_CAM_R&G & DEF_CORONA & DEF_DEC_PATH ) ? ADDERROR[ERR_PCK_R&G_RGBPATHONLY] : 0 )
) ;
//
error_message
ERR_PCK_R&G_NOTSUPPORTED, "Option Not supported by the digitizer."
ERR_PCK_R&G_RGBPATHONLY, "Option supported ONLY by RGB Path. Select <Force RGB path> in Advanced page."
eo_error_message
//
//enable = ENABLE[DAT_ENABLED & VDC_MONO ] ;
//enable = ENABLE[DAT_ENABLED & ( VDC_MONO | VDC_RGB_COL )] ;
//pagelinks = ( ( ( ! DEF_60HZ_HV_TOTAL_STD ) & ( ! DEF_60HZ_HV_TOTAL_STD ) | VDC_RGB_COL
// ) ? GRB_RGB_PATH_FORCED.SETVALUE[1] :
// 0
// ) + GVDC_VID_SIGNAL_STD.UPDATE + GVDT_HORIZONTAL.UPDATE + GVDT_VERTICAL.UPDATE ;
eo_param
//
// -----------------------------------------------
// A.Mas Modification : Added new param. 02/14/02
//
GEXP_USE_OUT MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
param_info
Advanced page
Send a timer ouput to external circuit
eo_param_info
//
enable = ENABLE[( DEF_BT254_PATH * GRB_ACT_IMMEDIATE * VDT_NINTRL )] ;
//
board_specific_value
no M_DEFAULT EXP_USE_OUT EXP_USE_OUT_AV yes
yes M_DEFAULT EXP_USE_OUT NO_BOPTION
eo_board_specific_value
//
eo_param
// --------------------------------------
//
GVDT_CL_USE_CAMERA_VALID MULT_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
//
enable = ENABLE[0] ;
//
eo_param
//
// -----------------------------------------------
//CAMERA
//
GCT_CAMERA_NUMBER
//pagelinks = ( GTAP_CONFIGURATION.UPDATE + GTAP_CONFIGURATION.VALID + GCT_CAMERA_TAPS.UPDATE ) ;
enable = ENABLE[( ! ( DEF_METEOR_II | OPTION_LC ) )] ;
//
//enable = ENABLE[( ! ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) )] ;
//enable = ENABLE[( ! ( OPTION_M2 | OPTION_LC ) )] ;
valid = DAT_ERROR ||
( ( VDC_ANA & ( CT_TAPS == 1 ) & ( CT_CAMERA > 0 ) ) ? ADDERROR[ERR_TOOMANYCAM] ) ;
//valid = DAT_ERROR ||
// ( ( VDC_ANA & ( CT_TAPS > 0 ) & ( CT_CAMERA > 0 ) ) |
// ( VDC_DIG ) ? ADDERROR[ERR_TOOMANYCAM] ) ;
//valid = DAT_ERROR ||
// ( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) & ( CT_CAMERA > 0 ) ) ? ADDERROR[ERR_TOOMANYCAM] ) ;
error_message
ERR_TOOMANYCAM, "Cannot have more than 1 camera in analog when using more than one Tap"
eo_error_message
eo_param
//
GCT_CAMERA_TAPS
pagelinks = GTAP_CONFIGURATION.VALID ;
enable = ENABLE[( ! ( DEF_METEOR_II | OPTION_LC ) )] ;
//
//enable = ENABLE[( ! ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) )] ;
//enable = ENABLE[( ! ( OPTION_M2 | OPTION_LC ) )] ;
valid = DAT_ERROR ||
(
( VDC_ANA & ( GVDC_VID_WIDTH > ( 8 + ( 2 * DEF_CORONA_II ) ) )
& ( CT_TAPS > 0 )
) ? ADDERROR[ERR_TOOMANYTAPS] :
( ( OPTION_II_DIG & VDC_DIG & ( GVDC_VID_WIDTH > 10 ) )
? ADDERROR[ERR_MAXVIDWIDTH] : 0 )
) ;
//
//valid = DAT_ERROR ||
// (
// ( VDC_ANA & ( GVDC_VID_WIDTH > ( 8 + ( 2 * ( OPTION_II | OPTION_II_DIG ) ) ) )
// & ( CT_TAPS > 0 )
// ) ? ADDERROR[ERR_TOOMANYTAPS] :
// ( ( OPTION_II_DIG & VDC_DIG & ( GVDC_VID_WIDTH > 10 ) )
// ? ADDERROR[ERR_MAXVIDWIDTH] : 0 )
// ) ;
//valid = DAT_ERROR ||
// ( ( VDC_ANA & ( GVDC_VID_WIDTH > ( 8 + ( 2 * ( OPTION_II | OPTION_II_DIG ) ) ) )
// & ( CT_TAPS > 0 ) ) ? ADDERROR[ERR_TOOMANYTAPS] ) ;
error_message
ERR_TOOMANYTAPS, "Cannot have more than 1 tap in analog when using more than 1 camera"
ERR_MAXVIDWIDTH, "Maximum Digital Video input width in Dual Taps is 10 Bits. Select 8 or 10 Bits."
eo_error_message
eo_param
//
GTAP_CONFIGURATION NUM_PAR|ED_FLD_STRING|BRD_OPT_ON
param_info
Tap Configuration
Tap Destination(s)
eo_param_info
board_specific_value
NO_STRING M_DEFAULT TAP_CONFIG M_DEFAULT yes 1
eo_board_specific_value
pagelinks = ( GCT_CAMERA_NUMBER.UPDATE + GCT_CAMERA_TAPS.UPDATE ) ;
//
//pagelinks = ( ( TAP_CONFIG == 0 ) ? TAP_CONFIG.SETVALUE[1] :
// ( TAP_CONFIG == TAP_CONFIG )
// ) ;
//
valid = ( ( ! DEF_TAP_VALID ) & ( TAP_CONFIG != 0 ) ) ? ADDERROR[ERR_INVTAP] ;
enable = ENABLE[( ! ( DEF_METEOR_II | OPTION_LC ) ) & DEF_BT254_PATH] ;
//
//enable = ENABLE[( ! ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) & DEF_BT254_PATH] ;
//enable = ENABLE[( ! ( OPTION_M2 | OPTION_LC ) ) & DEF_BT254_PATH] ;
//enable = ENABLE[DEF_BT254_PATH] ;
error_message
ERR_INVTAP, "Invalid tap destinations selected. Tap not supported."
eo_error_message
eo_param
//
//
// -----------------------------------------------
//
GSYC_ANA_TYPE
valid = ( ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) & DEF_DEC_PATH & SYC_SEP ? ADDERROR[ERR_MONOSYNCSEP] ) ;
error_message
ERR_MONOSYNCSEP, "The video signal Selected with separated sync NOT available by the Decoder path."
eo_error_message
eo_param
// -----------------------------------------------
//
// Desabled BLOCK Sync in Digital
//
GSYC_BLOC_SYNC
enable = ENABLE[SYC_ANA & SYC_COMP & ( ! ( DEF_METEOR_II | OPTION_LC ) )] ;
//
//enable = ENABLE[SYC_ANA & SYC_COMP & ( ! ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) )] ;
//enable = ENABLE[SYC_ANA & SYC_COMP & ( ! ( OPTION_M2 | OPTION_LC ) )] ;
eo_param
//
// -----------------------------------------------
//
// Desabled EXTernal VSync in Analog
//
GSYC_EXT_VSYNC
enable = ENABLE[0] ;
eo_param
//
// -----------------------------------------------
//
// RGB component video signal and separated SYNC,
// the SYNC input channel is fixed.
GSYC_ANA_CHANNEL
//********************************************************
// Separate SYNC from VIDEO
//
enable = ENABLE[( ! ( ( VDC_RGB_COL & SYC_SEP ) | DEF_DIGITIZER_MASTER | SYC_DIG | VDC_SVID ) )] ;
eo_param
//
// -----------------------------------------------
GVDC_VID_SIGNAL_TYPE
pagelinks = GSYC_FORMAT.UPDATE ;
//pagelinks = GSYC_FORMAT + GCT_CAMERA_TAPS ;
eo_param
// -----------------------------------------------
// The following 2 equations are use to manage
// the input channel boxes in Y/C mode. This was
// not supported by intellicam...
// -----------------------------------------------
GVDT_STANDARD
pagelinks = GVDC_VID_SIGNAL_STD.UPDATE ;
eo_param
// -----------------------------------------------
GVDC_VID_SIGNAL_STD
pagelinks = ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH0 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH1 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH2 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
( ( ( VDC_C_COLOR | DEF_MONO_VIA_DEC ) & VDC_IN_CH3 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[1] ) :
( ( VDC_RGB_COL & VDC_IN_CH0 & DEF_BT254_PATH ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] ) :
1 ) ) ) )
) + GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ;
//
//pagelinks = ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH0 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH1 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH2 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | DEF_MONO_VIA_DEC ) & VDC_IN_CH3 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[1] ) :
// ( ( VDC_RGB_COL & VDC_IN_CH0 & DEF_BT254_PATH ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH1 & DEF_RGB_SYNC_ANA_ON_R ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH2 & DEF_RGB_SYNC_ANA_ON_R ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH0 & DEF_RGB_SYNC_ANA_ON_G ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH2 & DEF_RGB_SYNC_ANA_ON_G ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH0 & DEF_RGB_SYNC_ANA_ON_B ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH1 & DEF_RGB_SYNC_ANA_ON_B ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH0 & DEF_RGB_SYNC_ANA_SEP ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[1] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH1 & DEF_RGB_SYNC_ANA_SEP ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[1] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & VDC_IN_CH2 & DEF_RGB_SYNC_ANA_SEP ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[1] ) :
// 1 ) ) ) ) ) ) ) ) ) ) ) ) )
// ) + GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ;
//pagelinks = ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH0 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH1 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH2 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | DEF_MONO_VIA_DEC ) & VDC_IN_CH3 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[1] ) :
// ( ( VDC_RGB_COL & VDC_IN_CH0 & DEF_BT254_PATH ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( VDC_IN_CH0 | DEF_RGB_SYNC_ANA_ON_R ) ) ? VDC_IN_CH0.SETVALUE[1] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( VDC_IN_CH1 | DEF_RGB_SYNC_ANA_ON_G ) ) ? VDC_IN_CH1.SETVALUE[1] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( VDC_IN_CH2 | DEF_RGB_SYNC_ANA_ON_B ) ) ? VDC_IN_CH2.SETVALUE[1] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & DEF_RGB_SYNC_ANA_SEP ) ? VDC_IN_CH3.SETVALUE[1] :
// 1 ) ) ) ) ) ) ) )
// ) + GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ;
//
// Valid removed for new Drivers support in Dual Taps : Red-Green , Red-Blue , Green-Blue
valid = (
( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( ( VDC_IN_CH0 & DEF_RGB_SYNC_ANA_ON_R ) |
( VDC_IN_CH1 & DEF_RGB_SYNC_ANA_ON_G ) |
( VDC_IN_CH2 & DEF_RGB_SYNC_ANA_ON_B )
)
) ? ADDERROR[ERR_VIDSYNC_SAME_CHANNEL] : 0
) ;
//
//valid = ( ( DEF_MONO_VIA_RGB & ( CT_TAPS == 1 ) & ( VDC_IN_CH2 | VDC_IN_CH3 ) ) ? ADDERROR[ERR_BAD_CH_SELECTED_AV] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( ( VDC_IN_CH0 & DEF_RGB_SYNC_ANA_ON_R ) |
// ( VDC_IN_CH1 & DEF_RGB_SYNC_ANA_ON_G ) |
// ( VDC_IN_CH2 & DEF_RGB_SYNC_ANA_ON_B )
// )
// ) ? ADDERROR[ERR_VIDSYNC_SAME_CHANNEL] : 0 )
// ) ;
error_message
ERR_VIDSYNC_SAME_CHANNEL, "Video and Sync. selected are in the same channel in separate sync. Change Video or Sync. channel."
eo_error_message
//
//pagelinks = ( ( VDC_SVID & VDC_IN_CH0 & DEF_DEC_PATH ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] ) :
// ( ( VDC_SVID & VDC_IN_CH1 & DEF_DEC_PATH ) ? VDC_IN_CH0.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH2 & DEF_DEC_PATH ) ? VDC_IN_CH3.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH3 & DEF_DEC_PATH ) ? VDC_IN_CH2.SETVALUE[1] :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH0 ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH1 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | ( VDC_MONO & SYC_COMP & ( ! CT_TAPS ) ) ) & VDC_IN_CH2 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[1] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( ( VDC_C_COLOR | DEF_MONO_VIA_DEC ) & VDC_IN_CH3 ) ? ( VDC_IN_CH0.SETVALUE[0] + VDC_IN_CH1.SETVALUE[0] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[1] ) :
// ( ( CT_TAPS & ( VDC_IN_CH0 | VDC_IN_CH1 ) ) ? ( VDC_IN_CH0.SETVALUE[1] + VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] + VDC_IN_CH3.SETVALUE[0] ) :
// ( ( VDC_RGB_COL & VDC_IN_CH0 & DEF_BT254_PATH ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[1] ) :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( VDC_IN_CH0 | DEF_RGB_SYNC_ANA_ON_R ) ) ? VDC_IN_CH0.SETVALUE[1] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( VDC_IN_CH1 | DEF_RGB_SYNC_ANA_ON_G ) ) ? VDC_IN_CH1.SETVALUE[1] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & ( VDC_IN_CH2 | DEF_RGB_SYNC_ANA_ON_B ) ) ? VDC_IN_CH2.SETVALUE[1] :
// ( ( DEF_MONO_VIA_RGB & SYC_ANA & SYC_SEP & ( ! CT_TAPS ) & DEF_RGB_SYNC_ANA_SEP ) ? VDC_IN_CH3.SETVALUE[1] :
// 1 ) ) ) ) ) ) ) ) ) ) ) ) )
// ) + GVDT_STANDARD.UPDATE + GVDT_TYPE.UPDATE ;
eo_param
// -----------------------------------------------
GVDC_ANA_VID_CH
pagelinks = ( ( VDC_SVID & VDC_IN_CH0 & DEF_DEC_PATH ) ? ( VDC_IN_CH1.SETVALUE[1] + VDC_IN_CH2.SETVALUE[0] ) :
( ( VDC_SVID & VDC_IN_CH1 & DEF_DEC_PATH ) ? VDC_IN_CH0.SETVALUE[1] :
( ( VDC_SVID & VDC_IN_CH2 & DEF_DEC_PATH ) ? VDC_IN_CH3.SETVALUE[1] :
( ( VDC_SVID & VDC_IN_CH3 & DEF_DEC_PATH ) ? VDC_IN_CH2.SETVALUE[1] :
0 ) ) )
) + GVDC_VID_SIGNAL_STD.UPDATE + GVDT_STANDARD.UPDATE + GSYC_ANA_TYPE.UPDATE;
valid = (
( DEF_BT254_PATH & VDC_IN_CH3 & VDC_ANA & ( TAP_CONFIG == 1 ) ? ADDERROR[ERR_NO_VIDEO_CH_AV] :
( ( DEF_MONO_VIA_RGB & ( CT_TAPS == 1 ) & ( VDC_IN_CH2 | VDC_IN_CH3 ) ) ? ADDERROR[ERR_BAD_CH_SELECTED_AV] :
( ( ( ( VDC_IN_CH0 & VDC_IN_CH1 & VDC_IN_CH2 ) |
( VDC_IN_CH0 & VDC_IN_CH1 ) | ( VDC_IN_CH1 & VDC_IN_CH2 ) ) & DEF_MONO_VIA_RGB
& ( TAP_CONFIG == 1 ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) ? ADDERROR[ERR_TOOMUCH_CH_SELECTED_AV] :
0 ) ) ) & ( ! VDC_SVID )
) ;
//valid = (
// ( DEF_MONO_VIA_RGB & VDC_IN_CH3 & VDC_ANA & ( TAP_CONFIG == 1 ) ? ADDERROR[ERR_NO_VIDEO_CH_AV] :
// ( ( ( ( VDC_IN_CH0 & VDC_IN_CH1 & VDC_IN_CH2 ) |
// ( VDC_IN_CH0 & VDC_IN_CH1 ) | ( VDC_IN_CH1 & VDC_IN_CH2 ) ) & DEF_MONO_VIA_RGB
// & ( TAP_CONFIG == 1 ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) ? ADDERROR[ERR_TOOMUCH_CH_SELECTED_AV] :
// 1 ) ) & ( ( ! VDC_SVID ) & DAT_ERROR )
// ) ;
//
// ( ( DEF_MONO_VIA_RGB & ( CT_TAPS == 1 ) & ( TAP_CONFIG == 0x81 ) & ( VDC_IN_CH2 | VDC_IN_CH3 ) ) ? ADDERROR[ERR_BAD_CH_SELECTED_AV] :
//valid = (
// ( ( VDC_SVID & VDC_IN_CH0 & DEF_DEC_PATH ) ? VDC_IN_CH1.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH1 & DEF_DEC_PATH ) ? VDC_IN_CH0.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH2 & DEF_DEC_PATH ) ? VDC_IN_CH3.SETVALUE[1] :
// ( ( VDC_SVID & VDC_IN_CH3 & DEF_DEC_PATH ) ? VDC_IN_CH2.SETVALUE[1] :
// ( DEF_MONO_VIA_RGB & VDC_IN_CH3 & VDC_ANA & ( TAP_CONFIG == 1 ) ? ADDERROR[ERR_NO_VIDEO_CH_AV] :
// ( ( ( ( VDC_IN_CH0 & VDC_IN_CH1 & VDC_IN_CH2 ) |
// ( VDC_IN_CH0 & VDC_IN_CH1 ) | ( VDC_IN_CH1 & VDC_IN_CH2 ) ) & DEF_MONO_VIA_RGB
// & ( TAP_CONFIG == 1 ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) ? ADDERROR[ERR_TOOMUCH_CH_SELECTED_AV] :
// ( ( DEF_MONO_VIA_RGB & ( CT_TAPS == 1 ) & ( VDC_IN_CH2 | VDC_IN_CH3 ) ) ? ADDERROR[ERR_BAD_CH_SELECTED_AV] :
// 1 ) ) ) ) ) ) ) & ( ( ! VDC_SVID ) & DAT_ERROR )
// ) ;
//
error_message
ERR_BAD_CH_SELECTED_AV, "Only Input Channels 0 and 1 available when using 2 Taps Configuration"
ERR_NO_VIDEO_CH_AV, "Video NOT available on Input Channel 3 by RGB Path. ONLY Input Channels 0-2."
ERR_TOOMUCH_CH_SELECTED_AV, " Only one Video Channel must be selected at once in monochrome "
eo_error_message
eo_param
//
// -----------------------------------------------
GSYC_FORMAT
pagelinks = GVDC_VID_SIGNAL_TYPE.UPDATE ;
valid = ( SYC_DIG & DEF_DEC_PATH ) ? ADDERROR[ERR_NO_DIGITAL_SYNC_AV] : 0 ;
error_message
ERR_NO_DIGITAL_SYNC_AV, "Digital synchronization not available by the Decoder path."
eo_error_message
eo_param
//
// -----------------------------------------------
//
GSYC_DIG_H_OUT
//
enable = ENABLE[( OPTION | OPTION_DIG | DEF_METEOR_II_MC | DEF_CORONA_II )] ;
//enable = ENABLE[( OPTION | OPTION_DIG | OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG |
// OPTION_MC_JPEG_DIG | OPTION_II | OPTION_II_DIG )] ;
//enable = ENABLE[( OPTION | OPTION_DIG | OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG )] ;
eo_param
//
// -----------------------------------------------
//
GSYC_DIG_V_OUT
//
enable = ENABLE[( OPTION | OPTION_DIG | DEF_METEOR_II_MC | DEF_CORONA_II )] ;
//enable = ENABLE[( OPTION | OPTION_DIG | OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG |
// OPTION_MC_JPEG_DIG | OPTION_II | OPTION_II_DIG )] ;
//enable = ENABLE[( OPTION | OPTION_DIG | OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG )] ;
eo_param
//
// -----------------------------------------------
// Round the PCK_FREQ at 4 Decimals
GPCK_FREQUENCY
valid = (
( ( ( PCK_FREQ & 0xffff00 ) != 12272384 ) & ( ( PCK_FREQ & 0xffff00 ) != 14749952 ) & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) ) ? ADDERROR[ERR_STD_PCK_FREQ] :
( ( ( PCK_FREQ < 1562500 ) & SYC_ANA & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_NG_PCLK_MIN] :
( ( ( PCK_FREQ < 87500 ) & SYC_DIG & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_SYCDIG_PCLK_MIN] :
( DEF_PCLK_MAX ? ADDERROR[ERR_OVERADC_PCLK_MAX] : 0 ) ) )
) ;
//
//valid = (
// ( ( ( PCK_FREQ & 0xffff00 ) != 12272384 ) & ( ( PCK_FREQ & 0xffff00 ) != 14749952 ) & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) ) ? ADDERROR[ERR_STD_PCK_FREQ] :
// ( ( ( PCK_FREQ < 1562500 ) & SYC_ANA & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_NG_PCLK_MIN] :
// ( ( ( PCK_FREQ < 87500 ) & SYC_DIG & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_SYCDIG_PCLK_MIN] : 0 ) )
// ) ;
//valid = (
// ( ( ( PCK_FREQ & 0xffff00 ) != 12272384 ) & ( ( PCK_FREQ & 0xffff00 ) != 14749952 ) & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) ) ? ADDERROR[ERR_STD_PCK_FREQ] :
// ( ( ( PCK_FREQ < 1562500 ) & SYC_ANA & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_NG_PCLK_MIN] :
// ( ( ( PCK_FREQ < 87500 ) & SYC_DIG & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_SYCDIG_PCLK_MIN] :
// ( ( OPTION_II_DIG & VDC_ANA & ( PCK_FREQ > 32000000 ) ) ? ADDERROR[ERR_OVERADC_PCLK_MAX] : 0 ) ) )
// ) ;
//valid = (
// ( ( ( PCK_FREQ & 0xffff00 ) != 12272384 ) & ( ( PCK_FREQ & 0xffff00 ) != 14749952 ) & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) ) ? ADDERROR[ERR_STD_PCK_FREQ] :
// ( ( ( PCK_FREQ < 1562500 ) & SYC_ANA & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_NG_PCLK_MIN] :
// ( ( ( PCK_FREQ < 87500 ) & SYC_DIG & ( ! ( PCK_CAM_GEN & ( ! PCK_CAM_R&G ) ) ) ) ? ADDERROR[ERR_SYCDIG_PCLK_MIN] : 0 ) )
// ) ;
error_message
ERR_STD_PCK_FREQ, "You must keep with THIS STANDARD video timing the clock frequency at 12.2726 Mhz (NTSC) or 14.75 Mhz (PAL)."
ERR_NG_PCLK_MIN, "The MINIMUM Pixel Freqency is 1.5625 Mhz with Analog Sync. when using Pixel clock from Digitizer."
ERR_SYCDIG_PCLK_MIN, "The MINIMUM Pixel Freqency is 87.5 Khz with Digital Sync. when using Pixel clock from Digitizer."
ERR_OVERADC_PCLK_MAX, "Maximum pixel clock frequency reached. Reduce the pixel clock to 30Mhz(Corona,Meteor_II,Meteor_II_MC), 32Mhz(Corona_II Analog), 40Mhz(Corona_II Digital)."
eo_error_message
eo_param
//
// -----------------------------------------------
//
GPCK_EXT_SIGNAL
valid = DAT_ERROR ||
(
( PCK_CAM_R&G & ( ! ( DEF_CORONA_II | OPTION | OPTION_DIG ) ) ) ? ADDERROR[ERR_PCK_R&G_NOTSUPPORTED] :
( ( PCK_CAM_R&G & DEF_CORONA & DEF_DEC_PATH ) ? ADDERROR[ERR_PCK_R&G_RGBPATHONLY] : 0 )
) ;
//
error_message
ERR_PCK_R&G_NOTSUPPORTED, "Option Not supported by the digitizer."
ERR_PCK_R&G_RGBPATHONLY, "Option supported ONLY by RGB Path. Select <Force RGB path> in Advanced page."
eo_error_message
eo_param
//
// -----------------------------------------------
//
//******************************************************************************************************
GVDT_TYPE
valid = ( ( VDT_NINTRL & ( DEF_METEOR_II | OPTION_LC ) ) ? ADDERROR[ERR_NO_PROG_VID_AV] : 0 ) ;
//
//valid = ( ( VDT_NINTRL & ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) ? ADDERROR[ERR_NO_PROG_VID_AV] : 0 ) ;
//valid = ( ( VDT_NINTRL & ( OPTION_M2 | OPTION_LC ) ) ? ADDERROR[ERR_NO_PROG_VID_AV] : 0 ) ;
error_message
ERR_NO_PROG_VID_AV, "Non-interlaced video Not supported by the Digitizer."
eo_error_message
eo_param
//
// -----------------------------------------------
//******************************************************************************************************
//
GVDL_USE_DEFAULT
pagelinks = GVDL_PEDESTAL.UPDATE ;
//
valid = (
( ( ! VDL_USE_DEFVAL ) & DEF_DEC_PATH & VDC_MONO ) ? ADDERROR[ERR_VDL_USE_DEFVAL] :
( ( VDL_PEDEST & DEF_DEC_PATH ) ? ADDERROR[ERR_FIXED_PEDESTAL] : 0 )
) ;
//
//valid = ( ( ! ( VDL_USE_DEFVAL ) ) & DEF_DEC_PATH & ( ! VDC_C_COLOR ) ) ? ADDERROR[ERR_VDL_USE_DEFVAL] : 0 ;
error_message
ERR_VDL_USE_DEFVAL, "Control of <video voltage swing, pedestal and references> not available. Use default."
ERR_FIXED_PEDESTAL, "Decoder automatically adjusts pedestal amplitude: Use default setting."
eo_error_message
eo_param
//
// -----------------------------------------------
//
GVDC_ANA_VID_C_CH
enable = ENABLE[0] ;
eo_param
//
// -----------------------------------------------
//
GVDL_PEDESTAL
pagelinks = GVDL_USE_DEFAULT.VALID ;
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_BT254_PATH & ( DEF_MONO_VIA_RGB | VDC_RGB_COL ) & ( ! VDL_USE_DEFVAL ) )] ;
eo_param
//
// -----------------------------------------------
//
GVDL_AMPLITUDE
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_BT254_PATH & ( DEF_MONO_VIA_RGB | VDC_RGB_COL ) & ( ! VDL_USE_DEFVAL ) )] ;
valid = (
( VDL_AMPL < 300 ) ? ADDERROR[ERR_TOO_SMALL_AMPLITUDE_AV] :
( ( ( VDL_AMPL != 700 ) & DEF_DEC_PATH ) ? ADDERROR[ERR_FIXED_AMPLITUDE] : 0 )
) ;
error_message
ERR_TOO_SMALL_AMPLITUDE_AV, "Minimum Video Voltage Swing available is 300mV."
ERR_FIXED_AMPLITUDE, "Decoder automatically adjusts voltage amplitude: Use default setting of 700 mV."
eo_error_message
eo_param
//
// -----------------------------------------------
//
GVDL_SWING
// Sync. Slicer detection in POS Swing ONLY for Corona & MetII/MC
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_BT254_PATH & ( DEF_MONO_VIA_RGB | VDC_RGB_COL ) & ( ! VDL_USE_DEFVAL ) )] ;
valid = ( ( ! VDL_POS_SWG ) ? ADDERROR[ERR_FIXED_VOLTSWG] : 0 ) ;
error_message
ERR_FIXED_VOLTSWG,"Negative and both voltage swing not available. Use Positive voltage swing."
eo_error_message
eo_param
//
// -----------------------------------------------
//
GVDL_BRIGHTNESS
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
eo_param
//
// -----------------------------------------------
//
GVDL_CONTRAST
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
eo_param
//
// -----------------------------------------------
//
GVDL_SATURATION
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
eo_param
//
// -----------------------------------------------
//
GVDL_HUE
//enable = ENABLE[0] ;
enable = ENABLE[( DEF_DEC_PATH & VDC_C_COLOR & ( ! VDL_USE_DEFVAL ) )] ;
eo_param
//
// -----------------------------------------------
//
GEXP_GEN_MODE
enable = ENABLE[1] ;
eo_param
// -----------------------------------------------
//
GEXP_GEN_MODE_2
enable = ENABLE[1] ;
eo_param
//
// -----------------------------------------------
//
// -----------------------------------------------
//
//
// -----------------------------------------------
// Si HEPVAL > HTOTAL => Erreur en cours !
//
GVDT_HORIZONTAL
valid = (
( ( DEF_VS_SAMPLING_MIN & DEF_BT254_PATH ) |
( ( VDT_HBPORCH < ( 6 + ( 2 * DEF_PAL ) ) ) & DEF_DEC_PATH ) ) ? ADDERROR[ERR_HBPORCH_MIN_VALUE] :
( ( DEF_HSPVAL_MIN & VDC_ANA ) ? ADDERROR[ERR_CLAMPING_VIDEO_BPO_VALUE] :
( ( DEF_HEPVAL_MAX & VDC_ANA ) ? ADDERROR[ERR_CLAMPING_VIDEO_FPO_VALUE] :
( DEF_ECSNGT_OVR & DEF_BT254_PATH ? ADDERROR[ERR_ECSNGT_OVRFLOW_VALUE] :
( DEF_DIG_HVNEG_VALUE ? ADDERROR[ERR_HNEGATIVE_VALUE] :
( ( DEF_VID_TIM_STD & VDT_INTERL & DEF_CORONA
& ( ( DEF_NTSC & ( ! DEF_MONO_VIA_DEC ) ) | ( DEF_PAL & ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) ) ) & SYC_ANA & ( VDT_HSYNC % 2 ) ) ? ADDERROR[ERR_PAIR_HS_MODULO2_VALUE] :
( ( DEF_VID_TIM_STD & VDT_INTERL & DEF_CORONA
& DEF_PAL & ( VDC_C_COLOR | VDC_SVID ) & SYC_ANA & ( ! ( VDT_HSYNC % 2 ) ) ) ? ADDERROR[ERR_IMPAIR_HS_MODULO2_VALUE] :
( ( VDT_INTERL & DEF_NTSC & ( ! DEF_60HZ_HV_TOTAL_STD ) & ( VDC_SVID | ( VDC_MONO & ( DEF_METEOR_II | OPTION_LC ) ) | ( VDC_C_COLOR ) ) & SYC_ANA ) ? ADDERROR[ERR_HTOTAL60HZ_VALUE] :
( ( VDT_INTERL & DEF_PAL & ( ! DEF_50HZ_HV_TOTAL_STD ) & ( VDC_SVID | ( VDC_MONO & ( DEF_METEOR_II | OPTION_LC ) ) | ( VDC_C_COLOR ) ) & SYC_ANA ) ? ADDERROR[ERR_HTOTAL50HZ_VALUE] :
( DEF_HTOTAL_ODD_INTERLACED ? ADDERROR[ERR_INTERLACED_HTOTAL_ODD_VALUE] :
0 ) ) ) ) ) ) ) ) )
) ;
//
//Correction 11/8/01 Add Front Porch Clamping
//valid = (
// ( ( DEF_VS_SAMPLING_MIN & DEF_BT254_PATH ) |
// ( ( VDT_HBPORCH < ( 6 + ( 2 * DEF_PAL ) ) ) & DEF_DEC_PATH ) ) ? ADDERROR[ERR_HBPORCH_MIN_VALUE] :
// ( DEF_HSPVAL_MIN & VDC_ANA ? ADDERROR[ERR_CLAMPING_VIDEO_VALUE] :
// ( DEF_ECSNGT_OVR & DEF_BT254_PATH ? ADDERROR[ERR_ECSNGT_OVRFLOW_VALUE] :
// ( DEF_DIG_HVNEG_VALUE ? ADDERROR[ERR_HNEGATIVE_VALUE] :
// ( ( DEF_VID_TIM_STD & VDT_INTERL & DEF_CORONA
// & ( ( DEF_NTSC & ( ! DEF_MONO_VIA_DEC ) ) | ( DEF_PAL & ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) ) ) & SYC_ANA & ( VDT_HSYNC % 2 ) ) ? ADDERROR[ERR_PAIR_HS_MODULO2_VALUE] :
// ( ( DEF_VID_TIM_STD & VDT_INTERL & DEF_CORONA
// & DEF_PAL & ( VDC_C_COLOR | VDC_SVID ) & SYC_ANA & ( ! ( VDT_HSYNC % 2 ) ) ) ? ADDERROR[ERR_IMPAIR_HS_MODULO2_VALUE] :
// ( ( VDT_INTERL & DEF_NTSC & ( ! DEF_60HZ_HV_TOTAL_STD ) & ( VDC_SVID | ( VDC_MONO & ( DEF_METEOR_II | OPTION_LC ) ) | ( VDC_C_COLOR ) ) & SYC_ANA ) ? ADDERROR[ERR_HTOTAL60HZ_VALUE] :
// ( ( VDT_INTERL & DEF_PAL & ( ! DEF_50HZ_HV_TOTAL_STD ) & ( VDC_SVID | ( VDC_MONO & ( DEF_METEOR_II | OPTION_LC ) ) | ( VDC_C_COLOR ) ) & SYC_ANA ) ? ADDERROR[ERR_HTOTAL50HZ_VALUE] :
// ( DEF_HTOTAL_ODD_INTERLACED ? ADDERROR[ERR_INTERLACED_HTOTAL_ODD_VALUE] :
// 0 ) ) ) ) ) ) ) )
// ) ;
// Correction 18/9/01 replacing OPTION's board for DEF's board
//valid = (
// ( ( DEF_VS_SAMPLING_MIN & DEF_BT254_PATH ) |
// ( ( VDT_HBPORCH < ( 6 + ( 2 * DEF_PAL ) ) ) & DEF_DEC_PATH ) ) ? ADDERROR[ERR_HBPORCH_MIN_VALUE] :
// ( DEF_HSPVAL_MIN & VDC_ANA ? ADDERROR[ERR_CLAMPING_VIDEO_VALUE] :
// ( DEF_ECSNGT_OVR & DEF_BT254_PATH ? ADDERROR[ERR_ECSNGT_OVRFLOW_VALUE] :
// ( DEF_DIG_HVNEG_VALUE ? ADDERROR[ERR_HNEGATIVE_VALUE] :
// ( ( DEF_VID_TIM_STD & VDT_INTERL & ( OPTION | OPTION_LC | OPTION_DIG )
// & ( ( DEF_NTSC & ( ! DEF_MONO_VIA_DEC ) ) | ( DEF_PAL & ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) ) ) & SYC_ANA & ( VDT_HSYNC % 2 ) ) ? ADDERROR[ERR_PAIR_HS_MODULO2_VALUE] :
// ( ( DEF_VID_TIM_STD & VDT_INTERL & ( OPTION | OPTION_LC | OPTION_DIG )
// & DEF_PAL & ( VDC_C_COLOR | VDC_SVID ) & SYC_ANA & ( ! ( VDT_HSYNC % 2 ) ) ) ? ADDERROR[ERR_IMPAIR_HS_MODULO2_VALUE] :
// ( ( VDT_INTERL & DEF_NTSC & ( ! DEF_60HZ_HV_TOTAL_STD ) & ( VDC_SVID | ( VDC_MONO & ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) | ( VDC_C_COLOR ) ) & SYC_ANA ) ? ADDERROR[ERR_HTOTAL60HZ_VALUE] :
// ( ( VDT_INTERL & DEF_PAL & ( ! DEF_50HZ_HV_TOTAL_STD ) & ( VDC_SVID | ( VDC_MONO & ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) | ( VDC_C_COLOR ) ) & SYC_ANA ) ? ADDERROR[ERR_HTOTAL50HZ_VALUE] :
// 0 ) ) ) ) ) ) )
// ) ;
error_message
ERR_HTOTAL60HZ_VALUE, "Horizontal Total Value must be 780 in NTSC by Decoder Path. Readjust the HTotal."
ERR_HTOTAL50HZ_VALUE, "Horizontal Total Value must be 944 in NTSC by Decoder Path. Readjust the HTotal."
ERR_IMPAIR_HS_MODULO2_VALUE, "Hsync must be ODD VALUE"
ERR_PAIR_HS_MODULO2_VALUE, "Hsync must be EVEN VALUE"
ERR_HNEGATIVE_VALUE, "NEGATIVE Value NOT Available"
ERR_HBPORCH_MIN_VALUE, "Minimum Horizontal back porch Reached. Increase Horizontal BPorch"
ERR_CLAMPING_VIDEO_BPO_VALUE, "Clamping inside video active. Increase Horizontal Back Porch"
ERR_CLAMPING_VIDEO_FPO_VALUE, "Clamping inside video active. Increase Horizontal Front Porch"
ERR_ECSNGT_OVRFLOW_VALUE, "Overflow of Noise Gating register. Reduce Horizontal TOTAL or increase Pixel Clock."
ERR_INTERLACED_HTOTAL_ODD_VALUE, "Htotal value must be even in interlaced video mode."
eo_error_message
eo_param
GVDT_VERTICAL
valid = (
DEF_DIG_HVNEG_VALUE ? ADDERROR[ERR_VNEGATIVE_VALUE] :
( ( DEF_DEC_PATH & DEF_DEC_60HZ & ( VDT_VBPORCH < 7 ) ) |
( DEF_DEC_PATH & DEF_DEC_50HZ & ( VDT_VBPORCH < 10 ) )
) ? ADDERROR[ERR_VBPORCH_MIN_VALUE] :
( ( DEF_DEC_60HZ & ( VDC_C_COLOR | VDC_SVID | ( VDC_MONO & ( DEF_METEOR_II | OPTION_LC ) ) ) & VDT_INTERL & ( ( VDT_VFPORCH + VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE ) != 525 ) ) ? ADDERROR[ERR_VTOTAL60HZ_VALUE] :
( ( DEF_DEC_50HZ & ( VDC_C_COLOR | VDC_SVID | ( VDC_MONO & ( DEF_METEOR_II | OPTION_LC ) ) ) & VDT_INTERL & ( ( VDT_VFPORCH + VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE ) != 625 ) ) ? ADDERROR[ERR_VTOTAL50HZ_VALUE] :
0 ) )
) ;
//
// Correction 18/9/01 replacing OPTION's board for DEF's board
//valid = (
// DEF_DIG_HVNEG_VALUE ? ADDERROR[ERR_VNEGATIVE_VALUE] :
// ( ( DEF_DEC_PATH & DEF_DEC_60HZ & ( VDT_VBPORCH < 7 ) ) |
// ( DEF_DEC_PATH & DEF_DEC_50HZ & ( VDT_VBPORCH < 10 ) )
// ) ? ADDERROR[ERR_VBPORCH_MIN_VALUE] :
// ( ( DEF_DEC_60HZ & ( VDC_C_COLOR | VDC_SVID | ( VDC_MONO & ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) ) & VDT_INTERL & ( ( VDT_VFPORCH + VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE ) != 525 ) ) ? ADDERROR[ERR_VTOTAL60HZ_VALUE] :
// ( ( DEF_DEC_50HZ & ( VDC_C_COLOR | VDC_SVID | ( VDC_MONO & ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) ) & VDT_INTERL & ( ( VDT_VFPORCH + VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE ) != 625 ) ) ? ADDERROR[ERR_VTOTAL50HZ_VALUE] :
// 0 ) )
// ) ;
error_message
ERR_VBPORCH_MIN_VALUE, "Minimum Vertical back porch Reached. Increase Vertical BPorch"
ERR_VTOTAL60HZ_VALUE, "Vertical Total Value must be 525 in NTSC by Decoder Path. Readjust the VTotal."
ERR_VTOTAL50HZ_VALUE, "Vertical Total Value must be 625 in NTSC by Decoder Path. Readjust the VTotal."
ERR_VNEGATIVE_VALUE, "NEGATIVE Value NOT Available"
eo_error_message
eo_param
//
// -----------------------------------------------
// -----------------------------------------------
// -----------------------------------------------
//
GVDC_VID_WIDTH
//enable = ENABLE[( VDC_DIG )] ;
valid = ( ( VDC_ANA & ( GVDC_VID_WIDTH > ( 8 + ( 2 * DEF_CORONA_II ) ) ) ) ? ADDERROR[ERR_BAD_BUS_WIDTH] :
0 ) ;
//
//valid = ( ( VDC_ANA & ( GVDC_VID_WIDTH > ( 8 + ( 2 * ( OPTION_II | OPTION_II_DIG ) ) ) ) ) ? ADDERROR[ERR_BAD_BUS_WIDTH] :
// 0 ) ;
//valid = ( ( VDC_ANA & ( GVDC_VID_WIDTH > 8 ) ) ? ADDERROR[ERR_BAD_BUS_WIDTH] :
// 0 ) ;
//
board_specific_value
"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV no|M_ARRAY_TWO
"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV no|M_ARRAY_TWO
"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV no|M_ARRAY_TWO
//"10 bits" 10 VDC_VID_WIDTH_10 VDC_VID_WIDTH_10_AV yes|M_ARRAY_TWO
//"12 bits" 12 VDC_VID_WIDTH_12 VDC_VID_WIDTH_12_AV yes|M_ARRAY_TWO
//"14 bits" 14 VDC_VID_WIDTH_14 VDC_VID_WIDTH_14_AV yes|M_ARRAY_TWO
eo_board_specific_value
error_message
ERR_BAD_BUS_WIDTH, "ONLY 8 Bits Bus Width in ANALOG Video Signal"
eo_error_message
eo_param
//
GGRB_ACTIVATION
valid = ( ( DEF_DEC_PATH & GRB_ACT_IMMEDIATE ) ? ADDERROR[ERR_INVALID_TRIGGER_EVENT] : 0 ) ;
error_message
ERR_INVALID_TRIGGER_EVENT, "Asynchronous Reset not supported by Decoder Path."
eo_error_message
eo_param
//
GGRB_TRG_SIGNAL
pagelinks = GGRB_TRG_FORMAT.UPDATE + GEXP_TRG_SIGNAL.UPDATE ;
valid = (
(
(
( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & ( ! ( GRB_MD_CONT ) ) &
( ( ( EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 ) & GRB_TRG_SIGNAL_APORT ) |
( ( EXP_MD_EXT | EXP_MD_EXT_2 ) & GRB_TRG_SIGNAL_DPORT )
)
) |
(
DEF_TIMER1_ENABLE & DEF_TIMER2_ENABLE &
( ( EXP_TRG_TTL_TIMER1 & EXP_MD_EXT_2 ) | ( EXP_TRG_TTL_TIMER2 & EXP_MD_EXT ) )
)
) ? ADDERROR[ERR_FORMAT_TRIGGER] :
( ( GRB_TRG_SIGNAL_APORT & GRB_TRG_422 ) ? ADDERROR[ERR_FORMAT_OPTO] : 0 )
) ;
//
//valid = (
// (
// ( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & ( ! ( GRB_MD_CONT ) ) &
// ( ( ( EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 ) & GRB_TRG_SIGNAL_APORT ) |
// ( ( EXP_MD_EXT | EXP_MD_EXT_2 ) & GRB_TRG_SIGNAL_DPORT )
// )
// ) |
// ( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & GRB_MD_CONT &
// ( EXP_TRG_TTL_TIMER1 & EXP_MD_EXT_2 ) | ( EXP_TRG_TTL_TIMER2 & EXP_MD_EXT )
// )
// ) ? ADDERROR[ERR_FORMAT_TRIGGER] :
// ( ( GRB_TRG_SIGNAL_APORT & GRB_TRG_422 ) ? ADDERROR[ERR_FORMAT_OPTO] : 0 )
// ) ;
board_specific_value
"analog port trigger ( OPTO TRIG )" M_DEFAULT GRB_TRG_SIGNAL_APORT GRB_TRG_SIGNAL_APORT_AV yes
"digital port trigger ( TTL TRIG )" M_DEFAULT GRB_TRG_SIGNAL_DPORT GRB_TRG_SIGNAL_DPORT_AV yes
"external hsync of digital port" M_DEFAULT GRB_TRG_SIGNAL_HSDPORT GRB_TRG_SIGNAL_HSDPORT_AV no
"external vsync of digital port" M_DEFAULT GRB_TRG_SIGNAL_VSDPORT GRB_TRG_SIGNAL_VSDPORT_AV no
"timer 1 output" M_DEFAULT GRB_TRG_SIGNAL_TIMER1 GRB_TRG_SIGNAL_TIMER1_AV yes
"timer 2 output" M_DEFAULT GRB_TRG_SIGNAL_TIMER2 GRB_TRG_SIGNAL_TIMER2_AV yes
"timer 1 output ( Vsync Input for WEN )" M_DEFAULT GRB_TRG_SIGNAL_TIMER1_WEN GRB_TRG_SIGNAL_TIMER1_WEN_AV yes
"timer 2 output ( Vsync Input for WEN )" M_DEFAULT GRB_TRG_SIGNAL_TIMER2_WEN GRB_TRG_SIGNAL_TIMER2_WEN_AV yes
eo_board_specific_value
error_message
ERR_FORMAT_TRIGGER, "Only one Hardware Trigger Format available at once : OPTO or TTL Trigger"
ERR_FORMAT_OPTO, "Only TTL Format available with OPTO Trigger"
eo_error_message
eo_param
//
//
// -----------------------------------------------
//
GGRB_TRG_POL
enable = ENABLE[( ! GRB_MD_CONT )] ;
eo_param
//
// -----------------------------------------------
//
GEXP_OUT_TIM_0
valid = (
( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 3 ) & ( ! EXP_MD_SW ) & EXP_MD_W_TRG
& ( EXP_CLOCK_HSYNC | EXP_CLOCK_TIMER2 )
)
? ADDERROR[ERR_MIN_DELAY_CNT3_Timer1] :
(
( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 4 ) & EXP_MD_W_TRG & ( ! EXP_MD_SW )
& ( ( EXP_SYN_CLK & ( ( ( ! EXP_MD_EXT ) & OPTION ) | ( ( ! EXP_MD_EXT ) & ( ! EXP_TRG_USER_BIT_TIMER1 ) & DEF_METEOR_II_MC ) ) )
| ( EXP_ASY_CLK & EXP_TRG_SIGNAL_TIMER2 )
)
) ? ADDERROR[ERR_MIN_DELAY_CNT4_Timer1] :
(
( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 5 ) & ( ! EXP_MD_SW )
& (
( EXP_SYN_CLK & EXP_MD_W_TRG
& ( ( EXP_MD_EXT & OPTION ) | ( ( EXP_MD_EXT | EXP_TRG_USER_BIT_TIMER1 ) & DEF_METEOR_II_MC )
)
) |
( EXP_ASY_CLK & EXP_MD_W_TRG
& ( ( ( ! EXP_TRG_SIGNAL_TIMER2 ) & ( ! EXP_MD_EXT ) & OPTION ) |
( ( EXP_MD_HSY | EXP_MD_VSY | EXP_TRG_TTL_TIMER1 ) & DEF_METEOR_II_MC )
)
)
| EXP_MD_PERD
)
) ? ADDERROR[ERR_MIN_DELAY_CNT5_Timer1] :
(
( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 6 ) & ( ! EXP_MD_SW )
& EXP_ASY_CLK & EXP_MD_W_TRG
& ( ( EXP_MD_EXT & OPTION ) | ( ( EXP_MD_EXT | EXP_TRG_USER_BIT_TIMER1 ) & DEF_METEOR_II_MC )
)
)
? ADDERROR[ERR_MIN_DELAY_CNT6_Timer1] :
(
(
( ( DEF_EXP_OUT_T0 > 0xffff ) | ( DEF_EXP_OUT_T1 > 0xffff ) |
( ( DEF_EXP_OUT_T0 + DEF_EXP_OUT_T1 ) > 0xffff )
) & ( ( EXP_OUT_T0 + EXP_OUT_T1 ) > ( 65535 - ( EXP_SYN_CLK | EXP_CLOCK_HSYNC ) ) )
) ? ADDERROR[ERR_CNTER_Timer1_Overflow] :
0 ) ) ) )
) ;
//
//valid = (
// ( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 3 ) & ( ! EXP_MD_SW ) & EXP_MD_W_TRG
// & ( EXP_CLOCK_HSYNC | EXP_CLOCK_TIMER2 )
// )
// ? ADDERROR[ERR_MIN_DELAY_CNT3_Timer1] :
// (
// ( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 4 ) & EXP_MD_W_TRG & ( ! EXP_MD_SW )
// & ( ( EXP_SYN_CLK & ( ( ( ! EXP_MD_EXT ) & OPTION ) | ( ( ! EXP_MD_EXT ) & ( ! EXP_TRG_USER_BIT_TIMER1 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) ) )
// | ( EXP_ASY_CLK & EXP_TRG_SIGNAL_TIMER2 )
// )
// ) ? ADDERROR[ERR_MIN_DELAY_CNT4_Timer1] :
// (
// ( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 5 ) & ( ! EXP_MD_SW )
// & (
// ( EXP_SYN_CLK & EXP_MD_W_TRG
// & ( ( EXP_MD_EXT & OPTION ) | ( ( EXP_MD_EXT | EXP_TRG_USER_BIT_TIMER1 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// ) |
// ( EXP_ASY_CLK & EXP_MD_W_TRG
// & ( ( ( ! EXP_TRG_SIGNAL_TIMER2 ) & ( ! EXP_MD_EXT ) & OPTION ) |
// ( ( EXP_MD_HSY | EXP_MD_VSY | EXP_TRG_TTL_TIMER1 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// )
// | EXP_MD_PERD
// )
// ) ? ADDERROR[ERR_MIN_DELAY_CNT5_Timer1] :
// (
// ( ( EXP_OUT_T0 > 0 ) & ( EXP_OUT_T0 < 6 ) & ( ! EXP_MD_SW )
// & EXP_ASY_CLK & EXP_MD_W_TRG
// & ( ( EXP_MD_EXT & OPTION ) | ( ( EXP_MD_EXT | EXP_TRG_USER_BIT_TIMER1 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// )
// ? ADDERROR[ERR_MIN_DELAY_CNT6_Timer1] :
// (
// (
// ( ( DEF_EXP_OUT_T0 > 0xffff ) | ( DEF_EXP_OUT_T1 > 0xffff ) |
// ( ( DEF_EXP_OUT_T0 + DEF_EXP_OUT_T1 ) > 0xffff )
// ) & ( ( EXP_OUT_T0 + EXP_OUT_T1 ) > ( 65535 - ( EXP_SYN_CLK | EXP_CLOCK_HSYNC ) ) )
// ) ? ADDERROR[ERR_CNTER_Timer1_Overflow] :
// 0 ) ) ) )
// ) ;
error_message
ERR_MIN_DELAY_CNT3_Timer1, "Minimnum Count of 3 for the Delay Duration"
ERR_MIN_DELAY_CNT4_Timer1, "Minimnum Count of 4 for the Delay Duration"
ERR_MIN_DELAY_CNT5_Timer1, "Minimnum Count of 5 for the Delay Duration"
ERR_MIN_DELAY_CNT6_Timer1, "Minimnum Count of 6 for the Delay Duration"
ERR_CNTER_Timer1_Overflow, "Maximum Timer1 Counter value reached. ( Active + Inactive <= 65535 or 65534 [Exposure Clk = Synchronous PCLK, HSync] )"
eo_error_message
eo_param
//
GEXP_OUT_TIM_0_2
valid = (
( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 3 ) & EXP_MD_W_TRG_2 & ( ! EXP_MD_SW_2 )
& ( EXP_CLOCK_2_HSYNC | EXP_CLOCK_2_TIMER1 )
)
? ADDERROR[ERR_MIN_DELAY_CNT3_Timer2] :
(
( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 4 ) & EXP_MD_W_TRG_2 & ( ! EXP_MD_SW_2 )
& ( ( EXP_SYN_CLK_2 & ( ( ( ! EXP_MD_EXT_2 ) & OPTION ) | ( ( ! EXP_MD_EXT_2 ) & ( ! EXP_TRG_USER_BIT_TIMER2 ) & DEF_METEOR_II_MC ) ) )
| ( EXP_ASY_CLK_2 & EXP_TRG_SIGNAL_2_TIMER1 )
)
) ? ADDERROR[ERR_MIN_DELAY_CNT4_Timer2] :
(
( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 5 ) & ( ! EXP_MD_SW_2 )
& (
( EXP_SYN_CLK_2 & EXP_MD_W_TRG_2
& ( ( EXP_MD_EXT_2 & OPTION ) | ( ( EXP_MD_EXT_2 | EXP_TRG_USER_BIT_TIMER2 ) & DEF_METEOR_II_MC )
)
) |
( EXP_ASY_CLK_2 & EXP_MD_W_TRG_2
& ( ( ( ! EXP_TRG_SIGNAL_2_TIMER1 ) & ( ! EXP_MD_EXT_2 ) & OPTION ) |
( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_TRG_TTL_TIMER2 ) & DEF_METEOR_II_MC )
)
)
| EXP_MD_PERD_2
)
) ? ADDERROR[ERR_MIN_DELAY_CNT5_Timer2] :
(
( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 6 ) & ( ! EXP_MD_SW_2 )
& EXP_ASY_CLK_2 & EXP_MD_W_TRG_2
& ( ( EXP_MD_EXT_2 & OPTION ) | ( ( EXP_MD_EXT_2 | EXP_TRG_USER_BIT_TIMER2 ) & DEF_METEOR_II_MC )
)
)
? ADDERROR[ERR_MIN_DELAY_CNT6_Timer2] :
(
(
( ( DEF_EXP_OUT_T0_2 > 0xffff ) | ( DEF_EXP_OUT_T1_2 > 0xffff ) |
( ( DEF_EXP_OUT_T0_2 + DEF_EXP_OUT_T1_2 ) > 0xffff )
) & ( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) > ( 65535 - ( EXP_SYN_CLK_2 | EXP_CLOCK_2_HSYNC ) ) )
) ? ADDERROR[ERR_CNTER_Timer2_Overflow] :
0 ) ) ) )
) ;
//
//valid = (
// ( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 3 ) & EXP_MD_W_TRG_2 & ( ! EXP_MD_SW_2 )
// & ( EXP_CLOCK_2_HSYNC | EXP_CLOCK_2_TIMER1 )
// )
// ? ADDERROR[ERR_MIN_DELAY_CNT3_Timer2] :
// (
// ( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 4 ) & EXP_MD_W_TRG_2 & ( ! EXP_MD_SW_2 )
// & ( ( EXP_SYN_CLK_2 & ( ( ( ! EXP_MD_EXT_2 ) & OPTION ) | ( ( ! EXP_MD_EXT_2 ) & ( ! EXP_TRG_USER_BIT_TIMER2 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) ) )
// | ( EXP_ASY_CLK_2 & EXP_TRG_SIGNAL_2_TIMER1 )
// )
// ) ? ADDERROR[ERR_MIN_DELAY_CNT4_Timer2] :
// (
// ( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 5 ) & ( ! EXP_MD_SW_2 )
// & (
// ( EXP_SYN_CLK_2 & EXP_MD_W_TRG_2
// & ( ( EXP_MD_EXT_2 & OPTION ) | ( ( EXP_MD_EXT_2 | EXP_TRG_USER_BIT_TIMER2 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// ) |
// ( EXP_ASY_CLK_2 & EXP_MD_W_TRG_2
// & ( ( ( ! EXP_TRG_SIGNAL_2_TIMER1 ) & ( ! EXP_MD_EXT_2 ) & OPTION ) |
// ( ( EXP_MD_HSY_2 | EXP_MD_VSY_2 | EXP_TRG_TTL_TIMER2 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// )
// | EXP_MD_PERD_2
// )
// ) ? ADDERROR[ERR_MIN_DELAY_CNT5_Timer2] :
// (
// ( ( EXP_OUT_T0_2 > 0 ) & ( EXP_OUT_T0_2 < 6 ) & ( ! EXP_MD_SW_2 )
// & EXP_ASY_CLK_2 & EXP_MD_W_TRG_2
// & ( ( EXP_MD_EXT_2 & OPTION ) | ( ( EXP_MD_EXT_2 | EXP_TRG_USER_BIT_TIMER2 ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// )
// ? ADDERROR[ERR_MIN_DELAY_CNT6_Timer2] :
// (
// (
// ( ( DEF_EXP_OUT_T0_2 > 0xffff ) | ( DEF_EXP_OUT_T1_2 > 0xffff ) |
// ( ( DEF_EXP_OUT_T0_2 + DEF_EXP_OUT_T1_2 ) > 0xffff )
// ) & ( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) > ( 65535 - ( EXP_SYN_CLK_2 | EXP_CLOCK_2_HSYNC ) ) )
// ) ? ADDERROR[ERR_CNTER_Timer2_Overflow] :
// 0 ) ) ) )
// ) ;
error_message
ERR_MIN_DELAY_CNT3_Timer2, "Minimnum Count of 3 for the Delay Duration"
ERR_MIN_DELAY_CNT4_Timer2, "Minimnum Count of 4 for the Delay Duration"
ERR_MIN_DELAY_CNT5_Timer2, "Minimnum Count of 5 for the Delay Duration"
ERR_MIN_DELAY_CNT6_Timer2, "Minimnum Count of 6 for the Delay Duration"
ERR_CNTER_Timer2_Overflow, "Maximum Timer2 Counter value reached. ( Active + Inactive <= 65535 or 65534 [Exposure CLK = Synchronous PCLK, HSync] )"
eo_error_message
eo_param
//
GEXP_CLOCK
// Max Car = 120 / Ligne
valid = ( EXP_CLOCK_TIMER2 & DEF_TIMER1_ENABLE &
( ( EXP_OUT_T0_2 == 0 ) | ( EXP_OUT_T1_2 == 0 ) ) ? ADDERROR[ERR_NOCLK_TIMER1] :
( EXP_CLOCK_TIMER2 & EXP_CLOCK_2_TIMER1 ? ADDERROR[ERR_2EXP_OUT_SELECT] :
( EXP_CLOCK_HSYNC & DEF_DEC_PATH ? ADDERROR[ERR_HS_NOT_AV] :
0 ) )
) ;
//
//valid = ( EXP_CLOCK_TIMER2 & DEF_TIMER1_ENABLE &
// ( ( EXP_OUT_T0_2 == 0 ) | ( EXP_OUT_T1_2 == 0 ) ) ? ADDERROR[ERR_NOCLK_TIMER1] :
// ( EXP_CLOCK_TIMER2 & EXP_CLOCK_2_TIMER1 ? ADDERROR[ERR_2EXP_OUT_SELECT] :
// 0 )
// ) ;
board_specific_value
"hsync clock" M_DEFAULT EXP_CLOCK_HSYNC EXP_CLOCK_HSYNC_AV yes
"vsync clock" M_DEFAULT EXP_CLOCK_VSYNC EXP_CLOCK_VSYNC_AV no
"timer 2 output" M_DEFAULT EXP_CLOCK_TIMER2 EXP_CLOCK_TIMER2_AV yes
eo_board_specific_value
error_message
ERR_NOCLK_TIMER1, "The Exposure timer 2 signal must be SET in mode <Periodic>"
ERR_2EXP_OUT_SELECT, "You must select ONE Exposure Output signal at once"
ERR_HS_NOT_AV, "Horizontal Sync. Clock not available by Decoder path"
eo_error_message
eo_param
//
GEXP_CLOCK_2
valid = ( EXP_CLOCK_2_TIMER1 & DEF_TIMER2_ENABLE &
( ( EXP_OUT_T0 == 0 ) | ( EXP_OUT_T1 == 0 ) ) ? ADDERROR[ERR_NOCLK_TIMER2] :
( EXP_CLOCK_2_TIMER1 & EXP_CLOCK_TIMER2 ? ADDERROR[ERR_2EXP_OUT_SELECT] :
( EXP_CLOCK_2_HSYNC & DEF_DEC_PATH ? ADDERROR[ERR_HS_NOT_AV] :
0 ) )
) ;
//
//valid = ( EXP_CLOCK_2_TIMER1 & DEF_TIMER2_ENABLE &
// ( ( EXP_OUT_T0 == 0 ) | ( EXP_OUT_T1 == 0 ) ) ? ADDERROR[ERR_NOCLK_TIMER2] :
// ( EXP_CLOCK_2_TIMER1 & EXP_CLOCK_TIMER2 ? ADDERROR[ERR_2EXP_OUT_SELECT] :
// 0 )
// ) ;
board_specific_value
"hsync clock" M_DEFAULT EXP_CLOCK_2_HSYNC EXP_CLOCK_2_HSYNC_AV yes
"timer 1 output" M_DEFAULT EXP_CLOCK_2_TIMER1 EXP_CLOCK_2_TIMER1_AV yes
eo_board_specific_value
error_message
ERR_NOCLK_TIMER2, "The Exposure timer 1 signal must be SET in mode <Periodic>"
ERR_2EXP_OUT_SELECT, "You must select ONE Exposure Output signal at once"
ERR_HS_NOT_AV, "Horizontal Sync. Clock not available by Decoder path"
eo_error_message
eo_param
//
GEXP_TRG_SIGNAL
enable = ENABLE[( DEF_TIMER1_ENABLE & ( ! EXP_MD_PERD ) )] ;
valid = ( ( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & ( ! ( GRB_MD_CONT ) ) &
( ( ( EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 ) & GRB_TRG_SIGNAL_APORT ) |
( ( EXP_MD_EXT | EXP_MD_EXT_2 ) & GRB_TRG_SIGNAL_DPORT )
)
) |
( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & GRB_MD_CONT &
( EXP_TRG_TTL_TIMER1 & EXP_MD_EXT_2 ) | ( EXP_TRG_TTL_TIMER2 & EXP_MD_EXT )
) ? ADDERROR[ERR_FORMAT_TRIGGER] :
( DEF_DEC_PATH & ( EXP_MD_HSY | EXP_MD_HSY_2 | EXP_MD_VSY | EXP_MD_VSY_2 ) ? ADDERROR[ERR_EXP_HSVS_AV] : 0 ) ) ;
board_specific_value
"TTL Trigger" M_DEFAULT EXP_TRG_TTL_TIMER1 EXP_TRG_TTL_TIMER1_AV yes
"timer 1 = 0" M_DEFAULT EXP_TRG_CNTEQ0_TIMER1 EXP_TRG_CNTEQ0_TIMER1_AV no
"timer 2 output" M_DEFAULT EXP_TRG_SIGNAL_TIMER2 EXP_TRG_SIGNAL_TIMER2_AV yes
"user 1 bit" M_DEFAULT EXP_TRG_USER_BIT_TIMER1 EXP_TRG_USER_BIT_TIMER1_AV yes
eo_board_specific_value
error_message
ERR_FORMAT_TRIGGER, "Only one Hardware Trigger Format available at once : OPTO or TTL Trigger"
ERR_EXP_HSVS_AV, "NOT Available in Decoder Path . Force RGB Path in Advance Page"
eo_error_message
eo_param
//
GEXP_TRG_SIGNAL_2
enable = ENABLE[( DEF_TIMER2_ENABLE & ( ! EXP_MD_PERD_2 ) )] ;
valid = ( ( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & ( ! ( GRB_MD_CONT ) ) &
( ( ( EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 ) & GRB_TRG_SIGNAL_APORT ) |
( ( EXP_MD_EXT | EXP_MD_EXT_2 ) & GRB_TRG_SIGNAL_DPORT )
)
) |
( ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) & GRB_MD_CONT &
( EXP_TRG_TTL_TIMER1 & EXP_MD_EXT_2 ) | ( EXP_TRG_TTL_TIMER2 & EXP_MD_EXT )
) ? ADDERROR[ERR_FORMAT_TRIGGER] :
( DEF_DEC_PATH & ( EXP_MD_HSY | EXP_MD_HSY_2 | EXP_MD_VSY | EXP_MD_VSY_2 ) ? ADDERROR[ERR_EXP_HSVS_AV] : 0 ) ) ;
board_specific_value
"TTL Trigger" M_DEFAULT EXP_TRG_TTL_TIMER2 EXP_TRG_TTL_TIMER2_AV yes
"timer 2 = 0" M_DEFAULT EXP_TRG_CNTEQ0_TIMER2 EXP_TRG_CNTEQ0_TIMER2_AV no
"timer 1 output" M_DEFAULT EXP_TRG_SIGNAL_2_TIMER1 EXP_TRG_SIGNAL_2_TIMER1_AV yes
"user 2 bit" M_DEFAULT EXP_TRG_USER_BIT_TIMER2 EXP_TRG_USER_BIT_TIMER2_AV yes
eo_board_specific_value
error_message
ERR_FORMAT_TRIGGER, "Only one Hardware Trigger Format available at once : OPTO or TTL Trigger"
ERR_EXP_HSVS_AV, "NOT Available in Decoder Path . Force RGB Path in Advance Page"
eo_error_message
eo_param
//
GEXP_TRG_FORMAT
enable = ENABLE[( DEF_TIMER1_ENABLE & ( ! EXP_MD_PERD ) )] ;
valid = ( DEF_TIMER1_ENABLE & DEF_TIMER2_ENABLE &
( ( EXP_TRG_TTL & EXP_TRG_422_2 ) | ( EXP_TRG_TTL_2 & EXP_TRG_422 ) ) ? ADDERROR[ERR_MISMATCH_FORMAT_TRIG] : 0 ) ;
error_message
ERR_MISMATCH_FORMAT_TRIG, "You select two differents formats trigger source TTL & 422 at once"
eo_error_message
eo_param
//
GEXP_TRG_FORMAT_2
enable = ENABLE[( DEF_TIMER2_ENABLE & ( ! EXP_MD_PERD_2 ) )] ;
eo_param
//
GEXP_TRG_POL
enable = ENABLE[( DEF_TIMER1_ENABLE & ( ! EXP_MD_PERD ) )] ;
eo_param
//
GEXP_TRG_POL_2
enable = ENABLE[( DEF_TIMER2_ENABLE & ( ! EXP_MD_PERD_2 ) )] ;
eo_param
//
GEXP_COMBINE ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 1 Combination
eo_param_info
board_specific_value
"timer 1" M_DEFAULT DUMMY_PAR NO_BOPTION yes
"timer 1 XOR timer 2" M_DEFAULT EXP_COMBINE_XOR M_DEFAULT yes
"timer 1 AND timer 2" M_DEFAULT EXP_COMBINE_AND M_DEFAULT yes
"timer 1 OR timer 2" M_DEFAULT EXP_COMBINE_OR M_DEFAULT yes
eo_board_specific_value
pagelinks = GEXP_GEN_MODE_2.VALID ;
enable = ENABLE[DEF_TIMER1_ENABLE] ;
eo_param
//
GEXP_PRESCALE1 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 1 Prescale
eo_param_info
board_specific_value
1 M_DEFAULT EXP_PRESCALE1_1 M_DEFAULT yes
2 M_DEFAULT EXP_PRESCALE1_2 M_DEFAULT yes
4 M_DEFAULT EXP_PRESCALE1_4 M_DEFAULT yes
8 M_DEFAULT EXP_PRESCALE1_8 M_DEFAULT yes
16 M_DEFAULT EXP_PRESCALE1_16 M_DEFAULT no
eo_board_specific_value
enable = ENABLE[DEF_TIMER1_ENABLE] ;
eo_param
//
GEXP_COMBINE_2 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 2 Combination
eo_param_info
board_specific_value
"timer 2" M_DEFAULT DUMMY_PAR NO_BOPTION yes
"timer 2 XOR timer 1" M_DEFAULT EXP_COMBINE_2_XOR M_DEFAULT yes
"timer 2 AND timer 1" M_DEFAULT EXP_COMBINE_2_AND M_DEFAULT yes
"timer 2 OR timer 1" M_DEFAULT EXP_COMBINE_2_OR M_DEFAULT yes
eo_board_specific_value
pagelinks = GEXP_GEN_MODE.VALID ;
enable = ENABLE[DEF_TIMER2_ENABLE] ;
eo_param
//
GEXP_PRESCALE2 ONE_VAL_PAR|BRD_OPT_ON|IS_INTERACTIVE
param_info
Exposure Signal Options
Timer 2 Prescale
eo_param_info
board_specific_value
1 M_DEFAULT EXP_PRESCALE2_1 M_DEFAULT yes
2 M_DEFAULT EXP_PRESCALE2_2 M_DEFAULT yes
4 M_DEFAULT EXP_PRESCALE2_4 M_DEFAULT yes
8 M_DEFAULT EXP_PRESCALE2_8 M_DEFAULT yes
16 M_DEFAULT EXP_PRESCALE2_16 M_DEFAULT no
eo_board_specific_value
enable = ENABLE[DEF_TIMER2_ENABLE] ;
eo_param
//
// -----------------------------------------------
// -----------------------------------------------
// -----------------------------------------------
//
//
//*************************************************
//*************************************************
// SECTION #3: BOARD LIMITATION DESCRIPTION (COMMON)
//*************************************************
//*************************************************
[COMMON_OPTIONS]
//
// ================================================
// Camera type
// ---------->
// ================================================
//
//
// Added JMcCalla 22Oct96
//
CT_LINE_SCAN_AVAIL no
CT_FRAM_SCAN_AVAIL yes
// mono comp RGB RGBP RGBA SVID ?YUVVID
CT_MAX_TAPS array 2 1 1 0 0 1 1
CT_MAX_CAMERA array 3 1 1 0 0 1 1
// ana dig
CT_MAX_CONNECTORS array 3 3
//
//
// ================================================
// Camera type
// <----------
// ================================================
//
// ================================================
// Video signal format (analog/digital)
// ----------------------------------->
// ================================================
//
YUVVID_AVAIL no
YUV_INPUT_AVAIL no
CHROMI_IN_AVAIL no
//
CLAMP_SYNC_AVAIL no
CLAMP_BPORCH_AVAIL yes
CLAMP_FPORCH_AVAIL equ
value = DEF_BT254_PATH ;
//
// ================================================
// Video signal format
// <-------------------
// ================================================
//
// ================================================
// Video timing
// ----------->
// ================================================
//
VID_STD_RS170_PCLK 12272600
VID_STD_RS170_HORZ array 58 60 22 640
VID_STD_RS170_VERT array 6 33 6 480
VID_STD_CCIR_PCLK 14750000
VID_STD_CCIR_HORZ array 69 85 22 768
VID_STD_CCIR_VERT array 5 42 2 576
// Actual 5 42 2 in RGB Path causing grab problem when stop continuous grab but OK with Actual Mil.
// Replaced with 5 41 3 because Bottom lines missing in RGB & Field inversion in compression.
//VID_STD_CCIR_VERT array 5 41 3 576
//VID_STD_RS170_VERT array 6 30 9 480
//
// Bus Width 10 Bits
VDC_VID_WIDTH_10_AV equ
value = ( DEF_CORONA_II * VDC_MONO ) ;
//value = ( ( OPTION_II | OPTION_II_DIG ) * VDC_MONO ) ;
//
// Bus Width 12 Bits
VDC_VID_WIDTH_12_AV equ
value = ( OPTION_II_DIG * VDC_MONO * VDC_DIG ) ;
// Bus Width 14 Bits
VDC_VID_WIDTH_14_AV equ
value = ( OPTION_II_DIG * VDC_MONO * VDC_DIG ) ;
//
// ================================================
// Video timing
// <-----------
// ================================================
//
// ================================================
// Pixel clock
// ---------->
// ================================================
//
PCLK_IN_POS_POL_AV yes
PCLK_IN_NEG_POL_AV equ
value = ( DEF_CORONA_II | DEF_METEOR_II_MC ) ;
PCLK_OUT_POS_POL_AV yes
PCLK_OUT_NEG_POL_AV no
PCK_IN_DELAY_AV equ
value = ( DEF_CORONA | DEF_CORONA_II ) ;
//HIGH_SPEED_GRAB yes
//
// ================================================
// Pixel clock
// <----------
// ================================================
//
// ================================================
// Synchronisation signal
// --------------------->
// ================================================
//
VDT_SERRATION_AVAIL no
VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_CAM_LATENCY_AV no
SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_C_IN_AV no
SYC_DIG_C_OUT_AV no
SYC_ASEP_O_MONO_AV equ
value = DEF_MONO_VIA_RGB ;
//
CSYN_IN_TTL_AV no
CSYN_IN_RS422_AV no
CSYN_OUT_TTL_AV no
CSYN_OUT_RS422_AV no
CSYN_IN_POS_POL_AV no
CSYN_IN_NEG_POL_AV no
CSYN_OUT_NEG_POL_AV no
CSYN_OUT_POS_POL_AV no
SYC_HVC_SAME_FORMAT yes
SYC_HS&VS_MUST_SDIR yes
SYC_HS&CS_MUST_SDIR yes
SYC_VS&CS_MUST_SDIR yes
SYC_HSY_MAY_I&O yes
SYC_VSY_MAY_I&O yes
SYC_CSY_MAY_I&O yes
SYC_ANAL_O_DIGVID_AV yes
//
// ================================================
// Synchronisation signal
// <---------------------
// ================================================
//
// ================================================
// GRAB signal
// --------------------->
// ================================================
//
GRB_TRG_SIGNAL_TIMER1_WEN_AV equ
value = ( DEF_BT254_PATH * GRB_ACT_IMMEDIATE * SYC_ANA * VDT_NINTRL * EXP_USE_OUT ) ;
//
//
GRB_TRG_SIGNAL_TIMER2_WEN_AV equ
value = ( DEF_BT254_PATH * GRB_ACT_IMMEDIATE * SYC_ANA * VDT_NINTRL * EXP_USE_OUT ) ;
//
//
// ================================================
// GRAB signal
// <---------------------
// ================================================
//
// ================================================
// Exposure
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
EXP_ASY_CLK_AV yes
//
// ** Asynchr. clock frequency (in Hz) ** USERCLK
EXP_ASY_CLK_FREQ 25000000
//
EXP_ASY_CLK_AV_2 yes
//
// ** Asynchr. clock frequency (in Hz) ** USERCLK
EXP_ASY_CLK_FREQ_2 25000000
//
//
EXP_CLOCK_HSYNC_AV equ
value = VDT_HSYNC_FREQ ;
EXP_CLOCK_2_HSYNC_AV equ
value = VDT_HSYNC_FREQ ;
EXP_CLOCK_TIMER2_AV equ
value = ( EXP_CLOCK_TIMER2 * ( 1 / ( ( EXP_OUT_T0_2 + EXP_OUT_T1_2 ) * ( 1 / EXP_CLK_FREQ_2 ) ) ) ) || 1 ;
EXP_CLOCK_2_TIMER1_AV equ
value = ( EXP_CLOCK_2_TIMER1 * ( 1 / ( ( EXP_OUT_T0 + EXP_OUT_T1 ) * ( 1 / EXP_CLK_FREQ ) ) ) ) || 1 ;
//
EXP_SYN_CLK_MAX_FREQ 30000000
EXP_CLK_DVED_AV no
EXP_CLK_DVED_AV_2 no
EXP_CLK_MAXDIV_FACT 1
EXP_DELYED_FR_TRG_AV yes
EXP_TIMER_MAX_VALUE 0xffff
EXP_TIMER_MIN_VALUE 0
EXP_CHK_MAXSUM_PERD no
EXP_CHK_MAXSUM_DEL no
EXP_CHK_MAXSUM_NDEL no
//EXP_CHK_MAXSUM_PERD yes
//EXP_CHK_MAXSUM_DEL yes
//EXP_CHK_MAXSUM_NDEL yes
EXP_NDEL_TRG_TTL_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_TTL_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_TTL_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_TTL_AV yes
EXP_DEL_OUT_422_AV yes
EXP_MD_PERD_AV yes
EXP_MD_WITH_TRG_AV_2 yes
EXP_MD_PERD_AV_2 yes
EXP_MD_WITH_TRG_AV yes
EXP_PERD_CLKDVED_AV no
EXP_DEL_CLKDVED_AV no
EXP_NDEL_CLKDVED_AV no
EXP_TEX_CLKDVED_AV no
EXP_THSY_CLKDVED_AV no
EXP_TVSY_CLKDVED_AV no
EXP_TSW_CLKDVED_AV no
EXP_PERD_CLKDVED_AV_2 no
EXP_DEL_CLKDVED_AV_2 no
EXP_NDEL_CLKDVED_AV_2 no
EXP_TEX_CLKDVED_AV_2 no
EXP_THSY_CLKDVED_AV_2 no
EXP_TVSY_CLKDVED_AV_2 no
EXP_TSW_CLKDVED_AV_2 no
//
// ================================================
// Exposure
// <-------
// ================================================
//
// ================================================
// none classified board options
// ---------------------------->
// ================================================
//
SYC_ANA_IN_CH_AV array 1 1 1 1
RS_330_SUPPORTED no
VACTIVE_INTERL_EVEN no
VDT_HORIZ_MAX_VAL 0x1000
VDT_VERT_MAX_VAL 0x1000
VDT_HSY_CNT_MIN 0
VDT_HBP_CNT_MIN 0
VDT_HACT_CNT_MIN 0
VDT_HFP_CNT_MIN 0
VDT_HSY+HBP_CNT_MIN 0
VDT_VSY_CNT_MIN 0
VDT_VBP_CNT_MIN 0
VDT_VACT_CNT_MIN 0
VDT_VFP_CNT_MIN 0
VDT_VSY+VBP_CNT_MIN 0
VACT_MULTV_ON_DIG 1
VACT_MULTV_ON_MONO array 1 1
VACT_MULTV_ON_MONOHI array 1 1
HACT_MULTV_ON_DIG 1
HACT_MULTV_ON_MONO array 1 1
HACT_MULTV_ON_MONOHI array 1 1
VTOT_ARR_ON_MONO no
VTOT_ARR_ON_CCOL array 525 625
VTOT_ARR_ON_RGB no
VTOT_ARR_ON_SVID no
VTOT_ARR_ON_YUV no
VTOT_ARR_ON_MONOHI no
CLAMP_TIMING_MIN array 250 750 275
//
// ================================================
// none classified board options
// <----------------------------
// ================================================
//
// ***********************************************
// ***********************************************
// SECTION #3: BOARD LIMITATION DESCRIPTION (A)
// ***********************************************
// ***********************************************
[OPTION]
CORONA
//
// Board Type
OPTION yes
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) CORONA
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV yes
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 300 2000
//ANA_VID_AMPL_LIMIT array 300 1999 => 300mV for MET2/MC limit sync detect
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
//
// ================================================
// Pixel clock CORONA
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
PLL_FREQ_LIMIT array 87500 30000000
//PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
PCLK_OUT_HF_MAXVAL 30000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal CORONA
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//*********************************************************************
// Separate SYNC from VIDEO
//SYC_ASEP_O_MONO_AV yes
//*********************************************************************
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure CORONA
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV no
EXP_DEL_TRG_422_AV no
EXP_NDEL_OUT_422_AV no
EXP_DEL_OUT_422_AV no
EXP_NDEL_TRG_422_AV_2 no
EXP_DEL_TRG_422_AV_2 no
EXP_NDEL_OUT_422_AV_2 no
EXP_DEL_OUT_422_AV_2 no
//
//
//
// ================================================
// Grab control CORONA
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
//
// ***********************************************
// ***********************************************
[OPTION_DIG]
CORONA/DIG
//
// Board Type
OPTION_DIG yes
OPTION no
OPTION_LC no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) CORONA/DIG
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 yes
GRB_RGB_PATH_FORCED_AV yes
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 1 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 1 0
SVID_AVAIL array 1 0
//
MONO_DIG_INPUT_AVAIL array 0 1 2 3
RGB_DIG_INPUT_AVAIL array 0
//
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL array 0 1
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 300 2000
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
VID_8BITS array 1 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
//
// ================================================
// Pixel clock CORONA/DIG
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV yes
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
PLL_FREQ_LIMIT array 87500 30000000
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
PCLK_OUT_HF_MAXVAL 120000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal CORONA/DIG
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV yes
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
//SYC_CAM_LATENCY_AV no
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure CORONA/DIG
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_422_AV yes
EXP_NDEL_TRG_422_AV_2 yes
EXP_DEL_TRG_422_AV_2 yes
EXP_NDEL_OUT_422_AV_2 yes
EXP_DEL_OUT_422_AV_2 yes
//
//
// ================================================
// Grab control CORONA/DIG
// ----------->
// ================================================
//
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
//
// ***********************************************
// ***********************************************
[OPTION_LC]
CORONA/LC
//
// Board Type
OPTION_LC yes
OPTION no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) CORONA/LC
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 0
C_COL_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL no
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
SVID_AVAIL array 1 0
YUVVID_AVAIL no
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL no
SVID_INPUT_AVAIL array 0 1
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//ANA_VID_AMPL_LIMIT array 0 1538
//ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
//
//
// ================================================
// Pixel clock CORONA/LC
// ---------->
// ================================================
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 87500 30000000 87500 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
//
//
// ================================================
// Synchronisation signal CORONA/LC
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM no
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_MONOHI_AV no
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_OUT_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
//
//
// ================================================
// Exposure CORONA/LC
// ------->
// ================================================
//
//
EXP_TRG_TTL_TIMER1_AV no
EXP_TRG_TTL_TIMER2_AV no
EXP_MD_WITH_TRG_AV no
EXP_MD_WITH_TRG_AV_2 no
EXP_MD_PERD_AV no
EXP_MD_PERD_AV_2 no
//
//
// ================================================
// Grab control CORONA/LC
// ----------->
// ================================================
//
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV no
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
//
// ***********************************************
// ***********************************************
[OPTION_II]
CORONA-II
//
// Board Type
OPTION_II yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
////
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
MONO_INPUT_AVAIL array 0 1 2
CCOL_INPUT_AVAIL no
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL no
YUVVID_AVAIL no
ANA_VID_AMPL_LIMIT array 300 2000
//ANA_VID_AMPL_LIMIT array 300 1999 => 300mV for MET2/MC limit sync detect
ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
// Patch for Corona2/Corona2-Dig to get 2 Taps in 10 Bits
// Ana Dig
CT_MAX_CONNECTORS array 4 4
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//
//
// ================================================
// Pixel clock CORONA-II
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 40000000 1000 40000000
PLL_FREQ_LIMIT array 87500 40000000
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
// ** Maximum output clock frequency that USERCLK can do (30 MHz)
PCLK_OUT_HF_MAXVAL 40000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal CORONA-II
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//*********************************************************************
// Separate SYNC from VIDEO
//SYC_ASEP_O_MONO_AV yes
//*********************************************************************
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV no
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV no
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV no
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV no
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV no
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure CORONA-II
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_SYN_CLK_MAX_FREQ 40000000
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV no
EXP_DEL_TRG_422_AV no
EXP_NDEL_OUT_422_AV no
EXP_DEL_OUT_422_AV no
EXP_NDEL_TRG_422_AV_2 no
EXP_DEL_TRG_422_AV_2 no
EXP_NDEL_OUT_422_AV_2 no
EXP_DEL_OUT_422_AV_2 no
//
//
//
// ================================================
// Grab control CORONA-II
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
// ***********************************************
// ***********************************************
[OPTION_II_DIG]
CORONA-II/DIG
//
// Board Type
OPTION_II_DIG yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_M2 no
OPTION_MC no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) CORONA-II/DIG
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 yes
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 1 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
MONO_INPUT_AVAIL array 0 1 2
MONO_DIG_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL no
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL no
// Patch for Corona2/Corona2-Dig to get 2 Taps in 10 Bits
// Ana Dig
CT_MAX_CONNECTORS array 4 4
VID_8BITS array 1 1
VID_16BITS array 0 1
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
ANA_VID_AMPL_LIMIT array 300 2000
ANA_VID_GAIN_AVAIL array 1000 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
//
// ================================================
// Pixel clock CORONA-II/DIG
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV yes
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 40000000 1000 40000000
PLL_FREQ_LIMIT array 87500 40000000
PCK_IN_DELAY_AV yes
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
PCLK_OUT_HF_MAXVAL 120000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal CORONA-II/DIG
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV yes
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure CORONA-II/DIG
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_SYN_CLK_MAX_FREQ 40000000
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_422_AV yes
EXP_NDEL_TRG_422_AV_2 yes
EXP_DEL_TRG_422_AV_2 yes
EXP_NDEL_OUT_422_AV_2 yes
EXP_DEL_OUT_422_AV_2 yes
//
//
// ================================================
// Grab control CORONA-II/DIG
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
//
//
// ***********************************************
// ***********************************************
[OPTION_M2]
METEOR-II
//
// Board Type
OPTION_M2 yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_MC no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) METEOR-II
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 0
C_COL_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL no
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
SVID_AVAIL array 1 0
YUVVID_AVAIL no
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL no
SVID_INPUT_AVAIL array 0 1
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//ANA_VID_AMPL_LIMIT array 0 1538
//ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
//
//
// ================================================
// Pixel clock METEOR-II
// ---------->
// ================================================
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 87500 30000000 87500 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
//
//
// ================================================
// Synchronisation signal METEOR-II
// --------------------->
// ================================================
// ana/dig
SYC_REC&GEN_BY_CAM no
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_MONOHI_AV no
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_OUT_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
//
//
// ================================================
// Exposure METEOR-II
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
EXP_TRG_TTL_TIMER1_AV no
EXP_TRG_TTL_TIMER2_AV no
EXP_MD_WITH_TRG_AV no
EXP_MD_WITH_TRG_AV_2 no
EXP_MD_PERD_AV no
EXP_MD_PERD_AV_2 no
//
//
// ================================================
// Grab control METEOR-II
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV no
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
//
// ***********************************************
// ***********************************************
[OPTION_MC]
METEOR-II/MC
//
// Board Type
OPTION_MC yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) METEOR-II/MC
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
MONO_INPUT_AVAIL array 0 1 2
CCOL_INPUT_AVAIL no
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL no
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
ANA_VID_AMPL_LIMIT array 300 2000
ANA_VID_GAIN_AVAIL array 1000 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
//
// ================================================
// Pixel clock METEOR-II/MC
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV yes
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
PLL_FREQ_LIMIT array 87500 30000000
//PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 0
PCK_IN_DELAY_MAXVAL 0
PCK_IN_DELAY_STEP 0
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
PCLK_OUT_HF_MAXVAL 120000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal METEOR-II/MC
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV yes
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure METEOR-II/MC
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_422_AV yes
EXP_NDEL_TRG_422_AV_2 yes
EXP_DEL_TRG_422_AV_2 yes
EXP_NDEL_OUT_422_AV_2 yes
EXP_DEL_OUT_422_AV_2 yes
//
//
// ================================================
// Grab control METEOR-II/MC
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
//
//
//
// ***********************************************
// ***********************************************
[OPTION_MC_DIG]
METEOR-II/MC/DIG
//
// Board Type
OPTION_MC_DIG yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC no
OPTION_M2_JPEG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) METEOR-II/MC/DIG
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL yes
DIG_VID_TTL no
DIG_VID_422 yes
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 1
RGB_COL_VID_AVAIL array 1 1
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
MONO_INPUT_AVAIL array 0 1 2
MONO_DIG_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL no
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL no
VID_8BITS array 1 1
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
ANA_VID_AMPL_LIMIT array 300 2000
ANA_VID_GAIN_AVAIL array 1000 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
//
// ================================================
// Pixel clock METEOR-II/MC/DIG
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV yes
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
PLL_FREQ_LIMIT array 87500 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
PCLK_OUT_HF_MAXVAL 120000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal METEOR-II/MC/DIG
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV yes
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure METEOR-II/MC/DIG
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_422_AV yes
EXP_NDEL_TRG_422_AV_2 yes
EXP_DEL_TRG_422_AV_2 yes
EXP_NDEL_OUT_422_AV_2 yes
EXP_DEL_OUT_422_AV_2 yes
//
//
// ================================================
// Grab control METEOR-II/MC/DIG
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
//
// ***********************************************
// ***********************************************
[OPTION_MC_JPEG]
METEOR-II/MC/MJPEG
//
// Board Type
OPTION_MC_JPEG yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC no
OPTION_MC_DIG no
OPTION_M2_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) METEOR-II/MC/MJPEG
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL array 1 0
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
C_COL_VID_AVAIL array 0 0
SVID_AVAIL array 0 0
MONO_INPUT_AVAIL array 0 1 2
CCOL_INPUT_AVAIL no
RGB_INPUT_AVAIL array 0
SVID_INPUT_AVAIL no
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
ANA_VID_AMPL_LIMIT array 300 2000
ANA_VID_GAIN_AVAIL array 1000 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV no
COLOR_CONTR_ADJ_AV no
COLOR_SATUR_ADJ_AV no
COLOR_HUE_ADJ_AV no
//
//
// ================================================
// Pixel clock METEOR-II/MC/MJPEG
// ---------->
// ================================================
//
PCLK_IN_TTL_AV yes
PCLK_IN_RS422_AV yes
PCLK_OUT_TTL_AV yes
PCLK_OUT_RS422_AV yes
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 1000 30000000 1000 30000000
PLL_FREQ_LIMIT array 87500 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
PCK_INT_DIVD_AV no
PCK_INTMAX_DIV_FACT 1
PCK_CAM_RG_INDIV_AV no
PCK_CAM_RG_IMAX_DIVF 1
PCK_CAM_RG_OUTDIV_AV no
PCK_CAM_RG_OMAX_DIVF 1
PCLK_OUT_HFREQ_AV no
PCLK_OUT_HF_MAX_MULF 2
PCLK_OUT_HF_MAXVAL 120000000
PCLK_OUT_AV_O_MONO array 1 1
PCLK_OUT_AV_O_CCOL array 0 0
PCLK_OUT_AV_O_RGB array 1 1
PCLK_OUT_AV_O_SVID no
PCLK_OUT_AV_O_YUV no
PCLK_OUT_AV_O_MONOHI array 1 1
//
//
// ================================================
// Synchronisation signal METEOR-II/MC/MJPEG
// --------------------->
// ================================================
//
SYC_REC&GEN_BY_CAM yes
//SYC_ASEP_O_MONO_AV yes Moved to Common Options section for variable setting.
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_RGB_AV yes
SYC_ASEP_O_SVID_AV no
//SYC_ASEP_O_YUV_AV no
SYC_ASEP_O_MONOHI_AV yes
//VDT_SERRATION_AVAIL no
//VDT_EQUALIZAT_AVAIL no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV yes
SYC_BLK_OUT_AV no
SYC_CAM_LATENCY_AV yes
//SYC_CAM_LATMAX_HTF 100
//
// *** New characteristics (rev 1.09) ********
// ** Information about availability of input // output sync signal.
SYC_DIG_ON_MONO_AV array 1 1
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_RGB_AV array 1 1
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 1 1
SYC_DIG_H_IN_AV yes
SYC_DIG_H_OUT_AV yes
SYC_DIG_V_IN_AV yes
SYC_DIG_V_OUT_AV yes
HSYN_IN_TTL_AV yes
HSYN_IN_RS422_AV yes
HSYN_OUT_TTL_AV yes
HSYN_OUT_RS422_AV yes
VSYN_IN_TTL_AV yes
VSYN_IN_RS422_AV yes
VSYN_OUT_TTL_AV yes
VSYN_OUT_RS422_AV yes
HSYN_IN_POS_POL_AV yes
HSYN_IN_NEG_POL_AV yes
HSYN_OUT_POS_POL_AV yes
HSYN_OUT_NEG_POL_AV yes
VSYN_IN_POS_POL_AV yes
VSYN_IN_NEG_POL_AV yes
VSYN_OUT_POS_POL_AV yes
VSYN_OUT_NEG_POL_AV yes
//
//
// ================================================
// Exposure METEOR-II/MC/MJPEG
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
//EXP_ASY_CLK_AV yes
//
//EXP_ASY_CLK_AV_2 yes
//
//EXP_CLOCK_HSYNC_AV yes
//
//EXP_CLOCK_2_HSYNC_AV yes
//
//EXP_CLOCK_TIMER2_AV yes
//
//EXP_CLOCK_2_TIMER1_AV yes
//
EXP_TRG_TTL_TIMER1_AV yes
EXP_TRG_TTL_TIMER2_AV yes
EXP_NDEL_TRG_422_AV yes
EXP_DEL_TRG_422_AV yes
EXP_NDEL_OUT_422_AV yes
EXP_DEL_OUT_422_AV yes
EXP_NDEL_TRG_422_AV_2 yes
EXP_DEL_TRG_422_AV_2 yes
EXP_NDEL_OUT_422_AV_2 yes
EXP_DEL_OUT_422_AV_2 yes
//
//
// ================================================
// Grab control METEOR-II/MC/MJPEG
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV yes
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV yes
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV yes
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV yes
GRAB_IMM_EXPPERD_AV yes
GRAB_ISK_EXPPERD_AV yes
GRB_TRG_SIGNAL_DPORT_AV yes
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV yes
GRB_TRG_SIGNAL_TIMER1_AV yes
//
//
// ***********************************************
// ***********************************************
[OPTION_M2_JPEG]
METEOR-II/MJPEG
//
// Board Type
OPTION_M2_JPEG yes
OPTION no
OPTION_LC no
OPTION_DIG no
OPTION_II no
OPTION_II_DIG no
OPTION_M2 no
OPTION_MC no
OPTION_MC_DIG no
OPTION_MC_JPEG no
OPTION_MC_JPEG_DIG no
//
// ================================================
// Video signal format (analog/digital) METEOR-II/MJPEG
// ----------------------------------->
// ================================================
//
ANA_VID_AVAIL yes
DIG_VID_AVAIL no
DIG_VID_TTL no
DIG_VID_422 no
GRB_RGB_PATH_FORCED_AV no
MONO_VID_AVAIL array 1 0
C_COL_VID_AVAIL array 1 0
RGB_COL_VID_AVAIL no
RGB_PACK_VID_AVAIL array 0 0
RGB_ALPHA_VID_AVAIL array 0 0
SVID_AVAIL array 1 0
YUVVID_AVAIL no
MONO_INPUT_AVAIL array 0 1 2 3
CCOL_INPUT_AVAIL array 0 1 2 3
RGB_INPUT_AVAIL no
SVID_INPUT_AVAIL array 0 1
VID_8BITS array 1 0
VID_16BITS array 0 0
VID_24BITS array 0 0
VID_32BITS array 0 0
VID_64BITS array 0 0
//ANA_VID_AMPL_LIMIT array 0 1538
//ANA_VID_GAIN_AVAIL array 1300 2000 2800 4000
COLOR_BRGHT_ADJ_AV yes
COLOR_CONTR_ADJ_AV yes
COLOR_SATUR_ADJ_AV yes
COLOR_HUE_ADJ_AV yes
//
//
// ================================================
// Pixel clock METEOR-II/MJPEG
// ---------->
// ================================================
//
PCLK_IN_TTL_AV no
PCLK_IN_RS422_AV no
PCLK_OUT_TTL_AV no
PCLK_OUT_RS422_AV no
HIGH_SPEED_GRAB yes
PCLK_FREQ_LIMIT array 87500 30000000 87500 30000000
PCK_IN_DELAY_AV no
PCK_IN_DELAY_MINVAL 9
PCK_IN_DELAY_MAXVAL 54
PCK_IN_DELAY_STEP 3
//
//
// ================================================
// Synchronisation signal METEOR-II/MJPEG
// --------------------->
// ================================================
// ana/dig
SYC_REC&GEN_BY_CAM no
SYC_ASEP_O_MONO_AV no
SYC_ASEP_O_CCOL_AV no
SYC_ASEP_O_SVID_AV no
SYC_ASEP_O_MONOHI_AV no
SYC_DIG_ON_MONO_AV array 0 0
SYC_DIG_ON_CCOL_AV array 0 0
SYC_DIG_ON_SVID_AV array 0 0
SYC_DIG_ON_MONOHI_AV array 0 0
SYC_DIG_H_IN_AV no
SYC_DIG_V_IN_AV no
SYC_DIG_H_OUT_AV no
SYC_DIG_V_OUT_AV no
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
//
// *** New characteristics (rev 1.08) ********
// ** Information about block sync. supported in input//output sync signal
SYC_BLK_IN_AV no
SYC_BLK_OUT_AV no
//
//
// ================================================
// Exposure METEOR-II/MJPEG
// ------->
// ================================================
//
//
// ** Exposure asynchronous clock signal information **
EXP_TRG_TTL_TIMER1_AV no
EXP_TRG_TTL_TIMER2_AV no
EXP_MD_WITH_TRG_AV no
EXP_MD_WITH_TRG_AV_2 no
EXP_MD_PERD_AV no
EXP_MD_PERD_AV_2 no
//
//
// ================================================
// Grab control METEOR-II/MJPEG
// ----------->
// ================================================
//
GRAB_ON_HW_TRG_AV yes
GRAB_ON_SW_TRG_AV no
GRAB_HW_TRG_TTL_AV yes
GRAB_HW_TRG_422_AV no
GRAB_START_ODD_AV yes
GRAB_START_EVEN_AV yes
GRAB_START_ANY_AV yes
GRAB_ACT_NXT_FRM_AV yes
GRAB_ACT_IMM_AV no
GRAB_ACT_IMM_SKNF_AV no
GRAB_NXT_EXPCKDV_AV no
GRAB_IMM_EXPCKDV_AV no
GRAB_ISK_EXPCKDV_AV no
GRAB_NXT_EXPPERD_AV no
GRAB_IMM_EXPPERD_AV no
GRAB_ISK_EXPPERD_AV no
GRB_TRG_SIGNAL_DPORT_AV no
GRB_TRG_SIGNAL_APORT_AV yes
GRB_TRG_SIGNAL_TIMER2_AV no
GRB_TRG_SIGNAL_TIMER1_AV no
//
//
//
//
// *********************************************
// *********************************************
// Section #2 : DEFINE VALUES
// *********************************************
// *********************************************
[DEFINE_VALUE]
//
//
// ===================================================
// Define values related with the KSO127 programmation
// ===================================================
//
// N.B.
// DEF utilisant un autre DEF doit etre toujours place apres ce DEF utilise dans son equation
// Raison : Valeur du DEF doit etre update
// ------------------------------------------------------------------
//
DEF_CORONA
value = ( OPTION | OPTION_LC | OPTION_DIG ) ;
//
// ------------------------------------------------------------------
DEF_CORONA_II
value = ( OPTION_II | OPTION_II_DIG ) ;
//
// ------------------------------------------------------------------
DEF_METEOR_II
value = ( OPTION_M2 | OPTION_M2_JPEG ) ;
//
// ------------------------------------------------------------------
DEF_METEOR_II_MC
value = ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ;
//
// ------------------------------------------------------------------
// Bt254 pixel pipe = 2 Rev1 , Raytheon pixel pipe = 3 Rev2,3,4
DEF_BTPIPE
value = 3 ;
// ------------------------------------------------------------------
// LUT pixel pipe
DEF_LUTPIPE
value = 3 ;
// ------------------------------------------------------------------
// Digital sync pipe 1 or 3 ( Receive PCLK & SYNCs from Camera )
DEF_DIG_SYNCPIPE
value = ( 3 - ( PCK_CAM_GEN * SYC_DIG * 2 ) ) ;
// ------------------------------------------------------------------
// Digital Video pipe
DEF_DIG_VIDPIPE
value = 1 ;
// ------------------------------------------------------------------
DEF_PSG_HSPLLFB
value = 1 + ( VDC_ANA * SYC_DIG * SYC_H_IN * ( VDT_HSYNC - 2 ) * ( VDT_HSYNC >= 2 ) ) ;
// ------------------------------------------------------------------
DEF_HSYNC_TRAILS_VSYNC
value = 2 ;
// ------------------------------------------------------------------
DEF_NTSC_HSYNC_TO_COLOR_BURST
// Value in pixel clock (12.2726 Mhz)
value = 7 ;
// ------------------------------------------------------------------
DEF_NTSC_COLOR_BURST_LENGTH
// Value in pixel clock (12.2726 Mhz)
value = 31 ;
// ------------------------------------------------------------------
DEF_HTOTAL_IN
value = ( VDT_HFPORCH + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) ;
// ------------------------------------------------------------------
DEF_HTOTAL_ODD_INTERLACED
value = ( VDT_INTERL & ( DEF_HTOTAL_IN % 2 ) ) ;
// ------------------------------------------------------------------
DEF_VTOTAL_IN
value = ( VDT_VFPORCH + VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE ) ;
// ------------------------------------------------------------------
//DEF_HACTIVE
//value = ( DEF_HTOTAL_IN - VDT_HFPORCH - VDT_HSYNC - VDT_HBPORCH ) ;
// ------------------------------------------------------------------
//DEF_HBPORCH
//value = ( ( VDT_HTOTAL - VDT_HFPORCH - VDT_HSYNC - VDT_HACTIVE ) * ( VDT_HBPORCH > 0 ) ) ;
// ------------------------------------------------------------------
//DEF_HFPORCH
//value = ( ( VDT_HTOTAL - VDT_HBPORCH - VDT_HSYNC - VDT_HACTIVE ) * ( VDT_HFPORCH > 0 ) ) ;
// ------------------------------------------------------------------
//DEF_HFPORCH_MAX
//value = ( ( VDT_HFPORCH > DEF_HFPORCH ) & ( DEF_HFPORCH < 0xFFFFFFFF ) ) ;
//value = ( ( VDT_HTOTAL < DEF_HTOTAL_IN ) & ( VDT_HFPORCH > DEF_HFPORCH ) & ( DEF_HFPORCH < 0xFFFFFFF0 ) ) ;
// ------------------------------------------------------------------
DEF_SYSCLK_FREQ
// frequency in Hz
value = 25000000 ;
// ------------------------------------------------------------------
// SYSCLK = 15625 Mhz pour DCF's Standards
DEF_SYSCLK_SEL
value = (
( ( ( ( PCK_FREQ / 12500000 ) * 250 ) > DEF_HTOTAL_IN ) & ( PCK_FREQ >= 12500000 ) ) ? 0 :
( ( ( ( ( PCK_FREQ / 6250000 ) * 250 ) > DEF_HTOTAL_IN ) & ( PCK_FREQ >= 6250000 ) ) ? 1 :
( ( ( ( ( PCK_FREQ / 3125000 ) * 250 ) > DEF_HTOTAL_IN ) & ( PCK_FREQ >= 3125000 ) ) ? 2 :
3 ) )
) ;
//
//value = (
// ( ( ( ( PCK_FREQ / 12500000 ) * 250 ) > VDT_HTOTAL ) & ( PCK_FREQ >= 12500000 ) ) ? 0 :
// ( ( ( ( ( PCK_FREQ / 6250000 ) * 250 ) > VDT_HTOTAL ) & ( PCK_FREQ >= 6250000 ) ) ? 1 :
// ( ( ( ( ( PCK_FREQ / 3125000 ) * 250 ) > VDT_HTOTAL ) & ( PCK_FREQ >= 3125000 ) ) ? 2 :
// 3 ) )
// ) ;
// ------------------------------------------------------------------
//DEF_EXPONENT
//value = ( 1 << DEF_SYSCLK_SEL ) ;
// ------------------------------------------------------------------
DEF_SYSCLK156MZ_MULT
value = ( ( DEF_SYSCLK_SEL == 3 ) ? 1 :
( ( DEF_SYSCLK_SEL == 2 ) ? 2 :
( ( DEF_SYSCLK_SEL == 1 ) ? 4 :
( ( DEF_SYSCLK_SEL == 0 ) ? 8 :
1 ) ) )
) ;
// ------------------------------------------------------------------
DEF_HFPORCH_60HZ
value = 22 ;
// ------------------------------------------------------------------
DEF_HSYNC_60HZ
value = 58 ;
// ------------------------------------------------------------------
DEF_HBPORCH_60HZ
value = 60 ;
// ------------------------------------------------------------------
DEF_HACTIVE_60HZ
value = 640 ;
// ------------------------------------------------------------------
DEF_HTOTAL_60HZ
value = 780 ;
// ------------------------------------------------------------------
DEF_HFPORCH_50HZ
value = 22 ;
// ------------------------------------------------------------------
DEF_HSYNC_50HZ
value = 69 ;
// ------------------------------------------------------------------
DEF_HBPORCH_50HZ
value = 85 ;
// ------------------------------------------------------------------
DEF_HACTIVE_50HZ
value = 768 ;
// ------------------------------------------------------------------
DEF_HTOTAL_50HZ
value = 944 ;
// ------------------------------------------------------------------
DEF_DIG_HVNEG_VALUE
value = ( ( VDT_HFPORCH == 0xFFFFFFFF ) | ( VDT_HBPORCH == 0xFFFFFFFF ) |
( VDT_VFPORCH == 0xFFFFFFFF ) | ( VDT_VBPORCH == 0xFFFFFFFF )
);
// ( DEF_HFPORCH == 0xFFFFFFFF ) | ( DEF_HBPORCH == 0xFFFFFFFF )
// ------------------------------------------------------------------
DEF_DAC8800_DEFAULT
value = 0x3b ;
// ------------------------------------------------------------------
// KS0127 chip delay value
DEF_KS_CHIP_DELAY
// 120/2
value = 60 ;
// ------------------------------------------------------------------
// KS0127 default horizontal cropping
// First and last pixel locations
DEF_KS_HAVB_60HZ_DEFAULT
// 334/2
value = 167 ;
// ------------------------------------------------------------------
DEF_KS_HAVE_60HZ_DEFAULT
// 58/2
value = 29 ;
// ------------------------------------------------------------------
DEF_KS_HS1B_60HZ_DEFAULT
// 65/2 = 32.5
value = 32 ;
// ------------------------------------------------------------------
DEF_KS_HS1E_60HZ_DEFAULT
// 220/2
value = 110 ;
// ------------------------------------------------------------------
DEF_KS_HAVB_50HZ_DEFAULT
// 415/2 = 207.5
value = 207 ;
// ------------------------------------------------------------------
DEF_KS_HAVE_50HZ_DEFAULT
// 59/2 = 29.5
value = 29 ;
// ------------------------------------------------------------------
DEF_KS_HS1B_50HZ_DEFAULT
// 65/2 = 32.5
value = 32 ;
// ------------------------------------------------------------------
DEF_KS_HS1E_50HZ_DEFAULT
// 270/2
value = 135 ;
// ------------------------------------------------------------------
// HBPORCH + HFPORCH
DEF_NTSC_PORCH
value = 82 ;
// ------------------------------------------------------------------
// Effective on the fly by the inputted changes for the NTSC timing
DEF_60HZ_HV_TOTAL_STD
//value = (
// ( VDT_HTOTAL == 780 ) & ( VDT_VTOTAL == 525 ) & ( ( PCK_FREQ & 0xffff00 ) == 12272384 )
// ) ;
value = (
( DEF_HTOTAL_IN == 780 ) & ( DEF_VTOTAL_IN == 525 ) & ( ( PCK_FREQ & 0xffff00 ) == 12272384 )
) ;
// ------------------------------------------------------------------
// Effective on the fly by the inputted changes for the PAL timing
DEF_50HZ_HV_TOTAL_STD
//value = (
// ( VDT_HTOTAL == 944 ) & ( VDT_VTOTAL == 625 ) & ( ( PCK_FREQ & 0xffff00 ) == 14749952 )
// ) ;
value = (
( DEF_HTOTAL_IN == 944 ) & ( DEF_VTOTAL_IN == 625 ) & ( ( PCK_FREQ & 0xffff00 ) == 14749952 )
) ;
// ------------------------------------------------------------------
// Effective after changes after validation for the NTSC & PAL timing
DEF_VDT_HV_TOTAL_STD
value = (
( ( VDT_HTOTAL == 780 ) & ( VDT_VTOTAL == 525 ) & ( ( PCK_FREQ & 0xffff00 ) == 12272384 ) ) |
( ( VDT_HTOTAL == 944 ) & ( VDT_VTOTAL == 625 ) & ( ( PCK_FREQ & 0xffff00 ) == 14749952 ) )
) ;
// ------------------------------------------------------------------
//DEF_HS_ERR_PAIR
//value = (
// ( DEF_60HZ_HV_TOTAL_STD & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID ) & ( VDT_HSYNC % 2 ) & SYC_ANA ) |
// ( VDC_RGB_COL & ( DEF_60HZ_HV_TOTAL_STD | DEF_50HZ_HV_TOTAL_STD ) & SYC_ANA & ( VDT_HSYNC % 2 ) )
// ) ;
// ------------------------------------------------------------------
//DEF_HS_ERR_IMPAIR
//value = ( DEF_50HZ_HV_TOTAL_STD & VDT_INTERL & ( VDC_C_COLOR | VDC_SVID ) & ( ! ( VDT_HSYNC % 2 ) ) & SYC_ANA ) ;
// ------------------------------------------------------------------
//DEF_HACTIVE_LOCK
//value = ( ! PCK_USE_OUT ) ;
//value = ( ( ( ! VDL_PEDEST ) * DEF_BT254_PATH ) + ( DEF_DEC_PATH * ( ! PCK_USE_OUT ) ) ) ;
//value = ( ( VDT_HACTIVE == DEF_HACTIVE ) & ( ! DEF_HS_ERR_PAIR ) & ( ! DEF_HS_ERR_IMPAIR ) ) ;
//value = ( VDT_HACTIVE == ( DEF_HTOTAL_IN - VDT_HFPORCH - VDT_HSYNC - VDT_HBPORCH ) ) ;
// ------------------------------------------------------------------
// The "DEF_VID_TIM_STD" value is set to '1'
// when the video timing is standard .
DEF_VID_TIM_STD
value = ( ( ( DEF_60HZ_HV_TOTAL_STD | DEF_50HZ_HV_TOTAL_STD | DEF_VDT_HV_TOTAL_STD ) & VDT_INTERL ) ? 1 : 0 ) ;
// ------------------------------------------------------------------
DEF_MONO_VIA_RGB
value = ( ( GRB_RGB_PATH_FORCED & VDC_MONO ) |
( ( DEF_METEOR_II_MC | DEF_CORONA_II ) & VDC_MONO ) |
( VDC_DIG & VDC_MONO ) |
( DEF_VID_TIM_STD & VDC_MONO & VDC_ANA & SYC_DIG ) |
( ( ! ( DEF_VID_TIM_STD ) ) & VDC_MONO & ( ! ( DEF_METEOR_II | OPTION_LC ) ) ) |
( ( ( GCT_CAMERA_TAPS > 0 ) | ( GCT_CAMERA_NUMBER > 0 ) ) & VDC_MONO & ( ! DEF_METEOR_II ) & ( ! OPTION_LC ) )
) ;
//
//value = ( ( GRB_RGB_PATH_FORCED & VDC_MONO ) |
// ( ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG |
// OPTION_II | OPTION_II_DIG
// ) & VDC_MONO ) |
// ( VDC_DIG & VDC_MONO ) |
// ( DEF_VID_TIM_STD & VDC_MONO & VDC_ANA & SYC_DIG ) |
// ( ( ! ( DEF_VID_TIM_STD ) ) & VDC_MONO & ( ! ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) ) ) |
// ( ( ( GCT_CAMERA_TAPS > 0 ) | ( GCT_CAMERA_NUMBER > 0 ) ) & VDC_MONO & ( ! ( OPTION_M2 | OPTION_M2_JPEG ) ) & ( ! OPTION_LC ) )
// ) ;
// ------------------------------------------------------------------
// "DEF_BT254_PATH" = '1' when the Bt254 data is used
// and the PSG generates the synchronization signals
// for the VIA and the Pixel Packer.
// Case 0 : RGB video signal
// Case 1 : Monochrome video with non-standard video timing
// Case 2 : Monochrome video with 2 taps camera
// Case 3 : Monochrome video with standard video timing
DEF_BT254_PATH
value = ( VDC_RGB_COL | DEF_MONO_VIA_RGB | DEF_METEOR_II_MC | DEF_CORONA_II | ( VDC_DIG & VDC_RGB_COL ) ) ;
//
//value = ( VDC_RGB_COL | DEF_MONO_VIA_RGB | OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG
// | OPTION_MC_JPEG_DIG | OPTION_II | OPTION_II_DIG | ( VDC_DIG & VDC_RGB_COL ) ) ;
//value = ( VDC_RGB_COL | DEF_MONO_VIA_RGB | OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG
// | OPTION_MC_JPEG_DIG | ( VDC_DIG & VDC_RGB_COL ) ) ;
// ------------------------------------------------------------------
DEF_MONO_VIA_DEC
value = ( ( VDC_MONO & ( ! ( GRB_RGB_PATH_FORCED ) ) ) & DEF_VID_TIM_STD
& ( ! ( DEF_METEOR_II_MC | DEF_CORONA_II ) )
& ( ( GCT_CAMERA_TAPS == 0 ) & ( GCT_CAMERA_NUMBER == 0 ) ) & VDC_ANA & SYC_ANA
) ;
//
//value = ( ( VDC_MONO & ( ! ( GRB_RGB_PATH_FORCED ) ) ) & DEF_VID_TIM_STD
// & ( ! ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG |
// OPTION_MC_JPEG_DIG | OPTION_II | OPTION_II_DIG
// )
// )
// & ( ( GCT_CAMERA_TAPS == 0 ) & ( GCT_CAMERA_NUMBER == 0 ) ) & VDC_ANA & SYC_ANA
// ) ;
//value = ( ( VDC_MONO & ( ! ( GRB_RGB_PATH_FORCED ) ) ) & DEF_VID_TIM_STD
// & ( ! ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// & ( ( GCT_CAMERA_TAPS == 0 ) & ( GCT_CAMERA_NUMBER == 0 ) ) & VDC_ANA & SYC_ANA
// ) ;
// ------------------------------------------------------------------
//
// "DEF_DEC_PATH" = '1' when the KS0127 video decoder
// is used for digitizing the video signal and generating
// the synchronization signals for the VIA and the Pixel Packer.
// Case 0 : Composite color video
// Case 1 : S-VIDEO video signal
// Case 2 : Monochrome video with standard video timing
DEF_DEC_PATH
value = ( ( DEF_MONO_VIA_DEC | VDC_C_COLOR | VDC_SVID | VDC_YUVVID ) * VDC_ANA * SYC_ANA ) ;
//value = ( ( DEF_MONO_VIA_DEC * ( ! ( OPTION_MC ) ) ) | ( VDC_C_COLOR & ( ! OPTION_MC ) ) | VDC_SVID | VDC_YUVVID ) ;
// ------------------------------------------------------------------
DEF_PSG_ON
value = ( DEF_BT254_PATH | SYC_H_OUT | SYC_V_OUT |
( DEF_DEC_PATH * ( EXP_MD_PERD | EXP_MD_W_TRG | EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) )
) ;
//
// ------------------------------------------------------------------
// Horizontal blanking in pixel clock; NTSC
DEF_HOR_BLANK_60HZ
value = ( VDT_HFPORCH + DEF_HSYNC_60HZ + VDT_HBPORCH ) ;
//value = ( VDT_HFPORCH + DEF_HSYNC_60HZ + VDT_HBPORCH ) ;
// ------------------------------------------------------------------
// Horizontal blanking in pixel clock; PAL
DEF_HOR_BLANK_50HZ
value = ( VDT_HFPORCH + DEF_HSYNC_50HZ + VDT_HBPORCH ) ;
// ------------------------------------------------------------------
// NTSC => 15.734 Khz +- 54 Hhz
DEF_NTSC
value = ( VDT_INTERL * ( VDT_HSYNC_FREQ >= 15680 ) * ( VDT_HSYNC_FREQ <= 15788 ) ) ;
// ------------------------------------------------------------------
// PAL => 15.625 Khz +- 54 Hhz
DEF_PAL
value = ( VDT_INTERL * ( VDT_HSYNC_FREQ >= 15571 ) * ( VDT_HSYNC_FREQ <= 15679 ) ) ;
// ------------------------------------------------------------------
// "DEF_PLL_ON" = '1' when the Bt254 is used and no
// input clock signal is available from the camera.
// <<<< Revoir pour le Grab port connector
DEF_PLL_ON
//value = (
// ( DEF_BT254_PATH == 1 )
// ( PCK_ITTL == 0 )
// ) ;
value = ( DEF_BT254_PATH ? 1 :
0 ) ;
// ------------------------------------------------------------------
DEF_DIGITIZER_MASTER
value = ( PCK_CAM_REC | PCK_CAM_R&G | ( ! ( SYC_CAM_GEN ) ) ) * DEF_PSG_ON ;
// ------------------------------------------------------------------
DEF_PCLK_MAX
value = ( PCK_FREQ > ( 30000000 + ( DEF_CORONA_II * 10000000 ) ) ) ;
//value = ( 30000000 + ( DEF_CORONA_II * 10000000 ) ) ) ;
// ------------------------------------------------------------------
DEF_VCO_FREQ
// frequency of VCO in Hz PCLK TOTAL DIV ( PDA * 4 ou LOAD CNTR * 2 )
value = (
( ( PCK_FREQ * 6 ) * ( ( PCK_FREQ > 25000000 ) & ( PCK_FREQ <= 30000000 ) & DEF_DIGITIZER_MASTER ) ) +
( ( PCK_FREQ * 8 ) * ( ( PCK_FREQ > 6250000 )
& ( ( ( PCK_FREQ <= 30000000 ) & SYC_CAM_GEN ) | ( ( PCK_FREQ <= 25000000 ) & DEF_DIGITIZER_MASTER ) ) ) ) +
( ( PCK_FREQ * 32 ) * ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ) +
( ( PCK_FREQ * 64 ) * ( ( PCK_FREQ > 780000 ) & ( PCK_FREQ <= 1600000 ) ) ) +
( ( PCK_FREQ * 160 ) * ( ( PCK_FREQ >= 87500 ) & ( PCK_FREQ <= 780000 ) ) ) +
( ( PCK_FREQ * 4 ) * ( ( PCK_FREQ > 30000000 ) * DEF_CORONA_II ) )
) * DEF_PLL_ON ;
//
//value = (
// ( ( PCK_FREQ * 6 ) * ( ( PCK_FREQ > 25000000 ) & ( PCK_FREQ <= 30000000 ) & DEF_DIGITIZER_MASTER ) ) +
// ( ( PCK_FREQ * 8 ) * ( ( PCK_FREQ > 6250000 )
// & ( ( ( PCK_FREQ <= 30000000 ) & SYC_CAM_GEN ) | ( ( PCK_FREQ <= 25000000 ) & DEF_DIGITIZER_MASTER ) ) ) ) +
// ( ( PCK_FREQ * 32 ) * ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ) +
// ( ( PCK_FREQ * 64 ) * ( ( PCK_FREQ > 780000 ) & ( PCK_FREQ <= 1600000 ) ) ) +
// ( ( PCK_FREQ * 160 ) * ( ( PCK_FREQ >= 87500 ) & ( PCK_FREQ <= 780000 ) ) ) +
// ( ( PCK_FREQ * 4 ) * ( ( PCK_FREQ > 30000000 ) * ( OPTION_II | OPTION_II_DIG ) ) )
// ) * DEF_PLL_ON ;
//value = (
// ( ( PCK_FREQ * 6 ) * ( ( PCK_FREQ > 25000000 ) & ( PCK_FREQ <= 30000000 ) & DEF_DIGITIZER_MASTER ) ) +
// ( ( PCK_FREQ * 8 ) * ( ( PCK_FREQ > 6250000 )
// & ( ( ( PCK_FREQ <= 30000000 ) & SYC_CAM_GEN ) | ( ( PCK_FREQ <= 25000000 ) & DEF_DIGITIZER_MASTER ) ) ) ) +
// ( ( PCK_FREQ * 32 ) * ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ) +
// ( ( PCK_FREQ * 64 ) * ( ( PCK_FREQ > 780000 ) & ( PCK_FREQ <= 1600000 ) ) ) +
// ( ( PCK_FREQ * 160 ) * ( ( PCK_FREQ >= 87500 ) & ( PCK_FREQ <= 780000 ) ) )
// ) * DEF_PLL_ON ;
// ------------------------------------------------------------------
DEF_PLL_PDA
value = (
( ( PCK_FREQ > 6250000 ) & ( PCK_FREQ <= 40000000 ) ) ? 1 :
( ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ? 4 :
( ( PCK_FREQ <= 1600000 ) ? 8 :
1 ) )
) * DEF_PLL_ON ;
//
//value = (
// ( ( PCK_FREQ > 6250000 ) & ( PCK_FREQ <= 30000000 ) ) ? 1 :
// ( ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ? 4 :
// ( ( PCK_FREQ <= 1600000 ) ? 8 :
// 1 ) )
// ) * DEF_PLL_ON ;
// ------------------------------------------------------------------
// Load counter by 3 ONLY in MASTER Mode
DEF_PLL_PATHDIV
value = (
( ( PCK_FREQ > 25000000 ) & ( PCK_FREQ <= 30000000 ) & DEF_DIGITIZER_MASTER ) ? 3 :
( ( PCK_FREQ <= 780000 ) ? 10 :
4 )
) * DEF_PLL_ON ;
//value = (
// ( ( PCK_FREQ > 25000000 ) & ( PCK_FREQ <= 30000000 ) ) ? 3 :
// ( ( PCK_FREQ <= 780000 ) ? 10 :
// 4 )
// ) * DEF_PLL_ON ;
DEF_VCO_FREQ_DEF
value = ( PCK_FREQ * DEF_PLL_PDA * ( 2 - ( DEF_CORONA_II * ( PCK_FREQ > 30000000 ) ) ) * DEF_PLL_PATHDIV
) ;
//
// Add CoronaII with Pclk = 40 Mhz without diviser2
//value = PCK_FREQ * DEF_PLL_PDA * ( 2 * ( PCK_FREQ <= 30000000 ) ) * DEF_PLL_PATHDIV ;
//value = PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ;
// ------------------------------------------------------------------
DEF_PLL_REG0
value = ( (
( ! DEF_DIGITIZER_MASTER ) * SYC_CAM_GEN *
( ( PCK_CAM_GEN & ( ! ( PCK_CAM_R&G ) ) ) | ( ! ( PCK_USE_OUT ) ) ) * 0x04F
) +
( DEF_DIGITIZER_MASTER * (
( 572 * ( PCK_FREQ < 500000 ) ) +
( 2047 * ( PCK_FREQ >= 500000 ) )
)
)
) * DEF_PLL_ON ;
//
//value = ( ( SYC_CAM_GEN * ( ( PCK_CAM_GEN & ( ! ( PCK_CAM_R&G ) ) ) | ( ! ( PCK_USE_OUT ) ) ) * 0x04F ) +
// ( DEF_DIGITIZER_MASTER * (
// ( 572 * ( PCK_FREQ < 500000 ) ) +
// ( 2047 * ( PCK_FREQ >= 500000 ) )
// )
// )
// ) * DEF_PLL_ON ;
// ( 2047 * ( PCK_FREQ > 500000 ) * ( PCK_FREQ <= 30000000 ) ) +
//value = ( ( SYC_CAM_GEN * ( ( PCK_CAM_GEN & ( ! ( PCK_CAM_R&G ) ) ) | ( ! ( PCK_USE_OUT ) ) ) * 0x04F ) +
// ( DEF_DIGITIZER_MASTER * (
// ( 2047 * ( PCK_FREQ >= 500000 ) ) +
// ( 572 * ( PCK_FREQ < 500000 ) )
// )
// )
// ) * DEF_PLL_ON ;
// ------------------------------------------------------------------
DEF_PLL_REG3
value = ( ( (
( DEF_PLL_REG0 * 25000000 )
/ ( PCK_FREQ * DEF_PLL_PDA * ( 2 - ( DEF_CORONA_II * ( PCK_FREQ > 30000000 ) ) ) * DEF_PLL_PATHDIV )
)
- 1.5 - ( 4 * ( ( PCK_FREQ < 9000000 ) & ( PCK_FREQ > 12800000 ) ) )
) * DEF_DIGITIZER_MASTER
) * DEF_PLL_ON ;
//
//value = ( ( ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) )
// - 1.5 - ( 4 * ( ( PCK_FREQ < 9000000 ) & ( PCK_FREQ > 12800000 ) ) )
// ) * DEF_DIGITIZER_MASTER
// ) * DEF_PLL_ON ;
//value = ( ( ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) )
// - 5.5 - ( 24 * ( PCK_FREQ >= 18500000 ) * ( PCK_FREQ < 19100000 ) )
// ) * DEF_DIGITIZER_MASTER
// ) * DEF_PLL_ON ;
//
//------------------------------------------------------------------
//DEF_REG3_DECIMAL
//value = ( ( ( ( 2047 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) ) * 1000000 ) - 2000000 ) ;
//------------------------------------------------------------------
DEF_PLL_FACTOR
value = (
( ( PCK_FREQ >= 10000 ) & ( PCK_FREQ < 200000 ) * 100000 ) +
( ( PCK_FREQ >= 200000 ) & ( PCK_FREQ < 500000 ) * 100267 ) +
(
(
( ( PCK_FREQ >= 500000 ) & ( PCK_FREQ <= 780000 ) ) |
( ( PCK_FREQ >= 3200000 ) & ( PCK_FREQ < 3700000 ) )
) * 100175
) +
( ( PCK_FREQ > 780000 ) & ( PCK_FREQ < 1000000 ) * 100110 ) +
( ( PCK_FREQ >= 1000000 ) & ( PCK_FREQ < 3200000 ) * 100152 ) +
( ( PCK_FREQ >= 3700000 ) & ( PCK_FREQ < 5000000 ) * 100248 ) +
( ( PCK_FREQ >= 5400000 ) & ( PCK_FREQ < 6300000 ) * 100335 ) +
( ( PCK_FREQ >= 6300000 ) & ( PCK_FREQ < 9000000 ) * 100103 ) +
( ( PCK_FREQ >= 9000000 ) & ( PCK_FREQ < 12800000 ) * 100150 ) +
( ( PCK_FREQ >= 12800000 ) & ( PCK_FREQ < 15500000 ) * 100200 ) +
( ( PCK_FREQ >= 15500000 ) & ( PCK_FREQ < 19100000 ) * 100256 ) +
(
(
( ( PCK_FREQ >= 19100000 ) & ( PCK_FREQ < 22500000 ) ) |
( ( PCK_FREQ >= 5000000 ) & ( PCK_FREQ < 5400000 ) )
) * 100309
) +
( ( PCK_FREQ >= 22500000 ) & ( PCK_FREQ < 25100000 ) * 100353 ) +
( ( PCK_FREQ >= 25100000 ) & ( PCK_FREQ < 27500000 ) * 100286 ) +
( ( PCK_FREQ >= 27500000 ) & ( PCK_FREQ < 29700000 ) * 100316 ) +
( ( PCK_FREQ >= 29700000 ) & ( PCK_FREQ <= 30000000 ) * 100336 ) +
( ( PCK_FREQ > 30000000 ) & ( PCK_FREQ <= 40000000 ) * 75200 )
) ;
//
//value = (
// ( ( PCK_FREQ >= 10000 ) & ( PCK_FREQ < 200000 ) * 100000 ) +
// ( ( PCK_FREQ >= 200000 ) & ( PCK_FREQ < 500000 ) * 100267 ) +
// (
// (
// ( ( PCK_FREQ >= 500000 ) & ( PCK_FREQ <= 780000 ) ) |
// ( ( PCK_FREQ >= 3200000 ) & ( PCK_FREQ < 3700000 ) )
// ) * 100175
// ) +
// ( ( PCK_FREQ > 780000 ) & ( PCK_FREQ < 1000000 ) * 100110 ) +
// ( ( PCK_FREQ >= 1000000 ) & ( PCK_FREQ < 3200000 ) * 100152 ) +
// ( ( PCK_FREQ >= 3700000 ) & ( PCK_FREQ < 5000000 ) * 100248 ) +
// ( ( PCK_FREQ >= 5400000 ) & ( PCK_FREQ < 6300000 ) * 100335 ) +
// ( ( PCK_FREQ >= 6300000 ) & ( PCK_FREQ < 9000000 ) * 100103 ) +
// ( ( PCK_FREQ >= 9000000 ) & ( PCK_FREQ < 12800000 ) * 100150 ) +
// ( ( PCK_FREQ >= 12800000 ) & ( PCK_FREQ < 15500000 ) * 100200 ) +
// ( ( PCK_FREQ >= 15500000 ) & ( PCK_FREQ < 19100000 ) * 100256 ) +
// (
// (
// ( ( PCK_FREQ >= 19100000 ) & ( PCK_FREQ < 22500000 ) ) |
// ( ( PCK_FREQ >= 5000000 ) & ( PCK_FREQ < 5400000 ) )
// ) * 100309
// ) +
// ( ( PCK_FREQ >= 22500000 ) & ( PCK_FREQ < 25100000 ) * 100353 ) +
// ( ( PCK_FREQ >= 25100000 ) & ( PCK_FREQ < 27500000 ) * 100286 ) +
// ( ( PCK_FREQ >= 27500000 ) & ( PCK_FREQ < 29700000 ) * 100316 ) +
// ( ( PCK_FREQ >= 29700000 ) * 100336 )
// ) ;
//------------------------------------------------------------------
DEF_PLL_REF_DIV
value = ( ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) ) * DEF_DIGITIZER_MASTER
) * DEF_PLL_ON ;
//
//value = ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) ) *
// ( ( ! ( SYC_CAM_GEN ) ) | ( SYC_CAM_GEN * ( PCK_CAM_REC | ( PCK_CAM_GEN * PCK_CAM_R&G ) ) ) ) ) * DEF_PLL_ON ;
//
// ------------------------------------------------------------------
DEF_LOOP_FREQ
value = ( DEF_SYSCLK_FREQ / ( DEF_PLL_REF_DIV + SYC_CAM_GEN ) ) ;
//
DEF_PLL_INTERNAL_LOOP_FLTR
value = (
( PCK_CAM_GEN * ( ! ( PCK_CAM_R&G ) ) ) | DEF_DIGITIZER_MASTER
) * DEF_PLL_ON ;
//
//value = ( ( ( ( PCK_CAM_GEN * ( ! ( PCK_CAM_R&G ) ) ) | ( ! ( PCK_USE_OUT ) ) ) *
// SYC_CAM_GEN * ( ( PCK_FREQ / ( DEF_PLL_REF_DIV + 1 ) ) >= 1000000 ) ) |
// ( DEF_DIGITIZER_MASTER * ( ( DEF_SYSCLK_FREQ / ( DEF_PLL_REF_DIV + SYC_CAM_GEN ) ) >= 1000000 ) )
// ) * DEF_PLL_ON ;
//value = ( ( ( ( PCK_CAM_GEN * ( ! ( PCK_CAM_R&G ) ) ) | ( ! ( PCK_USE_OUT ) ) ) *
// SYC_CAM_GEN * ( ( PCK_FREQ / ( DEF_PLL_REF_DIV + 1 ) ) >= 1000000 ) ) |
// ( ( PCK_CAM_REC | PCK_CAM_R&G | ( ! ( SYC_CAM_GEN ) ) ) *
// ( ( DEF_SYSCLK_FREQ / ( DEF_PLL_REF_DIV + SYC_CAM_GEN ) ) >= 1000000 ) ) ) * DEF_PLL_ON ;
// ------------------------------------------------------------------
DEF_PCK_NO_EXCHANGE
value = ( ( ! ( PCK_CAM_GEN ) ) & ( ! ( PCK_CAM_REC ) ) & ( ! ( PCK_CAM_R&G ) ) ) * DEF_PSG_ON ;
// ------------------------------------------------------------------
DEF_DEC_60HZ
value = ( VDT_STD_NTSC | ( DEF_VID_TIM_STD & DEF_NTSC ) | VDC_SVID ) * ( ( PCK_FREQ & 0xffff00 ) == 12272384 ) * DEF_DEC_PATH ;
//value = ( VDT_STD_NTSC | DEF_60HZ_HV_TOTAL_STD | VDC_SVID ) * ( ( PCK_FREQ & 0xffff00 ) == 12272384 ) * DEF_DEC_PATH ;
// ------------------------------------------------------------------
DEF_DEC_50HZ
value = ( VDT_STD_PAL | ( DEF_VID_TIM_STD & DEF_PAL ) | VDC_SVID ) * ( ( PCK_FREQ & 0xffff00 ) == 14749952 ) * DEF_DEC_PATH ;
//value = ( VDT_STD_PAL | DEF_50HZ_HV_TOTAL_STD | VDC_SVID ) * ( ( PCK_FREQ & 0xffff00 ) == 14749952 ) * DEF_DEC_PATH ;
// ------------------------------------------------------------------
DEF_MONO_CAM
value = ( VDC_MONO | ( GRB_RGB_PATH_FORCED & VDC_MONO ) ) ;
//
// ------------------------------------------------------------------
DEF_COLOR_CAM
value = ( VDC_C_COLOR | VDC_SVID | VDC_YUVVID | VDC_RGB_COL ) ;
// ------------------------------------------------------------------
DEF_RGB_SYNC_ANA_ON_R
value = ( ( ( VDC_RGB_COL & SYC_COMP ) | DEF_MONO_VIA_RGB ) & ( SYC_IN_CH == 0 ) ) * DEF_PSG_ON ;
//********************************************************
// SYNC on VIDEO
//
//enable = ENABLE[( ! ( ( ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) & SYC_SEP ) | DEF_DIGITIZER_MASTER | SYC_DIG | VDC_SVID ) )] ;
//********************************************************
// ------------------------------------------------------------------
DEF_RGB_SYNC_ANA_ON_G
value = ( ( ( VDC_RGB_COL & SYC_COMP ) | DEF_MONO_VIA_RGB ) & ( SYC_IN_CH == 1 ) ) * DEF_PSG_ON ;
//********************************************************
// SYNC on VIDEO
//
//value = ( ( ( VDC_RGB_COL & SYC_COMP ) | ( DEF_MONO_VIA_RGB & SYC_SEP ) ) & ( SYC_IN_CH == 1 ) ) * DEF_PSG_ON ;
//********************************************************
// ------------------------------------------------------------------
DEF_RGB_SYNC_ANA_ON_B
value = ( ( ( VDC_RGB_COL & SYC_COMP ) | DEF_MONO_VIA_RGB ) & ( SYC_IN_CH == 2 ) ) * DEF_PSG_ON ;
//********************************************************
// SYNC on VIDEO
//
//value = ( ( ( VDC_RGB_COL & SYC_COMP ) | ( DEF_MONO_VIA_RGB & SYC_SEP ) ) & ( SYC_IN_CH == 2 ) ) * DEF_PSG_ON ;
//********************************************************
// ------------------------------------------------------------------
DEF_RGB_SYNC_ANA_SEP
value = ( ( VDC_RGB_COL & SYC_SEP ) | ( DEF_MONO_VIA_RGB & ( SYC_IN_CH == 3 ) ) ) * DEF_PSG_ON ;
//
//********************************************************
// SYNC on VIDEO
//
//value = ( ( VDC_RGB_COL & SYC_SEP ) | ( DEF_MONO_VIA_RGB & SYC_SEP & ( SYC_IN_CH == 3 ) ) ) * DEF_PSG_ON ;
//********************************************************
// ------------------------------------------------------------------
DEF_GRAB_BY_VIA_RR
value = ( DEF_CORONA & DEF_DEC_PATH & ( VDT_STD_170 | VDT_STD_CCIR | VDC_SVID | VDC_C_COLOR ) & VDT_INTERL & VDC_ANA ) ;
//
//value = ( ( OPTION_LC | OPTION | OPTION_DIG ) & DEF_DEC_PATH & ( VDT_STD_170 | VDT_STD_CCIR | VDC_SVID | VDC_C_COLOR ) & VDT_INTERL & VDC_ANA ) ;
//value = ( ( OPTION | OPTION_DIG ) & DEF_DEC_PATH & ( VDT_STD_170 | VDT_STD_CCIR | VDT_STD_NTSC | VDT_STD_PAL ) & VDT_INTERL & VDC_ANA ) ;
// ------------------------------------------------------------------
DEF_CONT_SYNC_GRAB
value = ( GRB_MD_CONT | GRB_ACT_NXT_FRM ) * DEF_PSG_ON ;
//
// ------------------------------------------------------------------
DEF_RST_ASYNC_GRAB
value = ( GRB_ACT_IMMEDIATE | GRB_ACT_IMM_SKP_NFR ) * DEF_PSG_ON ;
//
// ------------------------------------------------------------------
DEF_TIMER1_ENABLE
value = ( EXP_MD_PERD | EXP_MD_W_TRG ) * DEF_PSG_ON ;
//
// ------------------------------------------------------------------
DEF_TIMER2_ENABLE
value = ( EXP_MD_PERD_2 | EXP_MD_W_TRG_2 ) * DEF_PSG_ON ;
//
// ------------------------------------------------------------------
//DEF_TIMER_HSCLK
//value = (
// ( ( VDT_HSYNC_FREQ * 478 ) / 15734 ) >= EXP_OUT_T1 ) |
// ( ( VDT_HSYNC_FREQ * 478 ) / 15734 ) >= EXP_OUT_T0 )
// ) ;
// ------------------------------------------------------------------
// PSG Internal PIPE of 3(Hsync_CLK & TIMER_CLK) 4-5(PixClk) 5-6(SysClk) for DELAY Timer1
DEF_EXP_OUT_T0
value = (
(
(
( EXP_OUT_T0 + ( EXP_SYN_CLK | EXP_CLOCK_HSYNC ) ) -
( ( 3 * EXP_CLOCK_HSYNC ) +
( ( 4 + EXP_MD_EXT + ( EXP_TRG_USER_BIT_TIMER1 * DEF_METEOR_II_MC )
) * EXP_SYN_CLK
) +
( ( 5 + EXP_MD_EXT + ( EXP_TRG_USER_BIT_TIMER1 * DEF_METEOR_II_MC )
- EXP_TRG_SIGNAL_TIMER2
) * EXP_ASY_CLK
)
) - ( 2 * EXP_CLOCK_TIMER2 )
) * EXP_MD_W_TRG * ( ! EXP_MD_SW )
) +
(
(
EXP_OUT_T0 - ( 2 + EXP_ASY_CLK )
) * EXP_MD_PERD
) +
( EXP_OUT_T0 * EXP_MD_SW )
) * ( EXP_OUT_T0 > 0 ) * DEF_PSG_ON ;
//
//value = (
// (
// (
// ( EXP_OUT_T0 + ( EXP_SYN_CLK | EXP_CLOCK_HSYNC ) ) -
// ( ( 3 * EXP_CLOCK_HSYNC ) +
// ( ( 4 + EXP_MD_EXT + ( EXP_TRG_USER_BIT_TIMER1 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// ) * EXP_SYN_CLK
// ) +
// ( ( 5 + EXP_MD_EXT + ( EXP_TRG_USER_BIT_TIMER1 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// - EXP_TRG_SIGNAL_TIMER2
// ) * EXP_ASY_CLK
// )
// ) - ( 2 * EXP_CLOCK_TIMER2 )
// ) * EXP_MD_W_TRG * ( ! EXP_MD_SW )
// ) +
// (
// (
// EXP_OUT_T0 - ( 2 + EXP_ASY_CLK )
// ) * EXP_MD_PERD
// ) +
// ( EXP_OUT_T0 * EXP_MD_SW )
// ) * ( EXP_OUT_T0 > 0 ) * DEF_PSG_ON ;
// ------------------------------------------------------------------
// Pix_Clk & Hsync_Clk : 1 Cnt less than the value input in Intellicam to the Scope
// du to internal MIL Structure.
DEF_EXP_OUT_T1
value = (
EXP_OUT_T1 + ( EXP_SYN_CLK | EXP_CLOCK_HSYNC | EXP_CLOCK_TIMER2 )
) * ( EXP_OUT_T1 > 0 ) * DEF_PSG_ON ;
//
//value = (
// EXP_OUT_T1 + ( EXP_SYN_CLK | EXP_CLOCK_HSYNC | EXP_CLOCK_TIMER2 )
// ) * ( EXP_OUT_T1 > 0 ) * DEF_PSG_ON ;
//value = ( EXP_OUT_T1 + ( EXP_SYN_CLK | EXP_CLOCK_HSYNC | EXP_CLOCK_TIMER2 ) ) * ( EXP_OUT_T1 > 0 ) * DEF_PSG_ON ;
// ------------------------------------------------------------------
// PSG Internal PIPE of 3(Hsync) 4-5(PixClk) 5-6(SysClk) for DELAY Timer1
DEF_EXP_OUT_T0_2
value = (
(
(
( EXP_OUT_T0_2 + ( EXP_SYN_CLK_2 | EXP_CLOCK_2_HSYNC ) ) -
( ( 3 * EXP_CLOCK_2_HSYNC ) +
( ( 4 + EXP_MD_EXT_2 + ( EXP_TRG_USER_BIT_TIMER2 * DEF_METEOR_II_MC )
) * EXP_SYN_CLK_2
) +
( ( 5 + EXP_MD_EXT_2 + ( EXP_TRG_USER_BIT_TIMER2 * DEF_METEOR_II_MC )
- EXP_TRG_SIGNAL_2_TIMER1
) * EXP_ASY_CLK_2
)
) - ( 4 * EXP_CLOCK_2_TIMER1 )
) * EXP_MD_W_TRG_2 * ( ! EXP_MD_SW_2 )
) +
(
( EXP_OUT_T0_2 - ( 2 + EXP_ASY_CLK_2 ) - ( 2 * EXP_CLOCK_2_TIMER1 ) ) * EXP_MD_PERD_2
) +
( EXP_OUT_T0_2 * EXP_MD_SW_2 )
) * ( EXP_OUT_T0_2 > 0 ) * DEF_PSG_ON ;
//
//value = (
// (
// (
// ( EXP_OUT_T0_2 + ( EXP_SYN_CLK_2 | EXP_CLOCK_2_HSYNC ) ) -
// ( ( 3 * EXP_CLOCK_2_HSYNC ) +
// ( ( 4 + EXP_MD_EXT_2 + ( EXP_TRG_USER_BIT_TIMER2 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// ) * EXP_SYN_CLK_2
// ) +
// ( ( 5 + EXP_MD_EXT_2 + ( EXP_TRG_USER_BIT_TIMER2 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// - EXP_TRG_SIGNAL_2_TIMER1
// ) * EXP_ASY_CLK_2
// )
// ) - ( 4 * EXP_CLOCK_2_TIMER1 )
// ) * EXP_MD_W_TRG_2 * ( ! EXP_MD_SW_2 )
// ) +
// (
// ( EXP_OUT_T0_2 - ( 2 + EXP_ASY_CLK_2 ) - ( 2 * EXP_CLOCK_2_TIMER1 ) ) * EXP_MD_PERD_2
// ) +
// ( EXP_OUT_T0_2 * EXP_MD_SW_2 )
// ) * ( EXP_OUT_T0_2 > 0 ) * DEF_PSG_ON ;
// ------------------------------------------------------------------
// Pix_Clk & Hsync_Clk : 1 Cnt less than the value input in Intellicam to the Scope
// du to internal structure of PSG.
DEF_EXP_OUT_T1_2
value = ( EXP_OUT_T1_2 + ( EXP_SYN_CLK_2 | EXP_CLOCK_2_HSYNC ) - EXP_CLOCK_2_TIMER1
) * ( EXP_OUT_T1_2 > 0 ) * DEF_PSG_ON ;
//
// ------------------------------------------------------------------
// PSG Internal PIPE of 4 for DELAY Timer2
//DEF_EXP_OUT_T0_2
//value = EXP_OUT_T0_2 ;
//value = ( EXP_OUT_T0_2 - ( 4 * ( EXP_OUT_T0_2 > 0 ) ) ) * DEF_PSG_ON ;
//
// Indicates if the tap configuration is valid
DEF_TAP_VALID
value = ( ( ( CT_TAPS == 0 ) & ( TAP_CONFIG == 1 ) & ( GVDC_VID_WIDTH <= 32 ) & ( CT_CAMERA <= 3 ) ) |
( ( CT_TAPS == 1 ) & ( TAP_CONFIG == 129 ) & ( GVDC_VID_WIDTH <= 16 ) & ( CT_CAMERA < 1 ) )
) ;
//
//value = ( ( CT_TAPS == 0 ) & ( TAP_CONFIG == 1 ) & ( GVDC_VID_WIDTH <= 32 ) &
//( CT_CAMERA <= 3 ) ) |
//( ( CT_TAPS == 1 ) & ( TAP_CONFIG == 129 ) & ( GVDC_VID_WIDTH <= 16 ) &
//( CT_CAMERA < 1 ) ) * DEF_PSG_ON ;
// ------------------------------------------------------------------
DEF_CLAMP_WIDTH
value = ( ( ( ( 19 / 10000000 ) * PCK_FREQ ) + 0.5 + ( PCK_FREQ < 263200 ) ) * DEF_PSG_ON ) ;
// ------------------------------------------------------------------
DEF_CLAMP_BORDER
value = (
(
( ( ( VDT_HBPORCH - DEF_CLAMP_WIDTH ) / 2 ) * ( VDT_HBPORCH >= DEF_CLAMP_WIDTH ) * VDT_CLP_BPO ) +
( ( ( VDT_HFPORCH - DEF_CLAMP_WIDTH ) / 2 ) * ( VDT_HFPORCH >= DEF_CLAMP_WIDTH ) * VDT_CLP_FPO )
)
* DEF_PSG_ON
) ;
//
//value = ( ( ( VDT_HBPORCH - DEF_CLAMP_WIDTH ) / 2 ) * ( VDT_HBPORCH >= DEF_CLAMP_WIDTH ) * DEF_PSG_ON ) ;
// ------------------------------------------------------------------
DEF_HBPORCH_MIN
value = (
(
( ( VDT_HBPORCH <= ( DEF_CLAMP_WIDTH + 2 ) ) * VDT_CLP_BPO ) +
( ( VDT_HFPORCH <= DEF_CLAMP_WIDTH ) * VDT_CLP_FPO )
) * VDC_ANA * DEF_PSG_ON
) ;
//
//value = ( ( VDT_HBPORCH <= ( DEF_CLAMP_WIDTH + 2 ) ) * VDT_CLP_BPO * VDC_ANA * DEF_PSG_ON ) ;
// ------------------------------------------------------------------
DEF_0,15_HBPORCH
value = (
(
( 0.15 * VDT_HBPORCH * VDT_CLP_BPO ) +
( 0.15 * VDT_HFPORCH * VDT_CLP_FPO )
) * DEF_PSG_ON
) ;
//
//value = 0.15 * VDT_HBPORCH * DEF_PSG_ON ;
// ------------------------------------------------------------------
DEF_ECSNGT_OVR
value = (
(
(
(
DEF_HTOTAL_IN - ( VDT_HSYNC / 2 ) -
( 3 * ( PCK_FREQ / ( 12500000 / ( 1 << DEF_SYSCLK_SEL ) ) ) )
) / ( PCK_FREQ / ( 12500000 / ( 1 << DEF_SYSCLK_SEL ) ) )
) * ( DEF_BT254_PATH * SYC_ANA )
) > 0xFF
) ;
// ------------------------------------------------------------------
//DEF_SYSCLK156MZ_MULT 1 => 4PCLKs en moins du aux aproximations car DTCVSR reste stable pendant DTCVSR
// 2 => 6PCLKs en moins en PCLK varie.
// 4 => 4PCLKs en moins
// 8 => 2PCLKs en moins
//
// MIN = VS Sampling > HECLMP ERROR IF VS Sampling <= HECLMP
DEF_VS_SAMPLING_MIN
value = (
(
(
( ( ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 2 ) * ( ( VDT_HSYNC + DEF_0,15_HBPORCH - 2 ) >= 0 ) ) * SYC_ANA ) +
( SYC_DIG * (
( ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 4 )
* ( ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 4 ) >= 0 ) * ( ! DEF_DIGITIZER_MASTER ) ) +
( DEF_DIGITIZER_MASTER * ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 4 ) )
)
)
) +
( ( 3 * PCK_FREQ ) / 1562500 ) -
( ( ( ( DEF_SYSCLK156MZ_MULT == 1 ) | ( DEF_SYSCLK156MZ_MULT == 4 ) ) * 4 ) +
( ( DEF_SYSCLK156MZ_MULT == 2 ) * 6 ) +
( ( DEF_SYSCLK156MZ_MULT == 8 ) * 2 )
)
) <=
(
(
(
( VDT_HSYNC + DEF_CLAMP_BORDER + DEF_CLAMP_WIDTH - ( DEF_RST_ASYNC_GRAB * SYC_DIG ) ) *
( DEF_RST_ASYNC_GRAB | ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) ) )
)
- ( DEF_CONT_SYNC_GRAB * ( 3 + SYC_DIG ) * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) )
) +
(
( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC < ( 2 + SYC_DIG ) ) ) * ( DEF_CLAMP_WIDTH - 1 - ( SYC_DIG * ( VDT_HSYNC < 2 ) ) )
) +
( VDT_HSYNC == 0 ) +
( ( DEF_CONT_SYNC_GRAB * 3 ) + SYC_DIG ) -
( DEF_DIGITIZER_MASTER * 5 )
)
) * SYC_ANA * VDT_CLP_BPO * DEF_PSG_ON ;
//
// ------------------------------------------------------------------
// MIN = HECLMP >= HSPVAL
DEF_HSPVAL_MIN
value = (
(
(
(
( VDT_HSYNC + DEF_CLAMP_BORDER + DEF_CLAMP_WIDTH - ( DEF_RST_ASYNC_GRAB * SYC_DIG ) ) *
( DEF_RST_ASYNC_GRAB | ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) ) )
) +
(
( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC < ( 2 + SYC_DIG ) ) ) *
( DEF_CLAMP_WIDTH + DEF_CLAMP_BORDER + VDT_HSYNC )
) -
( DEF_DIGITIZER_MASTER * 5 )
) >=
(
SYC_ANA ? ( DEF_PSG_HSPLLFB + VDT_HSYNC + VDT_HBPORCH + DEF_BTPIPE + DEF_LUTPIPE ) :
( ( SYC_DIG & ( ! DEF_DIGITIZER_MASTER ) ) ?
(
( ( VDT_HSYNC - 1 + VDT_HBPORCH - DEF_DIG_SYNCPIPE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE )
* ( ( ( VDT_HSYNC >= 0 ) & VDC_ANA ) | ( ( VDT_HSYNC + VDT_HBPORCH ) >= ( DEF_DIG_SYNCPIPE * VDC_DIG ) ) )
) +
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HTOTAL - DEF_DIG_SYNCPIPE ) * ( ( VDT_HSYNC + VDT_HBPORCH ) < ( DEF_DIG_SYNCPIPE * VDC_DIG ) )
* DEF_CONT_SYNC_GRAB
) +
( 2 * DEF_RST_ASYNC_GRAB * ( ( VDT_HSYNC + VDT_HBPORCH ) < ( DEF_DIG_SYNCPIPE * VDC_DIG ) ) )
) :
( SYC_DIG & DEF_DIGITIZER_MASTER ?
( VDT_HSYNC - 1 + VDT_HBPORCH + ( DEF_DIG_VIDPIPE * VDC_DIG ) + DEF_LUTPIPE )
) )
)
) * VDT_CLP_BPO * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH
) ;
//
// ------------------------------------------------------------------
DEF_HEPVAL_MAX
// PSG_HEPVAL >= PSG_HSCLMP + 10 (Delay Pix Valid) => ERROR
value = (
(
( SYC_ANA ? (
(
( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) *
( ( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) <= ( VDT_HTOTAL - 1 ) )
) +
(
( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - VDT_HTOTAL )
* DEF_CONT_SYNC_GRAB *
( ( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) > ( VDT_HTOTAL - 1 ) )
) +
( ( VDT_HTOTAL - 1 ) * DEF_RST_ASYNC_GRAB *
( ( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) > ( VDT_HTOTAL - 1 ) )
)
) :
( ( SYC_DIG & ( ! DEF_DIGITIZER_MASTER ) ) ?
(
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) *
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) <= ( VDT_HTOTAL - 1 ) )
) +
( ( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) - VDT_HTOTAL )
* DEF_CONT_SYNC_GRAB *
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
) +
( ( VDT_HTOTAL - 1 ) * DEF_RST_ASYNC_GRAB *
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
)
) :
( SYC_DIG & DEF_DIGITIZER_MASTER ?
(
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) *
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) <= ( VDT_HTOTAL - 1 ) )
) +
( ( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) - VDT_HTOTAL )
* DEF_CONT_SYNC_GRAB *
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
) +
( ( VDT_HTOTAL - 1 ) * DEF_RST_ASYNC_GRAB *
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
)
)
) )
) >=
( DEF_HTOTAL_IN - DEF_CLAMP_BORDER - DEF_CLAMP_WIDTH + 9 )
) * VDT_CLP_FPO * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH
) ;
//
// ( VDT_HTOTAL - DEF_CLAMP_BORDER - DEF_CLAMP_WIDTH - 1 )
// ------------------------------------------------------------------
// Video Gain of 2 Volts Input Max. to A/D
// GAIN Video Swing
// 4 0 - 500 mV
// 2.8 501 - 714 mV
// 2 715 - 1000 mV
// 1.3 1000 - 1538 mV
// 1 1539 - 2000 mV
DEF_VIDEO_GAIN
value = ( ! VDL_USE_DEFVAL ) &
( ( 4 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 4000 :
( ( ! VDL_USE_DEFVAL ) &
( ( 2.8 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 2800 :
( ( ! VDL_USE_DEFVAL ) &
( ( 2 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 2000 :
( ( ! VDL_USE_DEFVAL ) &
( ( 1.3 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 1300 :
( ( ! VDL_USE_DEFVAL ) & DEF_METEOR_II_MC & ( ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) <= 2000 ) ? 1000 :
( VDL_USE_DEFVAL ? 2800 :
1300 ) ) ) ) ) * DEF_PSG_ON ;
//
//value = ( ! VDL_USE_DEFVAL ) &
// ( ( 4 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 4000 :
// ( ( ! VDL_USE_DEFVAL ) &
// ( ( 2.8 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 2800 :
// ( ( ! VDL_USE_DEFVAL ) &
// ( ( 2 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 2000 :
// ( ( ! VDL_USE_DEFVAL ) &
// ( ( 1.3 * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) <= 2000 ) ? 1300 :
// ( ( ! VDL_USE_DEFVAL ) & ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) &
// ( ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) <= 2000 ) ? 1000 :
// ( VDL_USE_DEFVAL ? 2800 :
// 1300 ) ) ) ) ) * DEF_PSG_ON ;
DEF_PCK_IDLY_SEL
value = ( ( PCK_IDELAY > 9 ) * ( ( PCK_IDELAY - 9 ) / 3 ) ) * DEF_PSG_ON ;
//DEF_GAIN
//value = ( ( ! VDL_USE_DEFVAL ) *
// (
// ( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
// / 2619
// )
// ) ;
// ------------------------------------------------------------------
DEF_NEW_MODE_ASYNC_WEN_PULSE
value = (
EXP_USE_OUT * GRB_MD_HW_TRG * GRB_ACT_IMMEDIATE * VDT_NINTRL *
( GRB_TRG_SIGNAL_TIMER1_WEN | GRB_TRG_SIGNAL_TIMER2_WEN )
) ;
// ------------------------------------------------------------------
DEF_NEW_MODE_ASYNC_ONE_TIMER
value = ( EXP_USE_OUT * ( GRB_TRG_SIGNAL_TIMER1 | GRB_TRG_SIGNAL_TIMER2 ) ) ;
// ------------------------------------------------------------------
//
//
// *********************************************
// *********************************************
// Section #3 : BOARD REGISTER DEFINITION
// *********************************************
// *********************************************
[PARAMETER]
//
// =============================================
INFO_XSIZE
Horizontal image size
eo_information
1
0 12 unsigned flag_overflow
value = VDT_HACTIVE * ( 1 + ( ( TAP_CONFIG == 3 ) | ( TAP_CONFIG == 17 ) ) ) ;
//value = VDT_HACTIVE ;
no_define_value
//
// =============================================
INFO_YSIZE
Vertical image size
eo_information
1
0 12 unsigned flag_overflow
value = VDT_VACTIVE * ( 1 + ( ( TAP_CONFIG == 129 ) | ( TAP_CONFIG == 1025 ) ) ) ;
//value = VDT_VACTIVE ;
no_define_value
//
// =============================================
INFO_MODE
Corona DCF software specification (INFO_MODE)
eo_information
9
//
// ---------------------------------------------
MaskInterlaced regular
eo_information
0 1 unsigned flag_overflow
value = (
VDT_INTERL ? 0 :
( VDT_NINTRL ? 1 :
0 )
) ;
define_value
0 : Camera Interlaced
1 : Camera non interlaced
//
// ---------------------------------------------
MaskVideo regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
//
// ---------------------------------------------
MaskColor regular
eo_information
0 1 unsigned flag_overflow
value = (
DEF_MONO_CAM ? 0 :
( DEF_COLOR_CAM ? 1 :
0 )
) ;
define_value
0 : Camera monochrome
1 : Camera color
//
// ---------------------------------------------
MaskRGB regular
eo_information
0 1 unsigned flag_overflow
value = (
DEF_DEC_PATH ? 0 :
( DEF_BT254_PATH ? 1 :
0 )
) ;
define_value
0 : Decoder path
1 : RGB path
//
// ---------------------------------------------
MaskYC regular
eo_information
0 1 unsigned flag_overflow
value = VDC_SVID ;
define_value
0 : Camera non YC
1 : Camera YC
//
// ---------------------------------------------
GrabPathOvrd regular
eo_information
0 1 unsigned flag_overflow
value = ( DEF_GRAB_BY_VIA_RR ? 0 :
1 ) ;
define_value
0 : Grab using RR when possible
1 : Grab using VIA Only
//
// ---------------------------------------------
HWinVIAForce regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
0 : MIL VIA Hor. Window
1 : DCF VIA Hor. Window
//
// ---------------------------------------------
C_MASK_3TAP_MODE regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
0 : Max 2 Cameras/2Taps
1 : Max 3 Cameras/2Taps
//
// ---------------------------------------------
VCRInputMode regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
//value = MEMBER_VCR_INPUT_MODE ;
define_value
0 : Fast Input Mode
1 : VCR Input Mode
//
// =============================================
INFO_TYPE
?
eo_information
1
0 8 unsigned flag_overflow
value = 2 ;
no_define_value
// 1 : Line scan
// 2 : Frame scan
// 3 : Area scan
// 4 : Others
//
// =============================================
INFO_DEPTH
?
eo_information
1
0 8 unsigned flag_overflow
value = ( VDC_WD8 ? 8 :
( VDC_VID_WIDTH_10 ? 10 :
( VDC_VID_WIDTH_12 ? 12 :
( VDC_VID_WIDTH_14 ? 14 :
( VDC_WD16 ? 16 :
( VDC_WD24 ? 24 :
( VDC_WD32 ? 32 :
( VDC_WD64 ? 64 :
8 ) ) ) ) ) ) )
) ;
no_define_value
//
// =============================================
INFO_BAND
?
eo_information
1
0 8 unsigned flag_overflow
value = (
DEF_MONO_CAM ? 1 :
( DEF_COLOR_CAM ? 3 :
0 )
) ;
no_define_value
//1 : Mono
//3 : Color
//
// =============================================
INFO_INPUT
?
eo_information
1
0 8 unsigned flag_overflow
value = (
(
( VDC_MONO || VDC_C_COLOR || VDC_RGB_COL || VDC_SVID ) & ( ! VDC_DIG ) & VDC_IN_CH0 & ( TAP_CONFIG == 1 )
) ? 0 :
( (
(
( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 & ( CT_TAPS == 0 ) & ( CT_CAMERA == 0 )
) ||
( VDC_SVID & VDC_IN_CH2 ) ||
( ( CT_TAPS == 0 ) & ( CT_CAMERA == 1 ) )
) ? 1 :
( (
(
( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 )
) ||
( ( CT_TAPS == 0 ) & ( CT_CAMERA == 2 )
)
) ? 2 :
( (
( VDC_MONO || VDC_C_COLOR ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) &
DEF_DEC_PATH & VDC_IN_CH3
) ? 3 :
( VDC_DIG ? 5 :
0 ) ) ) )
) ;
//
//value = (
// ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_R ) ) || DEF_MONO_VIA_DEC ||
// VDC_C_COLOR || VDC_RGB_COL || VDC_SVID ) & ( ! VDC_DIG ) & VDC_IN_CH0 & ( TAP_CONFIG == 1 ) ) ? 0 :
// ( ( ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_G ) ) || DEF_MONO_VIA_DEC ||
// VDC_C_COLOR ) & VDC_IN_CH1 & ( CT_TAPS == 0 ) & ( CT_CAMERA == 0 ) ) ||
// ( VDC_SVID & VDC_IN_CH2 ) || ( ( CT_TAPS == 0 ) & ( CT_CAMERA == 1 ) ) ) ? 1 :
// ( ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_B ) ) || DEF_MONO_VIA_DEC || VDC_C_COLOR ) &
// VDC_IN_CH2 & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) ||
// ( ( CT_TAPS == 0 ) & ( CT_CAMERA == 2 ) ) ? 2 :
// ( ( ( VDC_MONO || VDC_C_COLOR ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) &
// DEF_DEC_PATH & VDC_IN_CH3 ) ? 3 :
// ( VDC_DIG ? 5 :
// 0 ) ) ) )
// ) ;
//
no_define_value
//0 : Analog Channel 0
//1 : Analog Channel 1
//2 : Analog Channel 2
//3 : Analog Channel 3
//4 : Digital TTL
//5 : Digital 422
//
// =============================================
INFO_PIXCLK
Pixel clock frequency
eo_information
1
0 32 unsigned flag_overflow
value = PCK_FREQ ;
no_define_value
//
// =============================================
INFO_PIPELINE
?
eo_information
1
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
//
// =============================================
INFO_MODULE_422
Digital video and sync module
eo_information
1
0 32 unsigned flag_overflow
value = ( VDC_DIG ? 0x60f00 :
0 ) ;
no_define_value
//
// =============================================
INFO_CHANNEL
Corona DCF software specification (INFO_CHANNEL)
eo_information
2
//
// ---------------------------------------------
VideoSignal regular
eo_information
0 4 unsigned flag_overflow
//
// Modify also INFO_INPUT
//
value = (
(
( VDC_MONO || VDC_C_COLOR || VDC_RGB_COL || VDC_SVID ) & VDC_IN_CH0 & ( TAP_CONFIG == 1 )
) ? 0 :
( (
(
( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH1 & ( CT_TAPS == 0 ) & ( CT_CAMERA == 0 )
) ||
( VDC_SVID & VDC_IN_CH2 ) ||
( ( CT_TAPS == 0 ) & ( CT_CAMERA == 1 ) )
) ? 1 :
( (
(
( VDC_MONO || VDC_C_COLOR ) & VDC_IN_CH2 & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 )
) ||
( ( CT_TAPS == 0 ) & ( CT_CAMERA == 2 )
)
) ? 2 :
( (
( VDC_MONO || VDC_C_COLOR ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) &
DEF_DEC_PATH & VDC_IN_CH3
) ? 3 :
0 ) ) )
) ;
//
//******************************************************************
// Sync on Video
//
//value = (
// ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_R ) ) || DEF_MONO_VIA_DEC ||
// VDC_C_COLOR || VDC_RGB_COL || VDC_SVID ) & VDC_IN_CH0 & ( TAP_CONFIG == 1 ) ) ? 0 :
// ( ( ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_G ) ) || DEF_MONO_VIA_DEC ||
// VDC_C_COLOR ) & VDC_IN_CH1 & ( CT_TAPS == 0 ) & ( CT_CAMERA == 0 ) ) ||
// ( VDC_SVID & VDC_IN_CH2 ) || ( ( CT_TAPS == 0 ) & ( CT_CAMERA == 1 ) ) ) ? 1 :
// ( ( ( ( DEF_MONO_VIA_RGB & ( ! DEF_RGB_SYNC_ANA_ON_B ) ) || DEF_MONO_VIA_DEC || VDC_C_COLOR ) &
// VDC_IN_CH2 & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) ||
// ( ( CT_TAPS == 0 ) & ( CT_CAMERA == 2 ) ) ? 2 :
// ( ( ( VDC_MONO || VDC_C_COLOR ) & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) &
// DEF_DEC_PATH & VDC_IN_CH3 ) ? 3 :
// 0 ) ) )
// ) ;
//******************************************************************
//
no_define_value
//
// ---------------------------------------------
VideoSync regular
eo_information
0 4 unsigned flag_overflow
value = (
( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR || VDC_SVID ) & SYC_COMP & VDC_IN_CH0 )
|| DEF_RGB_SYNC_ANA_ON_R ) ? 0 :
( ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH1 )
|| DEF_RGB_SYNC_ANA_ON_G ) ? 1 :
( ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR || VDC_SVID ) & SYC_COMP & VDC_IN_CH2 )
|| DEF_RGB_SYNC_ANA_ON_B ) ? 2 :
( ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH3 )
|| DEF_RGB_SYNC_ANA_SEP ) ? 3 :
0 ) ) )
) ;
//
//value = (
// ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR || VDC_SVID ) & SYC_COMP & VDC_IN_CH0 )
// || DEF_RGB_SYNC_ANA_ON_R ) ? 0 :
// ( ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH1 )
// || ( VDC_SVID & VDC_IN_CH2 ) || DEF_RGB_SYNC_ANA_ON_G ) ? 1 :
// ( ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH2 )
// || DEF_RGB_SYNC_ANA_ON_B ) ? 2 :
// ( ( ( ( ( VDC_MONO & ( CT_CAMERA == 0 ) & ( CT_TAPS == 0 ) ) || VDC_C_COLOR ) & SYC_COMP & VDC_IN_CH3 )
// || DEF_RGB_SYNC_ANA_SEP ) ? 3 :
// 0 ) ) )
// ) ;
no_define_value
// =============================================
INFO_XTAPSPERCH
Non adjacent pixel on x
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( TAP_CONFIG == 17 ) ;
//value = 1 + ( ( TAP_CONFIG == 17 ) | ( TAP_CONFIG == 51 ) |
//( TAP_CONFIG == 5137 ) ) ;
//value = 1 + ( ( TAP_CONFIG == 17 ) | ( TAP_CONFIG == 51 ) |
//( TAP_CONFIG == 5137 ) ) +
//( ( TAP_CONFIG == 85 ) * 3 ) ;
no_define_value
// =============================================
INFO_YTAPSPERCH
Non adjacent pixel on y
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( TAP_CONFIG == 1025 ) ;
//value = 1 + ( ( TAP_CONFIG == 1025 ) | ( TAP_CONFIG == 3075 ) |
//( TAP_CONFIG == 5137 ) ) ;
//value = 1 + ( ( TAP_CONFIG == 1025 ) | ( TAP_CONFIG == 3075 ) |
//( TAP_CONFIG == 5137 ) ) +
//( ( TAP_CONFIG == 9473 ) * 3 ) ;
no_define_value
// =============================================
INFO_XTAPSPERCHADJ
Adjacent pixel on x
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( TAP_CONFIG == 3 ) ;
//value = 1 + ( ( TAP_CONFIG == 3 ) | ( TAP_CONFIG == 51 ) |
//( TAP_CONFIG == 3075 ) ) ;
//value = 1 + ( ( TAP_CONFIG == 3 ) | ( TAP_CONFIG == 51 ) |
//( TAP_CONFIG == 3075 ) ) +
//( ( TAP_CONFIG == 15 ) * 3 ) ;
no_define_value
// =============================================
INFO_YTAPSPERCHADJ
Adjacent pixel on y
eo_information
1
1 32 unsigned flag_overflow
value = 1 + ( TAP_CONFIG == 129 ) ;
//value = 1 + ( TAP_CONFIG == 129 ) +
//( ( TAP_CONFIG == 897 ) * 3 ) ;
no_define_value
//
// *********************************************
// Bt254 Chip (begin)
// *********************************************
//
// =============================================
BT254_BTCOMMAND
Command register
eo_information
5
// ---------------------------------------------
syncdetlev regular
Sync detect level select
eo_information
0 1 unsigned flag_overflow
define_value
125 mv
50 mv
// ---------------------------------------------
reserved protected
Reserved
eo_information
0 1 unsigned flag_overflow
no_define_value
// ---------------------------------------------
coloutsel regular
Color output select
eo_information
0 2 unsigned flag_overflow
define_value
24-bit true color
15-bit true color
8-bit true color
8-bit pseudo color
// ---------------------------------------------
syndetsel regular
Sync detect select
eo_information
0 3 unsigned flag_overflow
define_value
RVID0
RVID1
GVID0
GVID1
BVID0
BVID1
SYNC0
SYNC1
// ---------------------------------------------
digsel regular
Digitize select
eo_information
0 1 unsigned flag_overflow
define_value
xVID0
xVID1
// -----------------------------------------------
// This 6 bits register specify the output current
// on the Bt254 IOUT0 output pin (IREDREF-)
// By default, the negative reference of the
// Bt254 ADs is fixed to 0V.
// -----------------------------------------------
// =============================================
BT254_BTIOOUT0
IOUT data register 0
eo_information
1
0 6 unsigned flag_overflow
no_define_value
// -----------------------------------------------
// Bt254 IOUT1 output pin (IGRNREF-)
// -----------------------------------------------
// =============================================
BT254_BTIOOUT1
IOUT data register 1
eo_information
1
0 6 unsigned flag_overflow
no_define_value
// -----------------------------------------------
// Bt254 IOUT2 output pin (IBLUREF-)
// -----------------------------------------------
// =============================================
BT254_BTIOOUT2
IOUT data register 2
eo_information
1
0 6 unsigned flag_overflow
no_define_value
// -----------------------------------------------
// Bt254 IOUT3 output pin (IREDLVL)
// By default, the voltage level used for DC restoration
// is 0V. So, during the clamping period, the BLANKING
// LEVEL of the video signal will be adjust to 0V.
// -----------------------------------------------
// =============================================
BT254_BTIOOUT3
IOUT data register 3
eo_information
1
0 6 unsigned flag_overflow
no_define_value
// -----------------------------------------------
// Bt254 IOUT4 output pin (IGRNLVL)
// -----------------------------------------------
// =============================================
BT254_BTIOOUT4
IOUT data register 4
eo_information
1
0 6 unsigned flag_overflow
no_define_value
// -----------------------------------------------
// Bt254 IOUT5 output pin (IBLULVL)
// -----------------------------------------------
// =============================================
BT254_BTIOOUT5
IOUT data register 5
eo_information
1
0 6 unsigned flag_overflow
no_define_value
//
// *********************************************
// Bt254 Chip (end)
// *********************************************
//
//
// *********************************************
// DAC8800 (begin)
// *********************************************
//
// =============================================
DAC8800_DAC_A
DAC #A (RREF-)
eo_information
1
0 8 unsigned flag_overflow
value = ( ( VDL_USE_DEFVAL * DEF_DAC8800_DEFAULT ) +
( ( ! VDL_USE_DEFVAL ) *
(
( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
/ 2619
) + 0.5
)
) * DEF_BT254_PATH ;
//
//value = DEF_DAC8800_DEFAULT * DEF_BT254_PATH ;
no_define_value
//
// =============================================
DAC8800_DAC_B
DAC #B (GREF-)
eo_information
1
0 8 unsigned flag_overflow
value = ( ( VDL_USE_DEFVAL * DEF_DAC8800_DEFAULT ) +
( ( ! VDL_USE_DEFVAL ) *
(
( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
/ 2619
) + 0.5
)
) * DEF_BT254_PATH ;
//
//value = DEF_DAC8800_DEFAULT * DEF_BT254_PATH ;
no_define_value
//
// =============================================
DAC8800_DAC_C
DAC #C (BREF-)
eo_information
1
0 8 unsigned flag_overflow
value = ( ( VDL_USE_DEFVAL * DEF_DAC8800_DEFAULT ) +
( ( ! VDL_USE_DEFVAL ) *
(
( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * ( VDL_AMPL - ( VDL_PEDEST * VDL_PED_AMP ) ) ) ) * 256 )
/ 2619
) + 0.5
)
) * DEF_BT254_PATH ;
//
//value = DEF_DAC8800_DEFAULT * DEF_BT254_PATH ;
no_define_value
//
//
// =============================================
DAC8800_DAC_E
DAC #E (RLEVEL)
eo_information
1
0 8 unsigned flag_overflow
value = ( ( VDL_USE_DEFVAL * DEF_DAC8800_DEFAULT ) +
(
( ( ! VDL_USE_DEFVAL ) *
( ( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2619 )
) + 0.5
)
) * DEF_BT254_PATH ;
//
//value = DEF_DAC8800_DEFAULT * DEF_BT254_PATH ;
no_define_value
//
// =============================================
DAC8800_DAC_F
DAC #F (GLEVEL)
eo_information
1
0 8 unsigned flag_overflow
value = ( ( VDL_USE_DEFVAL * DEF_DAC8800_DEFAULT ) +
(
( ( ! VDL_USE_DEFVAL ) *
( ( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2619 )
) + 0.5
)
) * DEF_BT254_PATH ;
//
//value = DEF_DAC8800_DEFAULT * DEF_BT254_PATH ;
no_define_value
//
// =============================================
DAC8800_DAC_G
DAC #G (BLEVEL)
eo_information
1
0 8 unsigned flag_overflow
value = ( ( VDL_USE_DEFVAL * DEF_DAC8800_DEFAULT ) +
(
( ( ! VDL_USE_DEFVAL ) *
( ( ( 2619 - ( ( DEF_VIDEO_GAIN / 1000 ) * VDL_AMPL ) ) * 256 ) / 2619 )
) + 0.5
)
) * DEF_BT254_PATH ;
//
//value = DEF_DAC8800_DEFAULT * DEF_BT254_PATH ;
no_define_value
//
//
// *********************************************
// DAC8800 (end)
// *********************************************
//
// *********************************************
// ICS-1522 Chip (begin)
// *********************************************
//
// ------------------------------------------------
//
// The PLL feadback divider is not used.
// This register is programmed at its default value
//
// =============================================
ICS1522_REG0
Feedback divider
eo_information
1
0x04F 11 unsigned flag_overflow
//
value = (
(
DEF_PLL_REG3 * DEF_DIGITIZER_MASTER *
(
(
PCK_FREQ * DEF_PLL_PDA * ( 2 - ( DEF_CORONA_II * ( PCK_FREQ > 30000000 ) ) )
* DEF_PLL_PATHDIV * DEF_PLL_FACTOR
)
/ 2500000000000
)
) +
( 0x4F * ( ! DEF_DIGITIZER_MASTER ) )
) * DEF_PLL_ON ;
//
//value = (
// (
// DEF_PLL_REG3 * DEF_DIGITIZER_MASTER *
// ( ( ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) * DEF_PLL_FACTOR ) / 2500000000000 )
// ) +
// ( 0x4F * ( ! DEF_DIGITIZER_MASTER ) )
// ) * DEF_PLL_ON ;
no_define_value
// =============================================
ICS1522_REG1
Feedback sync pulse
eo_information
1
0x003 11 unsigned flag_overflow
value = 0x003 * DEF_PLL_ON ;
no_define_value
// =============================================
ICS1522_REG2
Feedback sync pulse
eo_information
1
0x006 11 unsigned flag_overflow
value = 0x006 * DEF_PLL_ON ;
no_define_value
// =============================================
ICS1522_REG3
Reference register
eo_information
2
// ---------------------------------------------
refdiv regular
Reference divider
eo_information
0 10 unsigned flag_overflow
// Value = Feedback Divider * 25Mhz / PCLK * Output Scaler(PDA) * 2(Out Div.) * 4(Div4) or * (3 or 10)Load Counter
// Depend PCLK Frequency
// DEF_PLL_PDA = Value Selected 1,4,8 DEF_PLL_PATHDIV = 4 or 3 or 10 depend PCLK Frequency
value = DEF_PLL_REG3 * DEF_PLL_ON ;
//
//value = ( ( ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) )
// - 5.5 - ( 24 * ( PCK_FREQ >= 18500000 ) * ( PCK_FREQ < 19100000 ) )
// ) * DEF_DIGITIZER_MASTER
// ) * DEF_PLL_ON ;
//value = ( ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) ) * DEF_DIGITIZER_MASTER
// ) * DEF_PLL_ON ;
//value = ( ( DEF_PLL_REG0 * 25000000 ) / ( PCK_FREQ * DEF_PLL_PDA * 2 * DEF_PLL_PATHDIV ) ) *
// ( ( ! ( SYC_CAM_GEN ) ) | ( SYC_CAM_GEN * ( PCK_CAM_REC | ( PCK_CAM_GEN * PCK_CAM_R&G ) ) ) ) * DEF_PLL_ON ;
no_define_value
// ---------------------------------------------
refpol regular
Reference polarity
eo_information
0 1 unsigned flag_overflow
define_value
Positive egde
Negative edge
// ------------------------------------------------
//
// VCO FREQ. : 14M - 200M VCO VOLTAGE : 1.5 - 2.5V ( Stabilite )
// SELECT FREQ (VCO) V (Vco) % (Vco Max)
//
//
//
// 10M/V 14M a 22M 1.40V a 2.20V 6.09% a 9.57%
// 15M/V 22M a 30M 1.47V a 2.00V 9.57% a 16.30%
// 20M/V 30M a 37.5M 1.50V a 1.88V 16.30% a 18.26%
// 25M/V 37.5M a 66M 1.50V a 2.64V 18.26% a 28.69%
// 45M/V 66M a 113M 1.47V a 2.51v 28.69% a 55.65%
// 60M/V 113M a 156M 1.88V a 2.60V 55.65% a 69.56%
// 75M/V 156M a 202M 2.08V a 2.69V 69.56% a 86.96%
//
// N.B. Specs : VCO => 14Mhz - 230 Mhz & 3.5V Max.
// ------------------------------------------------
//
// =============================================
ICS1522_REG4
Multiple purposes
eo_information
7
// ---------------------------------------------
vco regular
VCO Gain
eo_information
4 3 unsigned flag_overflow
value = (
( ( DEF_VCO_FREQ >= 14000000 ) & ( DEF_VCO_FREQ < 22000000 ) ) ? 0 :
( ( ( DEF_VCO_FREQ >= 22000000 ) & ( DEF_VCO_FREQ < 30000000 ) ) ? 1 :
( ( ( DEF_VCO_FREQ >= 30000000 ) & ( DEF_VCO_FREQ < 37500000 ) ) ? 2 :
( ( ( DEF_VCO_FREQ >= 37500000 ) & ( DEF_VCO_FREQ < 66000000 ) ) ? 3 :
( ( ( DEF_VCO_FREQ >= 66000000 ) & ( DEF_VCO_FREQ < 113000000 ) ) ? 4 :
( ( ( DEF_VCO_FREQ >= 113000000 ) & ( DEF_VCO_FREQ < 156000000 ) ) ? 5 :
( ( ( DEF_VCO_FREQ >= 156000000 ) & ( DEF_VCO_FREQ < 202000000 ) ) ? 6 :
( ( ( DEF_VCO_FREQ >= 202000000 ) & ( DEF_VCO_FREQ <= 240000000 ) ) ? 7 :
4 ) ) ) ) ) ) )
) * DEF_PLL_ON ;
//
//value = (
// ( ( DEF_VCO_FREQ >= 14000000 ) & ( DEF_VCO_FREQ < 22000000 ) ) ? 0 :
// ( ( ( DEF_VCO_FREQ >= 22000000 ) & ( DEF_VCO_FREQ < 30000000 ) ) ? 1 :
// ( ( ( DEF_VCO_FREQ >= 30000000 ) & ( DEF_VCO_FREQ < 37500000 ) ) ? 2 :
// ( ( ( DEF_VCO_FREQ >= 37500000 ) & ( DEF_VCO_FREQ < 66000000 ) ) ? 3 :
// ( ( ( DEF_VCO_FREQ >= 66000000 ) & ( DEF_VCO_FREQ < 113000000 ) ) ? 4 :
// ( ( ( DEF_VCO_FREQ >= 113000000 ) & ( DEF_VCO_FREQ < 156000000 ) ) ? 5 :
// ( ( ( DEF_VCO_FREQ >= 156000000 ) & ( DEF_VCO_FREQ < 202000000 ) ) ? 6 :
// ( ( ( DEF_VCO_FREQ >= 202000000 ) & ( DEF_VCO_FREQ <= 240000000 ) ) ? 7 :
// 4 ) ) ) ) ) ) )
// ) * DEF_PLL_ON ;
define_value
10 MHz/V
15 MHz/V
20 MHz/V
25 MHz/V
45 MHz/V
60 MHz/V
75 MHz/V
90 MHz/V
// ---------------------------------------------
pdf regular
Phase frequency detector
eo_information
3 3 unsigned flag_overflow
value = 3 * DEF_PLL_ON ;
no_define_value
// ---------------------------------------------
pden regular
Phase frequency detector enable
eo_information
1 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
define_value
PFD disable
PFD enable
// ---------------------------------------------
int_flt regular
Loop filter select
eo_information
1 1 unsigned flag_overflow
// Internal Loop Filter = Lock on Pixel clock > 1 Mhz range else External in locking on HS < 1 Mhz
//value = ( PCK_CAM_XCHG & SYC_H_IN ? 0 :
// ( ( PCK_CAM_GEN & ( ! ( PCK_CAM_R&G ) ) ) ? 1 :
// ( ( ( ! ( PCK_CAM_XCHG ) ) & SYC_CAM_GEN & VDC_ANA & DEF_PSG_ON ) ? 2 :
// ( ( PCK_CAM_R&G | PCK_CAM_REC | ( ! ( SYC_CAM_GEN ) ) ) ? 3 :
// 2 ) ) )
// ) ;
value = ( DEF_PLL_INTERNAL_LOOP_FLTR ? 1 : 0 ) * DEF_PLL_ON ;
//value = ( ( ( PCK_CAM_GEN | PCK_CAM_REC | ( ! ( SYC_CAM_GEN ) ) | ( ! ( PCK_USE_OUT ) ) ) & DEF_PLL_INTERNAL_LOOP_FLTR ) ? 1 : 0 ) * DEF_PLL_ON ;
define_value
External loop
Internal loop
// ---------------------------------------------
int_vco regular
VCO Select
eo_information
1 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
define_value
External VCO
Internal VCO
// ---------------------------------------------
clk_sel regular
Feedback divider clock input select
eo_information
0 1 unsigned flag_overflow
define_value
VCO
OUT1
// ---------------------------------------------
reserved regular
Must be set to one
eo_information
1 1 unsigned flag_overflow
value = DEF_PLL_ON ;
no_define_value
// =============================================
ICS1522_REG5
Multiple purposes
eo_information
9
// ---------------------------------------------
fbk_sel regular
Feedback select
eo_information
0 1 unsigned flag_overflow
value = DEF_DIGITIZER_MASTER ;
//value = ( ( ! ( SYC_CAM_GEN ) ) | ( SYC_CAM_GEN * ( PCK_CAM_REC | ( PCK_CAM_GEN * PCK_CAM_R&G ) ) ) ) ;
define_value
fback w/PSG
internal fb
// ---------------------------------------------
fbk_pol regular
External feedback polarity
eo_information
0 1 unsigned flag_overflow
define_value
Positive edge
Negative edge
// ---------------------------------------------
add regular
Addition of 1 VCO cycle
eo_information
0 1 unsigned flag_overflow
no_define_value
// ---------------------------------------------
swlw regular
Removal of 1 VCO cycle
eo_information
0 1 unsigned flag_overflow
no_define_value
// ---------------------------------------------
pda regular
Output post-scaler
eo_information
3 2 unsigned flag_overflow
//value = 3 * DEF_PLL_ON ;
// DEF_VCO_FREQ
// frequency of VCO in Hz
//
// VCO FREQ. : 50M - 200M OUT
// PCLK VCO FREQ. VCO% TOTAL POST
// ( % Max:230) DIV SCALER ( Internal ) ( External )
//
// Camera & Digitizer generate Syncs
//
// (25.00 M - 30.00M 150 M - 180 M 65.22% a 78.26% /6 1 /3 (Ld Counter) /2)
// REMOVED LOAD COUNTER = 3
// 6.25 M - 25.00M 50 M - 200 M 21.74% a 86.96% /8 1 /4 /2
// 1.60 M - 6.25M 51.2M - 200 M 22.26% a 86.96% /32 4 /4 /2
// 780.0KHz - 1.60M 49.9M - 102.4M 21.69% a 44.70% /64 8 /4 /2
// 87.5KHz - 780KHz 14 M - 124.8M 6.09% a 54.26% /160 8 /10 (Ld Counter) /2
//
//
value = ( ( ( PCK_FREQ > 6250000 ) & ( PCK_FREQ <= 40000000 ) ) ? 3 :
( ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ? 1 :
0 )
) * DEF_PLL_ON ;
//
//value = ( ( ( PCK_FREQ > 6250000 ) & ( PCK_FREQ <= 30000000 ) ) ? 3 :
// ( ( ( PCK_FREQ > 1600000 ) & ( PCK_FREQ <= 6250000 ) ) ? 1 :
// 0 )
// ) * DEF_PLL_ON ;
define_value
Divide by 8
Divide by 4
Divide by 2
Divide by 1
// ---------------------------------------------
pdb regular
Feedback post-scaler
eo_information
3 2 unsigned flag_overflow
value = 3 * DEF_PLL_ON ;
define_value
Divide by 8
Divide by 4
Divide by 2
Divide by 1
// ---------------------------------------------
ld_lg regular
Fine phase adjust lead/lag
eo_information
1 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
no_define_value
// ---------------------------------------------
f_en regular
Fine phase adjust enable
eo_information
0 1 unsigned flag_overflow
no_define_value
// ---------------------------------------------
reserved regular
Must be set to one
eo_information
1 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
no_define_value
// =============================================
ICS1522_REG6
Multiple purposes
eo_information
9
// ---------------------------------------------
l regular
Load Counter
eo_information
0 3 unsigned flag_overflow
value = (
( PCK_FREQ <= 780000 ) ? 7 :
0
) * DEF_PLL_ON ;
//value = ( ( PCK_FREQ > 25000000 ) ? 0 :
// ( ( PCK_FREQ <= 780000 ) ? 7 :
// 0 )
// ) * DEF_PLL_ON ;
define_value
3 1-pos, 0-neg
4 pos edge
4 neg edge
5 1-neg, 0-pos
6 pos edge
8 pos edge
8 neg edge
10 neg edge
//Si 7Mhz-11Mhz ou 25Mhz-30Mhz => DIV = 3 (Load Counter) ELSE AUTRE PATH => DIV = 4
// ---------------------------------------------
omux1 regular
OUT1 Select
eo_information
0 1 unsigned flag_overflow
value = DEF_PLL_ON *
( ( ( PCK_FREQ > 25000000 ) & DEF_DIGITIZER_MASTER ) || ( PCK_FREQ <= 780000 ) ? 0 :
1 ) ;
//value = DEF_PLL_ON *
// ( ( ( PCK_FREQ > 25000000 ) & ( ! ( SYC_CAM_GEN ) ) ) || ( PCK_FREQ <= 780000 ) ? 0 :
// 1 ) ;
//value = DEF_PLL_ON *
// ( ( PCK_FREQ > 25000000 ) || ( PCK_FREQ <= 780000 ) ? 0 :
// 1 ) ;
define_value
Load Counter Output
Output Divided by 4 at 0 Degrees
// ---------------------------------------------
omux2 regular
OUT2 Select
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
define_value
Load Counter Output
Output Divided by 4 at 90 Degrees
// ---------------------------------------------
omux3 regular
OUT3 Select
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
define_value
Load Counter Output
Output Divided by 4 at 180 Degrees
// ---------------------------------------------
omux4 regular
OUT4 Select
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
define_value
Load Counter Output
Output Divided by 4 at 270 Degrees
// ---------------------------------------------
dacrst regular
Output reset
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
CLK+ High CLK- Low
CLK+ CLK- Toggling
// ---------------------------------------------
auxen regular
Output Test Mode
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Normal Output Operation
Output Test Mode
// ---------------------------------------------
auxclk regular
Output Clock when in Test Mode
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Output CLK+ CLK- in Test Mode
CLK+ CLK- Will Track AUXCLK
// ---------------------------------------------
extref regular
XTAL/EXTREF Input Buffer
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_PLL_ON ;
define_value
Crystal Input Operation
External Reference Input Operation
//
// *********************************************
// ICS-1522 Chip (end)
// *********************************************
//
//
// *********************************************
// Rainbow Runner Chip (Begin)
// *********************************************
//
//
// =============================================
RR_CROPLEFT0
.
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_DEC_60HZ ? ( VDT_HBPORCH - 2 ) :
( DEF_DEC_50HZ ? ( VDT_HBPORCH - 4 ) :
( DEF_BT254_PATH ? ( ( DEF_PSG_HSPLLFB + 1 ) + VDT_HBPORCH + DEF_BTPIPE + DEF_LUTPIPE - 2 + DEF_HSYNC_TRAILS_VSYNC ) :
0 ) )
) ;
no_define_value
// =============================================
RR_CROPRIGHT0
.
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_DEC_60HZ ? ( ( VDT_HBPORCH - 2 ) + VDT_HACTIVE - 1 ) :
( DEF_DEC_50HZ ? ( ( VDT_HBPORCH - 4 ) + VDT_HACTIVE - 1 ) :
( DEF_BT254_PATH ? ( ( DEF_PSG_HSPLLFB + 1 ) + VDT_HBPORCH + DEF_BTPIPE + DEF_LUTPIPE - 2 + DEF_HSYNC_TRAILS_VSYNC + VDT_HACTIVE - 1 ) :
0 ) )
) ;
no_define_value
// =============================================
RR_CROPTOP0
.
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_DEC_60HZ ? ( ( ( VDT_VSYNC - 1 ) + VDT_VBPORCH + 3 ) & 0xfffe ) :
( DEF_DEC_50HZ ? ( ( ( VDT_VSYNC - 1 ) + VDT_VBPORCH + 1 ) & 0xfffe ) :
( ( DEF_BT254_PATH & ( VDT_VBPORCH % 2 ) ) ? ( 13 + VDT_VBPORCH ) :
( ( DEF_BT254_PATH & ( ! ( VDT_VBPORCH % 2 ) ) ) ? ( 14 + VDT_VBPORCH ) :
0 ) ) )
) ;
no_define_value
// =============================================
RR_CROPBOTTOM0
.
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_DEC_60HZ ? ( ( ( VDT_VSYNC - 1 ) + VDT_VBPORCH + 3 ) + ( VDT_VACTIVE - 1 ) ) :
( DEF_DEC_50HZ ? ( ( ( VDT_VSYNC - 1 ) + VDT_VBPORCH + 1 ) + ( VDT_VACTIVE - 1 ) ) :
( ( DEF_BT254_PATH & ( VDT_VBPORCH % 2 ) ) ? ( 13 + VDT_VBPORCH + ( VDT_VACTIVE - 1 ) ) :
( ( DEF_BT254_PATH & ( ! ( VDT_VBPORCH % 2 ) ) ) ? ( 14 + VDT_VBPORCH + ( VDT_VACTIVE - 1 ) ) :
0 ) ) )
) ;
no_define_value
// ------------------------------------------------
//
//
// *********************************************
// Rainbow Runner Chip (End)
// *********************************************
//
//
// *********************************************
// Decoder KS0127 Chip (Begin)
// *********************************************
//
//
// =============================================
KS0127_HAVB
HAV start control
eo_information
1
0 11 signed no_flag_overflow
value = (
(
( DEF_DEC_60HZ *
( ( DEF_KS_CHIP_DELAY + ( DEF_HOR_BLANK_60HZ - VDT_HFPORCH ) )
- DEF_KS_HAVB_60HZ_DEFAULT + 3
)
) +
( DEF_DEC_50HZ *
( ( DEF_KS_CHIP_DELAY + ( DEF_HOR_BLANK_50HZ - VDT_HFPORCH ) )
- DEF_KS_HAVB_50HZ_DEFAULT + 3
)
)
) * 2 * DEF_DEC_PATH
) & 0x000000ff ;
no_define_value
//
// =============================================
//
KS0127_HAVE
HAV end control
eo_information
1
0 11 signed no_flag_overflow
value = (
(
( DEF_DEC_60HZ *
( ( DEF_KS_CHIP_DELAY - VDT_HFPORCH )
- DEF_KS_HAVE_60HZ_DEFAULT + 3
)
) +
( DEF_DEC_50HZ *
( ( DEF_KS_CHIP_DELAY - VDT_HFPORCH )
- DEF_KS_HAVE_50HZ_DEFAULT + 3
)
)
) * 2 * DEF_DEC_PATH
) & 0x000000ff ;
no_define_value
//
// =============================================
//
KS0127_HS1B
HS1 start control
eo_information
1
0 9 signed no_flag_overflow
value = (
(
( DEF_DEC_60HZ *
(
(
(
DEF_KS_CHIP_DELAY
- DEF_KS_HS1B_60HZ_DEFAULT + 3
) * 2
) >> 1
)
) +
( DEF_DEC_50HZ *
(
(
(
DEF_KS_CHIP_DELAY
- DEF_KS_HS1B_50HZ_DEFAULT + 3
) * 2
) >> 1
)
)
) * DEF_DEC_PATH
) & 0x000000ff - ( DEF_50HZ_HV_TOTAL_STD * ( VDC_C_COLOR | VDC_SVID | DEF_MONO_VIA_DEC ) ) ;
// Minus 1 for ENCODER Alignment Chroma in PAL Mode!
//
//value = (
// (
// ( DEF_DEC_60HZ *
// (
// (
// (
// DEF_KS_CHIP_DELAY
// - DEF_KS_HS1B_60HZ_DEFAULT + 3
// ) * 2
// ) >> 1
// )
// ) +
// ( DEF_DEC_50HZ *
// (
// (
// (
// DEF_KS_CHIP_DELAY
// - DEF_KS_HS1B_50HZ_DEFAULT + 3
// ) * 2
// ) >> 1
// )
// )
// ) * DEF_DEC_PATH
// ) & 0x000000ff - ( DEF_50HZ_HV_TOTAL_STD * ( VDC_C_COLOR | VDC_SVID ) ) ;
// Minus 1 for ENCODER Alignment Chroma in PAL Mode!
no_define_value
//
// =============================================
//
KS0127_HS1E
HS1 end control
eo_information
1
0 9 signed no_flag_overflow
value = (
(
( DEF_DEC_60HZ *
(
(
(
( DEF_KS_CHIP_DELAY + DEF_HSYNC_60HZ )
- DEF_KS_HS1E_60HZ_DEFAULT + 3
) * 2
) >> 1
)
) +
( DEF_DEC_50HZ *
(
(
(
( DEF_KS_CHIP_DELAY + DEF_HSYNC_50HZ )
- DEF_KS_HS1E_50HZ_DEFAULT + 3
) * 2
) >> 1
)
)
) * DEF_DEC_PATH
) & 0x000000ff ;
no_define_value
//
// =============================================
//
KS0127_HXTRA
Horizontal extra
eo_information
1
0 11 signed no_flag_overflow
value = (
(
(
(
( DEF_DEC_60HZ *
( ( DEF_KS_CHIP_DELAY - VDT_HFPORCH )
- DEF_KS_HAVE_60HZ_DEFAULT + 3
)
) +
( DEF_DEC_50HZ *
( ( DEF_KS_CHIP_DELAY - VDT_HFPORCH )
- DEF_KS_HAVE_50HZ_DEFAULT + 3
)
)
) * 2 * DEF_DEC_PATH
) & 0x00000700
) >> 6
) |
(
(
(
(
( DEF_DEC_60HZ *
( ( DEF_KS_CHIP_DELAY + ( DEF_HOR_BLANK_60HZ - VDT_HFPORCH ) )
- DEF_KS_HAVB_60HZ_DEFAULT + 3
)
) +
( DEF_DEC_50HZ *
( ( DEF_KS_CHIP_DELAY + ( DEF_HOR_BLANK_50HZ - VDT_HFPORCH ) )
- DEF_KS_HAVB_50HZ_DEFAULT + 3
)
)
) * 2 * DEF_DEC_PATH
) & 0x00000700
) >> 3
) ;
no_define_value
//
// =============================================
//
//
KS0127_CMDA
Control Register A
eo_information
7
// ---------------------------------------------
IFMT regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Input 50 HZ
Input 60 Hz
// ---------------------------------------------
MNFMT regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Without IFMT Bit
With IFMT Bit
// ---------------------------------------------
PIXEL regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Output Data Square Pixel
Output Data CCIR 601 rate
// ---------------------------------------------
XT24 regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Ext. CLK 26.8 Mhz
Ext. CLK 24.576 Mhz
// ---------------------------------------------
HFSEL regular
eo_information
0 2 unsigned flag_overflow
value = 0 ;
//value = ( MEMBER_VCR_INPUT_MODE * 2 ) ;
define_value
Force loop to Very Fast
Force loop to Fast
Force loop to VCR Time constant
Force loop to TV Time constant
// ---------------------------------------------
VSE regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Line 10/10.5
Line 9 /9.5
// ---------------------------------------------
POWDN regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Normal operation
Most Chip functions disable
//
// =============================================
//
//
KS0127_CMDD
Control Register D
eo_information
1
1 8 unsigned flag_overflow
// Register Bit 0 : 1 = Rising Edge | 0 = Falling Edge
value = ( ( ( DEF_METEOR_II | OPTION_LC ) & GRB_TRG_NEG ) ? 0 : 1 ) ;
//
//value = ( ( ( OPTION_M2 | OPTION_M2_JPEG | OPTION_LC ) & GRB_TRG_NEG ) ? 0 : 1 ) ;
//value = ( ( ( OPTION_M2 | OPTION_LC ) & GRB_TRG_NEG ) ? 0 : 1 ) ;
no_define_value
//
// =============================================
//
KS0127_CHROMA
Control Register A
eo_information
6
// ---------------------------------------------
CKILL regular
eo_information
0 2 unsigned flag_overflow
value = ( ( VDC_MONO & DEF_DEC_PATH ) ? 3 : 0 ) ;
define_value
Auto Detect Mode
reserved
Color Always ON
Data Forced to Code 128
// ---------------------------------------------
CORE regular
eo_information
0 2 unsigned flag_overflow
value = 0 ;
define_value
No Coring
Chroma Data 128+-1
Chroma Data 128+-3
Chroma Data 128+-7
// ---------------------------------------------
CBW regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Chroma Bandwidth = 850 kHz
Chroma Bandwidth = 550 kHz
// ---------------------------------------------
PALN regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Select NTSC-N
Select PAL-N
// ---------------------------------------------
PALM regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Select Tracking for NTSC-M
Select Tracking for PAL-M
// ---------------------------------------------
ACCFRZ regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Color Gain tracks the input
Color Gain freezes to sat. level
// =============================================
//
KS0127_POLCTL
Timing signal polarity control
eo_information
8
// ---------------------------------------------
hs1pl regular
HS1 Polarity
eo_information
0 1 unsigned flag_overflow
value = 0x01 * DEF_DEC_PATH ;
define_value
Active High
Active Low
// ---------------------------------------------
vavpl regular
VAV Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
hs2pl regular
HS2 Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
ehavpl regular
EHAV Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
havpl regular
HAV Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
oddpl regular
ODD Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
vspl regular
VS Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
evavpl regular
EVAV Polarity
eo_information
0 1 unsigned flag_overflow
define_value
Active High
Active Low
// ---------------------------------------------
//0 8 unsigned flag_overflow
//// POLCTL[0] = HS1PL = 1 (HS1 polarity is active low)
//// POLCTL[5] = ODDPL = 0 (ODD polarity is active high)
//// POLCTL[6] = VSPL = 0 (VS polarity is active high)
//value = 0x01 * DEF_DEC_PATH ;
//no_define_value
//
// =============================================
//
KS0127_LUMA
Luma control register
eo_information
7
// ---------------------------------------------
HYPK regular
eo_information
1 2 unsigned flag_overflow
value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 0 : 1
) * DEF_DEC_PATH ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 0 : 1
// ) * DEF_DEC_PATH ;
define_value
Less than nominal peaking
Nominal peaking
Increased peaking
Maximum peaking
// ---------------------------------------------
CTRAP regular
eo_information
1 1 unsigned flag_overflow
value = ( ( VDC_C_COLOR & DEF_50HZ_HV_TOTAL_STD ) ? 1 : 0
) * DEF_DEC_PATH ;
//value = ( ( VDC_C_COLOR & ( DEF_50HZ_H_TOTAL_ACTIVE_STD & DEF_50HZ_V_TOTAL_ACTIVE_STD ) ) ? 1 : 0
// ) * DEF_DEC_PATH ;
define_value
No Chroma Trap
Chroma Trap Enabled
// ---------------------------------------------
HYBWR regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Full Bandwidth
Reduced Bandwidth
// ---------------------------------------------
PED regular
eo_information
0 1 unsigned flag_overflow
value = ( DEF_60HZ_HV_TOTAL_STD * ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) ) * DEF_DEC_PATH ;
//value = ( DEF_60HZ_H_TOTAL_ACTIVE_STD * DEF_60HZ_V_TOTAL_ACTIVE_STD * ( VDC_MONO | VDC_C_COLOR | VDC_SVID ) ) * DEF_DEC_PATH ;
define_value
No Pedestal
Pedestal Enabled
// ---------------------------------------------
RGBH regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Luminance = 16-235
Luminance = 0-255
// ---------------------------------------------
UNIT regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Luma DC Gain = PED & RGBH
Luma DC Gain = 1
// ---------------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
no_define_value
//
// =============================================
//
KS0127_CON
Contrast control
eo_information
1
0 8 signed no_flag_overflow
value = (
( VDL_CONTR < 50 ) ? ( ( - 128 ) + ( VDL_CONTR * ( 128 / 50 ) ) ) :
( ( VDL_CONTR == 50 ) ? 0 :
( ( VDL_CONTR > 50 ) ? ( ( VDL_CONTR - 50 ) * ( 127 / 50 ) ) :
0 ) )
) ;
no_define_value
//
//value = (
// ( VDL_CONTR < 50 ) ? ( ( - 128 ) + ( VDL_CONTR * ( 128 / 50 ) ) ) :
// ( ( VDL_CONTR == 0 ) ? 50 :
// ( ( VDL_CONTR > 50 ) ? ( ( VDL_CONTR - 50 ) * ( 127 / 50 ) ) :
// 50 ) )
// ) ;
// =============================================
//
KS0127_BRT
Brightness control
eo_information
1
0 8 signed no_flag_overflow
value = (
( VDL_BRGHT < 50 ) ? ( ( - 128 ) + ( VDL_BRGHT * ( 128 / 50 ) ) ) :
( ( VDL_BRGHT == 50 ) ? 0 :
( ( VDL_BRGHT > 50 ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
0 ) )
) ;
no_define_value
//
//value = (
// ( VDL_BRGHT < 50 ) ? ( ( - 128 ) + ( VDL_BRGHT * ( 128 / 50 ) ) ) :
// ( ( VDL_BRGHT == 0 ) ? 50 :
// ( ( VDL_BRGHT > 50 ) ? ( ( VDL_BRGHT - 50 ) * ( 127 / 50 ) ) :
// 50 ) )
// ) ;
// =============================================
//
KS0127_SAT
Color saturation control
eo_information
1
0 8 signed no_flag_overflow
value = (
( VDL_SATUR < 50 ) ? ( ( - 128 ) + ( VDL_SATUR * ( 128 / 50 ) ) ) :
( ( VDL_SATUR == 50 ) ? 0 :
( ( VDL_SATUR > 50 ) ? ( ( VDL_SATUR - 50 ) * ( 127 / 50 ) ) :
0 ) )
) ;
no_define_value
//
//value = (
// ( VDL_SATUR < 50 ) ? ( ( - 128 ) + ( VDL_SATUR * ( 128 / 50 ) ) ) :
// ( ( VDL_SATUR == 0 ) ? 50 :
// ( ( VDL_SATUR > 50 ) ? ( ( VDL_SATUR - 50 ) * ( 127 / 50 ) ) :
// 50 ) )
// ) ;
// =============================================
//
KS0127_HUE
Hue control
eo_information
1
0 8 signed no_flag_overflow
value = (
( VDL_HUE < 50 ) ? ( ( - 128 ) + ( VDL_HUE * ( 128 / 50 ) ) ) :
( ( VDL_HUE == 50 ) ? 0 :
( ( VDL_HUE > 50 ) ? ( ( VDL_HUE - 50 ) * ( 127 / 50 ) ) :
0 ) )
) ;
no_define_value
// =============================================
//
//
//
//
// Ajout de registre(s) dans les Fichiers DCF
// =============================================
// KS0127
//
// Scaler uses FULL bandwidth, comb is disabled
//
KS0127_VERTIA
Vertical Processing Control A
eo_information
4
// ---------------------------------------------
VCTRL regular
Luminance Vertical Filter
eo_information
0 3 unsigned flag_overflow
value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 0 : 2
) * DEF_DEC_PATH ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 0 : 2
// ) * DEF_DEC_PATH ;
define_value
Scaler LPF path, Comb HPF
Scaler Full bandwidth, Comb Disable
Scaler Disable, Comb Full bandwidth
Scaler LPF path, Comb Disable
Scaler Disable, Comb uses HPF path
Reserved
Reserved
Reserved
// ---------------------------------------------
VRT2X regular
Vertical Scaler Filter Select
eo_information
0 1 unsigned flag_overflow
value = 0 * DEF_DEC_PATH ;
define_value
3-Tap Vertical Scaler Filter
5-Tap Vertical Scaler Filter
// ---------------------------------------------
YCMBCO regular
Luma Comb Filter Coefficients Selection
eo_information
0 3 unsigned flag_overflow
value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 2 : 3 ) * DEF_DEC_PATH ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 2 : 3 ) * DEF_DEC_PATH ;
define_value
[1/4 1/2 1/2]
[3/8 1/2 1/8]
[1/2 1/2 0]
[1 0 0]
[0 1 0]
[1/2 1/2 0]
[0 1/2 1/2]
[1/8 1/2 3/8]
// ---------------------------------------------
MNYCMB regular
Luma Comb Filter Coefficients Mode
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_DEC_PATH ;
define_value
Automatic Luma Comb Filter
Manual Luma Comb Filter
//
// Patch de Jean-Luc pour Vista Medical (SCALING)######################################
// ==============================================
KS0127_VERTIB
Vertical Processing Control B
eo_information
5
//---------------------------------------------
reserved protected
eo_information
0 1 unsigned no_flag_overflow
no_define_value
//---------------------------------------------
VSCLEN regular
eo_information
1 2 unsigned flag_overflow
value = 1 * DEF_DEC_PATH ;
define_value
Vertical scaling Enabled
Vertical scaling Disabled
V. scaling disabled 1-line delay
V. scaling disabled 2-line delay
//---------------------------------------------
HYDEC regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Luma decimation Enabled
Luma decimation Disabled
//---------------------------------------------
HYBWI regular
eo_information
0 1 unsigned flag_overflow
value = ( ( VDC_MONO | VDC_SVID ) ? 1 : 0 ) * DEF_DEC_PATH ;
define_value
Normal bandwidth
Bandwidth 1MHz Higher
//---------------------------------------------
HYLPF regular
eo_information
0 3 unsigned flag_overflow
value = 0 ;
define_value
Full bandwidth
4.5MHz bandwidth
3.5MHz bandwidth
2.5MHz bandwidth
1.5MHz bandwidth
reserved
reserved
reserved
//
// ==============================================
KS0127_VERTIC
Vertical Processing Control C
eo_information
6
//---------------------------------------------
EVAVOD regular
eo_information
0 1 unsigned no_flag_overflow
value = 1 * DEF_DEC_PATH ;
define_value
Disabled during ODD Field
Enabled during ODD Field
//---------------------------------------------
EVAVEV regular
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_DEC_PATH ;
define_value
Disabled during EVEN Field
Enabled during EVEN Field
//---------------------------------------------
VYBW regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Full Bandwidth
Reduced Bandwidth
//---------------------------------------------
ACMBEN regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Active comb disabled
Active comb enabled
//---------------------------------------------
CCMBCO regular
eo_information
0 3 unsigned flag_overflow
value = ( ( VDC_C_COLOR & DEF_60HZ_HV_TOTAL_STD ) ? 0 : 4 ) * DEF_DEC_PATH ;
//value = ( ( VDC_C_COLOR & ( DEF_60HZ_H_TOTAL_ACTIVE_STD & DEF_60HZ_V_TOTAL_ACTIVE_STD ) ) ? 0 : 4 ) * DEF_DEC_PATH ;
define_value
Coeff. set [ 1/2 1/2 0 ]
Coeff. set [ 1/4 1/2 1/4 ]
Coeff. set [ 0 1/2 1/2 0 0 ]
Coeff. set [ 0 1/4 1/2 1/4 0 ]
Coeff. set [ 1 0 0 ]
Coeff. set [ 0 1 0 ]
Coeff. set [ 0 0 1 ]
No Output ( Disabled )
//---------------------------------------------
MNCCMB regular
eo_information
0 1 unsigned flag_overflow
value = 1 * DEF_DEC_PATH ;
define_value
Filter coeff. automatic
Filter coeff. manual
//
//==============================================
KS0127_HSCLL
Horizontal Scaling low byte
eo_information
2
//---------------------------------------------
CMBMOD regular
eo_information
0 1 unsigned flag_overflow
define_value
Comb enabled on COMB_EN
Comb enabled on VAV active
//----------------------------------------------
HSCL[6:0] regular
eo_information
0 7 unsigned flag_overflow
no_define_value
//==============================================
KS0127_HSCLH
Horizontal Scaling high byte [14:7]
eo_information
1
0 8 unsigned flag_overflow
no_define_value
//==============================================
KS0127_VSCLL
Vertical Scaling low byte
eo_information
3
//---------------------------------------------
ACMBRE regular
eo_information
0 1 unsigned flag_overflow
define_value
High Threshold
Low Threshold
//----------------------------------------------
ACMBCO regular
eo_information
0 1 unsigned flag_overflow
define_value
100% comb
75% comb
//----------------------------------------------
VSCL[5:0] regular
eo_information
0 6 unsigned flag_overflow
no_define_value
//==============================================
KS0127_VSCLH
Vertical Scaling high byte [13:6]
eo_information
1
0 8 unsigned flag_overflow
no_define_value
//==============================================
KS0127_OFMTB
Output Control B
eo_information
7
//---------------------------------------------
reserved protected
eo_information
0 1 unsigned no_flag_overflow
no_define_value
//----------------------------------------------
EVAVG regular
eo_information
0 1 unsigned no_flag_overflow
define_value
EVAV not gated with VAV
EVAV gated with VAV
//----------------------------------------------
EVEHAV regular
eo_information
0 1 unsigned no_flag_overflow
define_value
No additionnal qualifier
EHAV uses qualifier from EVAND
//----------------------------------------------
EVHAV regular
eo_information
0 1 unsigned no_flag_overflow
define_value
No additionnal qualifier
HAV uses qualifier from EVAND
//----------------------------------------------
EVHS1 regular
eo_information
0 1 unsigned no_flag_overflow
define_value
No additionnal qualifier
HS1 uses qualifier from EVAND
//----------------------------------------------
EVAND regular
eo_information
0 2 unsigned no_flag_overflow
define_value
Qualifier is logic '0'
Qualifier is EVAV
Reserved
Qualifier is VAV
//----------------------------------------------
VSVAV regular
eo_information
0 1 unsigned no_flag_overflow
define_value
Output normal VS
VAV is output on VS pin
//==============================================
KS0127_VAVB
VAV Begin Value
eo_information
3
//---------------------------------------------
VAVEV0 regular
eo_information
0 1 unsigned no_flag_overflow
value = 0 ;
no_define_value
//----------------------------------------------
VAVOD0 regular
eo_information
0 1 unsigned no_flag_overflow
value = 0 ;
no_define_value
//----------------------------------------------
VAVB[6:1] regular
eo_information
0 6 unsigned flag_overflow
value = 0 ;
no_define_value
//==============================================
KS0127_VAVE
VAV End Value [8:1]
eo_information
1
0 8 unsigned flag_overflow
value = 0 ;
no_define_value
//
//Added for noise problem
// =============================================
//
KS0127_EXCTRL
Additional Tracking related controls
eo_information
7
// ---------------------------------------------
CLEVEL regular
Programmable CKILL level select but
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Chroma level is 11 IRE
Chroma level is 5.5 IRE
// ---------------------------------------------
BISTE regular
Test Bit for BIST Mode
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Memory fault detected
Memory correct/functional
// ---------------------------------------------
BISTM regular
Bist Memory Test Mode Enable
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Normal mode.Bist not operation
Bist En, memory test started
// ---------------------------------------------
AUCPWD regular
Auto Chroma ADC power down mode enabled when appropriate input format selected
eo_information
0 1 unsigned flag_overflow
// Noise Horizontal dark lines moving up in picture with KS0127 Rev B in MeteorII_STD.
value = DEF_DEC_PATH ;
//
//value = 0 ;
define_value
During Chip Pwr down mode
When CVBS input or case '0'
// ---------------------------------------------
ALTHAV regular
Allows HS2 to be HAV control during this VBI interval
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
HAVB/HAVE = HAV all frame
HS2B,HS2E = HAV (VAV low)
// ---------------------------------------------
TREE regular
Input and Bidirectional pin for test of VOH/VOL/VIH/VIL.PAL nand tree controlled by this bit
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Normal PAD Operation
Nand tree operation mode
// ---------------------------------------------
ENINCST regular
Scaler enable control bit during VBI
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Scaler ON during VBI interval
Scaler OFF during VBI interval
//
//----------------------------------------------
//
// Fin de la patch de Jean-Luc pour Vista Medical (SCALING)############################
//
//
//
// *********************************************
// Decoder KS0127 Chip (End)
// *********************************************
//
//
// *********************************************
// Pixel Packer Chip (end)
// *********************************************
//
// ------------------------------------------------
//PIXPACK_SERINTCTL
//.
//eo_information
//1
//0 8 unsigned flag_overflow
//no_define_value
// ------------------------------------------------
PIXPACK_PIXCTL
.
eo_information
1
0 8 unsigned flag_overflow
no_define_value
// ------------------------------------------------
PIXPACK_COUNT1
.
eo_information
1
0 8 unsigned flag_overflow
no_define_value
// ------------------------------------------------
PIXPACK_COUNT2
.
eo_information
1
0 8 unsigned flag_overflow
no_define_value
//
// *********************************************
// VIA (begin)
// *********************************************
//
//==============================================
VIA_GRABCTRL
Grab control register
eo_information
21
//---------------------------------------------
grabctrl_grabadis protected
SW default: grab operation specified by other grabctrl bits
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
grabctrl_grabsen protected
SW default: continuous grab disabled
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
grabctrl_gsnpsht protected
SW default: grab based on grabsen
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
grabctrl_ghrtrg regular
default: ignore /ihsync until GHTOTAL is reached
eo_information
1 1 unsigned flag_overflow
value = 1 ;
define_value
Ignore IHSYNC/
Start a new field/frame on IHSYNC/
//---------------------------------------------
grabctrl_gvrtrg regular
default: ignore /ivsync until GVTOTAL is reached
eo_information
1 1 unsigned flag_overflow
value = 1 ;
define_value
Ignore IVSYNC/
Start a new field/frame on IVSYNC/
//---------------------------------------------
grabctrl_igvalid regular
default: consider only iclk cycles with ivalid active
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Use IVALID
Ignore IVALID
//---------------------------------------------
grabctrl_gcptmd regular
default: ignore icapture line
eo_information
0 2 unsigned flag_overflow
value = ( ( ! ( GRB_MD_CONT ) ) ? 3 : 0 ) ;
define_value
Ignore ICAPTURE
Rising edge
Grab if high
Rising edge then reset
//---------------------------------------------
grabctrl_gscnmd regular
eo_information
0 2 unsigned flag_overflow
value = VDT_INTERL ;
define_value
Progressive scan mode
Interlaced video mode
Line grab mode
Reserved
//---------------------------------------------
grabctrl_gregudt regular
eo_information
0 3 unsigned flag_overflow
value = (
( DEF_BT254_PATH & VDT_NINTRL & ( ! DEF_NEW_MODE_ASYNC_WEN_PULSE ) & ( EXP_USE_OUT == 0 ) ) ? 6 :
( ( VDT_INTERL & GRB_ACT_IMMEDIATE & ( CT_TAPS == 1 ) & ( TAP_CONFIG == 0x81 ) ) ? 5 :
( ( DEF_NEW_MODE_ASYNC_WEN_PULSE | ( EXP_USE_OUT * GRB_ACT_IMMEDIATE * VDT_NINTRL ) ) ? 7 : 0 ) )
) ;
//
//value = (
// ( DEF_BT254_PATH & VDT_NINTRL & ( ! DEF_NEW_MODE_ASYNC_WEN_PULSE ) ) ? 6 :
// ( ( VDT_INTERL & GRB_ACT_IMMEDIATE & ( CT_TAPS == 1 ) & ( TAP_CONFIG == 0x81 ) ) ? 5 :
// ( DEF_NEW_MODE_ASYNC_WEN_PULSE ? 7 : 0 ) )
// ) ;
define_value
Start odd
Start even
Start any
Grab odd
Grab even
Grab one field
Grab one frame
Grab one frame
//---------------------------------------------
// By convention, odd fields always contain the first line
// of an interlaced frame
grabctrl_gfldpol regular
default: odd fields are identified by ifield low
eo_information
0 1 unsigned flag_overflow
value = (
(
( ( ( ! ( VDT_VSYNC % 2 ) ) & ( ! ( VDT_VBPORCH % 2 ) ) ) |
( ( VDT_VSYNC % 2 ) & ( VDT_VBPORCH % 2 ) )
) * ( ! DEF_DIGITIZER_MASTER )
) +
(
( ( ( ! ( VDT_VSYNC % 2 ) ) & ( VDT_VBPORCH % 2 ) ) |
( ( VDT_VSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) )
) * DEF_DIGITIZER_MASTER
)
) * DEF_BT254_PATH * VDT_INTERL ;
//
//value = (
// (
// ( ( ( ! ( VDT_VSYNC % 2 ) ) & ( VDT_VBPORCH % 2 ) ) |
// ( ( VDT_VSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) )
// ) * ( ! DEF_DIGITIZER_MASTER )
// ) +
// (
// ( ( ( ! ( VDT_VSYNC % 2 ) ) & ( VDT_VBPORCH % 2 ) ) |
// ( ( VDT_VSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) )
// ) * DEF_DIGITIZER_MASTER
// )
// ) * DEF_BT254_PATH * VDT_INTERL ;
define_value
Odd fields are low
Odd fields are high
//---------------------------------------------
grabctrl_gintlad regular
eo_information
0 1 unsigned flag_overflow
value = VDT_INTERL ;
no_define_value
//---------------------------------------------
grabctrl_glnrv regular
default: grab from left to right
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
//---------------------------------------------
grabctrl_ghsmode regular
default: horizontal reference on rising iclk when /ihsync is low
eo_information
0 2 unsigned flag_overflow
value = ( ( SYC_H_OUT & SYC_H_ONEG ) | ( SYC_DIG & SYC_H_IN & SYC_H_INEG ) | ( SYC_ANA & ( ! SYC_H_OUT ) ) ) ;
//
//value = ( ( SYC_H_OUT & SYC_H_ONEG ) | ( SYC_DIG & SYC_H_IN & SYC_H_INEG ) | SYC_ANA ) ;
//value = ( ( SYC_ANA & SYC_H_OUT & SYC_H_ONEG ) | ( SYC_DIG & SYC_H_IN & SYC_H_INEG ) |
// ( DEF_DIGITIZER_MASTER & SYC_DIG & SYC_H_OUT & SYC_H_ONEG ) |
// ( VDC_RGB_COL & VDT_INTERL & ( DEF_60HZ_HV_TOTAL_STD | DEF_50HZ_HV_TOTAL_STD ) )
// ) ;
//value = ( ( SYC_ANA & SYC_H_OUT & SYC_H_ONEG ) | ( SYC_DIG & SYC_H_IN & SYC_H_INEG ) |
// ( VDC_RGB_COL & VDT_INTERL & ( DEF_60HZ_HV_TOTAL_STD | DEF_50HZ_HV_TOTAL_STD ) ) ) ;
define_value
IHSYNC/ low is reference
IHSYNC/ high is reference
Ignore IHSYNC/
Reserved
//---------------------------------------------
grabctrl_gvsmode regular
default: vertical reference on rising iclk when /ivsync is low
eo_information
0 1 unsigned flag_overflow
// Added Pulse Width OR 1 Pulse cases in Asynchronous Reset => 1rst edge VS in comp. Non Interlaced
// Case WEN pulse config => Reference Low
value = (
(
SYC_V_OUT & SYC_V_ONEG &
( ! DEF_NEW_MODE_ASYNC_ONE_TIMER )
) |
( SYC_DIG & SYC_V_IN & SYC_V_INEG ) |
( GRB_ACT_IMMEDIATE * SYC_ANA * ( ! SYC_V_ONEG ) * ( EXP_USE_OUT == 0 ) )
) ;
//
//value = (
// (
// SYC_V_OUT & SYC_V_ONEG &
// ( ! DEF_NEW_MODE_ASYNC_ONE_TIMER )
// ) |
// ( SYC_DIG & SYC_V_IN & SYC_V_INEG ) |
// (
// GRB_ACT_IMMEDIATE * SYC_ANA * ( ! SYC_V_ONEG ) *
// ( DEF_NEW_MODE_ASYNC_ONE_TIMER )
// )
// ) ;
define_value
IVSYNC/ low is reference
IVSYNC/ high is reference
//---------------------------------------------
grabctrl_gintdst protected
default: the MVP receives the grab interrupts
eo_information
0 1 unsigned flag_overflow
// value = HANDLE BY SW ;
no_define_value
//---------------------------------------------
grabctrl_glinten protected
default: disable grab line interrupts
eo_information
0 2 unsigned flag_overflow
// value = HANDLE BY SW ;
no_define_value
//---------------------------------------------
grabctrl_soginten protected
default: enable SoG interrupts
eo_information
0 1 unsigned flag_overflow
// value = HANDLE BY SW ;
no_define_value
//---------------------------------------------
grabctrl_eoginten protected
default: enable EoG interrupts
eo_information
0 1 unsigned flag_overflow
// value = HANDLE BY SW ;
no_define_value
//---------------------------------------------
grabctrl_ivldpol regular
default: use ivalid directly: ivalid is active high
eo_information
0 2 unsigned flag_overflow
//value = EQUATION MAY BE USED
value = 0 ;
//value = ( VDC_DIG ? 2 :
// 0 ) ;
define_value
IVALID is active high
IVALID is active low
IVALID is active high
IVALID is active low
//---------------------------------------------
grabctrl_grbsrc protected
default: source of grab is the grab port
eo_information
0 1 unsigned flag_overflow
// value = HANDLE BY SW ;
no_define_value
//---------------------------------------------
reserved protected
Unused bits.
eo_information
0 5 unsigned flag_overflow
no_define_value
//==============================================
VIA_GVWSTART
Vertical window start
eo_information
1
0 16 unsigned flag_overflow
value = (
( DEF_DEC_PATH & DEF_DEC_60HZ ) ? ( VDT_VBPORCH - 6 ) :
( ( DEF_DEC_PATH & DEF_DEC_50HZ ) ? ( VDT_VBPORCH - 9 ) :
( ( DEF_BT254_PATH & VDT_INTERL ) ? 1 :
0 ) )
) ;
//
//value = (
// ( DEF_DEC_PATH & DEF_DEC_60HZ ) ? ( VDT_VBPORCH - 6 ) :
// ( ( DEF_DEC_PATH & DEF_DEC_50HZ ) ? ( VDT_VBPORCH - 9 ) :
// ( ( DEF_BT254_PATH ) ? 1 : 0
// ) )
// ) ;
no_define_value
//==============================================
VIA_GVWSTOP
Vertical window stop
eo_information
1
0 16 unsigned flag_overflow
//
value = (
( DEF_DEC_PATH & DEF_DEC_60HZ ) ? ( ( VDT_VBPORCH - 6 ) + ( VDT_VACTIVE - 1 ) ) :
( ( DEF_DEC_PATH & DEF_DEC_50HZ ) ? ( ( VDT_VBPORCH - 9 ) + ( VDT_VACTIVE - 1 ) ) :
( ( DEF_BT254_PATH * EXP_USE_OUT * GRB_ACT_IMMEDIATE * VDT_NINTRL ) ? ( VDT_VACTIVE - 1 ) :
( ( DEF_BT254_PATH * ( ! ( EXP_USE_OUT * GRB_MD_HW_TRG ) ) ) ? 0xffff :
0 ) ) )
) ;
//
no_define_value
//==============================================
VIA_GVTOTAL
Vertical total
eo_information
1
0xffff 16 unsigned flag_overflow
//
value = (
( ( ! ( DEF_BT254_PATH * EXP_USE_OUT * GRB_MD_HW_TRG ) ) * 0xffff ) +
( DEF_BT254_PATH * EXP_USE_OUT * GRB_ACT_IMMEDIATE * VDT_NINTRL * ( VDT_VTOTAL - 1 ) )
) ;
//
no_define_value
//==============================================
VIA_GHWSTART
Horizontal window start
eo_information
1
0 16 unsigned flag_overflow
value = 0 ;
no_define_value
//==============================================
VIA_GHWSTOP
Horizontal window stop
eo_information
1
0 16 unsigned flag_overflow
//
value = (
( ( ! ( DEF_BT254_PATH * EXP_USE_OUT * GRB_MD_HW_TRG ) ) * 0xffff ) +
( DEF_BT254_PATH * EXP_USE_OUT * GRB_ACT_IMMEDIATE * VDT_NINTRL * ( VDT_HACTIVE - 1 ) )
) ;
//
//value = 0xffff ;
no_define_value
//==============================================
VIA_GHTOTAL
Horizontal total
eo_information
1
0 16 unsigned flag_overflow
value = (
( ( ! ( DEF_BT254_PATH * EXP_USE_OUT * GRB_MD_HW_TRG ) ) * 0xffff ) +
( DEF_BT254_PATH * EXP_USE_OUT * GRB_ACT_IMMEDIATE * VDT_NINTRL * ( VDT_HTOTAL - 1 ) )
) ;
//value = 0xffff ;
// value = ( VDT_HFPORCH + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) ;
no_define_value
//==============================================
VIA_HGIOCTRL
Host General I/O Control
eo_information
1
0 32 unsigned flag_overflow
// No more used for CORONA-LC & METEOR-II-STD REV 1 & REV 2 => Use Decoder CMDD's Register Bit 0 for Both Boards
value = 0 ;
no_define_value
//==============================================
// **************************************************************
//
// Bits Field 6 5 4 3 in GPIXFMT
// CH3 CH2 CH1 CH0
// 8 BITS Corona/Meteor_II_MC Ana Dig
// 0 0 1 1 = 3 => Red Green 0x118 0x118
// 0 1 0 1 = 5 => Red Blue 0x128 ---
// 0 1 1 0 = 6 => Green Blue 0x130 ---
//
// For CoronaII ONLY: Done exclusivly by Driver which overwrite value in DCF.
// Limited to 2 first channel because noise problem on Blue on CoronaII.
// 8 BITS Corona_II Ana Dig
// 0 0 1 1 = 3 => Red Green 0x9f9 0x10
// 10 BITS Corona_II
// 0 0 1 1 = 3 => Red Green 0x1f9 0x99
//
// **************************************************************
// Default Value = 0x118 for 2 Taps which don't affect grab in 1 Tap
VIA_GPIXFMT
Grab control register
eo_information
7
//---------------------------------------------
gpixfmt_gstfmt regular
eo_information
0 3 unsigned flag_overflow
value = 0 ;
//
//value = ( CT_TAPS * ( VDC_ANA | ( VDC_DIG * VDC_VID_WIDTH_10 ) ) * ( OPTION_II | OPTION_II_DIG ) ) ;
//value = ( CT_TAPS * ( OPTION_II | OPTION_II_DIG ) ) ;
// value = 0 ;
define_value
1 Byte/Plane
2 Bytes/Plane
3 Bytes/plane
4 Bytes/Plane
1 Byt/Pln all 3 Display
Reserved
Reserved
Reserved
//---------------------------------------------
gpixfmt_gtsize regular
eo_information
3 4 unsigned flag_overflow
// CoronaII Overwrited from DCF MeteorII/MC Dual Taps.
value = ( CT_TAPS * VDC_IN_CH0 * VDC_IN_CH1 * 3 ) ;
//
//value = ( CT_TAPS * VDC_IN_CH0 * VDC_IN_CH1 *
// ( 3 + ( 12 * VDC_ANA * ( OPTION_II | OPTION_II_DIG ) ) -
// ( VDC_DIG * VDC_WD8 * ( OPTION_II | OPTION_II_DIG ) )
// )
// ) ;
//value = ( CT_TAPS * VDC_IN_CH0 * VDC_IN_CH1 * ( 3 + ( 12 * ( OPTION_II | OPTION_II_DIG ) ) ) ) ;
//value = ( CT_TAPS * VDC_IN_CH0 * VDC_IN_CH1 * 3 ) ;
no_define_value
//---------------------------------------------
gpixfmt_gbitchnl regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
//
//value = ( CT_TAPS * ( VDC_ANA | ( VDC_DIG * VDC_VID_WIDTH_10 ) ) * ( OPTION_II | OPTION_II_DIG ) ) ;
//value = ( CT_TAPS * ( OPTION_II | OPTION_II_DIG ) ) ;
//value = 0 ;
define_value
8 Bits/Channel
16 Bits/Channel
//---------------------------------------------
gpixfmt_gnbchnl regular
eo_information
1 2 unsigned flag_overflow
value = CT_TAPS ;
//
//value = ( ( CT_TAPS * ( ! ( OPTION_II | OPTION_II_DIG ) ) ) |
// ( CT_TAPS * VDC_ANA * ( OPTION_II | OPTION_II_DIG ) )
// ) ;
//value = CT_TAPS ;
define_value
1 Channel
2 Channels
3 Channels
4 Channels
//---------------------------------------------
gpixfmt_gcolor regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Grab port=Byte order
Exchange bytes order
//---------------------------------------------
gpixfmt_gbtxtrct regular
eo_information
0 2 unsigned flag_overflow
value = 0 ;
//
//value = ( CT_TAPS * ( OPTION_II | OPTION_II_DIG ) * ( VDC_ANA * VDC_WD8 ) ) ;
//value = ( CT_TAPS * VDC_WD8 * ( OPTION_II | OPTION_II_DIG ) ) ;
//value = 0 ;
define_value
Byte Extract desable
Extract ( 9:2)
Extract (11:4)
Extract (13:6)
//---------------------------------------------
gpixfmt_gfmtcvr regular
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No conversion
Convert 8 to 10 bits channel
//---------------------------------------------
// *********************************************
// VIA (end)
// *********************************************
//
//
// *********************************************
// PSGTC (begin)
// *********************************************
//
// -----------------------------------
// PSG HTOTAL Register
// -----------------------------------
//==============================================
PSG_HTOTAL
Horizontal total count
eo_information
1
0 12 unsigned flag_overflow
value = ( VDT_HTOTAL - 1 ) * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG HSSYNC Register
// -----------------------------------
//==============================================
PSG_HSSYNC
Horizontal start sync
eo_information
1
0 12 unsigned flag_overflow
//value = ( SYC_ANA & DEF_CONT_SYNC_GRAB ? ( ( VDT_HTOTAL - 1 ) - DEF_HSYNC_TRAILS_VSYNC ) :
// ( SYC_DIG & DEF_CONT_SYNC_GRAB & ( ! DEF_DIGITIZER_MASTER ) ? ( ( VDT_HTOTAL - 1 ) - DEF_DIG_SYNCPIPE ) :
// ( SYC_DIG & DEF_DIGITIZER_MASTER ? ( ( SYC_CAM_LATENCY > 0 ) * ( VDT_HTOTAL - SYC_CAM_LATENCY ) ) :
// 0 ) )
// ) * DEF_PSG_ON * DEF_BT254_PATH ;
value = ( SYC_ANA & DEF_CONT_SYNC_GRAB ? ( ( VDT_HTOTAL - 1 ) - DEF_HSYNC_TRAILS_VSYNC ) :
( SYC_DIG & DEF_CONT_SYNC_GRAB & ( ! DEF_DIGITIZER_MASTER ) ? ( ( VDT_HTOTAL - 1 ) - DEF_DIG_SYNCPIPE ) :
( SYC_DIG & DEF_DIGITIZER_MASTER ? ( ( SYC_CAM_LATENCY > 0 ) * ( VDT_HTOTAL - SYC_CAM_LATENCY ) ) :
0 ) )
) * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG HESYNC Register
// -----------------------------------
// Ajout condition ( VDT_HSYNC == 0 ) en SYNC DIG. pour garder min. HS = 1 pour RST HCOUNT du VIA meme User set HS = 0.
// Mode RST Async. => Pas RRUNNER & Qd { Hsync < DIG_SYN_PIPE } => HS = 1 Min.
//==============================================
PSG_HESYNC
Horizontal end sync
eo_information
1
0 12 unsigned flag_overflow
//value = ( SYC_ANA ? (
// (
// (
// ( ( ( VDT_HSYNC - 1 ) - DEF_HSYNC_TRAILS_VSYNC ) * ( VDT_HSYNC >= 3 ) ) +
// ( ( VDT_HTOTAL - 3 + VDT_HSYNC ) * ( VDT_HSYNC > 0 ) * ( VDT_HSYNC < 3 ) ) +
// ( ( VDT_HTOTAL - 2 ) * ( VDT_HSYNC == 0 ) )
// ) * DEF_CONT_SYNC_GRAB
// ) +
// ( ( VDT_HSYNC + ( VDT_HSYNC == 0 ) ) * DEF_RST_ASYNC_GRAB )
// ) :
// ( SYC_DIG & ( ! DEF_DIGITIZER_MASTER ) ?
// ( ( ( ( VDT_HSYNC - 1 ) - DEF_DIG_SYNCPIPE ) * DEF_CONT_SYNC_GRAB * ( VDT_HSYNC > DEF_DIG_SYNCPIPE ) ) +
// ( ( VDT_HTOTAL - 1 - DEF_DIG_SYNCPIPE + VDT_HSYNC ) * DEF_CONT_SYNC_GRAB * ( VDT_HSYNC <= DEF_DIG_SYNCPIPE ) ) +
// ( VDT_HSYNC == 0 ) +
// ( ( DEF_RST_ASYNC_GRAB * ( VDT_HSYNC != 0 ) ) * VDT_HSYNC )
// ) :
// ( SYC_DIG & DEF_DIGITIZER_MASTER ?
// ( ( VDT_HSYNC * ( VDT_HSYNC > 0 ) * ( SYC_CAM_LATENCY == 0 ) )
// + ( ( VDT_HSYNC == 0 ) * ( SYC_CAM_LATENCY == 0 ) )
// + ( ( VDT_HSYNC - SYC_CAM_LATENCY ) * ( SYC_CAM_LATENCY <= VDT_HSYNC ) * ( SYC_CAM_LATENCY > 0 ) * ( VDT_HSYNC > 0 ) )
// + ( ( VDT_HTOTAL - ( SYC_CAM_LATENCY - VDT_HSYNC ) ) * ( SYC_CAM_LATENCY > VDT_HSYNC ) * ( VDT_HSYNC > 0 ) )
// + ( ( VDT_HTOTAL - SYC_CAM_LATENCY + 1 ) * ( VDT_HSYNC == 0 ) * ( SYC_CAM_LATENCY > 1 ) )
// ) : 1
// ) )
// ) * DEF_PSG_ON * DEF_BT254_PATH ;
//
value = ( SYC_ANA ? (
(
(
( ( ( VDT_HSYNC - 1 ) - DEF_HSYNC_TRAILS_VSYNC ) * ( VDT_HSYNC >= 3 ) ) +
( ( VDT_HTOTAL - 3 + VDT_HSYNC ) * ( VDT_HSYNC > 0 ) * ( VDT_HSYNC < 3 ) ) +
( ( VDT_HTOTAL - 2 ) * ( VDT_HSYNC == 0 ) )
) * DEF_CONT_SYNC_GRAB
) +
( ( VDT_HSYNC + ( VDT_HSYNC == 0 ) ) * DEF_RST_ASYNC_GRAB )
) :
( SYC_DIG & ( ! DEF_DIGITIZER_MASTER ) ?
( ( ( ( VDT_HSYNC - 1 ) - DEF_DIG_SYNCPIPE ) * DEF_CONT_SYNC_GRAB * ( VDT_HSYNC > DEF_DIG_SYNCPIPE ) ) +
( ( VDT_HTOTAL - 1 - DEF_DIG_SYNCPIPE + VDT_HSYNC ) * DEF_CONT_SYNC_GRAB * ( VDT_HSYNC <= DEF_DIG_SYNCPIPE ) ) +
( VDT_HSYNC == 0 ) +
( ( DEF_RST_ASYNC_GRAB * ( VDT_HSYNC != 0 ) ) * VDT_HSYNC )
) :
( SYC_DIG & DEF_DIGITIZER_MASTER ?
( ( VDT_HSYNC * ( VDT_HSYNC > 0 ) * ( SYC_CAM_LATENCY == 0 ) )
+ ( ( VDT_HSYNC == 0 ) * ( SYC_CAM_LATENCY == 0 ) )
+ ( ( VDT_HSYNC - SYC_CAM_LATENCY ) * ( SYC_CAM_LATENCY <= VDT_HSYNC ) * ( SYC_CAM_LATENCY > 0 ) * ( VDT_HSYNC > 0 ) )
+ ( ( VDT_HTOTAL - ( SYC_CAM_LATENCY - VDT_HSYNC ) ) * ( SYC_CAM_LATENCY > VDT_HSYNC ) * ( VDT_HSYNC > 0 ) )
+ ( ( VDT_HTOTAL - SYC_CAM_LATENCY + 1 ) * ( VDT_HSYNC == 0 ) * ( SYC_CAM_LATENCY > 1 ) )
) : 1
) )
) * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG HSPVAL Register
// -----------------------------------
// Analog Video pipe = 6 & Digital Video Pipe = 1
//==============================================
PSG_HSPVAL
Horizontal start pixel valid
// Pas Wrap around avec PVAL en RESET ASYNCHRONE
eo_information
1
0 12 unsigned flag_overflow
//
value = (
SYC_ANA ? ( DEF_PSG_HSPLLFB + VDT_HSYNC + VDT_HBPORCH + DEF_BTPIPE + DEF_LUTPIPE ) :
( ( SYC_DIG & ( ! DEF_DIGITIZER_MASTER ) ) ?
(
( ( VDT_HSYNC - 1 + VDT_HBPORCH - DEF_DIG_SYNCPIPE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE )
* ( ( ( VDT_HSYNC >= 0 ) & VDC_ANA ) | ( ( VDT_HSYNC + VDT_HBPORCH ) >= ( DEF_DIG_SYNCPIPE * VDC_DIG ) ) )
) +
( ( VDT_HSYNC + VDT_HBPORCH + VDT_HTOTAL - DEF_DIG_SYNCPIPE ) * ( ( VDT_HSYNC + VDT_HBPORCH ) < ( DEF_DIG_SYNCPIPE * VDC_DIG ) )
* DEF_CONT_SYNC_GRAB
) +
( 2 * DEF_RST_ASYNC_GRAB * ( ( VDT_HSYNC + VDT_HBPORCH ) < ( DEF_DIG_SYNCPIPE * VDC_DIG ) ) )
) :
( SYC_DIG & DEF_DIGITIZER_MASTER ?
( VDT_HSYNC - 1 + VDT_HBPORCH + ( DEF_DIG_VIDPIPE * VDC_DIG ) + DEF_LUTPIPE )
) )
) * DEF_PSG_ON * DEF_BT254_PATH ;
//
no_define_value
// -----------------------------------
// PSG HEPVAL Register
// -----------------------------------
//==============================================
PSG_HEPVAL
Horizontal end pixel valid
eo_information
1
0 12 unsigned flag_overflow
//
// Change in analog sync for cases HEPVAL > HTOTAL 0,1,2 Cont. Grab; Clip to HTOTAL in Async. Reset.
value = ( SYC_ANA ? (
(
( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) *
( ( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) <= ( VDT_HTOTAL - 1 ) )
) +
(
( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - VDT_HTOTAL )
* DEF_CONT_SYNC_GRAB *
( ( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) > ( VDT_HTOTAL - 1 ) )
) +
( ( VDT_HTOTAL - 1 ) * DEF_RST_ASYNC_GRAB *
( ( DEF_PSG_HSPLLFB + DEF_BTPIPE + DEF_LUTPIPE + VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE ) > ( VDT_HTOTAL - 1 ) )
)
) :
( ( SYC_DIG & ( ! DEF_DIGITIZER_MASTER ) ) ?
(
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) *
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) <= ( VDT_HTOTAL - 1 ) )
) +
( ( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) - VDT_HTOTAL )
* DEF_CONT_SYNC_GRAB *
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
) +
( ( VDT_HTOTAL - 1 ) * DEF_RST_ASYNC_GRAB *
( ( VDT_HSYNC - 1 - DEF_DIG_SYNCPIPE + VDT_HBPORCH + VDT_HACTIVE + ( DEF_DIG_VIDPIPE * VDC_DIG ) + ( DEF_BTPIPE * VDC_ANA ) + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
)
) :
( SYC_DIG & DEF_DIGITIZER_MASTER ?
(
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) *
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) <= ( VDT_HTOTAL - 1 ) )
) +
( ( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) - VDT_HTOTAL )
* DEF_CONT_SYNC_GRAB *
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
) +
( ( VDT_HTOTAL - 1 ) * DEF_RST_ASYNC_GRAB *
( ( VDT_HSYNC - 1 + VDT_HBPORCH + VDT_HACTIVE + DEF_LUTPIPE ) > ( VDT_HTOTAL - 1 ) )
)
)
) )
) * DEF_PSG_ON * DEF_BT254_PATH ;
//
no_define_value
// -----------------------------------
// PSG HSCLMP Register
// -----------------------------------
//
// DIGITAL Sync & ANALOG VIDEO : CLAMP START END
// BPORCH ESYNC SPVAL
// HSYNC SSYNC ESYNC
// FPORCH EPVAL HSSYNC
//
// HSCLMP = 0 When 1) Asynchronous reset Sync Ana or Dig
// 2) Continuous Grab when HS = 2 in Ana Sync or HS = 3 in Dig Sync
//==============================================
PSG_HSCLMP
Horizontal start clamp
eo_information
1
0 12 unsigned flag_overflow
// Clamping in Hor. Back Porch
// PSG_HSCLMP = VDT_HESYNC + DEF_CLAMP_BORDER +- Selon Barriere >0 ( 0 + ) OU <0 ( HTOTAL - X )
//
// Clamping in Hor. Front Porch
// PSG_HSCLMP = VDT_HSYNC + VDT_HBPORCH + VDT_HACTIVE - DEF_CLAMP_WIDTH - DEF_CLAMP_BORDER
value = (
(
(
(
(
( VDT_HSYNC + DEF_CLAMP_BORDER - ( DEF_RST_ASYNC_GRAB * SYC_DIG ) ) *
( DEF_RST_ASYNC_GRAB | ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) ) )
) +
(
( DEF_CLAMP_BORDER + VDT_HSYNC ) * ( VDT_HSYNC < ( 2 + SYC_DIG ) )
) -
( DEF_DIGITIZER_MASTER * 5 )
) * VDT_CLP_BPO
) +
(
(
VDT_HTOTAL - DEF_CLAMP_BORDER - DEF_CLAMP_WIDTH - 1
) * VDT_CLP_FPO
)
) * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH
) ;
//
//value = (
// (
// ( VDT_HSYNC + DEF_CLAMP_BORDER - ( DEF_RST_ASYNC_GRAB * SYC_DIG ) ) *
// ( DEF_RST_ASYNC_GRAB | ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) ) )
// ) +
// (
// ( DEF_CLAMP_BORDER + VDT_HSYNC ) * ( VDT_HSYNC < ( 2 + SYC_DIG ) )
// ) -
// ( DEF_DIGITIZER_MASTER * 5 )
// ) * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG HECLMP Register
// -----------------------------------
//==============================================
PSG_HECLMP
Horizontal end clamp
eo_information
1
0 12 unsigned flag_overflow
// Clamping in Hor. Back Porch
// PSG_HECLMP = PSG_HSCLMP + DEF_CLAMP_WIDTH
// PSG_HECLMP = VDT_HSSYNC + DEF_CLAMP_BORDER
// + DEF_CLAMP_WIDTH +- Selon Barriere >0 ( 0 + ) OU <0 ( HTOTAL - X )
// Clamping in Hor. Front Porch
// PSG_HECLMP = VDT_HTOTAL - 1 - DEF_CLAMP_BORDER
value = (
(
(
(
(
( VDT_HSYNC + DEF_CLAMP_BORDER + DEF_CLAMP_WIDTH - ( DEF_RST_ASYNC_GRAB * SYC_DIG ) ) *
( DEF_RST_ASYNC_GRAB | ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) ) )
) +
(
( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC < ( 2 + SYC_DIG ) ) ) *
( DEF_CLAMP_WIDTH + DEF_CLAMP_BORDER + VDT_HSYNC )
) -
( DEF_DIGITIZER_MASTER * 5 )
) * VDT_CLP_BPO
) +
(
(
VDT_HTOTAL - DEF_CLAMP_BORDER - 1
) * VDT_CLP_FPO
)
) * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH
) ;
//
//value = (
// (
// ( VDT_HSYNC + DEF_CLAMP_BORDER + DEF_CLAMP_WIDTH - ( DEF_RST_ASYNC_GRAB * SYC_DIG ) ) *
// ( DEF_RST_ASYNC_GRAB | ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC >= ( 2 + SYC_DIG ) ) ) )
// ) +
// (
// ( DEF_CONT_SYNC_GRAB * ( VDT_HSYNC < ( 2 + SYC_DIG ) ) ) *
// ( DEF_CLAMP_WIDTH + DEF_CLAMP_BORDER + VDT_HSYNC )
// ) -
// ( DEF_DIGITIZER_MASTER * 5 )
// ) * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH ;
//
no_define_value
// -----------------------------------
// PSG HSPLLFB Register
// -----------------------------------
//==============================================
PSG_HSPLLFB
Horizontal start pll feadback signal
eo_information
1
0 12 unsigned flag_overflow
value = DEF_PSG_HSPLLFB * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG VTOTAL Register
// -----------------------------------
// Pipe NOT included in Vertical timings because just few PIXCLK's in the complete Line.
//==============================================
PSG_VTOTAL
Vertical total count
eo_information
1
0 12 unsigned flag_overflow
//value = ( VDT_VTOTAL - 1 ) * DEF_PSG_ON * DEF_BT254_PATH ;
value = ( VDT_VTOTAL - 1 ) * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG SVCNT Register
// -----------------------------------
//==============================================
PSG_SVCNT
Vertical start count
eo_information
1
0 12 unsigned flag_overflow
value = 0 ;
no_define_value
//
// -----------------------------------
// PSG VSSYNC Register
// -----------------------------------
//==============================================
PSG_VSSYNC
Vertical start sync
eo_information
1
0 12 unsigned flag_overflow
value = ( 0 * DEF_PSG_ON ) ;
no_define_value
// -----------------------------------
// PSG VESYNC Register
// -----------------------------------
//==============================================
PSG_VESYNC
Vertical end sync
eo_information
1
0 12 unsigned flag_overflow
value = (
SYC_ANA ? ( ( ( VDT_VBPORCH % 2 ) * ( ( ( VDT_VSYNC - 1 ) * ( VDT_VSYNC > 1 ) ) + ( VDT_VSYNC <= 1 ) ) ) +
( ( ! ( VDT_VBPORCH % 2 ) ) * ( ( ( VDT_VSYNC - 2 ) * ( VDT_VSYNC > 2 ) ) + ( VDT_VSYNC <= 2 ) ) )
) :
( SYC_DIG & ( VDT_VSYNC > 0 ) ? VDT_VSYNC : 1
)
) * DEF_PSG_ON * DEF_BT254_PATH ;
//value = (
// SYC_ANA ? ( ( ( VDT_VBPORCH % 2 ) * ( VDT_VSYNC - 1 ) ) + ( ( ! ( VDT_VBPORCH % 2 ) ) * ( VDT_VSYNC - 2 ) ) ) :
// ( SYC_DIG & ( VDT_VSYNC > 0 ) ? VDT_VSYNC : 1
// )
// ) * DEF_PSG_ON ;
// ( VDT_VBPORCH % 2 ) ? ( VDT_VSYNC - 1 ) :
// ( ( ! ( VDT_VBPORCH % 2 ) ) ? ( VDT_VSYNC - 2 ) :
// 0 )
// ) * DEF_PSG_ON ;
//value = ( VDT_VSYNC - 1 ) * DEF_PSG_ON ;
no_define_value
// -----------------------------------
// PSG VSPVAL Register
// -----------------------------------
//==============================================
PSG_VSPVAL
Vertical start pval
eo_information
1
0 12 unsigned flag_overflow
// Remove 2 lines IN PAL Timing By RGB Path
value = ( SYC_ANA ? ( VDT_VSYNC + VDT_VBPORCH - 1 - ( DEF_50HZ_HV_TOTAL_STD * 2 ) ) :
( SYC_DIG ? ( VDT_VSYNC + VDT_VBPORCH - 1 ) : 0
)
) * DEF_PSG_ON * DEF_BT254_PATH ;
//
//value = ( SYC_ANA ? ( ( ( DEF_BT254_PATH & VDT_NINTRL ) * ( VDT_VSYNC + VDT_VBPORCH - 1 ) )
// + ( VDT_INTERL * ( VDT_VSYNC + VDT_VBPORCH - 1 ) ) ) :
// ( SYC_DIG ? ( VDT_VSYNC + VDT_VBPORCH - 1 ) : 0
// )
// ) * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG VEPVAL Register
// -----------------------------------
// ( 3 * ( VDC_RGB_COL & VDC_ANA ) ) => Pour DXC-9000 VEPVAL 3 CNT en MOINS
//==============================================
PSG_VEPVAL
Vertical end pval
eo_information
1
0 12 unsigned flag_overflow
// Remove 1 line for compatibility vertical cropping with RGB & Dec Path in Analog Sync.
value = ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( DEF_50HZ_HV_TOTAL_STD * SYC_ANA * 2 ) ) * DEF_PSG_ON * DEF_BT254_PATH ) ;
//
//value = ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - ( ! CT_TAPS ) - ( DEF_50HZ_HV_TOTAL_STD * VDT_INTERL * 2 ) ) * DEF_PSG_ON * DEF_BT254_PATH ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 - ( DEF_50HZ_HV_TOTAL_STD * VDT_INTERL * 2 ) ) * DEF_PSG_ON * DEF_BT254_PATH ) ;
//value = ( ( VDT_VSYNC + VDT_VBPORCH + VDT_VACTIVE - 1 ) * DEF_PSG_ON * DEF_BT254_PATH ) ;
no_define_value
// -----------------------------------
// PSG VSCLMP Register
// -----------------------------------
// Start clamping at least 2 lines : 1st lost in reset time and second for 1 line minimum for VSYNC
//==============================================
PSG_VSCLMP
Vertical start clamp
eo_information
1
0 12 unsigned flag_overflow
value = ( ( VDT_VSYNC + 2 ) - ( ( ( VDT_VSYNC + 2 ) > VDT_VBPORCH ) * 2 ) - ( VDT_VBPORCH == 0 ) ) *
VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH ;
//
//value = ( ( VDT_VSYNC + 2 ) * VDC_ANA ) * DEF_PSG_ON * DEF_BT254_PATH ;
//value = ( 2 * VDT_VSYNC ) * DEF_PSG_ON ;
no_define_value
// -----------------------------------
// PSG VECLMP Register
// -----------------------------------
//==============================================
PSG_VECLMP
Vertical end clamp
eo_information
1
0 12 unsigned flag_overflow
//value = ( VDT_VTOTAL - 2 + ( VDT_VFPORCH == 0 ) ) * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH ;
value = ( VDT_VTOTAL - 2 + ( VDT_VFPORCH == 0 ) ) * VDC_ANA * DEF_PSG_ON * DEF_BT254_PATH ;
no_define_value
// -----------------------------------
// PSG HVRCTLL Register
// -----------------------------------
//==============================================
PSG_HVRCTL
Horizontal and vertical reset control
eo_information
11
//---------------------------------------------
hrstsel regular
Horizontal reset selection
eo_information
0 3 unsigned flag_overflow
// Select TTL or RS422 HS to RESET HCOUNT
//
value = (
SYC_DIG & SYC_CAM_GEN & SYC_H_IN ? 2 :
( SYC_DIG & SYC_CAM_GEN & SYC_V_IN & ( ! ( SYC_H_IN ) ) ? 3 :
( ( SYC_DIG & DEF_DIGITIZER_MASTER & VDC_DIG & GRB_TRG_SIGNAL_TIMER1 ) ? 6 :
( ( SYC_DIG & DEF_DIGITIZER_MASTER & VDC_DIG & GRB_TRG_SIGNAL_TIMER2 ) ? 7 :
( ( DEF_DEC_PATH & SYC_CAM_GEN & ( SYC_H_OUT | SYC_V_OUT ) ) ? 0 :
1 ) ) ) )
) * DEF_PSG_ON * DEF_BT254_PATH ;
//value = ( SYC_DIG & SYC_CAM_GEN & SYC_H_IN ? 2 :
// ( SYC_DIG & SYC_CAM_GEN & SYC_V_IN & ( ! ( SYC_H_IN ) ) ? 3 :
// ( ( DEF_DEC_PATH & SYC_CAM_GEN & ( SYC_H_OUT | SYC_V_OUT ) ) ? 0 :
// 1 ) )
// ) * DEF_PSG_ON ;
define_value
DECHS input pin
NGCSYNC output pin
PINHSYNC input pin
PINVSYNC input pin
TRIGGER input pin
EXP1 output pin
EXP2 output pin
Reserved
//---------------------------------------------
hrstpol regular
Horizontal reset polarity control
eo_information
0 1 unsigned flag_overflow
// Invert if Negative Pulse ; RESET at RISING Edge
value = (
( DEF_BT254_PATH & ( SYC_ANA | ( SYC_DIG & SYC_H_INEG ) ) ) ? 1 : 0
) * DEF_PSG_ON ;
//
//value = (
// (
// ( DEF_BT254_PATH & ( SYC_ANA | ( SYC_DIG & SYC_H_INEG ) ) ) |
// ( DEF_DEC_PATH & SYC_CAM_GEN & ( SYC_H_OUT | SYC_V_OUT ) )
// ) ? 1 : 0
// ) * DEF_PSG_ON ;
define_value
No polarity inversion
The selected signal is inverted
//---------------------------------------------
hrsten regular
Horizontal reset enable
eo_information
0 1 unsigned flag_overflow
// Reset HCOUNT SI Digital HS
//value = 0 * ( ! DEF_DEC_PATH ) ;
value = ( ( ( VDC_DIG & SYC_DIG & SYC_CAM_GEN & ( SYC_H_IN | SYC_V_IN ) ) | ( DEF_DEC_PATH & ( SYC_H_OUT | SYC_V_OUT ) ) & SYC_CAM_GEN ) ? 1 : 0
) * DEF_PSG_ON ;
define_value
Horizontal reset disable
Horizontal reset enable
//---------------------------------------------
hrsbysyn regular
Horizontal reset bypass synchronization
// No Resynchronization when Digital Sync and PCLK received from Camera to miniminise pipeline and HSYNC pulse width
eo_information
0 1 unsigned flag_overflow
value = ( PCK_CAM_GEN * SYC_DIG ) * ( ! DEF_DEC_PATH ) ;
define_value
Resynchronization
No resynchronization
//---------------------------------------------
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
//---------------------------------------------
vrstsel regular
Vertical reset selection
eo_information
0 3 unsigned flag_overflow
// Selection EXP1 & EXP2 not STANDARD .
// Select TTL or RS422 VS to RESET VCOUNT
// Reset VS Counter if WEN Pulse ( Old or New mode ) or New mode 1 Timer Grab.
// N.B. Old mode Wen pulse => with & without : send to external circuit other than camera
// (check on or off) .
// => new old mode decoding = timers setting ONLY !
//
value = (
(
( SYC_DIG & SYC_V_IN ) | DEF_NEW_MODE_ASYNC_WEN_PULSE |
(
GRB_ACT_IMMEDIATE & ( ! DEF_NEW_MODE_ASYNC_ONE_TIMER ) &
(
( GRB_TRG_SIGNAL_TIMER1 & EXP_MD_VSY & EXP_MD_W_TRG & ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
( GRB_TRG_SIGNAL_TIMER2 & EXP_MD_VSY_2 & EXP_MD_W_TRG_2 & ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
)
)
) ? 2 :
( ( DEF_DEC_PATH & SYC_CAM_GEN & ( SYC_H_OUT | SYC_V_OUT ) ) ? 0 :
( (
DEF_DIGITIZER_MASTER & GRB_ACT_IMMEDIATE & GRB_TRG_SIGNAL_TIMER1 &
( ! DEF_NEW_MODE_ASYNC_WEN_PULSE ) & ( ! EXP_MD_VSY )
) ? 4 :
( (
DEF_DIGITIZER_MASTER & GRB_ACT_IMMEDIATE & GRB_TRG_SIGNAL_TIMER2 &
( ! DEF_NEW_MODE_ASYNC_WEN_PULSE ) & ( ! EXP_MD_VSY_2 )
) ? 5 :
1 ) ) )
) * DEF_PSG_ON * DEF_BT254_PATH ;
//
//value = (
// (
// ( SYC_DIG & SYC_V_IN ) | DEF_NEW_MODE_ASYNC_WEN_PULSE |
// (
// GRB_ACT_IMMEDIATE & ( ! DEF_NEW_MODE_ASYNC_ONE_TIMER ) &
// (
// ( GRB_TRG_SIGNAL_TIMER1 & EXP_MD_VSY & EXP_MD_W_TRG & ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
// ( GRB_TRG_SIGNAL_TIMER2 & EXP_MD_VSY_2 & EXP_MD_W_TRG_2 & ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
// )
// )
// ) ? 2 :
// ( ( DEF_DEC_PATH & SYC_CAM_GEN & ( SYC_H_OUT | SYC_V_OUT ) ) ? 0 :
// ( (
// ( GRB_ACT_IMMEDIATE & GRB_TRG_SIGNAL_TIMER1 & EXP_USE_OUT ) |
// ( ( ! GRB_MD_CONT ) & DEF_DIGITIZER_MASTER & GRB_TRG_SIGNAL_TIMER1 )
// ) ? 4 :
// ( (
// ( GRB_ACT_IMMEDIATE & GRB_TRG_SIGNAL_TIMER2 & EXP_USE_OUT ) |
// ( ( ! GRB_MD_CONT ) & DEF_DIGITIZER_MASTER & GRB_TRG_SIGNAL_TIMER2 )
// ) ? 5 :
// 1 ) ) )
// ) * DEF_PSG_ON * DEF_BT254_PATH ;
define_value
DECVS input pin
EXVSYNC
PINVSYNC input pin
TRIGGER input pin
EXP1 ouput pin
EXP2 ouput pin
Reserved
Reserved
//---------------------------------------------
vrstpol regular
Vertical reset polarity control
eo_information
0 1 unsigned flag_overflow
//value = 0 * ( ! DEF_DEC_PATH ) ;
// Invert if Negative Pulse ; RESET at RISING Edge at Start VS OR End Timer for Exposure
value = (
(
( SYC_DIG * SYC_V_INEG ) |
(
GRB_ACT_IMMEDIATE *
(
( GRB_TRG_NEG * DEF_NEW_MODE_ASYNC_WEN_PULSE ) |
(
( ! EXP_USE_OUT ) *
(
( GRB_TRG_SIGNAL_TIMER1 * EXP_MD_VSY * EXP_MD_W_TRG * EXP_TRG_NEG * ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
( GRB_TRG_SIGNAL_TIMER2 * EXP_MD_VSY_2 * EXP_MD_W_TRG_2 * EXP_TRG_NEG_2 * ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
)
) |
(
DEF_DIGITIZER_MASTER * EXP_USE_OUT * ( ! DEF_NEW_MODE_ASYNC_WEN_PULSE ) * ( ! EXP_MD_VSY ) *
( ( GRB_TRG_SIGNAL_TIMER1 * EXP_OUT_POS ) | ( GRB_TRG_SIGNAL_TIMER2 * EXP_OUT_POS_2 ) )
)
)
)
) * DEF_PSG_ON * DEF_BT254_PATH
) ;
//
// New equations for use 1 Timer in Pulse Width and Wen Pulse modes in asynchronous reset.
//value = (
// (
// ( SYC_DIG * SYC_V_INEG ) |
// (
// GRB_ACT_IMMEDIATE *
// (
// (
// GRB_TRG_NEG * ( DEF_NEW_MODE_ASYNC_ONE_TIMER | DEF_NEW_MODE_ASYNC_WEN_PULSE )
// ) |
// (
// ( ! EXP_USE_OUT ) *
// (
// ( GRB_TRG_SIGNAL_TIMER1 * EXP_MD_VSY * EXP_MD_W_TRG * EXP_TRG_NEG * ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
// ( GRB_TRG_SIGNAL_TIMER2 * EXP_MD_VSY_2 * EXP_MD_W_TRG_2 * EXP_TRG_NEG_2 * ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
// )
// )
// )
// )
// ) * DEF_PSG_ON * DEF_BT254_PATH
// ) ;
//
define_value
No polarity inversion
The selected signal is inverted
//---------------------------------------------
vrsten regular
Vertical reset enable
eo_information
0 1 unsigned flag_overflow
// ALWAYS ENABLED !
value = ( DEF_PSG_ON * DEF_BT254_PATH ) ;
//
//value = 1 * ( ( DEF_DIGITIZER_MASTER * ( GRB_TRG_SIGNAL_TIMER1 | GRB_TRG_SIGNAL_TIMER2 ) ) |
// ( ! DEF_DIGITIZER_MASTER )
// ) * DEF_PSG_ON * DEF_BT254_PATH ;
define_value
Vertical reset disable
Vertical reset enable
//---------------------------------------------
vrsbysyn regular
Vertical reset bypass synchronization
eo_information
0 1 unsigned flag_overflow
value = ( PCK_CAM_GEN * SYC_DIG ) * ( ! DEF_DEC_PATH ) ;
//value = 0 * ( ! DEF_DEC_PATH ) ;
define_value
Resynchronization
No resynchronization
//---------------------------------------------
vrstpval regular
Vertical reset pval output signal
eo_information
0 1 unsigned flag_overflow
value = ( ! ( GRB_MD_CONT ) ) * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
reserved2 protected
eo_information
0 1 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG OUTCTL Register
// -----------------------------------
//==============================================
PSG_OUTCTL
Output control
eo_information
12
//---------------------------------------------
pllfbpol regular
Pll feadback output polarity control
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
define_value
Active high
Active low
//---------------------------------------------
clamppol regular
Clamping output polarity control
eo_information
0 1 unsigned flag_overflow
//value = 0 * ( ! DEF_DEC_PATH ) ;
value = ( VDC_DIG ? 1 :
0 ) ;
define_value
Active high
Active low
//---------------------------------------------
pvalpol regular
Pixel valid output polarity control
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
define_value
Active high
Active low
//---------------------------------------------
// Fieldpol value is function of the number of equalization pulse
// during the vertical front porch leading the odd field ( by convention,
// odd field contains the first complete line of and interlaced frame) .
// If VDT_VFPORCH is even, fieldpol = '1' .
// If VDT_VFPORCH is odd, fieldpol = '0' . <-- Sony xc711p
fieldpol regular
Field output polarity control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
//value = (
// DEF_DEC_PATH ? 0 :
// ( ( DEF_BT254_PATH & ( ! ( VDT_HSYNC % 2 ) ) & ( VDT_VBPORCH % 2 ) ) ? 1 :
// ( ( DEF_BT254_PATH & ( ! ( VDT_HSYNC % 2 ) ) & ( ! ( VDT_VBPORCH % 2 ) ) ) ? 0 :
// ( ( DEF_BT254_PATH & ( VDT_HSYNC % 2 ) & ( VDT_VBPORCH % 2 ) ) ? 1 :
// ( ( DEF_BT254_PATH & ( VDT_HSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) ) ? 0 :
// 0 ) ) ) )
// ) ;
//
// ( ( DEF_BT254_PATH & ( ! VDC_RGB_COL ) & ( ! DEF_DIGITIZER_MASTER ) & ( VDT_HSYNC % 2 ) & ( VDT_VBPORCH % 2 ) ) ? 0 :
// ( ( DEF_BT254_PATH & ( ! VDC_RGB_COL ) & ( ! DEF_DIGITIZER_MASTER ) & ( VDT_HSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) ) ? 1 :
// ( ( DEF_BT254_PATH & ( VDC_RGB_COL | ( DEF_DIGITIZER_MASTER & DEF_MONO_VIA_RGB ) ) & ( VDT_HSYNC % 2 ) & ( VDT_VBPORCH % 2 ) ) ? 1 :
// ( ( DEF_BT254_PATH & ( VDC_RGB_COL | ( DEF_DIGITIZER_MASTER & DEF_MONO_VIA_RGB ) ) & ( VDT_HSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) ) ? 0 :
//value = (
// DEF_DEC_PATH ? 0 :
// ( ( DEF_BT254_PATH & ( ! DEF_50HZ_HV_TOTAL_STD ) & ( ! ( VDT_HSYNC % 2 ) ) & ( VDT_VBPORCH % 2 ) & ( ! VDC_RGB_COL ) ) ? 1 :
// ( ( DEF_BT254_PATH & ( ! ( VDT_HSYNC % 2 ) ) & ( ! ( VDT_VBPORCH % 2 ) ) ) ? 0 :
// ( ( DEF_BT254_PATH & VDC_ANA & ( ! DEF_50HZ_HV_TOTAL_STD ) & ( VDT_HSYNC % 2 ) & ( VDT_VBPORCH % 2 ) ) ? 1 :
// ( ( DEF_BT254_PATH & VDC_ANA & ( VDT_HSYNC % 2 ) & ( ! ( VDT_VBPORCH % 2 ) ) ) ? 0 :
// 0 ) ) ) )
// ) ;
//
define_value
Active high
Active low
//---------------------------------------------
hsyncpol regular
Horizontal sync output polarity control
eo_information
0 1 unsigned flag_overflow
value = (
( ( SYC_H_OUT & SYC_H_ONEG ) | ( SYC_DIG & SYC_H_IN & SYC_H_INEG ) | ( SYC_ANA & ( ! SYC_H_OUT ) )
) ? 1 : 0
) ;
//
//value = (
// ( ( SYC_H_OUT & SYC_H_ONEG ) | ( SYC_H_IN & SYC_H_INEG ) | SYC_ANA ) ? 1 : 0
// ) ;
//value = (
// ( ( SYC_H_OUT & SYC_H_ONEG ) | ( SYC_H_IN & SYC_H_INEG ) |
// ( VDC_RGB_COL & VDT_INTERL & ( DEF_60HZ_HV_TOTAL_STD | DEF_50HZ_HV_TOTAL_STD ) )
// ) ? 1 : 0
// ) ;
define_value
Active high
Active low
//---------------------------------------------
vsyncpol regular
Vertical sync output polarity control
eo_information
0 1 unsigned flag_overflow
value = (
( ( SYC_V_OUT & SYC_V_ONEG ) | ( SYC_DIG & SYC_V_IN & SYC_V_INEG ) ) ? 1 : 0
) ;
//value = (
// ( ( SYC_ANA & SYC_V_OUT & SYC_V_ONEG ) | ( SYC_DIG & SYC_V_IN & SYC_V_INEG )
// ) ? 1 : 0
// ) ;
define_value
Active high
Active low
//---------------------------------------------
ngcsypol regular
Noise gate csync output polarity control
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
define_value
Active high
Active low
//---------------------------------------------
reserved1 protected
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
fieldsel regular
Field output source select
eo_information
0 1 unsigned flag_overflow
value = (
DEF_DEC_PATH ? 0 :
( DEF_BT254_PATH ? 1 :
0 )
) ;
define_value
DECFIELD input pin
FIELD signal (field detection logic)
//---------------------------------------------
fldctl regular
Field control
eo_information
0 2 unsigned flag_overflow
value = 1 * ( ! DEF_DEC_PATH ) * ( SYC_CAM_GEN | ( ! SYC_CAM_GEN * VDT_NINTRL ) ) ;
//value = 1 * ( ! DEF_DEC_PATH ) * SYC_CAM_GEN ;
no_define_value
//---------------------------------------------
trgsel regular
Trigger selection
eo_information
0 1 unsigned flag_overflow
value = ( EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 | GRB_TRG_SIGNAL_DPORT ? 0 : 1 ) ;
//value = ( ( ( DEF_TIMER1_ENABLE & GRB_MD_CONT & EXP_TRG_TTL_TIMER1 ) |
// ( DEF_TIMER2_ENABLE & GRB_MD_CONT & EXP_TRG_TTL_TIMER2 ) |
// ( ( ! ( GRB_MD_CONT ) ) & ( GRB_TRG_SIGNAL_DPORT | EXP_TRG_TTL_TIMER1 | EXP_TRG_TTL_TIMER2 ) ) ) ? 0 : 1
// ) ;
// TRIGGER1 = TTL
// TRIGGER2 = OPTO COUPLER
define_value
TRIGGER1
TRIGGER2
//---------------------------------------------
reserved2 protected
eo_information
0 4 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG CPTCTL Register
// -----------------------------------
//==============================================
PSG_CPTCTL
Capture control
eo_information
4
//---------------------------------------------
captpol regular
Capture polarity control
// Inverse en Trigger Mode Single Shot
eo_information
0 1 unsigned flag_overflow
// Add condition WEN Pulse where Pol controlled by Timer's polarity OUTPUT
// Timer1 always used for WEN Pulse if both timers use Trigger (OPTO or TTL)
//
value = (
( ! GRB_MD_CONT ) *
(
( GRB_TRG_NEG *
( ! ( GRB_TRG_SIGNAL_APORT | GRB_TRG_SIGNAL_TIMER1_WEN | GRB_TRG_SIGNAL_TIMER2_WEN ) )
) |
( GRB_TRG_POS * GRB_TRG_SIGNAL_APORT ) |
(
( EXP_OUT_POS * GRB_TRG_SIGNAL_TIMER1_WEN ) |
( EXP_OUT_POS_2 * GRB_TRG_SIGNAL_TIMER2_WEN )
)
)
) ;
//
define_value
Selected capture signal not inverted
Selected capture is inverted
//---------------------------------------------
captsel regular
Capture source selection
eo_information
0 3 unsigned flag_overflow
// Timer1 always used for WEN Pulse if both timers use Trigger (OPTO or TTL)
value = (
( ( ! ( GRB_MD_CONT ) ) & ( GRB_TRG_SIGNAL_APORT | GRB_TRG_SIGNAL_DPORT ) ) ? 1 :
( ( GRB_TRG_SIGNAL_TIMER1 | GRB_TRG_SIGNAL_TIMER1_WEN ) ? 2 :
( ( GRB_TRG_SIGNAL_TIMER2 | GRB_TRG_SIGNAL_TIMER2_WEN ) ? 3 :
( GRB_MD_SW_TRG ? 5 :
0 ) ) )
) ;
//
//value = ( ( ( ! ( GRB_MD_CONT ) ) & ( GRB_TRG_SIGNAL_APORT | GRB_TRG_SIGNAL_DPORT ) ) ? 1 :
// ( GRB_TRG_SIGNAL_TIMER1 ? 2 :
// ( GRB_TRG_SIGNAL_TIMER2 ? 3 :
// ( GRB_MD_SW_TRG ? 5 :
// 0 ) ) )
// ) ;
//value = ( ( GRB_MD_HW_TRG & GRB_ACT_NXT_FRM ) ? 1 :
// ( GRB_TRG_SIGNAL_TIMER1 ? 2 :
// ( GRB_TRG_SIGNAL_TIMER2 ? 3 :
// ( GRB_MD_SW_TRG ? 5 :
// 0 ) ) )
// ) ;
define_value
FVAL signal
TRIGGER input pin
EXP1 output pin
EXP2 output pin
PINCAPT input pin
CAPTSOFT
Reserved
Reserved
//---------------------------------------------
captsoft regular
Capture output pin controlled by software
eo_information
0 1 unsigned flag_overflow
value = 0 ;
no_define_value
//---------------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG SRSCTL Register
// -----------------------------------
//==============================================
PSG_SRSCTL
Signal reset control
eo_information
9
//---------------------------------------------
hsyncrst regular
Horizontal sync output reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
vsyncrst regular
Vertical sync output reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
pllfbrst regular
Pll feadback output reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
pvalrst regular
Pval output signal reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
clamrst regular
Clamp output signal reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
reserved1 protected
eo_information
0 3 unsigned flag_overflow
no_define_value
//---------------------------------------------
vcntrst regular
Vertical counter software reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
hcntrst regular
Horizontal counter software reset control
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
No effect
Reset
//---------------------------------------------
reserved2 protected
eo_information
0 6 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG PSGCFG1 Register
// -----------------------------------
//==============================================
PSG_PSGCFG1
PSG configuration register #1
eo_information
5
//---------------------------------------------
intrlace regular
Interlace video selection
eo_information
0 1 unsigned flag_overflow
value = VDT_INTERL * ( ! DEF_DEC_PATH );
define_value
Non-interlaced
Interlaced
//---------------------------------------------
reserved1 protected
eo_information
0 2 unsigned flag_overflow
no_define_value
//---------------------------------------------
frmscan regular
Frame scan mode
eo_information
0 1 unsigned flag_overflow
value = ( DEF_NEW_MODE_ASYNC_WEN_PULSE | ( EXP_USE_OUT * GRB_ACT_IMMEDIATE * VDT_NINTRL ) ) ;
//
//value = DEF_NEW_MODE_ASYNC_WEN_PULSE ;
define_value
No effect
Stop vcnt=vtotal
//---------------------------------------------
pclktest regular
Pixel clock test
eo_information
0 1 unsigned flag_overflow
define_value
No effect
PIXCLK test mode
//---------------------------------------------
reserved2 protected
eo_information
0 3 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG PSGCFG2 Register
// -----------------------------------
//==============================================
PSG_PSGCFG2
PSG configuration register #2
eo_information
9
//---------------------------------------------
psgtrmd regular
PSG trigger mode
eo_information
0 1 unsigned flag_overflow
value = 0 ; // <<<<<<<<<<<<<<<<<<Revoir
define_value
Trigger mode is on
Trigger mode is off
//---------------------------------------------
halffrm regular
Half frame
eo_information
0 1 unsigned flag_overflow
value = 0 ; // <<<<<<<<<<<<<<<<<<Revoir
define_value
1 entire frame
1 field only
//---------------------------------------------
pfldsel regular
PSG field selection
eo_information
0 2 unsigned flag_overflow
value = 0 ; // <<<<<<<<<<<<<<<<<<Revoir
define_value
First complete field
Reserved
Even field
// <<<<<<<<<<<<<<<<<<Revoir
Odd field
// <<<<<<<<<<<<<<<<<<Revoir
//---------------------------------------------
ptrgpol regular
PSG trigger polarity control
eo_information
0 1 unsigned flag_overflow
value = 0 ; // <<<<<<<<<<<<<<<<<<Revoir
define_value
Not inverted
Inverted
//---------------------------------------------
trgbysyn regular
Trigger bypass synchronization
eo_information
0 1 unsigned flag_overflow
value = 0 ; // <<<<<<<<<<<<<<<<<<Revoir
define_value
Synchronization
No synchronization
//---------------------------------------------
psoftrg regular
PSG software trigger control
eo_information
0 1 unsigned flag_overflow
define_value
PSG software trigger low
PSG software trigger high
//---------------------------------------------
prstrgdt regular
PSG reset trigger detection mechanism
eo_information
0 1 unsigned flag_overflow
define_value
No effect
Reset PSG triger detection
//---------------------------------------------
ptrgsl regular
PSG trigger selection
eo_information
0 3 unsigned flag_overflow
value = 0 ; // <<<<<<<<<<<<<<<<<<Revoir
define_value
PSGHSYNC output pin
PSGVSYNC output pin
TRIGGER input pin
EXP1 output pin
EXP2 output pin
PSOFTRG
Trigger tied to '0'
Reserved
//---------------------------------------------
reserved protected
Reserved Register
eo_information
0 5 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG ECSNGT Register
// -----------------------------------
//==============================================
PSG_ECSNGT
End csync noise gate
eo_information
1
0 8 unsigned flag_overflow
// ( HT - HS/2 - 3 x PCLK/SYS_NGCLK )
//
// ECSNGT = QTE Pixels Clk
// Enleve VDT_INTERL pour permettre Grab 1 Field en mode Non Entrelace
//value = ( ( DEF_BT254_PATH & VDC_ANA & ( DEF_SYSCLK_SEL == 3 ) ) ?
// ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 1562500 ) ) ) / ( PCK_FREQ / 1562500 ) ) :
// ( ( DEF_BT254_PATH & VDC_ANA & ( DEF_SYSCLK_SEL == 2 ) ) ?
// ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 3125000 ) ) ) / ( PCK_FREQ / 3125000 ) ) :
// ( ( DEF_BT254_PATH & VDC_ANA & ( DEF_SYSCLK_SEL == 1 ) ) ?
// ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 6250000 ) ) ) / ( PCK_FREQ / 6250000 ) ) :
// ( ( DEF_BT254_PATH & VDC_ANA & ( DEF_SYSCLK_SEL == 0 ) ) ?
// ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 12500000 ) ) ) / ( PCK_FREQ / 12500000 ) ) :
// 0 ) ) )
// ) * SYC_ANA ;
//
value = ( ( DEF_BT254_PATH & SYC_ANA & ( DEF_SYSCLK_SEL == 3 ) ) ?
( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 1562500 ) ) ) / ( PCK_FREQ / 1562500 ) ) :
( ( DEF_BT254_PATH & SYC_ANA & ( DEF_SYSCLK_SEL == 2 ) ) ?
( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 3125000 ) ) ) / ( PCK_FREQ / 3125000 ) ) :
( ( DEF_BT254_PATH & SYC_ANA & ( DEF_SYSCLK_SEL == 1 ) ) ?
( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 6250000 ) ) ) / ( PCK_FREQ / 6250000 ) ) :
( ( DEF_BT254_PATH & SYC_ANA & ( DEF_SYSCLK_SEL == 0 ) ) ?
( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 12500000 ) ) ) / ( PCK_FREQ / 12500000 ) ) :
0 ) ) )
) ;
no_define_value
// -----------------------------------
// PSG NGCTL Register
// -----------------------------------
//==============================================
PSG_NGCTL
Noise gating control
eo_information
6
//---------------------------------------------
csynsel regular
Csync input selection
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
define_value
SSCSYNC input pin
PINHSYNC input pin
//---------------------------------------------
sscspol regular
Sscsync signal polarity control
eo_information
0 1 unsigned flag_overflow
value = 1 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
pinhspol regular
Pinhsync signal polarity control
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
ngpsclr regular
Noise gating prescaler selection
eo_information
0 2 unsigned flag_overflow
// ECSNGT = QTE Pixels Clk
value = ( DEF_SYSCLK_SEL * DEF_BT254_PATH ) ;
//value = ( ( ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 1562500 ) ) ) * ( PCK_FREQ >= 1562500 ) ) > ( ( VDT_HTOTAL / 2 ) + VDT_HSYNC ) )
// & ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 1562500 ) ) ) < ( VDT_HTOTAL * ( PCK_FREQ >= 1562500 ) ) ) ? 3 :
// ( ( ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 3125000 ) ) ) * ( PCK_FREQ >= 3125000 ) ) > ( ( VDT_HTOTAL / 2 ) + VDT_HSYNC ) )
// & ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 3125000 ) ) ) < ( VDT_HTOTAL * ( PCK_FREQ >= 3125000 ) ) ) ? 2 :
// ( ( ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 6250000 ) ) ) * ( PCK_FREQ >= 6250000 ) ) > ( ( VDT_HTOTAL / 2 ) + VDT_HSYNC ) )
// & ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 6250000 ) ) ) < ( VDT_HTOTAL * ( PCK_FREQ >= 6250000 ) ) ) ? 1 :
// ( ( ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 12500000 ) ) ) * ( PCK_FREQ >= 12500000 ) ) > ( ( VDT_HTOTAL / 2 ) + VDT_HSYNC ) )
// & ( ( VDT_HTOTAL - ( VDT_HSYNC / 2 ) - ( 3 * ( PCK_FREQ / 12500000 ) ) ) < ( VDT_HTOTAL * ( PCK_FREQ >= 6250000 ) ) ) ? 0 :
// 3 ) ) ) ) * ( ! DEF_DEC_PATH ) * ( SYC_ANA ) ;
define_value
12.5 Mhz
6.25 Mhz
3.125 Mhz
1.5625 Mhz
//---------------------------------------------
reserved protected
eo_information
0 2 unsigned flag_overflow
no_define_value
//---------------------------------------------
pfdenmd regular
eo_information
0 1 unsigned flag_overflow
value = SYC_BLK ;
define_value
PFDEN Always HIGH
PFDEN = EXVSYNC
// -----------------------------------
// PSG DTCVSR Register
// -----------------------------------
//==============================================
PSG_DTCVSR
Detection vsync sample
eo_information
1
0 32 unsigned flag_overflow
// PSG_DTCVSR = HS + ( 85% * HBPORCH ) + 1.92 uS 1.92 uS => 3CKS 1.5625Mhz | 6CKS 3.125Mhz etc
value = (
(
(
( ( ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 2 ) * ( ( VDT_HSYNC + DEF_0,15_HBPORCH - 2 ) >= 0 ) ) * SYC_ANA ) +
( SYC_DIG * (
( ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 4 )
* ( ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 4 ) >= 0 ) * ( ! DEF_DIGITIZER_MASTER ) ) +
( DEF_DIGITIZER_MASTER * ( VDT_HSYNC + VDT_HBPORCH - DEF_0,15_HBPORCH - 4 ) )
)
)
) / ( PCK_FREQ / ( 1562500 * DEF_SYSCLK156MZ_MULT ) )
) + ( 3 * DEF_SYSCLK156MZ_MULT )
) * VDC_ANA * SYC_ANA * DEF_PSG_ON * DEF_BT254_PATH ;
//
no_define_value
// -----------------------------------
// PSG EXTCTL1 Register
// -----------------------------------
//==============================================
PSG_EXTCTL1
External control register #1
eo_information
11
// -----------------------------------
// The following field controls the selection
// of the PLL external reference input.
// Case 0 : When a digital HSYNC is supplied, but no pixel clock,
// it should be used as a reference to the PLL in order
// to regenerate the missing synchronized pixel clock.
// Case 1 : The digital pixel clock should not source the PLL's
// external reference unless a different frequency is required
// which must be synchronized to the digital pixel clock input.
// Case 2 : For line-locking to a composite sync signal (CSYNC), either
// digital or analog, the Noise Gated Composite SYNC signal
// should be selected as the PLL's external reference.
// Case 3 : The 25 Mhz system clock is used as a stable reference
// for arbitrary frequency generation when CORONA is used
// as a SYNC generator.
//
// At the moment, case 1 and 3 are not supported. And, case 0 has
// precedence over case 2.
//
//---------------------------------------------
pllsrc regular
Pll source
eo_information
0 2 unsigned flag_overflow
//value = (
// DEF_PLL_ON *
// (
// SYC_H_IN ? 0 :
// ( ( ~ SYC_H_IN ) ? 2 :
// 0 )
// )
// ) ;
value = ( DEF_PCK_NO_EXCHANGE & SYC_CAM_GEN & SYC_DIG & SYC_H_IN ? 0 :
( ( PCK_CAM_GEN & ( ! ( PCK_CAM_R&G ) ) ) ? 1 :
( ( ( ! ( PCK_CAM_XCHG ) ) & SYC_CAM_GEN & VDC_ANA & DEF_PSG_ON ) ? 2 :
( DEF_DIGITIZER_MASTER ? 3 :
2 ) ) )
) ;
//value = ( PCK_CAM_XCHG & SYC_H_IN ? 0 :
// ( ( PCK_CAM_GEN & ( ! ( PCK_CAM_R&G ) ) ) ? 1 :
// ( ( ( ! ( PCK_CAM_XCHG ) ) & SYC_CAM_GEN & VDC_ANA & DEF_PSG_ON ) ? 2 :
// ( ( PCK_CAM_R&G | PCK_CAM_REC | ( ! ( SYC_CAM_GEN ) ) ) ? 3 :
// 2 ) ) )
// ) ;
define_value
Digital hsync input
Digital pixel clock input
Noise gated composite sync
System clock
//---------------------------------------------
// Pixel clock source selection
clksrc regular
Clock source
eo_information
0 2 unsigned flag_overflow
value = (
( PCK_CAM_GEN | VDC_DIG ) ? 0 :
( DEF_DEC_PATH ? 2 :
1 )
) ;
define_value
Digital pixel clock input
PLL's clock output
Decoder clock output
Reserved
//---------------------------------------------
// The HSYNC & VSYNC signals are used to synchronize together all the
// acquisition devices on a line and field basis, respectively.
syncsrc regular
Synchronization source
eo_information
0 2 unsigned flag_overflow
value = (
( SYC_H_IN & SYC_V_IN ) ? 0 :
( ( DEF_BT254_PATH & ( ( ! SYC_H_IN ) | ( ! SYC_V_IN ) ) ) ? 1 :
( DEF_DEC_PATH ? 2 :
0 ) )
) ;
define_value
Digital HSYNC & VSYNC inputs
PSG's HSYNC & VSYNC outputs
Decoder's HSYNC & VSYNC outputs
Reserved
//---------------------------------------------
valsel regular
Valid signal selection
eo_information
0 2 unsigned flag_overflow
value = (
( DEF_PSG_ON & DEF_BT254_PATH ) ? 0 :
( DEF_DEC_PATH ? 1 :
0 )
) ;
define_value
PSG's pixel valid output
Decoder's pixel valid output (HAV)
Digital pixel valid input
Reserved
//---------------------------------------------
ckoutsel regular
Clock output selection
eo_information
0 1 unsigned flag_overflow
value = ( PCK_CAM_GEN * ( ! PCK_CAM_R&G ) ) ;
//
//value = 0 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
// VIA DISPLAY INTERFACE CONTROL !
decdsrc regular
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
rgb_decn regular
RGB/DECODER selection
eo_information
0 1 unsigned flag_overflow
value = (
DEF_BT254_PATH ? 1 :
( DEF_DEC_PATH ? 0 :
0 )
) ;
no_define_value
//---------------------------------------------
dhspol regular
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
dvspol regular
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
dsyncltc regular
eo_information
0 1 unsigned flag_overflow
value = 0 * ( ! DEF_DEC_PATH ) ;
no_define_value
//---------------------------------------------
syncsel regular
eo_information
0 2 unsigned flag_overflow
value = (
DEF_RGB_SYNC_ANA_ON_R ? 0 :
( DEF_RGB_SYNC_ANA_ON_G ? 1 :
( DEF_RGB_SYNC_ANA_ON_B ? 2 :
( DEF_RGB_SYNC_ANA_SEP ? 3 :
0 ) ) )
) * ( ! DEF_DEC_PATH ) ;
define_value
0 : Sync on RED
1 : Sync on GREEN
2 : Sync on BLUE
3 : Separated sync
// -----------------------------------
// PSG EXTCTL2 Register
// -----------------------------------
//==============================================
PSG_EXTCTL2
External control register #2
eo_information
8
//
// When "asyncdir = 0", the VIDEO INPUT CONNECTOR SYNC pins
// are in input mode.
// When "asyncdir = 1", the PSG SYNC (PSGHSYNC and
// PSGVSYNC) are outputed on the VIDEO INPUT CONNECTOR SYNC pins.
//---------------------------------------------
asyncdir regular
eo_information
0 1 unsigned flag_overflow
value = (
( ( SYC_H_OUT & SYC_H_OTTL ) | ( SYC_V_OUT & SYC_V_OTTL ) ) ? 1 : 0
) ;
//
//value = (
// ( ( SYC_H_OUT | SYC_V_OUT ) & ( SYC_H_OTTL | SYC_V_OTTL | SYC_H_ITTL | SYC_V_ITTL ) ) ? 1 :
// ( ( SYC_H_IN | SYC_V_IN ) ? 0 :
// 0 )
// ) ;
//no_define_value
define_value
Synchronisation : Input mode
Synchronisation : Output mode
// 0 = INPUT
// 1 = OUTPUT
//---------------------------------------------
asyncen regular
eo_information
0 1 unsigned flag_overflow
// Asynchronous reset with WEN Pulse enable Sync buffer ( Old & New method )
value = ( VDC_ANA *
(
(
PCK_CAM_GEN * ( ! ( SYC_H_OUT & SYC_H_OTTL ) ) * ( ! ( SYC_V_OUT & SYC_V_OTTL ) )
) |
(
( SYC_H_OUT | SYC_V_OUT | SYC_H_IN | SYC_V_IN ) *
( SYC_H_OTTL | SYC_V_OTTL | SYC_H_ITTL | SYC_V_ITTL )
) |
( SYC_ANA * GRB_ACT_IMMEDIATE * DEF_NEW_MODE_ASYNC_WEN_PULSE ) |
(
GRB_ACT_IMMEDIATE * SYC_ANA * ( ! EXP_USE_OUT ) *
(
( GRB_TRG_SIGNAL_TIMER1 * EXP_MD_VSY * EXP_MD_W_TRG * ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
( GRB_TRG_SIGNAL_TIMER2 * EXP_MD_VSY_2 * EXP_MD_W_TRG_2 * ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
)
)
)
) ;
//
//value = ( VDC_ANA *
// (
// (
// ( SYC_H_OUT | SYC_V_OUT | SYC_H_IN | SYC_V_IN ) *
// ( SYC_H_OTTL | SYC_V_OTTL | SYC_H_ITTL | SYC_V_ITTL )
// ) |
// ( SYC_ANA * GRB_ACT_IMMEDIATE * DEF_NEW_MODE_ASYNC_WEN_PULSE ) |
// (
// GRB_ACT_IMMEDIATE * SYC_ANA * ( ! EXP_USE_OUT ) *
// (
// ( GRB_TRG_SIGNAL_TIMER1 * EXP_MD_VSY * EXP_MD_W_TRG * ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
// ( GRB_TRG_SIGNAL_TIMER2 * EXP_MD_VSY_2 * EXP_MD_W_TRG_2 * ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
// )
// )
// )
// ) ;
//value = ( VDC_ANA *
// ( ( ( SYC_H_OUT | SYC_V_OUT | SYC_H_IN | SYC_V_IN ) * ( SYC_H_OTTL | SYC_V_OTTL | SYC_H_ITTL | SYC_V_ITTL ) )
// | ( PCK_USE_OUT & PCK_OTTL )
// )
// ) ;
//value = VDC_ANA * DEF_BT254_PATH * DEF_PSG_ON ;
define_value
Analog port SYNC pins disable
Analog port SYNC pins enable
//---------------------------------------------
// At this moment, the GRAB PORT is used
// only in input mode
grabdir regular
eo_information
0 1 unsigned flag_overflow
//value = 0 * ( ! DEF_DEC_PATH ) ;
value = (
( SYC_H_OUT * SYC_H_O422 ) | ( SYC_V_OUT * SYC_V_O422 )
) ;
//
//value = (
// ( ( SYC_H_OUT | SYC_V_OUT ) & ( SYC_H_O422 | SYC_V_O422 ) ) ? 1 :
// ( ( ( SYC_H_IN | SYC_V_IN ) & ( SYC_H_I422 | SYC_V_I422 ) ) ? 0 :
// 0 )
// ) ;
//value = (
// ( ( SYC_H_OUT | SYC_V_OUT ) & ( SYC_H_O422 | SYC_V_O422 | SYC_H_I422 | SYC_V_I422 ) ) ? 1 :
// ( ( SYC_H_IN | SYC_V_IN ) ? 0 :
// 0 )
// ) ;
define_value
Grab port - input mode
Grab port - output mode
//---------------------------------------------
grbprten regular
eo_information
0 1 unsigned flag_overflow
value = (
( ( SYC_H_OUT | SYC_V_OUT | SYC_H_IN | SYC_V_IN ) *
( SYC_H_O422 | SYC_V_O422 | SYC_H_I422 | SYC_V_I422 )
) | PCK_O422 | PCK_I422 | VDC_DIG | ( GRB_TRG_422 & GRB_TRG_SIGNAL_DPORT ) |
EXP_TRG_422 | EXP_OUT_422 | EXP_TRG_422_2 | EXP_OUT_422_2
) ;
//value = ( ( ( SYC_H_OUT | SYC_V_OUT | SYC_H_IN | SYC_V_IN ) * ( SYC_H_O422 | SYC_V_O422 | SYC_H_I422 | SYC_V_I422 ) )
// | ( PCK_USE_OUT & PCK_O422 )
// ) ;
define_value
Grab port disable
Grab port enable
//---------------------------------------------
expen regular
eo_information
0 1 unsigned flag_overflow
value = ( DEF_TIMER1_ENABLE | DEF_TIMER2_ENABLE ) ;
define_value
Exposure Output Disabled
Exposure Output Enabled
//---------------------------------------------
ackouten regular
eo_information
0 1 unsigned flag_overflow
//Enabled when Corona Board with WEN Pulse Configuration apart Pclk output setting.
value = (
( PCK_USE_OUT * ( DEF_CORONA_II | ( DEF_CORONA * DEF_BT254_PATH ) | DEF_METEOR_II_MC ) ) |
( PCK_OTTL * ( ! ( PCK_USE_OUT * PCK_OTH_REC ) ) ) |
(
SYC_ANA * DEF_CORONA * DEF_BT254_PATH *
(
DEF_NEW_MODE_ASYNC_WEN_PULSE |
(
GRB_ACT_IMMEDIATE * SYC_ANA * ( ! EXP_USE_OUT ) *
(
( GRB_TRG_SIGNAL_TIMER1 * EXP_MD_VSY * EXP_MD_W_TRG * ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
( GRB_TRG_SIGNAL_TIMER2 * EXP_MD_VSY_2 * EXP_MD_W_TRG_2 * ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
)
)
)
)
) ;
//
//value = (
// ( PCK_OTTL * ( ! ( PCK_USE_OUT * PCK_OTH_REC ) ) ) |
// (
// SYC_ANA * DEF_CORONA * DEF_BT254_PATH *
// (
// DEF_NEW_MODE_ASYNC_WEN_PULSE |
// (
// GRB_ACT_IMMEDIATE * SYC_ANA * ( ! EXP_USE_OUT ) *
// (
// ( GRB_TRG_SIGNAL_TIMER1 * EXP_MD_VSY * EXP_MD_W_TRG * ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ) |
// ( GRB_TRG_SIGNAL_TIMER2 * EXP_MD_VSY_2 * EXP_MD_W_TRG_2 * ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) )
// )
// )
// )
// )
// ) ;
//value = ( PCK_OTTL * ( PCK_OTH_REC | PCK_CAM_REC | PCK_CAM_R&G ) ) ;
//value = 0 * ( ! DEF_DEC_PATH ) ;
define_value
Analog Port PCLK Disabled
Analog Port PCLK Enabled
//---------------------------------------------
dckouten regular
eo_information
0 1 unsigned flag_overflow
//value = 0 * ( ! DEF_DEC_PATH ) ;
value = ( PCK_O422 * ( PCK_OTH_REC | PCK_CAM_REC | PCK_CAM_R&G ) ) ;
define_value
Digital Port PCLK Disabled
Digital Port PCLK Enabled
//---------------------------------------------
reserved protected
eo_information
0 1 unsigned flag_overflow
no_define_value
//
//
// -----------------------------------
// PSG EXTCTL3 High Register
// -----------------------------------
//==============================================
PSG_EXTCTL3
External control register #3 High
eo_information
3
//---------------------------------------------
clkdel regular
Clock delay
eo_information
0 4 unsigned flag_overflow
value = DEF_PCK_IDLY_SEL ;
//value = ( ( ! DEF_DEC_PATH ) & VDC_DIG & DEF_PSG_ON ? 9 :
// 0 ) ;
define_value
Delay = 9 nS
Delay = 12 nS
Delay = 15 nS
Delay = 18 nS
Delay = 21 nS
Delay = 24 nS
Delay = 27 nS
Delay = 30 nS
Delay = 33 nS
Delay = 36 nS
Delay = 39 nS
Delay = 42 nS
Delay = 45 nS
Delay = 48 nS
Delay = 51 nS
Delay = 54 nS
//---------------------------------------------
gainsel regular
Gain selection
eo_information
0 2 unsigned flag_overflow
// Add gain of 1 on METEORII/MC ONLY !!!! With Bit 4 in SRCCTRL of PSG Gainsel(2)
// Gainsel(2) = 0 => EXTCTL3 Selected Gainsel(2) = 1 => Unity Gain of 1
// when DEF_VIDEO_GAIN = 4000 ( 4000/1000 = 4)
value = ( DEF_VIDEO_GAIN == 1300 ) ? 0 :
( ( DEF_VIDEO_GAIN == 2000 ) ? 1 :
( ( DEF_VIDEO_GAIN == 4000 ) ? 2 :
( ( DEF_VIDEO_GAIN == 2800 ) ? 3 :
0 ) ) ) ;
//value = ( 3 * ( DEF_BT254_PATH ) * DEF_PSG_ON ) ;
define_value
Gain = 1.3
Gain = 2.0
Gain = 4.0
Gain = 2.8
//---------------------------------------------
reserved protected
eo_information
0 2 unsigned flag_overflow
no_define_value
//
// -----------------------------------
// PSG SRCCTRL Register
// -----------------------------------
PSG_SRCCTRL
Source control register
eo_information
6
//---------------------------------------------
vidsel0 regular
Channel 0 Video Selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Video source = Channel 0
Video source = RED_C_OUT
//---------------------------------------------
vidsel1 regular
Channel 1 Video Selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Video source = Channel 1
Video source = RED_C_OUT
//---------------------------------------------
vidsel2 regular
Channel 2 Video Selection
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Video source = Channel 2
Video source = RED_C_OUT
//---------------------------------------------
clkpol regular
External clock polarity selection
eo_information
0 1 unsigned flag_overflow
value = ( PCK_INEG * ( DEF_CORONA_II | DEF_METEOR_II_MC ) ) ;
//
//value = 0 ;
define_value
Not Inverted
Inverted
//---------------------------------------------
gainsel(2) regular
Extra Unity Video Gain
eo_information
0 1 unsigned flag_overflow
value = ( DEF_METEOR_II_MC * ( DEF_VIDEO_GAIN == 1000 ) ) ;
//
//value = ( ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) * ( DEF_VIDEO_GAIN == 1000 ) ) ;
//value = ( OPTION_MC * ( DEF_VIDEO_GAIN == 1000 ) ) ;
define_value
Video Gain = EXTCTRL3
Video Gain = 1
//---------------------------------------------
reserved protected
eo_information
0 3 unsigned flag_overflow
no_define_value
// -----------------------------------
// PSG TIMER #1 Register
// -----------------------------------
//==============================================
PSG_T1SCNT
Timer #1 Set Count
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_EXP_OUT_T0 + DEF_EXP_OUT_T1
) * DEF_TIMER1_ENABLE ;
no_define_value
// -----------------------------------
// PSG TIMER #2 Register
// -----------------------------------
//==============================================
PSG_T2SCNT
Timer #2 Set Count
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_EXP_OUT_T0_2 + DEF_EXP_OUT_T1_2
) * DEF_TIMER2_ENABLE ;
no_define_value
// -----------------------------------
// PSG EXPOSURE #1 Register
// -----------------------------------
//==============================================
PSG_EXP1S
Exposure #1 Start
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_EXP_OUT_T1
) * DEF_TIMER1_ENABLE ;
no_define_value
// -----------------------------------
// PSG EXPOSURE #2 Register
// -----------------------------------
//==============================================
PSG_EXP2S
Exposure #2 Start
eo_information
1
0 16 unsigned flag_overflow
value = (
DEF_EXP_OUT_T1_2
) * DEF_TIMER2_ENABLE ;
no_define_value
// -----------------------------------
// PSG CONTROL TIMER #1 Register
// -----------------------------------
//==============================================
PSG_T1CTL
Timer #1 ConTrol
eo_information
9
//---------------------------------------------
t1clksl regular
Timer #1 Clock Source Select
eo_information
0 3 unsigned flag_overflow
// Hard Trigger Asyn. reset Ext. Exposure PCLK Exposure
value = ( DEF_TIMER1_ENABLE & EXP_SYN_CLK ? 2 :
( DEF_TIMER1_ENABLE & EXP_ASY_CLK ? 0 :
( DEF_TIMER1_ENABLE & SYC_CAM_GEN & EXP_CLOCK_HSYNC & SYC_DIG ? 3 :
( DEF_TIMER1_ENABLE & EXP_CLOCK_HSYNC
& ( ( SYC_ANA & SYC_CAM_GEN ) | ( SYC_DIG & ( ! ( SYC_CAM_GEN ) ) ) ) ? 4 :
( DEF_TIMER1_ENABLE & EXP_CLOCK_TIMER2 ? 5 :
0 ) ) ) )
) ;
define_value
SYSCLK input pin
PCLK input pin
PIXCLK input pin
PINHSYNC input pin
PSGHSYNC input pin
exp2 (not combine)
RESERVED
RESERVED
//---------------------------------------------
t1clkpol regular
Timer #1 Clock Polarity
eo_information
0 1 unsigned flag_overflow
value = ( ( SYC_DIG * SYC_H_INEG ) | SYC_ANA ) * EXP_CLOCK_HSYNC ;
define_value
Selected Clock input NOT Inverted
Selected Clock input Inverted
//---------------------------------------------
t1trgsl regular
Timer #1 Trigger Source Select
eo_information
0 4 unsigned flag_overflow
value = ( EXP_MD_W_TRG & ( EXP_MD_EXT | EXP_TRG_TTL_TIMER1 ) ? 0 :
( EXP_MD_W_TRG & EXP_MD_SW ? 5 :
( EXP_MD_W_TRG & EXP_MD_HSY & SYC_DIG ? 1 :
( EXP_MD_W_TRG & EXP_MD_HSY & SYC_ANA ? 3 :
( EXP_MD_W_TRG & EXP_MD_VSY & ( SYC_DIG | ( SYC_ANA & PCK_USE_OUT & ( ! SYC_V_IN ) ) ) ? 2 :
( EXP_MD_W_TRG & EXP_MD_VSY & SYC_ANA ? 4 :
( EXP_MD_PERD ? 6 :
( EXP_MD_W_TRG & EXP_TRG_SIGNAL_TIMER2 ? 7 :
( EXP_MD_W_TRG & EXP_TRG_USER_BIT_TIMER1 ? 8 :
0 ) ) ) ) ) ) ) )
) ;
define_value
TRIGGER input pin
PINHSYNC input pin
PINVSYNC input pin
PSGHSYNC input pin
PSGVSYNC input pin
Software Trigger (T1SOFTRG)
t1cnteq0 signal
exp2 (not combined)
usr1 input pin
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
//---------------------------------------------
t1trgpol regular
Timer #1 Trigger Input Polarity
eo_information
0 1 unsigned flag_overflow
value = (
( EXP_TRG_NEG * ( ( ! DEF_METEOR_II_MC ) |
( ( ! EXP_TRG_USER_BIT_TIMER1 ) * DEF_METEOR_II_MC )
)
) +
( EXP_TRG_POS * ( EXP_TRG_USER_BIT_TIMER1 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) )
) ;
//
//value = (
// ( EXP_TRG_NEG * ( ( ! ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) |
// ( ( ! EXP_TRG_USER_BIT_TIMER1 ) * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// ) +
// ( EXP_TRG_POS * ( EXP_TRG_USER_BIT_TIMER1 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) )
// ) ;
define_value
Trigger input NOT Inverted
Trigger input Inverted
//---------------------------------------------
t1onesht regular
Timer #1 ONE Shot mode enable
eo_information
0 1 unsigned flag_overflow
value = ( ( ! EXP_MD_PERD ) & ( ! ( EXP_MD_HSY & EXP_CLOCK_HSYNC ) ) ) ;
//value = ( ! ( EXP_MD_PERD ) ) ;
//value = (
// ( ( GRB_MD_HW_TRG & GRB_ACT_IMMEDIATE & ( ! ( EXP_TRG_SIGNAL_2_TIMER1 ) ) ) |
// ( GRB_MD_HW_TRG & GRB_ACT_IMMEDIATE & EXP_TRG_SIGNAL_2_TIMER1 ) ) ? 1 : 0
// ) * DEF_BT254_PATH ;
define_value
Counter #1 is in continuous mode
Counter #1 is in monoshot mode
//---------------------------------------------
t1tsclr regular
Timer #1 Trigger Scaler Selection
eo_information
0 2 unsigned flag_overflow
value = ( DEF_TIMER1_ENABLE & EXP_PRESCALE1_2 ? 1 :
( DEF_TIMER1_ENABLE & EXP_PRESCALE1_4 ? 2 :
( DEF_TIMER1_ENABLE & EXP_PRESCALE1_8 ? 3 :
0 ) )
) ;
//value = ( DEF_TIMER1_ENABLE & EXP_PRESCALE1_2 ? 0 :
// ( DEF_TIMER1_ENABLE & EXP_PRESCALE1_4 ? 1 :
// ( DEF_TIMER1_ENABLE & EXP_PRESCALE1_8 ? 2 :
// ( DEF_TIMER1_ENABLE & EXP_PRESCALE1_16 ? 3 :
// 0 ) ) )
// ) ;
define_value
1 trigger every 1 is captured
1 trigger every 2 is captured
1 trigger every 4 is captured
1 trigger every 8 is captured
//---------------------------------------------
t1tpsclr regular
Timer #1 Trigger PreScaler
eo_information
0 1 unsigned flag_overflow
value = ( DEF_TIMER1_ENABLE & ( EXP_PRESCALE1_2 | EXP_PRESCALE1_4 | EXP_PRESCALE1_8 ) ? 1 :
0
) ;
//
// All Prescaler 1-16 = 0 in Intellicam
//value = ( DEF_TIMER1_ENABLE & ( ! ( EXP_PRESCALE1_1 ) ) ? 1 :
// 0
// ) ;
define_value
The timer trigger is not pre_scaled
PreScaled Via T1TRGSL & T1TSCLR
//---------------------------------------------
t1cmbn regular
Timer #1 Combine selection
eo_information
0 2 unsigned flag_overflow
value = ( DEF_TIMER1_ENABLE & EXP_COMBINE_XOR ? 1 :
( DEF_TIMER1_ENABLE & EXP_COMBINE_AND ? 2 :
( DEF_TIMER1_ENABLE & EXP_COMBINE_OR ? 3 :
0 ) )
) ;
define_value
EXP1 = T1 Exposure
EXP1 = T1 Exposure XORED T2 Exposure
EXP1 = T1 Exposure ANDED T2 Exposure
EXP1 = T1 Exposure ORED T2 Exposure
//---------------------------------------------
t1pol regular
Timer #1 Output Polarity
eo_information
0 1 unsigned flag_overflow
value = EXP_OUT_NEG ;
define_value
Active High
Active Low
// -----------------------------------
// PSG CONTROL TIMER #2 Register
// -----------------------------------
//==============================================
PSG_T2CTL
Timer #2 ConTrol
eo_information
9
//---------------------------------------------
t2clksl regular
Timer #2 Clock Source Select
eo_information
0 3 unsigned flag_overflow
value = ( DEF_TIMER2_ENABLE & EXP_SYN_CLK_2 ? 2 :
( DEF_TIMER2_ENABLE & EXP_ASY_CLK_2 ? 0 :
( DEF_TIMER2_ENABLE & SYC_CAM_GEN & EXP_CLOCK_2_HSYNC & SYC_DIG ? 3 :
( DEF_TIMER2_ENABLE & EXP_CLOCK_2_HSYNC
& ( ( SYC_ANA & SYC_CAM_GEN ) | ( SYC_DIG & ( ! ( SYC_CAM_GEN ) ) ) ) ? 4 :
( DEF_TIMER2_ENABLE & EXP_CLOCK_2_TIMER1 ? 5 :
0 ) ) ) )
) ;
define_value
SYSCLK input pin
PCLK input pin
PIXCLK input pin
PINHSYNC input pin
PSGHSYNC input pin
exp1 (not combine)
RESERVED
RESERVED
//---------------------------------------------
t2clkpol regular
Timer #2 Clock Polarity
eo_information
0 1 unsigned flag_overflow
value = ( ( SYC_DIG * SYC_H_INEG ) | SYC_ANA ) * EXP_CLOCK_2_HSYNC ;
define_value
Selected Clock input NOT Inverted
Selected Clock input Inverted
//---------------------------------------------
t2trgsl regular
Timer #2 Trigger Source Select
eo_information
0 4 unsigned flag_overflow
value = ( EXP_MD_W_TRG & ( EXP_MD_EXT_2 | EXP_TRG_TTL_TIMER2 ) ? 0 :
( EXP_MD_W_TRG_2 & EXP_MD_SW_2 ? 5 :
( EXP_MD_W_TRG_2 & EXP_MD_HSY_2 & SYC_DIG ? 1 :
( EXP_MD_W_TRG_2 & EXP_MD_HSY_2 & SYC_ANA ? 3 :
( EXP_MD_W_TRG_2 & EXP_MD_VSY_2 & ( SYC_DIG | ( SYC_ANA & PCK_USE_OUT & ( ! SYC_V_IN ) ) ) ? 2 :
( EXP_MD_W_TRG_2 & EXP_MD_VSY_2 & SYC_ANA ? 4 :
( EXP_MD_PERD_2 ? 6 :
( EXP_MD_W_TRG_2 & EXP_TRG_SIGNAL_2_TIMER1 ? 7 :
( EXP_MD_W_TRG_2 & EXP_TRG_USER_BIT_TIMER2 ? 8 :
0 ) ) ) ) ) ) ) )
) ;
define_value
TRIGGER input pin
PINHSYNC input pin
PINVSYNC input pin
PSGHSYNC output pin
PSGVSYNC output pin
Software Trigger (T1SOFTRG)
t2cnteq0 signal
exp1 (not combined)
usr2 input pin
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
Output Trigger Selection Tied to '0'
//---------------------------------------------
t2trgpol regular
Timer #2 Trigger Input Polarity
eo_information
0 1 unsigned flag_overflow
value = (
( EXP_TRG_NEG_2 * ( ( ! DEF_METEOR_II_MC ) |
( ( ! EXP_TRG_USER_BIT_TIMER2 ) * DEF_METEOR_II_MC )
)
) +
( EXP_TRG_POS_2 * ( EXP_TRG_USER_BIT_TIMER2 * DEF_METEOR_II_MC ) )
) ;
//
//value = (
// ( EXP_TRG_NEG_2 * ( ( ! ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) |
// ( ( ! EXP_TRG_USER_BIT_TIMER2 ) * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) )
// )
// ) +
// ( EXP_TRG_POS_2 * ( EXP_TRG_USER_BIT_TIMER2 * ( OPTION_MC | OPTION_MC_DIG | OPTION_MC_JPEG | OPTION_MC_JPEG_DIG ) ) )
// ) ;
define_value
Trigger input NOT Inverted
Trigger input Inverted
//---------------------------------------------
t2onesht regular
Timer #2 ONE Shot mode enable
eo_information
0 1 unsigned flag_overflow
value = ( ( ! EXP_MD_PERD_2 ) & ( ! ( EXP_MD_HSY_2 & EXP_CLOCK_2_HSYNC ) ) ) ;
//value = ( ! ( EXP_MD_PERD_2 ) ) ;
//value = (
// ( ( GRB_MD_HW_TRG & GRB_ACT_IMMEDIATE & ( ! ( EXP_TRG_SIGNAL_2_TIMER1 ) ) ) |
// ( GRB_MD_HW_TRG & GRB_ACT_IMMEDIATE & EXP_TRG_SIGNAL_2_TIMER1 ) ) ? 1 : 0
// ) * DEF_BT254_PATH ;
define_value
Counter #1 is in continuous mode
Counter #2 is in monoshot mode
//---------------------------------------------
t2tsclr regular
Timer #2 Trigger Scaler Selection
eo_information
0 2 unsigned flag_overflow
value = ( DEF_TIMER2_ENABLE & EXP_PRESCALE2_2 ? 1 :
( DEF_TIMER2_ENABLE & EXP_PRESCALE2_4 ? 2 :
( DEF_TIMER2_ENABLE & EXP_PRESCALE2_8 ? 3 :
0 ) )
) ;
//value = ( DEF_TIMER2_ENABLE & EXP_PRESCALE2_2 ? 0 :
// ( DEF_TIMER2_ENABLE & EXP_PRESCALE2_4 ? 1 :
// ( DEF_TIMER2_ENABLE & EXP_PRESCALE2_8 ? 2 :
// ( DEF_TIMER2_ENABLE & EXP_PRESCALE2_16 ? 3 :
// 0 ) ) )
// ) ;
define_value
1 trigger every 1 is captured
1 trigger every 2 is captured
1 trigger every 4 is captured
1 trigger every 8 is captured
//---------------------------------------------
t2tpsclr regular
Timer #2 Trigger PreScaler
eo_information
0 1 unsigned flag_overflow
value = ( DEF_TIMER2_ENABLE & ( EXP_PRESCALE2_2 | EXP_PRESCALE2_4 | EXP_PRESCALE2_8 ) ? 1 :
0
) ;
//
//value = ( DEF_TIMER2_ENABLE & ( ! ( EXP_PRESCALE2_1 ) ) ? 1 :
// 0
// ) ;
define_value
The timer trigger is not pre_scaled
PreScaled Via T2TRGSL & T2TSCLR
//---------------------------------------------
t2cmbn regular
Timer #2 Combine selection
eo_information
0 2 unsigned flag_overflow
value = ( DEF_TIMER2_ENABLE & EXP_COMBINE_2_XOR ? 1 :
( DEF_TIMER2_ENABLE & EXP_COMBINE_2_AND ? 2 :
( DEF_TIMER2_ENABLE & EXP_COMBINE_2_OR ? 3 :
0 ) )
) ;
define_value
EXP1 = T2 Exposure
EXP1 = T2 Exposure XORED T1 Exposure
EXP1 = T2 Exposure ANDED T1 Exposure
EXP1 = T2 Exposure ORED T1 Exposure
//---------------------------------------------
t2pol regular
Timer #2 Output Polarity
eo_information
0 1 unsigned flag_overflow
value = EXP_OUT_NEG_2 ;
define_value
Active High
Active Low
//------------------------------------
// PSG MISCELLANEOUS CONTROL TIMER #1 Register
// -----------------------------------
//==============================================
PSG_T1MISCTL
Timer #1 MIScelleneous ConTrol
eo_information
7
//---------------------------------------------
// Software set bit to 1 in Asychronous reset !
t1setarm regular
Timer #1 Set Arm
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Next Trigger No Effect
Next Triger Start Counter
//---------------------------------------------
t1armen regular
Timer #1 Trigger Arm Enable
eo_information
0 1 unsigned flag_overflow
// Timer1 always used for WEN Pulse if both timers use Trigger (OPTO or TTL)
value = (
DEF_TIMER1_ENABLE *
(
EXP_MD_PERD | GRB_MD_CONT |
( GRB_ACT_IMMEDIATE * GRB_TRG_SIGNAL_TIMER1_WEN * VDT_NINTRL )
)
) ;
//
//value = ( EXP_MD_PERD | GRB_MD_CONT ) * DEF_TIMER1_ENABLE ;
define_value
MonoShot Mode ( T1SETARM = 1 )
Continuous Mode ( T1SETARM = X )
//---------------------------------------------
t1softrg regular
Timer #1 Software Trigger
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Set T1SOFTRG LOW
Set T1SOFTRG HIGH
//---------------------------------------------
t1cnten regular
Timer #1 Counter Enable
eo_information
0 1 unsigned flag_overflow
value = DEF_TIMER1_ENABLE ;
define_value
Timer #1 Counter Disabled
Timer #1 Counter Enabled
//---------------------------------------------
// This Bit Enable or desable the counter when in continuous mode.
t1reset regular
Timer #1 Reset
eo_information
0 1 unsigned flag_overflow
// Reset in Disable Mode
value = ( ! ( DEF_TIMER1_ENABLE ) ) ;
define_value
Timer1 normal use
Reset Timer1
// -----------------------------------
t1trgmsk regular
T1TrgMsk
eo_information
0 1 unsigned flag_overflow
value = ( DEF_CORONA_II * DEF_TIMER1_ENABLE ) ;
//
//value = 0 ;
define_value
Timer1 resets on Trigger
Timer1 ignore trigger while activated
// -----------------------------------
reserved protected
reserved
eo_information
0 2 unsigned flag_overflow
no_define_value
// -----------------------------------
//
// PSG MISCELLANEOUS CONTROL TIMER #2 Register
// -----------------------------------
//==============================================
PSG_T2MISCTL
Timer #2 MIScelleneous ConTrol
eo_information
7
//---------------------------------------------
t2setarm regular
Timer #2 Set Arm
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Next Trigger No Effect
Next Triger Start Counter
//---------------------------------------------
t2armen regular
Timer #2 Trigger Arm Enable
eo_information
0 1 unsigned flag_overflow
// Timer1 always used for WEN Pulse if both timers use Trigger (OPTO or TTL)
value = (
DEF_TIMER2_ENABLE *
(
EXP_MD_PERD_2 | GRB_MD_CONT |
( GRB_ACT_IMMEDIATE * GRB_TRG_SIGNAL_TIMER2_WEN * VDT_NINTRL )
)
) ;
//
//value = ( EXP_MD_PERD_2 | GRB_MD_CONT ) * DEF_TIMER2_ENABLE ;
define_value
MonoShot Mode ( T2SETARM = 1 )
Continuous Mode ( T2SETARM = X )
//---------------------------------------------
t2softrg regular
Timer #2 Software Trigger
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Set T2SOFTRG LOW
Set T2SOFTRG HIGH
//---------------------------------------------
t2cnten regular
Timer #2 Counter Enable
eo_information
0 1 unsigned flag_overflow
value = DEF_TIMER2_ENABLE ;
define_value
Timer #2 Counter Disabled
Timer #2 Counter Enabled
//---------------------------------------------
// This Bit Enable or desable the counter when in continuous mode.
t2reset regular
Timer #2 Reset
eo_information
0 1 unsigned flag_overflow
// Reset Qd Timer2 disable
value = ( ! ( DEF_TIMER2_ENABLE ) ) ;
define_value
Timer2 normal use
Reset Timer2
//
// -----------------------------------
t2trgmsk regular
T2TrgMsk
eo_information
0 1 unsigned flag_overflow
value = ( DEF_CORONA_II * DEF_TIMER2_ENABLE ) ;
//
//value = 0 ;
define_value
Timer2 resets on Trigger
Timer2 ignore trigger while activated
// -----------------------------------
reserved protected
reserved
eo_information
0 2 unsigned flag_overflow
no_define_value
// -----------------------------------
//
//
/ PSG CONTROL USER BITS Register
// -----------------------------------
//==============================================
PSG_USRBIT1
User Bits ConTrol #1
eo_information
7
//---------------------------------------------
// Read INPUT Pin
USRIN_1 regular
User Bit IN 1
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
// Read INPUT Pin
USRIN_2 regular
User Bit IN 2
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
// Read/Write OUTPUT Pin
USROUT_1 regular
User Bit OUT 1
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
//---------------------------------------------
// Read/Write OUTPUT Pin
USROUT_2 regular
User Bit OUT 2
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
Low
High
//---------------------------------------------
// Read/Write OUTPUT Pin
USROUT_3 regular
User Bit OUT 1
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
<CORONA & METEORII_MC> Reserved / <CORONA-II> Low
<CORONA & METEORII_MC> Reserved / <CORONA-II> High
//---------------------------------------------
// Read/Write OUTPUT Pin
USROUT_4 regular
User Bit OUT 1
eo_information
0 1 unsigned flag_overflow
value = 0 ;
define_value
<CORONA & METEORII_MC> Reserved / <CORONA-II> Low
<CORONA & METEORII_MC> Reserved / <CORONA-II> High
//---------------------------------------------
reserved protected
Reserved
eo_information
0 2 unsigned flag_overflow
no_define_value
//==============================================
PSG_LOCKDTEC
Lock Detect for Corona2 ONLY
eo_information
5
//---------------------------------------------
SYNCPLSDLY regular
Synchronisation Pulse Delay
eo_information
1 4 unsigned flag_overflow
no_define_value
//---------------------------------------------
reserved protected
Reserved
eo_information
0 4 unsigned flag_overflow
no_define_value
//---------------------------------------------
FBKPLSWD regular
Feedback Pulse width
eo_information
3 5 unsigned flag_overflow
no_define_value
//---------------------------------------------
FRCULCK protected
Force Unlock
eo_information
0 1 unsigned flag_overflow
no_define_value
//---------------------------------------------
reserved protected
Reserved
eo_information
0 2 unsigned flag_overflow
no_define_value
//---------------------------------------------
//
//==============================================
PSG_FLTCTL
Input Filter Select for Corona2 ONLY
eo_information
4
//---------------------------------------------
B_FLT regular
Blue Filter Select
eo_information
2 2 unsigned flag_overflow
value = 2 ;
define_value
8 Mhz
10 Mhz
12.5 Mhz
Bypass
//---------------------------------------------
G_FLT regular
Green Filter Select
eo_information
2 2 unsigned flag_overflow
value = 2 ;
define_value
8 Mhz
10 Mhz
12.5 Mhz
Bypass
//---------------------------------------------
R_FLT regular
Red Filter Select
eo_information
2 2 unsigned flag_overflow
value = 2 ;
define_value
8 Mhz
10 Mhz
12.5 Mhz
Bypass
//---------------------------------------------
reserved protected
Reserved
eo_information
0 2 unsigned flag_overflow
no_define_value
//---------------------------------------------
//
// *********************************************
// PSGTC (end)
// *********************************************
// =============================================
//
//
//
// *********************************************
// ZORAN 016 (begin)
// *********************************************
//
//
//==============================================
ZR36016_NAX
Window Area Register NAX
eo_information
1
0 12 unsigned flag_overflow
// Values changed 8 Sept/00
value = (
VDT_HBPORCH -
( DEF_DEC_PATH * ( 3 + ( DEF_50HZ_HV_TOTAL_STD * 2 ) ) ) +
( DEF_BT254_PATH * 8 )
) ;
//
//value = (
// VDT_HBPORCH -
// ( DEF_DEC_PATH * ( 4 + ( DEF_50HZ_HV_TOTAL_STD * 3 ) ) ) +
// ( DEF_BT254_PATH * 8 )
// ) ;
no_define_value
//==============================================
ZR36016_NAY
Window Area Register NAY
eo_information
1
0 12 unsigned flag_overflow
// Nay = 0x14 instead 0x15 for two lines blanking to bottom of Frame => grabbing 2 lines earlier.
// Changes in VSPVAL & VEPVAL done.
value = (
( VDT_VBPORCH / 2 ) -
( DEF_DEC_PATH * ( 3 + ( 2 * DEF_50HZ_HV_TOTAL_STD ) ) ) -
( DEF_BT254_PATH * DEF_50HZ_HV_TOTAL_STD )
) ;
//
//value = (
// ( ( VDT_VSYNC + VDT_VBPORCH ) / 2 ) -
// ( DEF_DEC_PATH * ( 6 + DEF_50HZ_HV_TOTAL_STD ) ) -
// ( DEF_BT254_PATH * 3 ) - 0.5
// ) ;
//value = ( ( DEF_60HZ_HV_TOTAL_STD * ( ( ( VDC_C_COLOR | VDC_SVID | DEF_MONO_VIA_DEC ) * 0x000D ) + ( ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) * 0x0010 )
// )
// ) +
// ( DEF_50HZ_HV_TOTAL_STD * ( ( ( VDC_C_COLOR | VDC_SVID | DEF_MONO_VIA_DEC ) * 0x0010 ) + ( ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) * 0x0014 )
// )
// )
// ) ;
//value = ( ( DEF_60HZ_HV_TOTAL_STD * ( ( ( VDC_C_COLOR | VDC_SVID | DEF_MONO_VIA_DEC ) * 0x000D ) + ( ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) * 0x0010 )
// )
// ) +
// ( DEF_50HZ_HV_TOTAL_STD * ( ( ( VDC_C_COLOR | VDC_SVID | DEF_MONO_VIA_DEC ) * 0x0010 ) + ( ( VDC_RGB_COL | DEF_MONO_VIA_RGB ) * 0x0015 )
// )
// )
// ) ;
no_define_value
// ------------------------------------------------
//
// *********************************************
// ZORAN 016 (end)
// *********************************************
// =============================================
//
[EOF]
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.