Release Note for BCM5704 BOOT Code Firmware
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Version 3.19:
1. Changed the default configuration Limit_10 to "yes" for both ports.
Problem: Change request from Broadcom internal. When building the
5704 NIC Adapters, it is desirable to have the Limit_10
setting default "yes".
Change: This version have both port's WoL setting default to 10 Mbps.
This change only affects to the NIC adapters that are
manufactured using bootcode's built-in default values,
typically, all Broadcom NIC adapters are built this way.
This change does not affect those who manufacture the NIC
Adapter using customized NvRAM image file method, since a
customized NvRAM will typically override many configurable
settings, including the WoL setting.
Version 3.18:
1. Applied workaround for PCIX-133Mhz
Problem: We had blue screen in PCIX-133Mhz system
Cause: Under this environment, there was setup time compatibility
issue with chipset which caused Address/Data bus parity error.
Fix: By raising 2.5V to 2.7V and lower 1.2V to 1.14V could
workaround this problem. This workaround is applied to all
revisions, PCIX-133Mhz bus only.
Version 3.17:
1. Added support for Swapped TTmode
Reason: The future revision of chip added a new feature of Swapped TTMode
in Dual MAC mode. This version is changed to support that mode.
2. Restored PowerDissipated/PowerConsumed initialization.
Problem: In revision A2, we found some devices CPU would hang after
performing a write into PowerDissipated/PowerConsumed registers.
To workaround the problem, the initialization was skipped in
version 3.13 or later. Therefore, version 3.13 to 3.16 was not
supporting this feature.
Cause: After ASIC team's investigation, they have concluded that it
was simply bad chip failed to be screened off in ATE test.
Fix: Restored the PowerDissipated/PowerConsumed initialization so
the function will work.
3. Changed double write to single write to enable auto-powerdown feature
Problem: The earlier version of bootcodes were writing phy register twice
to enable auto-powerdown feature. There was no side effect nor
problem in writing twice.
Fix: After confirmed with phy team, the code is changed to write only
once to save some code space.
Version 3.16:
1. Fixed chip powered down bug
Problem: When SECFG has both port WoL disabled and Window goes
Hybernate with one port WoL enabled and other disabled,
both port would be shut down.
Cause: When bootcode detects PCI power goes away and WoL was
not enbled by driver, it was trying to shutdown the port.
Since NVRAM indicating both port does not have WoL enabled,
the shutdown routine was trying to shutdown everything by
setting chip power down bit and caused the whole chip to
shutdown.
Fix: When driver post signature for WoL, bootcode will not do
anything and let driver to handle everything.
Version 3.15:
1. Fixed PXE ROM size bug
Problem: The secfg option 29, expansion ROM size was not taking effect.
Cause: Bootcode did not program the correct value in the register.
Fix: Bootcode is changed to program correct expansion ROM size
setting in NVRAM configuration into register.
2. Enabled alternate clock at power down mode for lower power consumption.
Problem: Once the power is fully powered and then power goes away, the
chip was consuming more power than it should.
Cause: The ASIC is designed to run at low speed (alternate clock) when
at the powerup if the main PCI power is not present. When
there is full power, it will switch to main clock with faster
speed. When it lose power from full power, the ASIC does not
automatically switch back to alternate clock. Bootcode has to
switch it.
Fix: When system loses main power, it will switch the core clock to
use Alternate clock (12.5M) to save power consumption.
Version 3.14
1. Fixed configuration read bug.
Problem: Both primary and secondary port were reading the primary
port configuration setting.
Cause: This problem was introduced in 3.13, when adding support to data
structure version 1.
Fix: With fix, each port now will read correct NVRAM configuration
setting.
Version 3.13
1. Fixed CPU hang problem (disabled PowerDissipated/PowerConsumed cfg.)
2. Supports Shared Memory data structure version 1
3. Removed phase 2 image loading failure LED blink feature (to save space)
4. Added Alt. Clock control. (slow clock when in VAUX only. Speed up
with full power)
Version 3.12
1. Support A2 silicon.
Version 3.11
1. Disable secondary port WoL/ASF/PXE feature on Turbo-Teaming mode.
2. Removed SST Flash support.
3. Removed workaround for D3_HOT checking for turbo teaming mode.
4. Added 2nd phase signature.
5. Added delay to kick off PCI reset workaround to cover long PCI
reset assertion case.
Version 3.10
1. Lowering power consumption in first stage loader instead 2nd.
2. Added workaround for D3_HOT checking for turbo teaming mode change.
3. Support WoL Limit 10 configuration
4. Support Turbo Teaming Revision
5. Propagate PXE enable bit to share memory
Version 3.09
1. Changed NVRAM corruption workaround algorithm
2. Put back VAUX control cut off logic.
3. Propagate the BothPort100/10Capable info. to Driver.
4. Isolates the primary port.
Version 3.08
1. Fixed WoL problem with new alogorithm on PCI Reset Workaround
2. Fixed PXE problem with new alogorithm on PCI Reset Workaround
Version 3.07.8
1. Added extra halt bit setting before assembly halt instruction to
prevent tx cpu to kick in PCI reset workaround
Version 3.07.7
1. Applied unconditional GRC reset in the beginning
2. Applied new algorithm on PCI Reset Workaround
Version 3.07.2
1. Removed debug code in 3.07
Version 3.07:
1. Added a reset logic to wait for register 590 until it's ready
2. Added a debug code to blink LED when firmware is reset
3. Launch PCI Reset Workaround only with revision A1
4. Fixed bug to Cut off power when WoL is disabled on both ports
Version 3.06:
1. Use MAC id in GRC register for A1 instead of using PCI Cfg reg.
2. Applied workaround for revision A0/A1 dectection
3. Fixed A0 problem in 3.04
4. Fixed Phy device power down problem intruduced in 3.03
(Version 3.05 is a test version, never got released)
Version 3.04:
1. Implemented workaround for BCM5704 A1 which issues GRC device reset
when PCI reset is detected.
Version 3.03:
1. Make sure AUAX power is not turned of if other port has ASF/WOL enabled.
2. Support PowerSaving
3. Changed Phase1/Phase2 parameter passing to avoid bootcode/driver MII
access racing condition.
4. Support FiberWoLCapable Config.
5. Support portSwap Config.
6. Support BothPort100MbpsCapable Config.
7. Fixed ASF enable bit bug to the driver
8. Fixed PXE/Wol relation bug
9. Fixed MAC address programming to all 16 MAC address registers.
10. Implemented a new WOL scheme that requires drivers released
after 07/17/02. Legacy drivers will continue to behave according
to the old scheme.
Version 3.02:
1. Fixed State Reg. 2nd stage boodcode override bug
2. Fixed WOL when power down from PXE or DOS driver.
3. Fixed the timing on the ASF enable information propagation.
4. Fixed secondary WOL bug.
5. When both port WOL are enabled in NIC design, it switches to 10mps
6. Added workaround for ATMEL flash corruption problem
7. Fixed driver/bootcode race condition on MII register read problem
8. Turned VAUX off when WoL is disabled at standby power
** note ** this version (WoL) will only work with 2nd or later board revision.
Version 3.01:
1. Fixed PXE speed bug
2. Removed CIOB GPIO0 & GPIO2 access
3. Added PCIX State Reg. RETRY_SAME_DMA workaround
Version 3.00:
1. Fixed Mac address assignment problem.
Version 2.18:
1. Fixed WoL bug
Version 2.17:
1. Fixed hardware configuration loading bug.
Version 2.16:
1. Fixed Primary/Secondary device dection bug
2. Change Secondary configuration default value to be same as primary
Version 2.15:
Initial Version
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