Release Note for BCM5703S BOOT Code Firmware
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Version 2.29:
1. Fixed link issue.
Problem: When plug and unplug cable cannot reestablish the link
Cause: When only tx cable is disconnected, link still shows up good
link, therefore, the firmware will not kick off to renegotiate
the link again when link is back.
Fix: Changed to check not only link changed but also cfg changed
status.
Version 2.28:
1. Fixed possible PXE hang problem
Problem: When PXE is enabled, some system may potentially not come up.
Cause: Autonegotiation timeout loop was taking too much time and caused
BIOS PXE read timeout.
Fix: Added PXE event service in the timeout loop.
2. Fixed halted CPU problem.
Problem: During code review, a potential problem was discovered.
Cause: If WoL is enabled, at VAUX power mode, the RxCPU is halted.
We needed to keep processor running even at VAUX only mode in
order to monitor the link status. The potential problem if
processor is halted could be; After powering off the device,
removing the link and re-connect again, the device will lose
link. Or, the link LED may still be on even if the cable is
disconnected.
Fix: Not to halt processor even WoL is enabled.
Version 2.27:
1. Fixed PXE ROM size bug
Problem: The secfg option 29, expansion ROM size was not taking effect.
Cause: Bootcode did not program the correct value in the register.
Fix: Bootcode is changed to program correct expansion ROM size
setting in NVRAM configuration into register.
2. Supports Shared Memory data structure version 1
Problem: Driver need more information from bootcode.
Cause: More feature is needed to support in driver.
Fix: Changed the shared data structure from version 0 to version 1
to pass new data in new fields.
3. Removed phase 2 image loading failure LED blink feature (to save space)
Problem: Image size is growing to 8k limit. We needed to remove the
Debug feature out to save space.
Effects: If first phase bootcode has failed to load second phase code,
the older code will blink both traffic and link LED.
This version will no longer blink the LED.
Version 2.26
1. Support WoL Limit 10 speed
Original code: Speed is always 10/100
New feature: Speed can be limited to 10 only. (secfg. Option 34)
2. Fixed Auto-Negotiation/Driver communication bug
Problem: Driver auto-negotiation parameter was not passed correctly.
Cause: The bit to indicate parameter is valid from driver accidentally
got cleared. This result in losing parameter information from
driver.
Fix: Preserved the validation bit.
3. Fixed Auto-Negotiation with PXE slow down bug
Problem: PXE code loads very slowly
Cause: PXE service routine is in same main loop and Auto-Negotiation
service routine. Each Auto-negotiation routine takes milliseconds
for service before it returns to control to loop. When BIOS is
loading PXE code, it takes too much time to load PXE code.
Fix: The monitoring of Link status does not need to be in tight loop.
The code is changed to service Auto-negotiation in every 100 ms
while PXE service routine is service in tight loop.
4. Added 2nd phase signature.
Problem: Driver/Diagnostics could not tell when the 2nd phase bootcode
initialization is complete.
Cause: We only had 1st phase signature but we didn't have 2nd phase
signature.
Fix: Added 2nd phase signature.
Version 2.25:
1. Improved NVRAM corruption workaround algorithm
Problem: The problem described in 2.23 item 2 still exist.
Theologically, there is potential problem when PC jumps
to NVRAM write routine with invalid register content
when losing power.
Fix: Enhance the original workaround by not only check of VPD
write event, but also construct the command outside of
VPD event 'if' check. Thus, if PC happens to be jumping
outside of 'if' statement, it is protected by VPD write
event. If the PC happens to jump inside of if statement,
it will write harmless command since the command is not
constructed yet.
Also, when power is deteriorating, most likely the address
jump will incorrectly jump from high to low address.
Therefore, moved the NVRAM write routine to the highest
address in the module.
Version 2.24:
1. Reversed the NVRAM corruption workaround algorithm to original method
Problem: The new workaround method does not work with other firmware
Cause: Other firmware, such as ASF or TCP segmentation firmware
does not reserve the special register content. Thus, the
workaround does not work if other firmware is loaded.
Fix: Reversed back to original method. With double check of NVRAM
write only if VPD event bit is present.
Version 2.23:
1. Use default MAC address for entry 0 to 15
Problem: We were accepting NULL Mac address packets.
Cause: Mac address 4 to 15 was not initialized.
Fix: Initialize all Mac address registers 0-15.
2. Changed NVRAM corruption workaround algorithm
Problem: Theologically, there is potential problem when PC jumps
to NVRAM write routine with invalid register content
when losing power.
Cause: When the device is losing power, the power drains down
slowly. In the mean time, internal CPU is still running
with deteriorating logic value. Under this condition, PC
can jump in invalid NVRAM write routine and issue write
command to NVRAM and cause the NVRAM corruption.
Fix: Reserved one CPU General Purpose Register to be used for
command to write NVRAM. If any jumps should occur, it will
write an harmless command into NVRAM command register.
Version 2.22:
1. Fixed PXE speed Config. bug
Problem: PXE speed setting was not taking effect.
Cause: The PXE speed was not programmed correctly
Fix: Program PXE speed according to secfg setting
2. Improved PXE loading speed
Problem: PXE was taking too much time to load and cause system hang
Cause: BIOS was reading PXE in byte. Each by access, we needed to
Access NVRAM to return data.
Fix: Our ASIC design always read data in word (4 bytes) size.
For each ROM byte read it will be wasted of time to read
the entire 4 byte-word again. Changed algorithm to save the
read data in memory, acting as cache.
3. Supports dynamic bootcode location
Problem: The bootcode had to be in fixed address 0x200. When the next
application is programmed right after the bootcode image,
upgrading larger bootcode image requires bootcode to be
allocated in another location
Cause: We never needed dynamic bootcode allocation support until now
Fix: Added new algorithm to support dynamic bootcode allocation
4. Added new WOL communication with driver
Problem: Bootcode was always taking over driver WoL setting.
Cause: There was no communication between driver and firmware. Upon
power down, firmware was taking over control for WoL
initialization.
Fix: Implemented a new WOL scheme that communicate with drivers.
For older driver version older than 07/17/02, if WoL is enabled
by driver, firmware will not touch anything. For newer driver,
it will post signature. And depends on the commands. Firmware
will act accordingly.
5. Implemented WOL. Enabled by FiberWoLCapable Config
Problem: WOL support was needed for Fiber module.
Change: Implemented WoL feature in Fiber module. Due to power consumption
issue. Only supported in LOM design.
6. Propagated NVRAM setting regarding WOL even on device reset.
Problem: NVRAM setting was not propagated to shared memory on
device reset.
Fix: Propagate NVRAM setting regarding WOL even on device reset
7. Added NVRAM corruption protection
Problem: NVRAM corruption was seen
Cause: When powering off, the power drops down slowly. The CPU was
still running under deteriorating illegal power and cause
to jump to NVRAM write routine and caused NVRAM corruption.
Fix: The workaround was to put a VPD write event qualification
before actual write command.
8. Propagated the ASF enable information to shared memory before
signature
Problem: Driver was getting incorrect ASF enable status.
Cause: ASF enable bit was initialized in shared memory after the
signature
Fix: Propapated the ASF enable information to shared memory
before signature
9. Changed Phase1/Phase2 parameter passing to void bootcode/driver
race condition
Problem: Fixed PHY access contention problem with driver
Cause: Phase 2 code needed some information requires MII access;
however, since the signature has been posted by first phase,
the driver already have the ownership of MII access. By reading
MII register in 2nd phase code, caused firmware/driver MII read
conflict.
Fix: The information need by 2nd phase was read in 1st phase and
passed the information to 2nd code via shared memory as
parameter passing.
10. Added Phase1 NVRAM access arbitration logic
Problem: Phase 1 bootcode was not using arbitration logic accessing NVRAM
Fix: Added arbitration logic in NVRAM access.
11. Fixed NULL MAC address problem (thought to be)
Problem: The device was accepting NULL MAC address packets.
Cause: Only Mac Address register 0 was programmed. All other
Mac was left was default value 0.
Fixed: Program all MAC registers (1 to 3) with the MacAddress in
NVRAM.
(Later, we found out that this did not fix the problem since
5703 has 16 MAC addresses instead of just 4. The Mac address
register 4 to 15 was in different location. It was later
fixed in version 2.23 item 1)
Version 2.21:
1. Propagate GPIO_1 usage to driver and corrected the usage
in a VPD operation.
2. Corrected the LED behavior in auto-negotiation.
3. Included "fulltime" fiber auto-negotiation.
4. Allow fallback to 1000FD when auto-negotiation fails.
5. Corrected the method of determining ASIC rev for fiber.
6. Updated LED modes of operations.
Version 2.19:
1. Initialize SerDes to correct voltage for A1.
2. Introduced new GPIO_1 usage for some LOM design.
3. Fixed pxe speed initialization (CQ#3488).
4. Restored range check for VPD access.
Version 2.18:
1. Support fastboot initiative.
Version 2.17:
1. Employed block read method when loading other firmwares (e.g. ASF)
from non-volatile memory.
2. Added CRC checking before loading phase 2 bootcode. All speed LEDs
will light up when CRC check fails.
3. Added CRC checking before loading other firmware (e.g. ASF). All
speed LEDs will light up when CRC check fails (CQ#3259).
4. Fixed a bug where a system cannot boot up if phase 2 bootcode is
corrupted.
5. Fixed a bug where Windows does not wake up from standby due to
bootcode cutting off aux power.
6. Eliminated flash interface reset as this may cause non-volatile
memory module to become out of sync.
7. Corrected expansion ROM address to dword aligned, eliminating
lockup during expansiom ROM service through PCI-X (CQ#3259).
8. Uses 0x16A7 as the new device ID in the boot image.
Version 2.16:
1. Employed block read method when loading codes from non-volatile
memory.
Version 2.15:
1. Speed up the PXE loading (CQ#3108).
2. Implemented two-phase loading to speed up the boot process.
3. Enable expansion ROM bit in phase one booting to avoid BIOS missing
to load PXE when enabled.
4. Firmware stops running after loading ASF to avoid interference.
5. Use software arbitration support by the hardware when accessing
non-volatile memory.
6. Fixed a bug where the firmware did not clear VPD request after
it is serviced.
Version 2.14:
1. Moved multiple boot agent codes and fixed uninitialized variable bug.
Version 2.13:
1. Initialized SerDes configuration register.
2. Embedded version string into the executable binary.
3. Support multiple boot agents.
4. Set LED to PHY mode when card first receives auxilary power.
5. Enable PXE loading from flash memory.
6. Disabled the setup for max PCI retry, default to zero.
Version 2.12:
1. Added ASF support.
Version 2.11:
1. Fixed Non-Buffer VPD write bug
Version 2.10:
1. Added flash write support for VPD.
2. Added auto negotiation for 5703S.
Version 2.8:
1. Branched bootcode into several versions to be silicon specific.
2. Fixed flash timeout problem.
Version 2.7:
1. Added 5703 support.
Version 2.6:
1. Added generic loader support. This is a requirement for ASF support.
Version 2.5:
1. Fixed the cable unplug/replug problem on PCI-X setting.
Version 2.4:
1. Fixed cable unplug/replug problem (CQ#1998).
Version 2.3:
1. Added 100Mbps WOL on A3/B5 boards.
2. Fixed zero mac address when enabling WOL on fiber card (CQ#2236).
Version 2.2:
1. Initialize PME Status upon the first time power-up.
Version 2.1:
1. Fixed bug on WOL.
2. Temporarily disable BCM5703 support.
3. Fixed link loss on fiber card.
Version 2.0:
1. Added WOL support
2. Added BCM5703 support
Version 1.9:
1. Added features so that neccessary manufacturing information is
stored in the shared memory. This allows host driver can query
these information.
Version 1.8:
1. Fixed a problem where PXE is not operatable in version 1.7.
Version 1.7:
1. Added logic for 1.3v and 1.8v voltage source.
2. Added logic forcing PCI mode.
Version 1.6:
1. Added BCM5701 support.
* Initialize BCM5701 to use PHY LED mode.
* Initialize BCM5701's PHY to advertise 10/100/1000.
2. Timer prescaler is now initialized to reflect 66Mhz core clock.
Version 1.5:
1. Added BCM5700 Fiber support.
Version 1.4:
1. Initialize BAR after first reset.
Version 1.3:
1. Changed so that default manufacturing information now has proper
power consumption and dissipation.
Version 1.2:
1. Fixed a problem where firmware has problem accessing PHY registers
during bootup time for NIC rev.12 and above.
Version 1.1:
1. Format of ASIC revision ID has been changed. Changed to generate
PCI revision ID correctly.
ASIC Rev. PCI Revision ID
======== ===============
B0 0x10
B1 0x11
Version 1.0:
1. Initialize PHY LED mode based on subsystem vendor ID.
* Dell Viper LOM (0x1028) : Triple speed mode (MII 0x10 = 0x0)
* Other : link/speed mode (MII 0x10 = 0x2)
Version 0.8:
1. Initialize PHY LED mode based on subsystem device ID.
* Dell Viper LOM (0x1028) : Triple speed mode (MII 0x10 = 0x2)
* Other : link/speed mode (MII 0x10 = 0x0)
Version 0.7:
1. Initialize PHY (BCM5401) with scripts so that NIC has link after
power-on-reset before driver is loaded.
Version 0.6:
1. Initialize Chip Revision ID in PCI configuration space.
Version 0.5:
1. Added logic to perform PHY H/W reset.
2. Initialize VPD delay so that BIOS can access VPD.
Version 0.4:
Initial release.
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