releases.txt Driver File Contents (

             Release Note for Shasta Bootcode Firmware
                5721, 5750, 5751, 5751m, 5751f, 5789, 
                  5753, 5753m, 5753f, 5781, 5903m 
 Version 3.65 ---- 11/28/06 
1. Fixed NVRAM read bug

    Due to other project change, since version 3.63, shared_config was read
    NVRAM access FIRST/LAST bit can only be used in consecutive addresses.
    When reading configurations from offset 0xc4,0xc8 and 0xdc, 0xdc could
    not be read in one bulk read. 
    Shared_config 0xdc was read separately from previous bulk read.
 Version 3.64 ---- 11/14/06 
1. Cannot see PXE banner

  Problem: CQ 27423
    Enable PXE and reboot the system, PXE code was not loaded and executed.
    When BIOS boot up it will detect the existence of expansion ROM by write 
    all 1's to Expansion ROM Base Address and expect read back the expansion 
    ROM size and valid status.  
    Some how at this time bootcode still in the middle of initialization, 
    the Expansion ROM regsiter's settings was not ready yet, 
    so the return value will be 0's.  Which means Expansion ROM is disabled.
    Move the Expansion ROM initialization to earlier stage at Phase1 boot code.
 Version 3.63 ---- 11/13/06 
1. PCIE Link Polarity

  Enhancement: CQ#27039, CQ#26767, CQ#27105
    Apply PCIE Link polarity workaround only at hardware reset (POR or 
 Version 3.62 ---- 9/15/06 
1. Link speed issue

  Enhancement: CQ26652
    We have compatibility issue with Intel NIC Intel Pro/1000MT based LOM 
    (NDIS5.1 8.5.14, Auto detect for Speed/Duplex parameter, Windows XP 
    Professional SP2 O/S). The symptom shows when WoL is disabled and there
    is no management firmware loaded, after first time power up, the link 
    partner settles at speed 10H where our device settle at 1000F after the 
    link negotiation. To workaround the issue, bootcode is changed to use 
    different method to initialize the phy. 
    This issue exists not only in this device but all NetXtreme I products.  

 Version 3.61 ---- 7/28/06 
1. Fixed RxMBUF base and length issue.

  Problem: CQ 26107
    5721, 5751m and 5903m bootcode version 3.60 does not initialize RxMBuf
    base and length (0x4408 and 0x440c) correctly.
    Due to code reduction, mobile and server based bootcode assembly code
    were changed incorrectly.
    Fixed the start up assembly code correctly.
    This problem only seen in 5721, 5751m and 5903m. The bootcodes for 5750, 
    5751, 5751f, 5789, 5753, 5753m, 5753f, and 5781 has no impact and should
    be exactly the same as version 3.60.  
 Version 3.60 ---- 7/05/06 
1. IPMI traffic fails when LOM is disabled by BIOS
  Problem: CQ#25290
    The IPMI traffic does not work when LOM is disabled by BIOS.  
    With certain platform, when the device is disabled by BIOS, PERST# is
    asserted and refclk is removed. Under this condition, the workaround 
    implemented for unstable refclk in version 3.52 logic will kick in 
    and cause bootcode to wait for stable refclk. Since the clock will 
    never be available, hence, bootcode is stuck in forever loop and cannot 
    proceed to load IPMI firmware. 
    Added one second timeout when waiting for stable refclk. The bootcode
    will advance when the timeout expires.
    Since there is no refclk is available; furthermore, the PERST# is 
    asserted under this condition, the PCI domain registers become not 
    accessible. Since bootcode has many PCI domain register access after
    exiting the loop, all those register access become invalid and will 
    timeout causing further delay to load IPMI code. The estimated delay is
    about 3 to 4 seconds compare to normal boot under this particular 
    condition. (There is no impact and no delay under normal condition.)
2. Enabled second phase fastboot feature

    Only the first phase bootcode NVRAM loading is bypassed with the older
    bootcodes. Starting with this version, the second phase is also pre-
    reserved and NVRAM code loading is bypassed. 

    Since the bootcode is no longer reload from NVRAM, the boot time will be
    much faster. Upon reset, there will be only few words of configuration 
    NVRAM access.

 Version 3.59 ---- 3/07/06 
1. VPD-R checksum error

  Problem: Related CQ#23565, CQ#23566
    VPD-R checksum was incorrect
    Checksum was calculated from VPD-R to the end of VPD-R region; however,
    the specification indicates that Checksum should be calculated from the
    offset zero.
    Corrected the checksum
2. Initialized Cardbus pointer register

  Enhancement: CQ#23431
    Since Cardbus support is no longer a requirement, in order to pass
    the plug-fest compliance test, we write zero to register 0x28 to disable
    cardbus feature.     

 Version 3.58 ---- 2/15/06 
1. Fixed revision issue

  Problem: CQ#23294
    For all B step revision were reported as A step revisions
    Revision now is reading from register 2018 instead of 68; However,
    there was a coding error, shifted metal revision incorrectly. 
    Corrected the error 
    This error was created in version 3.57, #1.   
 Version 3.57 ---- 2/14/06 
1. Changed revision reading

    CPU reads incorrect silicon revision id in D3 power state.
    In D3 power state, except OOB, the PCI/PCIE registers are not accessible.
    All reads returns zero. Because of this, the read is not reliable.
    Instead of reading from register 0x68, the code is changed to read the
    revision id from register 0x2018. The register 0x2018 is available at all
2. PCIE link polarity workaround problem

  Problem: CQ#14612
    After Windows shutdown or DOS shutdown, the link stay at 10mb and WoL does
    not work.
    The PCIE link polarity check loop was stuck in waiting for PCIE link to
    come up while there was no VMain. Since VMain drains slowly, there was 
    a time bootcode come up seeing VMain present and apply the PCIE link 
    polarity workaround. The workaround has implemented to wait for PCIE 
    link to come up and check for the polarity. In this case, since the 
    VMain slowly goes away, PCIE link never came up and the loop was stuck 
    Put a VMain check in the workaround loop. If the VMain goes away, it will
    break out of the loop and ignore PCIE polarity workaround.
3. Fixed WoL for OS/DOS shutdown

  Problem: CQ#22944, CQ#23220
    Can't waked up by wake on lan after OS shutdown
    CPU got hang in switching to alternate clock while there is no VMain.
    When there is no VMain, bootcode cannot access PCI domain registers.
    Therefore, the code is changed to not to switch to alternate clock when
    there is no Vmain.
 Version 3.56 ---- 12/08/05 
Since we are no longer generating bootcode for PCI bus v1.00, starting this 
version, the version extention 'a' will no longer be used to indicate PCI 

1. Changed PLL status polling

  Problem: CQ#22283
    Bootcode version 3.52 to 3.55 did not work on some systems. 
    The device may disappear, link at 10ms, and cause b57diag CPU test to
    In Shasta, depends on some system, the PLL status returned warning
    code instead of success code for low voltage. Since the workaroud for 
    v3.52, #1 uses this code to determine good PLL status, the bootcode
    was hang waiting success code.
    Changed to poll for status bit instead of error code. 
2. Force PCIE polarity

  Problem: CQ#22100,CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254
    In some platform, the PCIE link polarity comes up incorrectly. 
    ASIC could not handle all cases correctly.
    Wait until PCIE link comes up. Then based on the link polarity status
    detected by ASIC polarity auto detect, firmware will then force the 
    PCIE link to the correct polarity. 
 Version 3.55 ---- 11/11/05 
1. Fixed WoL was not working issue.

  Problem: CQ#14614
    WoL was not working on OOB, DOS shutdown or Windows S5 case. 
    Version 3.52 (#2) added workaround for platforms that show an unstable 
    PCIE refclk during power up. Nevertheless, there is a limitation to 
    this workaround as to where it requires VMAIN to be present. In systems 
    where there is no VMAIN present and there is no PCI-E REFCLK at all for 
    the cases outlined above the bootcode will loop forever, therefore not 
    enabling WoL.
    Added a condition to the "unstable PCI-E Refclk" workaround to apply
    this fix only when there is VMain present.  In cases where there is no 
    VMAIN present, the boot code will no longer check/wait for a "stable 
    PCI-E Refclk" before continuing.
 Version 3.54 ---- 10/27/05
1. Fixed data corruption issue

  Problem: CQ#14509
    Data corruption is reported by the NDIS tester while running NDIS Tests
    The stack pointer is initialized incorrectly. The file was shared by
    other project has only 48K RxMbuf. Since this device has 64K, the stack 
    pointer should be initialized to 0x20000, instead, it was initialized to
    0x1c000, the receive data buffer area. As bootcode constantly modifying
    stack content, as result, it was causing Ethernet traffic data corruption.
    Changed the stack pointer back to 0x20000.
    This issue has been intruduced in version 3.52, 3.53.      
 Version 3.53 ---- 10/18/05
1. Cable Sense Mode Enhancement

    By changing GPHY programming, further 16~20mA could be saved in Cable
    Sense mode.

    This change only affect 5903m. 
2. Move GPIO initialization to Phase1 code

    Originally, activating VAUX power was done in phase 2 bootcode.
    However, once driver waited for phase1 signature, driver may start to 
    configure GPIO for WoL setting. The 2nd phase GPIO initialization may 
    destroy driver's setting.
    This problem was worked around by driver by waiting for phase2 bootcode
    to be loaded before the GPIO initialization. This change does not 
    affect anything since driver already have the work around. 
 Version 3.52 ---- 10/7/05
1. Removed Engineer release change

    The version 3.51 was for engineering test purpose. The change is removed.
2. Worked around unstable PCIE refclk issue

    The bootcode cannot initialize PCIE registers reliablity in some

    In some particular system, the PCIE refclk was not stable for a long 
    period of time. Accessing PCI config. space registers, 0x7d00 and 
    0x7e00 block registers relying on this clock. When the clock is not
    available, all access to those registers will timeout and read will 
    return zero.
    Since all access performed to 0x7d00, 0x7e00, and
    PCI config. space is invalid until the clock is available, many 
    initialization may not be done correctly; or at least it may read
    incorrect revision ID. 
    Therefore, to ensure the code is executed properly, we need to ensure
    the clock is there first before proceeding with initialization. 
    Put a wait loop until refclk is stable before move on to initialization
3. Enabled Cable Sense feature for 5903M
    Enabled cable sense feature for 5903M.
    The secfg option 53. Cable Sense Enable is ignored. It unconditionally
    enables cable sense for 5903M. 
 Version 3.51 ---- 9/7/05 (Engineering Release)
1. Enabled ECD 12429 

    Enabled ECD 12429 ASIC fix for 5903M or newer devices.

 Version 3.50 ---- 9/7/05 
1. Dropped A0 support

  Problem: CQ#13691
    Voltage was incorrect when PERST_L is held active.
    In the condition: VMAIN on, and PERST_L is held active, the bootcode 
    cannot access the PCIE registers. At this time, if bootcode read revision
    register (0x68) it always returns zero (A0). For Revision A0, we needed
    a workaround to adjust the voltage. The voltage change should be done only 
    in A0; however since all newer revision devices are mistakenly treated as
    A0 under this condition, the voltage was altered. As result, caused the
    device to mis-function.
    Removed A0 support, therefore, bootcode will not alter the voltage in any

2. Changed "DeadDead" routine for 5903M

    5903M needed to use different method of shutting down the device.
    5903M has ASIC change so further power saving shutdown is possible.
    Changed the shutdown routine for 5903M.
3. Removed CDR Freq value workaround for 5903M or newer rev.

    The workaround for CDR (Clock & Data Recovery) "Tracking was taking much
    too long" issue has been corrected in 5903M or newer revision. 
    Therefore, keep this workaround only for older revisions. 

4. Added L0s performance

    The 5903M or newer device is allowed to change PCIE serdes parameter to
    boost up the performance. The firmware will change the parameter for
    5903M or newer devices.
5. Enabled ECD12650 ASIC fix    

    ECD12650 (Low Power Mode fix) is available in 5903M or newer revision. This 
    change is to enable the fix if the device is 5903M or newer.    
 Version 3.49 ---- 6/9/05 
1. Enabled CQ11121 ASIC fix

    In revision C0 or later, there is ASIC fix for CQ11121. This version
    enables the fix.
  CQ11121 Problem:
    Data Link Layer Retry Logic will corrupt TLP upon receiving NAK
    The Data Link Layer's retry buffer logic will merge two TLPs, a receiving 
    TLP from the Transaction Layer with a replay TLP from the retry buffer, 
    which will generate a corrupted TLP upon receiving a NAK from the Link 
    Partner. The corner case arises whenever the rising edge of the GotNAK 
    signal occurs at the same time with the rising edge of the TransGrant 
    signal. The GotNAK signal is used by the retry logic to initiate replay 
    of a pending (unacked) TLP. The TransGrant signal is used by the Transaction 
    Layer to initiate a new TLP transfer. When the rising edge of these two 
    signals occur, a corrupted TLP is generated if the length of the replayed 
    TLP is shorter than the length of the receiving TLP from the Transaction 
    Layer. This results in system blue screened and/or Data Corruption.  

    This change is fixed in ASIC C0 or newer chip, bit 23 of 0x7d00 is a bit to
    enable it. This version of bootcode will enable this fix by sitting bit 23
    of 0x7d00 to 1.
 Version 3.48 ---- 5/16/05 
1. Fixed CQ12650

    LOM disappears after multiple LOW_PWR assertion/deassertion cycles

    When the PLL (Phase Lock Loop) Power Management bit is enabled 
    (register 0x7d00[4]=1), during exhausted multiple cycles of WoL testing
    (entering/resuming from D3_COLD), there is a small chance that the 
    device can lock-up.

    This is because when the 0x7d00[4] bit being set, when the PERST# is 
    asserted AND when  the chip enters PCIE L2 link state, the internal PLL 
    will be powered down. Some time later, when the PERST# is disserted, 
    the chip will try to re-establish PCIE link, at this time the PLL may 
    not able to restart because the capacitor (internal in the chip) that 
    feeding VCD is in a "intermediate charged state".

    Due to a similar problem in the past, this bit (0x7d00[4]) was cleared 
    in bootcode version v3.33 (change item #1). In bootcode version v3.45 
    to v3.47, this issue thought to be fixed in ASIC revision C0, so these 
    3 versions of bootcode was modified to leave this bit (0x7d00[4]) set, 
    for chip revision C0 or newer devices. However, by leaving this bit set, 
    we then discovered it causes "device disappear" problem.

    Clear PLL power management bit, bit 4 of 0x7d00, as part of bootcode 

    This change will only affect chip revision C0 or newer devices and will 
    cause the chip to consume slightly more power during D3-Cold state only.  
    (between 55mA to 75mA, depending on whether or not the "PCIE reference 
    clock" is shut-down or not).  No power consumption affected in other 

 Version 3.47 ---- 4/25/05 
1. Fixed device disappearing problem

  Problem: CQ12650
    After numerous power on/off test, in rare cases, possibly, the device
    can disappear. 
    PCIE PLL can get stuck in the powerdown state if it does not receive 
    a proper reset after exiting the IDDQ state (which can be enabled by 
    either Low Power Mode pin or the powerdown register bit)
    Not to use powerdown register bit to shutdown the device, but instead,
    the bootcode shut down individual blocks such as GPhy, PCIE Tx/Rx Serdes,
    PCI clocks, and slowing down the core clock.
    Without using shutdown register bit, and shutdown the device by each 
    individual blocks, will consume more power.
    It used to be around 10mA with shutdown bit, now the device will
    consume around 150mA at 1.2V power rail and 30mA at 2.5V.
    When deaddead feature is used to disable the device, the device will
    consume about 90mA at 1.2V and 41mA at 2.5V when VMain present. When
    VMain is turned off, it consumes around 70mA at 1.2 and 40mA at 2.5V.        

2. Fixed "deaddead" feature problem

    After depositing "deaddead" to 0xb50, the device was not shutting down.
    The data cache was turned on. When the data cache is on, the external (host)
    change of shared memory content (deaddead mark) was not able to be detected
    by internal CPU. 
    Turned off data cache before entering the service loop. 
 Version 3.46 ---- 2/28/05 
1. Fixed the bug in v3.45

  Problem: CQ#12253
    ASF secure section was not working.    
    Revision information was not posted correctly in shared memory.
    This bug was created in v3.45 due to other project's change.
    Code was erroneously coded.
    Fixed the software bug.
 Version 3.45 ---- 2/23/05 
1. Enabling ASIC Rev. C0 fixes

    ASIC team has evaluated following ASIC fixes and requesting to enabling them:

      1. Enable CQ11234 Fix.       (set bit 8 of 0x7C04)
         In the previous revision of ASIC, when a PCI-E training error
         condition is detected, the link training error bit at uncorrectable 
         Error Status Register will be set. Optionally, depending on the 
         training error mask and severity setting, an uncorrectable error 
         message may be sent upstream to the root complex. This is required 
         by the PCIE v1.0a spec. 

         However, the training error has not been well defined in the spec
         v1.0a, and false triggering is highly undesirable. In the draft PCIE 
         v1.1 the link training error is removed from the specification.

         In Rev C0, the ASIC added a programmable feature to support this
         change. This version of bootcode sets the bit (0x7c04[8]) which is to 
         instruct the ASIC to remove training error bits from pcie advanced 
         error reporting registers and to be PICE v1.1 compliance. 

       2. Enable CQ11386/CQ9321 fix (set bit 27 of 0x7C00)
         In the previous revision of ASIC, under some corner conditions
         (such as when the Chipset's Replay Timer parameter is programmed
         incorrectly), Shasta will send a packet on the PCI-E bus which causes 
         the chipset to viewed as an "unexpected completion".

         In Rev C0, the ASIC had address this minor issue, however the h/w
         fix is by default "disabled".

         This version of bootcode enables the h/w change (sets 0x7c00[27]).
      3. Enable CQ11011 Fix        (clear bit 18 of 0x7D00 && setting bit 4 of 0x7D00)
         In the previous version of ASIC, when the chip enters D3-Cold, the
         chip internal PLL clock and power management can intermittently become
         unstable for a few microseconds.

         In Rev C0, this issue was fixed.  However, the firmware needs to 
         program the ASIC (clear bit 0x7d00[18] and set bit 0x7d00[4]) so
         that when the chip enters D3-cold, the PLL clock and power management
         are stable.

         The firmware workaround was implement for this version 3.33, item#1 
         and version 3.34, item#3. The code now is changed to if the chip 
         revision is C0 or newer, apply this change. Otherwise, keep the old 
         firmware wordaround.
      4. Enable CQ11211 Fix        (set bit 24 of 0x7D00)
         In the previous version of Shasta, if a PME_TURN_OFF message is
         received before the device is first placed into a D3hot state 
         (and L1 link state), the device will generate an internal reset 
         because this "power-down" sequence was unexpected.  This power-
         down sequence is not legal per the PCI 1.0a spec, but is permitted 
         in the ECN 37 which is included in the draft PCI-E v1.1. spec.
         An unexpected reset could then lead to other problems. For
         instance, WoL configuration information could be lost, which could 
         cause some forms of WoL to not work.  

         In Rev C0, the ASIC has been changed to support ECN 37 so an
         internal reset is not generated under this circumstance. However 
         the h/w fix is by default "disabled" (for backward compatibility).

         This version of bootcode enables the h/w fix (sets 0x7d00[24]).

      5. Enable CQ9987 Fix         (Clear bit 18 of 0x2018)      
         In the previous version of ASIC, when ASF (or IPMI) f/w is trying
         to enqueue an Ethernet packet into the MacTxQueue, if the MacTxQueue 
         is already full, and if there is a register access from the Host,
         that register access may fail.

         This particular problem was avoided by older ASF and IPMI f/w.  The
         f/w would wait until the MacTxQueue is not full, and then submit the
         packet into the queue, hence avoiding the problem.

         However, in Rev C0, this problem is properly fixed in the ASIC, and
         the f/w workaround is no longer needed.  However, the fix in the
         device was by default "disabled" (for backward compatibility).

         This version of bootcode enables the h/w fix (clears 0x2818[18]).

 Version 3.44 ---- 2/11/05 
1. Changed Power budgeting data count definition

    Using v3.43, user must use seprg to program the bootcode; this will
    cause user to lose some custom data in the device.
    upgfrm will not copy the new default power budgeting data to the
    configuration. When enabling hot-plug feature without a valid
    power budgeting data, hot-plug function will not work. Therefore,
    upgfrm command was not recommended for version 3.43.
    Changed the specification so new diagnostic can determine if the
    old structure and new structure. This new spec. also allow user
    to disable hot-plug feature.
    Since the bit definition is changed, v3.43 is no longer compatible. 
    Therefore, version v3.43 will be removed from the release directory.
    In order to ensure the hot-plug feature, this version or the 
    future versions of bootcodes requires b57diag version 7.58 or newer
    to upgrade.
2. Fixed bootcode size

    The release for 5721, 5751m, 5753, and 5753m was 12k in size.
    The bootcode has grown beyond 8k limit before releasing version 3.43.
    After the code deduction, the code size now is under 8k. The built 
    environment has been changed in 5751 project, but not others; therefore, 
    even though, the code was under 8k, other project was still building
    12k images.
    Fixed the built environment to reduce the output file size.
 Version 3.43 ---- 2/8/05 
Due to the Power Budget feature enhancement, when upgrading firmware
from 3.42 or earlier version to 3.43 or later version, b57diag command
seprg should be used. If upgfrm command is used, the Power Budget default
value (Manufacturing block) will not be updated. It will cause problem.

Always use seprg command to update this version from older version.

1. Enabled PCIE Link L1 for C0 or newer chips

    For Shata C0 or newer chip, L1 can be supported. Changed the
    code advertise L1 for C0 or new chips.
2. Disabled ASIC CQ10453 fix

    Revision C0 or later has CQ10453 Fix. This feature is not
    fully tested and ASIC team recommend to disable it until 
    further notice.
    Disabled the Fix.  
3. Removed L0s performance Optimization workaround.

    After adding many feature and workarounds, the code size has reached to
    8k limit. We had to find a way to reduce the code.
    The L0s performance optimization feature implemented in version 3.27, #2, 
    later, found only works better in some machines and make it worse in other.
    Once there was a discussion about removing this feature. Then, decided to 
    changed it to be configurable in version 3.39, #2. Since by default it is
    disabled, and most of the time, we want it to be disabled, in order to save 
    some code space, this feature is removed.
   Removed the L0s performance optimization workaround and the configuration.
4. Enhanced CDR Freq. Value workaround performance

    With further analysis, and testing, ASIC team found with combination
    of other Rx Timer value (reg.2) and CRD_RW value (reg.7) works the
    best. Bootcode now is changed use that value.
5. Added C0 HotPlug feature

    Added HotPlug Power Budget data programming to support HotPlug feature.
6. Removed NVRAM speed speed-up routine

    Code size is over 8k, we needed to find a way to reduce the code size.
    Originally, if 20MHz or faster NVRAM is used, phase 1 was changing the default
    6MHz NVRAM clock to 16.6MHz for 2nd phase code loading.
    However, since we need to reduce the code size, this feature is removed.
7. Removed CQ#11849 workaround, version 3.41,#2

    ASIC team is still analyzing the result of workaround. This workaround may
    potentially upset Intel chipset. 
    This workaround is removed until further analysis.                 
 Version 3.42 ---- 1/20/05 
1. Fixed PXE problem

    Using version 3.41, if PXE is enabled, the system will hang.
    The workaround applied in version 3.41 has a code will stay
    in tight loop without servicing PXE. When system BIOS try to read
    PXE without bootcode servicing the read, system will hang. 
    Changed the algorithm to service PXE while applying the workaround
    for cq#11849.  

    Version 3.41 is removed from release directory.     
 Version 3.41 ---- 1/19/05 
1. Changed CDR Frequency value

    By changing CDR (Clock & Data Recovery) Freq. value can boost
    performance. This change is recommended by ASIC team.
2. Changed Rx Error Thresholds

  Problem: CQ#11849
    Rebooting the system causes the LOM to no longer be seen by the 
    BIOS and a message is displayed on the screen which says the LOM 
    is no longer present.
    The default error threshold to cause error event was too large
    for some system, the link error was not able to be detected.
    Since the link could not be established correctly, the device
    Reduce all thresholds, frame error([8:11]), disparity error([4:7]), 
    and code error([0:3]), from default value of 0xf to 0x3. Then, have 
    bootcode to poll for any error condition. If an error is detected, 
    re-sync the link. When link is reestablished, the device will be 
    visible from the host.

 Version 3.40 ---- 11/19/04 
1. Fixed device appearing problem after WoL awake up

  Problem: CQ#11532 
    Device is disappeared once awaken in WoL
    The change in v3.38, #2, Serdes Jitter workaround was not able to be
    garanteed to be performed before bit synchronization / clock recovery.
    If it done after, it will cause chip to generate GRC reset internally.
    The reset will cause the bootcode to restart and reapply the workaround 
    again. Because of the endless reset, the host is not able to see the device.
    Removed Serdes Tx/Rx Jitter workaround. (v3.38, #2)
2. Fixed a software bug

    The correct logic to apply L0s performance enhancement was suppose to be: 
    If the workaround is enabled, apply the workaround only if it is non-driver
    Version 3.39, the logic was erroneously coded as:
    If the workaround is enabled, apply the workaround if it is non-driver
    reset or it is LOM.

    Software bug
    This bug only exists in v3.39.
    Since by default, the L0s performanace enhancement workaround is disabled,
    there should be no problems. The problem can be seen only when the
    L0s performance workaround is enabled and LOM setting is set.
 Version 3.39 ---- 11/11/04 
1. Fixed PCIE Serdes register write bug

    PCIE Serdes register write routine was not working
    This problem was introduced in version 3.34 when the code is changed
    Fixed the bug.
    1. Starting version 3.34 to 3.38, the L0s workaround was not working 
       correctly due to the erroneous write routine. 
    2. Version 3.38, #1 workaround around was not working at all.
    This fix should fix both problems

2. Added configuration option to disable/enable L0s performance workaround

    L0s performance workaround added in version 3.27, #2 could cause some
    system to crash. 
    When host was in L0s state, our device possibly cannot perform a write to 
    PCIE rx serdes registers due to the missing PCIE clock.
    When we cannot change the time in phase tracking mode before asserting
    receive sequencer done, and changing FTS value, it will cause system to hang
    Added a feature so user can enable or disable this L0s performance 
    enhancement. This feature will be disabled by default.   
 Version 3.38 ---- 11/09/04 
1. Removed advertisement of L1 ASPM (Change in v3.31)

    This feature is not fully debugged and analyzed yet.
    We disable this feature for now until we fully debugged
    this feature.
2. Applied workaround for Serdes Tx/Rx Jitter issue due to bad PLL locking

  Problem: CQ#11193
    PCIE Serdes PLL can pick a bad pll_lock range value @ power up.  In fact, 
    the pll_range value is jumping from one extreme to another from chip to 
    chip @ power-up.  The pll_range value is a prime determinant of the TX 
    jitter, and that it is the wideband / random jitter which is increasing, 
    particularly above 10MHz. Over all, this problem causes our device to fail 
    the PCIE Tx/Rx Jitter requirements.
    Change the PLL reference from BandGap to VDD/R based.  And, force the PLL 
    lock range bits to 0.
3. Removed NIC cut off delay time feature

    In NIC, when firmware detects VMain is not present and WoL is diabled, 
    it will cut off power by using GPIO 1 to generate a rising edge.
    This debug feature is to delay the time before cutting off the power. 
    The user had choice of delaying 250ms, 150ms, 50ms, or 0ms before cut 
    off power. By default, the delay time was 250ms (which, we had a bug in 
    PCIE devices since we could actually slow down the clock in VAUX only state
    and 250ms delay became 5 sec. delay) and later was changed to no delay by 
    default in version 3.34, #2. However, this feature not only appears to be 
    no value in final product but also to cause excessive power comsumption 
    before cutting off power. Since code size is approaching to 8k limit, 
    we need to remove this feature. 
    Removed this feature.
    Changing VAUX cut off delay value in NVRAM configuration (offset 0xc4, [23:24])
    will take no effect.
 Version 3.37 ---- 10/26/04 
1. Fixed EEPROM VPD write problem

    VPD write was not working for SEEPROM
    After version 3.35, the eeprom type checking was checking as
    [SO,SI,SCLK,CS]= 0000 instead of 1000. As result, when the setting
    is 1000, it could not recongnize as EEPROM and then skipped the write
    Fixed the software bug. 
 Version 3.36 ---- 10/15/04 
1. Added ST M45PExxx/Saifun SA25Fxxx/AT25F512N support

  The following is the supported NVRAM summary:
  SO:   Bit 25, Flash Size,     internal pull-up 
  SI:   Bit 24, Protected Mode, internal pull-down
  SCLK: Bit 1,  Buffered Mode,  internal pull-down
  CS:   Bit 0,  Flash Mode,     internal pull-down

  [SO,SI,SCLK,CS] Device       VPD Write         Memo         
  --------------- ------------ ------- -------------------------
       1000       AT24C512        Yes  SEEPROM, AT24Cxxx, any size              
       0111       SA25F0xx        No   Saifun SA25F005/010/020 (512KB/1MB/2MB)
       1011       AT45DB011B      Yes  Atmel Buffered 1MB Flash
       1101       ST M45PEx0      Yes  ST M45PE80/M45PE40/M45PE20/M45PE10 8/4/2/1MB Flash
  ST M45PEx0 has been support since v3.25; however, it is was not included in 5789/5781.
  For 5789/5781, this is the first version to support this device.     
2. Fixed VAUX only state revision detection problem
   Device:5753, 5753m, 5753f, 5781 only

    For 12x12 package devices, in VAUX only state, the voltages is programmed
    For 12x12 package devices, in VAUX only state, PCI config. Space is not
    accessible. As result, the revision could not be read correctly. It always
    returns zero. We had a workaround to change voltage in revision 0. Since
    we read zero as revision in VAUX only state, the workaround had changed
    the 1.2 and 2.5 voltages for 12x12 device in VAUX only state.
    Use compiler option to force revision to 1 for 12x12 devices.
    This problem will occur only when in VAUX power only state (When computer
    Main power is off). Also, this problem only seen in 12x12 devices and the 
    change will only affects those devices. (5753, 5753m, 5753f, and 5781).
3. Drives unused GPIO pins to output
   Device:5753, 5753m, 5753f, 5781 only
    When GPIO is not used and there is no connection, the GPIO pins are
    left tri-state without pull-up or pull-down. With floating voltage, 
    it can cause reliability issue.
    By default, all GPIO are input pins. When it has no connection and it is
    not in use, the pin will not be driven by anything.
    Change the unsed GPIO pins to outputs.
    Only when configuration is set to LOM will take effect since NIC
    uses all GPIO pins for WoL circuit.
    This change is only made for 12x12 devices only. (5753, 5753m, 5753f, and 5781)
    For other devices, since we don't know how it would impact the
    existing design, no change is made for those devices.    
 Version 3.35 ---- 10/8/04 
1. Removed GPIO2 driving for 12x12 devices

    After detecting VMain is off, if the configuration is set to be NIC, 
    bootcode was driving GPIO2 low.
    Software bug.
    Removed the code to drive GPIO2 for 12x12 devices.
    This change will only effect 12x12 devices. (5751, 5753m, 5753f, 5781)
2. Fixed power down problem for 12x12 devices

    When WoL and ASF are disabled and losing VMain, bootcode was not able
    to shutdown the device.
    Bootcode was looping forever to check PCI Power Present bit. PCI Power 
    Present bit does not exist in 12x12 package.
    Fixed the bug.
    This change will only effect 12x12 devices. (5751, 5753m, 5753f, 5781)
 Version 3.34 ---- 10/4/04
1. Enable ASIC bug fixes by default

    Since many of the ASIC bug fixes are verified and validated by ASIC
    team, bootcode is changed to enable those verified fixes by default.
    In addition to data-fifo-protect fix enabled in v3.32, #3,
    enabled CQ9583_FIX, CQ9804_FIX, and CQ10362_FIX. 
    CQ10362 is enabled by default by ASIC; therefore, it has been always
    CQ9321 is not enabled in this version.  
2. Changed default VAUX cut off delay time value.

    In NIC, when WoL is disabled and turning off VMain, firmware takes 
    5 seconds to cut off VAUX. 
    In NIC, when WoL is disabled and device loses VMain, bootcode will
    use circuit to cut off VAUX instead using power-down bit in register.
    This can save more power than using register power-down bit.
    The bootcode is designed to have adjustable VAUX cut off delay 
    parameter in feature configuration. (NVRAM offset 0xc4, bit 23,24)
    It can be set to delay 250ms, 150ms, 100ms, or 50ms. By default,
    it is using the longest delay 250ms.
    5705 family devices core clock is slower than 5702/3/4 devices,
    in combination of slow clock mode, 250ms became 5 seconds.
    1. Changed the delay time 5 seconds back to 250ms. 
    2. Changed the default value to be no delay.
    In order to have the default value changed, the secfg command must
    be used to program the bootcode. Upgfrm command will only update
    the bootcode but not the configuration.
3. Extension to v3.33, #1 fix

    Version 3.33, #1 bug fix was not complete. Just disabling 
    powerdown pll (bit 4 of 0x7d00) was not good enough.
    It still showed same problem.
    Other state machine also needed to be disabled to prevent to failure.
    By disabling bit 0, 1, 2, and 16 can solve the problem.
    bit 16: Disable Power Management Control.
    bit 2: Disable transaction layer power management
    bit 1: Disable data link layer power management.
    bit 0: Disable physical layer power management.
4. Initial release for 5753, 5753m, 5753f, and 5781    
 Version 3.33 ---- 9/27/04
1. Fixed device disappearing problem

    After the numerous testing of hibernate or standby from Windows, 
    the device may disappear.
    There was a race condition between the CORE_CLK switching & the PLL
    powerdown logic. In rare condition, PCIE PLL is powered down first
    before device switching to CORE_CLK mode for all the internal PCIE
    function, this will cause device to lock-up until cold reset. 
    Not to powerdown pll when the device goes into the D3C state.
  Side effect:
    The device will consume higher power consumption, but it is still
    within 375mA limit.
2. Added SST 1MB non-buffered flash (SST45VF010) support

     Added SST 1MB non-buffer support. Same as SST 512KB,
     no VPD write is supported.
   The following is the supported NVRAM summary:
   SO:   Bit 25, Flash Size,     internal pull-up 
   SI:   Bit 24, Protected Mode, internal pull-down
   SCLK: Bit 1,  Buffered Mode,  internal pull-down
   CS:   Bit 0,  Flash Mode,     internal pull-down

   [SO,SI,SCLK,CS] Device         Write         Memo         
   --------------- -------------- ----- ----------------------------
        1000       AT24C512        Yes  SEEPROM, AT24Cxxx, any size
        1011       AT45DB011B      Yes  Atmel Buffered 1MB Flash
        1001       SST SST45VF010  No   SST Non-Buffered 1MB Flash
        0001       SST SST45VF512  No   SST Non-Buffered 512KB Flash
        1101       ST M45PE80      Yes  ST 8MB Flash
 Version 3.32 ---- 9/23/04
1. Added SST 512KB non-buffered flash (SST45VF512) support

    Added SST 512KB non-buffered support; however, due to the size of the
    buffer is needed to perform a write, VPD write function is not
    If VPD write operation is attempted, it will simply return
    completion status without any action.
2. Added 12x12 package support

    New 12x12 package now is supported.
    As the version branch, b is used to indicate 12x12 bootcode.
    For example:    
      ee5751c3.32a  -- 15x15 package bootcode.
      ee5751c3.32b  -- 12x12 package bootcode.
3. Enabling Data FIFO bug fix

    This ASIC bug fix has been enabled from driver; however,
    due to the nature of the bug, enabling from driver may not 
    be reliable. 

    Enabling this bug fix in bootcode.
 Version 3.31 ---- 9/3/04
1. Enhancement

   Advertise L1 ASPM capability.
   The changed is made to set bit both bit 10:11 of register 0xdc. 
   Note: This change is only 5751m; therefore, the release is only 
         made for 5751m and 5751f.
 Version 3.30 ---- reversed

   Due to the WoL problem found with the workaround item #1 in v3.30 in 
   Windows OS, the decision is made to remove the workaround. All v3.30 
   releases are removed from release directory.
   The change in #2 is kept. Any version newer than v3.30 will not have
   any static routines.  
 Version 3.30 ---- 7/13/04
1. Applied extension of workaround for CQ#9901.
   Fixing/Affecting: CQ#10452, CQ#10509, CQ#10510

    In Linux system, when unload driver, may cause system to generate
    NMI, hang, or shutdown.
    This problem (CQ 10510) is not seen on all systems, but has been 
    observed on a system that uses the Intel Lindenhurst chipset when 
    running the Linux 2.6 kernel. This problem (CQ 10510) has never been 
    observed under Windows on any system.

    In Linux system, when driver request OS to put device to D3Hot,
    there is another PCI config read from 0 followed right after the 
    write to 0x4c with value 3.
    Since the moment our device is put to D3Hot state, our device enters
    L1 state; therefore, the read command data is generated but pending
    due to L1 state and cause bus to choke.
    In PCI-E spec (section 5.6.1) requires host SW to not access a device 
    for 10ms after it is put into a D3hot state, and that this bootcode 
    change is needed to workaround a scenario where the newer Linux 2.6 
    kernel does not follow the PCI-E standard.     
    Put a new algorithm to delay the entering to L1 state. 
    When in D0 state: We disabled state machine from entering L1 state.
    When in D3 state: We wait for at least 10us, then enable state machine
                      to enter L1 state after the read command completes.
    This workaround works only when firmware is still running. It is proven
    to be working in Linux system; however, in Windows driver case, since
    the firmware is halted while shutting down. This workaournd will not
    This fix does not affect 5750 device.                           

2. All "static" routine has been changed to public routine from this version. 

    A compiler problem has been found in ASF/IMPI firmware code. As precaution,
    all static routine has been changed to public routine to prevent possible
    compiler error. 
 Version 3.29 ---- 6/22/04
1. Fixed CQ#10407, CQ#10386 problem in Linux system

    When driver is putting the device into D3Hot state in Linux
    system, the system may intermittently hang. 
    Immediately after driver writes 3 into offset 0x4c to place
    device into D3Hot state, Linux system performs a config read
    from offset 0. Since our device will go to L1 in D3Hot state,
    it needed to come back to L0 state to comply to the config
    read. If the read cycle was too soon, our device may not sync
    up the link with the chipset and cause system to hang.
    In addition to the workaround applied to CQ#9901, v3.27, item #1,
    using value 0 instead 1 in tx_idle_min_time will reduce the L1 to
    L0 turn around time from 44ns to 36ns. Within shorter window, it
    fixed the problem.  

 Version 3.28 ---- 6/9/04
1. Applied workaround for CQ#10304

	When the system transitions from VMain to S5 with WOL enabled, the
	transition from Windows to S5 results in a lower power consumption
	compared to the transition from DOS to S5.
    The Windows shutdown involves setting of the PCI Config Power Management
    register (to D3 HOT state) before shutting off the VMain.  This action 
    causes the ASIC to shutdown certain PCIE Serdes related logic, hence
    the power consumption is lower.  Where in the DOS shutdown, the PCI Config
    Power Management register was not set, hence after the VMain is cut-off,
    certain PCIE Serdes logic remains active, hence consume more power.

    Modify the bootcode to monitor the PowerPresent status bit, when detected
    the VMain went away, the bootcode turns off PCIE Serdes Tx and Rx blocks
    and lowered the power consumption by about 80mA, which bring the total
    power consumption (in both OOB and VMain->S5 case) to below 375mA.
    Note, there are certain blocks of logic cannot be disabled without setting
    the PCI Config Power Management register (to D3 Hot state).  When shutting
    down the system from DOS, bootcode can only disable PCIE Serdes Tx and Rx blocks,
    therefore, the power consumption will be different between the two (shutting down
    from Windows vs. shutting down from DOS).
 Version 3.27 ---- 5/26/04
1. Applied workaround for CQ#9901

    If the link partner requests an exit from the L1 state immediately 
    after the L1 state is entered, the power management state machine 
    may lose sync with the link training state machine, resulting in a 
    system hang.  
    The signal which indicates that the link training state machine is 
    in the L1 state is only asserted for 4ns.  The signal must be sampled 
    by the power management state machine, which runs on an 8ns clock 
    period. If the power management state machine does not see that the 
    link training state machine went through L1, then the system may lock up.  
    Change the default value of tx_idle_min_time at 0x7e34 bit [15:8] from 
    0x5 to 0x1, and set the 0x7e34 bit 30 to 1. 
2. Optimized for L0s exit latency 

    When system enables L0s, our default value for L0s exit latency could be
    adjusted for better performance. By fine tuning this, we could improve
    5751M performance.

 Version 3.26 ---- 5/10/04

1. Enabled fixed for idle ordered set in B0

  Problem: (ECDs #9535 and #9413)
    When connected to MCH, there is an issue when going to D3Hot. 
    One of the synptom is when changing advanced properties in 
    Windows, the device will be disappeared or no wake-up from S1.
    The 5751 receiver fails to detect an electrical idle ordered set 
    if it is sent after a partially completed DLLP or TLP.  This causes 
    the link training state machine to see an unexpected electrical idle 
    and transition to the recovery state instead of the L0s, L1 or L2 state.
    As result, the chip resets.
    ASIC has this fix in A3 or later silicons. In b0 or A3, by default it 
    is not enabled. Bootcode is changed to enable the fix upon reset.      

 Version 3.25 ---- 5/5/04

1. Fixed disabling device LED problem

    After writing 0xdeaddead to put down the device, possibly LED can be
    left on.
    Depending on the moment the device is shutting down. The LED state
    will freeze as is. When is was on, it would be left on.
    Forced LED to be turned off before shutdown.
2. Enable PXE only when PXE image exists

    System may hang when PXE is enabled without PXE image.
    Due to user error, it is possible PXE is enabled without image.
    Bootcode was enabling PXE based on enable/disable. As result,
    bootcode is returning garbage.
    Advertise PXE only when there is PXE image and PXE is enabled.

3. Added new support for Flash ST M45PE80 part

   Added new support for Flash ST M45PE80 part for VPD write routine. 
   M45PE80 uses M25P10-A pin straps.
   [SO,SI,CS,SCLK] = 1110
   SO - internal pull-up, no need to pull-down
   SI - internal pull-down, need to pull-up
   CS - internal pull-down, need to pull-up
   SCLK - internal pull-down, no need to pull-up. 
 Version 3.24 ---- 04/30/04

1. Fixed disabling device potential problem

    Shutdown signature potentially could be over written by phase 1 bootcode.
    This problem should not happen normally. However, for any reason, if the
    Shutdown signature, 0xdeaddead, were written before phase2 bootcode 
    loading up, it will be over written by negate of reset signature by 
    phase1 bootcode.
    Put a check in phase 1 bootcode to not to write negate of signature if 
    there is Shutdown signature present.
2. Initial version for 5751f and 5789.          
 Version 3.23 ---- 4/27/04

1. Removed debugging blinking

    A debug blinking has left in version 3.22. As result, every time when 
    there is reset, LED will be blinked 5 times.
    Removed the blinking.
2. Fixed NIC disabling device feature problem

    For NIC, after writing 0xdeaddead to disable the device, the device shuts
    down correctly; however, when VMain goes away, the device will be out of
    shutdown mode and consume more power than desired.
    When VMain goes away, switching to VAUX power, the WoL circuit generated
    a hard reset to the device. As result, the device is out of shutdown mode.
    Drive GPIO2 low before shutdown. This will switch power supply from VMain 
    to VAUX smoothly. When VMain goes away, since we are already in VAUX power, 
    the hardware will not generate a reset to the device.

 Version 3.22 ---- 4/26/04
1. Fixed disabling device feature

    The feature added in v3.21 to disable the device was not working 
    After disabling PCI-E clocks, CPU was polling power-down bit; however, 
    when device lose VMain, it generated reset and cause CPU not to able to 
    power down the device.
    Disable PLL first and then power down the device immediately. 
    Putting the device to D3Hot state is not needed. As soon as the value 
    0xdeaddead is written to shared memory 0xb50, the device will be powered 
    down immediately. Only a system reset or AC power plug/unplug can bring 
    back the device once it is disabled.
 Version 3.21 ---- 4/23/04
1. Added disabling device feature

    Some customer requested a mechanism to 
      (a) disable the NIC via software control and 
      (b) the NIC will consume lowest possible power when disabled.
    A mechanism is provided to the host by writing a hex value of 0xdeaddead 
    into NIC's shared memory at location 0xb50 prior to NIC reset.  The 
    bootcode is implemented to continuesly monitor this special hex value, 
    if detected, the bootcode will disable the NIC device on the PCI bus, 
    which causes the NIC to become invisible to the Host in the subsequent 
    PCI bus scan.
    Furthermore, before the bootcode disables the device, the firmware will 
    program the device to a lowest possible power consumption level to save 
    system's power supply.
    To disable the device (from HOST), write a hex value 0xdeaddead to 
    shared memory location 0xb50 (use pci config cycle, memory access).
    A subsequent "hard reset" to the NIC, such as "PCI Reset" or "Power 
    On Reset" without writing the hex value 0xdeaddead will cause the NIC 
    to resume its normal operation.
    This change only affect PCI-E devices (5751, 5751m, and 5721).
    There is no change between v3.20 and v3.21 for 5750.
 Version 3.20 ---- 4/21/04
1. Added blinking feature when loading ASF code failed.

    Loading ASF failure case has been seen on certain system.
    In order to indicate loading ASF failed, blinking LED feature has been 
2. Fixed ASF code/phase two bootcode loading bug

    Depends on size of bootcode or ASF code, ASF code or Phase-Two bootcode
    code could not be loaded.
    When the last word of the image falls to NVRAM offset 0xXXXX00. The 
    NVRAM read command was set incorrectly. Both First and Last bit should 
    be set when reading, but only Last bit was set.
    Fixed the algorithm.         
 Version 3.19 ---- 4/19/04
1. Applied the workaround for higher BER problem

    On certain corners, bit-error-rate(BER) was higher then desired
    when cable length was 70m or less.
    By increasing hybrid bias current can reduce the BER. 

2. Removed ClockRun Enable

    Upon reset, the BroadSafe clock was disabled when mini-pci configuration
    bit was set.
    5703 A3 or later and Shasta has removed the clock-run enable bit.
    clock-run always enabled. In Shasta, this bit has been redefined 
    to disable BroadSafe clock. As result, if user configured the
    device as "mini-pci", BroadSafe clock would be disabled.
    Clock-Run enable function has been removed from Shasta devices.   
 Version 3.18 ---- 3/29/04

1. Added Shared Traffic/Link LED mode LED control workaround

    In Shared Traffic/Link LED mode, Speed LED/Traffic LED will not work 
    unless if driver is loaded. 
    Hardware design was using signal from MAC control registers to control
    the LEDs. The MAC registers require driver initialization; therefore, 
    without driver, the LED will not work. 
    Initialize LED mode to phy1 mode to source the signal from phy block 
    instead of MAC and change phy LED control register in phy to change the 
    LED behavior to act like Shared Traffic/Link LED mode.
  Side effect:
    By doing this, the LED mode will be phy1 which can confuse the application
    software. The application software will have to know exactly what mode it
    is from the configuration and apply the same workaround whenever there is
    phy reset. Another option is override the LED mode back to Shared Traffic/
    Link LED mode when driver is loaded. 
2. Changed to advertise the supported MPS of 128
    After OS/2 was loaded , running cctest from a server will hang system.
    By hardware default, we advertise we support up to 4k in size. With Intel 
    PDK systems, it negotiate to 512 bytes. For some reasons, the size
    512 lock up the system. 
    Changed to advertise the supported MPS to 128 bytes. This workaround 
    applies to PCI Express systems only. It does not apply to 5750.   
 Version 3.17 ---- 3/23/04

1. Load ASF code in 256 byte block

    When ASF is enabled, the ASF code was loaded in one big block.
    This will result in BroadSafe starving from NVRAM access.
    Phase one code loading phase two code did follow the 256 byte
    block read; however, phase two code loading ASF code was not.
    Change to read NVRAM 256 blocks and release the arbitration
    before loading the next 256 blocks.
2. Fixed the cause for b57diag cputest (C2) failure
    When running b57diag, cputest was failing if the test was
    was running after B4 (mbuf memory test).
    Version 3.16 had a bug that a variable was used unassigned.
    After the mbuf memory test (b4), the memory is left with test
    pattern of aa55aa55. The bootcode was using the variable as
    a pointer to reference 32 bit value. Since the value aa55aa55
    is not word aligned, it caused internal CPU to have data alignment
    error and CPU is halted. 
    Initialized the variable before use.
3. Slowed clock in WoL mode

    The v3.15 fix to slow down the clock on WoL was not functioning.

    Since Clock Control register is in PCI config. space, the legacy 
    devices could not touch the register to slow down the clock when 
    it detected VMain is out. The code was skipping  clock control 
    register access. For PCI Express devices, we could access at any
    time, therefore the power status check is no longer needed.
    For PCI Express devices (5751, 5751m, 5721), it will configure
    Clock Control register to slow down clock regardless of the power
 Version 3.16 ---- 3/17/04

1. Modified config. space access for PCI express devices

    Always access PCI config space for PCI express devices
    For the legacy devices, PCI config space was not accessible during
    VAUX only state. Therefore, the pointer to config. space will 
    point to a variable instead hardware address to prevent from 
    hardware access in VAUX only state. (Otherwise the code will hang)
    In PCI Express, the config. space is always accessible even if the
    PCI Main power is not there. Therefore, the code now is changed for
    PCI express devices to access hardware PCI Config space unconditionally.

  Note: This change does not affect 5750 bootcode.

2. Changed to Shared Memory Structure 2.

    Added more hardware information in offset 0xd2c, hwinfo0 field. 
    New defines: Bit 8:15 = device id. 
    In detail:
    Bit 8:10  Sub Device ID
    Bit 11    Serdes
    Bit 12:15 Device Family 

3. Added new support for future Shared Traffic/Link LED mode.

    The Shared Traffic/Link LED mode setting specification is changed. For
    any future ASIC will have to use new setting. 
    Same as Combo LED mode before, the Speed LED was not working properly
    unless if driver is loaded. Since the LED control was controlled by MAC
    registers, unless the registers was initialized by driver, it would not
    function properly. This means, without driver, such as in DOS mode, the
    speed LED will not indicate correct speed.
    The Shared Traffic/Link LED mode setting now is changed as follow:
    Chip Rev.          LED Control Reg. [15:11]
    ---------         -------------------------
    A0/A1:                      01000
    Any other revision:         01011

    This version of firmware will look at the chip revision, programs the 
    corresponding setting based on the revision. 

 For Version 3.15 or earlier's release history, 
 please see version 3.15's release.txt.
Download Driver Pack

How To Update Drivers Manually

After your driver has been downloaded, follow these simple steps to install it.

  • Expand the archive file (if the download file is in zip or rar format).

  • If the expanded file has an .exe extension, double click it and follow the installation instructions.

  • Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.

  • Find the device and model you want to update in the device list.

  • Double-click on it to open the Properties dialog box.

  • From the Properties dialog box, select the Driver tab.

  • Click the Update Driver button, then follow the instructions.

Very important: You must reboot your system to ensure that any driver updates have taken effect.

For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.

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