releases.txt Driver File Contents (

         Release Note for Jade/Caesar Bootcode Firmware
              5787, 5787f, 5787m, 5754, 5754m, 5786

 Version 3.26 ---- 6/20/07
1. Serial number get changed issue 

  The workaround for CQ#28997 in V3.25 only restores 0x164[31:28] and 0x168[7:0] after setting bit 23 of 0x7c04.
  In this release, the entire 32 bits of 0x164 and 0x168 will be restored.

 Version 3.25 ---- 6/19/07
1. Serial number get changed issue

  Problem: CQ#28997
    The serial number in offset 0x164/168 get changed after reset. As result, OS will
    treat our device as new device in the system. 
	Under certain corner cases, the Reserved bits of 0x164[31:28] or 0x168[7:0]  may not have default value set correctly.  

    Firmware will write back the hardware default value after setting bit 23 of 0x7c04. 
 Version 3.24 ---- 12/29/06
1. Remove "L1 PLL Power Down" as a configurable option in NVRAM
  Enhancement: (CQ#27936)
    Remove the "L1 PLL Power Down" feature (CQ#27236) as a configurable option in NVRAM

2. Fixed Timer Prescale value such that the timer tick will be 1us

  Problem: (CQ#27938)
    Currently, one timer tick will take 2us with the default Timer Prescale value in register 6804[7:1].  
    The default Timer Prescale value 0x7f has been used and has not been adjusted correctly.   
    Changed the Timer Prescale value to 65 in register 6804[7:1].

    This fix will impact the timing of execution of bootcode for 5705 and newer devices.  

 Version 3.23 ---- 11/28/06 
1. Fixed NVRAM read bug

    Due to other project change, since version 3.22, shared_config was read
    NVRAM access FIRST/LAST bit can only be used in consecutive addresses.
    When reading configurations from offset 0xc4,0xc8 and 0xdc, 0xdc could
    not be read in one bulk read. 
    Shared_config 0xdc was read separately from previous bulk read.
 Version 3.22 ---- 11/07/06 
1. Improve Enhancement Request CQ#27236
    This version adds logic to read configurable option from the NVRAM for 
    allow/disallow SerDes PLL power down feature.

    V3.21a Bootcode for 5787M is obsoleted.

2. PCIE Link Polarity

  Enhancement: CQ#27039, CQ#26767, CQ#27105
    Apply PCIE Link polarity workaround only at hardware reset (POR or 
3. Improve PCIE SerDes PLL Power Down Feature

  Enhancement: CQ#27236 
    Poll the actual clkreq state at 0x68A4[2] and Gphy link status at 0x460[3]:
    a. If 0x68A4[2]=1 and 0x460[3]=0, then enables PLL power down by writing 
       0x7d54 with 0x7000. 
    b. Else, then disables PLL power down by writing 0x7d54 with 0x7080.
    This enhancement is only applicable to 5787M.  

4. Increase the Fast Training Sequence(FTS) timming
  Problem: CQ14315
    If L0s is enabled on the BRCM chip a "yellow bang", or a system hang 
    condition can occur.
    During the L0s to L0 exit transition, symbol lock can be lost if the 
    system reference clock has not fully stabilized what leads the PCI-E 
    link training state machine to go through the "detect" state.  Going 
    through "detect" causes an internal reset to the BRCM chip what causes 
    "yellow bang" and/or a system hang condition based on the chipset 
    1. Change Serdes RX Timer from 768 ns to 2 uS to make sure the 
       Serdes CDR is stable before it sends data to the Physical Layer.  
    2. Increase FTS Count from 1uS to 2.25 uS to avoid intermittent GRC 
       Reset when L0s is enabled.
    Since RX Timer value and FTS Count change only needed before PCIE link 
    training, bootcode will initialize those values and retrain the PCIE 
    link during cold reset only. When driver reset, this workaround is 
    bypassed to avoid PCIE link retrain. 
    Increasing the amount of FTS required to transition from L0s to L0, 
    performance impact between 1uS to 2.25uS is un-noticeable.
 Version 3.21 ---- 10/24/06 
1. Improve PCIE SerDes PLL Power Down Feature in conjunction with clkreq being enabled.
  Enhancement: CQ#27236 
    Poll the actual clkreq state at 0x68A4[2]:
    a. If 0x68A4[2]=1, then enables PLL power down by writing 0x7d54 with 0x7000.
    b. if 0x68a4[2]=0, then disables PLL power down by writing 0x7d54 with 0x7080.
    This enhancement is only applicable to 5787M.
    There are 2 version of boot code for 5787M. 
    One is V3.21 and the other is V3.21a. 
    V3.21a has this enhancement enabled.
 Version 3.20 ---- 10/09/06 
1. L1 exit latency improvement
  Enhancement: CQ#27044
    Improve the L1 exit latency when Clock Request is enabled.
    No change for non-Mobile parts.
 Version 3.19 ---- 10/05/06 
1. Enable Clock Request
  Enhancement: CQ#26951 
    The clock request was disabled in version 3.18 for CQ #26629 for Mobile parts. 
    Change to use h/w default setting.

 Version 3.18 ---- 9/15/06 
1. Disable Clock Request
  Enhancement: CQ#26629
    The clock request enabled feature is not fully tested. This feature needs 
    to be disabled for RC 10.0 release.
    The ClockReq is automatically disabled by h/w on a non-Mobile parts; therefore,
    this change does not affect non-Mobile parts.

2. Link speed issue

  Enhancement: CQ26652
    We have compatibility issue with Intel NIC Intel Pro/1000MT based LOM 
    (NDIS5.1 8.5.14, Auto detect for Speed/Duplex parameter, Windows XP 
    Professional SP2 O/S). The symptom shows when WoL is disabled and there
    is no management firmware loaded, after first time power up, the link 
    partner settles at speed 10H where our device settle at 1000F after the 
    link negotiation. To workaround the issue, bootcode is changed to use 
    different method to initialize the phy. 
    This issue exists not only in this device but all NetXtreme I products.  

 Version 3.17 ---- 7/27/06 
1. Set the voltage limit to prevent VCO control out of range.

  Problem: (CQ25114)
    VCO control voltage will go out of range. 
    ASIC default value has been changed. 
    At power up, the firmware is required to prevent SerDes PLL VCO control
    voltage goes out of range. Firmware will change the PCISerdes register,
    port 0x29, reg. 0xd default value back to 0x102d.
2. Removed disabling of ClkReq.

  Enhancement: CQ26097
    Since version 3.10 disabled ClkReq., we could not test ClkReq function. 
    Per project lead's decision, the feature was disabled before validation.
    However, without enabling it, PQA will not be able to test it. Therefore,
    we will enable this feature. 
    The change is made so firmware will not touching register 0xdc. The value
    to advertise ClkReq feature will be based on the hardware default.
    The ClkReq is enabled only in Mobil devices. 
    Since chip revision A0 and A1 had a bug in ClkReq and hardware default for
    mobile devices are enabled, programming this firmware to A0, A1 revision 
    chips can cause some problem.
    Bootcode's change may also get over written. Updated driver should be used
    to ensure the function is enabled. (Refer to CQ26098 to find out the
    correct driver version that address this issue.)  
 Version 3.16 ---- 7/25/06 
1. Wrong revision.

  Problem: (CQ26037)
    The chip revision posted in Shared memory 0xd2c was incorrect.
    Bug introduced in version 3.15. The metal revision mask was changed 
    by other project incorrectly.
    Changed back to the correct mask.
    Any revision sensitive routines or workaround was affected by this.
    One example is ASF firmware: when ASF is enabled, the firmware
    will based on wrong revision to initialize GPhy incorrectly. As
    result, the link disappears. 
2. Changed VPD default Product String

    Per MRD requirement, the VPD default product string is now changed from 
    "Broadcom NetXtreme Gigabit Ethernet Controller" to "Broadcom NetLink
    Gigabit Fiber Controller". For 5787f, the string is changed to 
    "Broadcom NetXtreme Fast Ethernet Controller"
    Any application uses product string based on VPD data, the string will 
    be changed.
3. Cable Sense Support

    The GPhy was shutdown even if the cable sense mode is enabled.
    Coding error
    Changed the code so it does not power down the Gphy if cable
    sense mode is enabled.
4. Changed Shutdown routine

    The original was taking many steps to shutdown each component
    separately before shutting down the chip. For Jade, the ASIC is
    designed to shutdown all blocks once the device shutdown bit is
    set. Therefore, to save code space, the code is changed to 
    shutdown the device simply by setting the shutdown bit.
5. Turn off Cable Sense issue

    Once the Cable Sense was turned on, it could not be turned off until 
    the next power cycle to the chip. 
    The Cable Sense mode was cleared on by POR only. Since the bootcode only
    turns cable sense on when it is enable, assuming any reset would clear
    Cable Sense configuration, it was not clearing the configuration until
    the next power cycle.
    Not just turn on but also turn off the configuration according to the
    NVRAM setting.             
6. Enhanced Force PCIE polarity workaround algorithm
    Bootcode may not work under certain platform under special condition.
    Please refer to CQ#25290 for the detail of the particular platform.
    If the device is placed in a system violates the specification - with
    VMain present and holding PEReset asserted. (Some platform use this method
    to disable the LOM by BIOS) The device may get stuck in forever loop in 
    PCIE polarity workaround algorithm implemented in version 3.07.
    Added one second timeout when waiting for stable PCIE link. The bootcode
    will advance when the timeout expires.    

 Version 3.15 ---- 5/15/06 
1. Change phy settings for better link detection.
  Enhancement: CQ24525
    Shut off SMDSP clock after programming the Tab registers.
2. Enabled second phase fastboot feature

    Only the first phase bootcode NVRAM loading is bypassed with the older
    bootcodes. Starting with this version, the second phase is also pre-
    reserved and NVRAM code loading is bypassed. 

    Since the bootcode is no longer reload from NVRAM, the boot time will be
    much faster. Upon reset, there will be only few words of configuration 
    NVRAM access.  
 Version 3.14 ---- 3/22/06 
1. Changed SSID
  Enhancement: CQ#23848
    For Jade devices, bit-15 of SSID needs to be set to 1.
    There is no impact/change for Caesar devices.     

 Version 3.13 ---- 3/07/06 
1. VPD-R checksum error

  Problem: Related CQ#23565, CQ#23566
    VPD-R checksum was incorrect
    Checksum was calculated from VPD-R to the end of VPD-R region; however,
    the specification indicates that Checksum should be calculated from the
    offset zero.
    Corrected the checksum
2. Initialized Cardbus pointer register

  Enhancement: CQ#23431
    Since Cardbus support is no longer a requirement, in order to pass
    the plug-fest compliance test, we write zero to register 0x28 to disable
    cardbus feature.
 Version 3.12 ---- 2/09/06
1. Enable PEReset Mask
      On certain systems, when entering S5 state (with WoL enabled), the 
      LOM current draw on the 1.2V rail can fluctuate between ~90mA and 
      ~150mA from shutdown to shutdown.

      On certain systems (with WoL enabled), the 5754/A1 LOM may disappear 
      during repeated S5 Power-Cycle tests.
    As part of the bootcode f/w logic, the NIC f/w will make access to 
    certain registers (0x00-0xff and 0x7c00-0x7fff) when the firmware 
    detected that the Vmain power goes low.  Due to CQ23039, the register 
    bit that the firmware used for detecting the "Vmain power state" can 
    also toggles between logical '0' and '1', and this leads to f/w to not 
    able to make reliable read/write access to the registers (0x00-0xff and 
    0x7c00-0x7fff), which ultimately causes bad behaviors that is described 
    in CQ22684.
    Firmware now enables the PEReset Mask register bit (0x68a4[16]=1).  By 
    enabling this register bit, the chip exits the reset state after the 
    current fluctuation become stabilized, which eliminates the toggling of 
    the "Vmain power" detection register bit, which ultimately enables 
    successful access to the register (0x00-0xff, 0x7c00-0x7fff) by the f/w.
    Fixes CQ#23039 and CQ#22684.

 Version 3.11 ---- 1/24/06
1. Changed CQ#22832 fix

  Problem: CQ#22832
    The CQ#22832 request to change 0x7d00 access to read-modify-write still
    have problem on some system when reference clock is not stable. 
    Absolute-write may corrupt register 0x7D00 content under corner conditions.
    Changed to code to not to touch 0x7d00 at all. 
    There is no impact if the WOL feature is not enabled in our device. There
    is also no impact if the system always broadcasts PME_Turn_Off tlp message
    to downstream before it removed the main power in system OOB or hibernate 
    There is little power consumption increase when a) WOL is enabled in our 
    device and b) the system ungracefully removes the main power without 
    sending out PME_Turn_Off tlp message to downstream in system OOB or 
    hibernate scenario. The current draw in our device is measured at 236mA 
    as compared to 172mA before this change. 
    Since there is no more 0x7d00 access, version 3.10, #4 (Enabled ASIC 
    fix for CQ#11011), is undone. Using hardware default value. 

2. Enabled ASIC fix for tx Ethernet packet corruption on late collision

  Enhancement: CQ#22908, CQ#14561, CQ#14521
    Since the ASIC is fixed and verified by ASIC team, we are enabling the
    fix in this version.
 Version 3.10 ---- 1/18/06
1. Disabled clkreq#

  Enhancement: CQ#22829
    Disable clkreq# for all the revision of the Mobile parts until the feature 
    is fully verified with engineering system. This is done by clearing bit 18
    of 0xdc and bit 8 of 0xe0. 
2. Changed 0x7d00 access to absolute write

  Problem: CQ#22832
    A value of 0xa000 was left in register 0x7d00 and caused the device to 
    When the device was put into D3 power state, due to the clock issue, the 
    PCIE registers become not accessible. If read-modify-write were used at
    this point, the read will fail and returning zero to CPU. Then, after
    CPU modify the content and write back, many critical bits are cleared in
    register 0x7d00. As result, the subsequence reset, the device could not
    establish PCIE link and disappears from the host. 
    Changed 0x7d00 register to absolute write instead of read-modify-write.
3. Changed revision reading

    CPU reads incorrect silicon revision id in D3 power state.
    In D3 power state, except OOB, the PCI/PCIE registers are not accessible.
    All reads returns zero. Because of this, the read is not reliable.
    Instead of reading from register 0x68, the code is changed to read the
    revision id from register 0x2018. The register 0x2018 is available at all
4. Enabled ASIC fix for CQ#11011

    The decision has been made to enable this ASIC fix to be consistent with
    Shasta/Baxter. This is done by clearing bit 18 of 0x7d00.          
 Version 3.09 ---- 1/09/06
1. Changed 2.5V voltage regulator value

    The DVT tests with Jade A1 parts indicate that the 2.5V regulator default 
    output is low. Bootcode now will change the 2.5V regulator so it is close
    to 2.5V.
2. Enable clock request for A2 or newer revision

    Due to the ASIC bug, the clock request was disabled in version 3.03, #2. 
    Since this feature has been fixed in A2 or newer revision, starting this 
    version, the clock request will be enabled back for A2 or newer devices.
 Version 3.08 ---- 12/08/05
1. Fixed device disappearing issue

  Problem: CQ#22330
    When VMain is turned off, either from OOB case or turn off the system by
    power button, next boot, the device disappears to the host.
    The workaround logic put in v3.07, #1 to force PCIE link polarity
    requires to wait until the link is up when there is VMain. However,
    the PCIE Tx/Rx was turned off when bootcode sense there was no
    VMain to save power. On next boot, since the code to turn back on
    PCIE Tx/Rx was placed after the PCIE link polarity workaround to wait 
    for PCIE link, the link never came up and stuck in the loop forever. 
    Moved the code to turn on PCIE Tx/Rx prior to PCIE link polarity
 Version 3.07 ---- 12/06/05
1. Force PCIE polarity

  Problem: CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254
    In some platform, the PCIE link polarity comes up incorrectly. 
    ASIC could not handle all cases correctly.
    Wait until PCIE link comes up. Then based on the link polarity status
    detected by ASIC polarity auto detect, firmware will then force the 
    PCIE link to the correct polarity.
2. Enable refclock auto switching

    The workaround in version 3.06, #1 is not stable. CPU could read "good"
    link indication without REFCLK. 
    Without clock, the interface can timeout and return anything left in
    the data bus. 
    Enable auto clock switching. When enabled, the clock will automatically
    switched to internal clock when there is no ref. clock available.
3. Removed ref.clock advertisement in A0/A1.

    When ref.clock support is advertised, the device gets unwanted reset.
    If clkreq# enabled, it may intermittently caused SerDes PLL state machine 
    misbehavior and lead to GRC reset.

    This problem will be fixed in ASIC A2. For A0/A1, firmware will disable
    ref.clock advertisement.                   
 Version 3.06 ---- 11/22/05
1. Fixed WoL was not working issue.

  Problem: CQ#14614
    WoL was not working on OOB case. 
    Version 3.03 (#1) added workaround for platforms that show an unstable 
    PCIE refclk during power up. Nevertheless, there is a limitation to 
    this workaround as to where it requires VMAIN to be present. In systems 
    where there is no VMAIN present and there is no PCI-E REFCLK at all for 
    the cases outlined above the bootcode will loop forever, therefore not 
    enabling WoL.
    Added a condition to the "unstable PCI-E Refclk" workaround to apply
    this fix only when there is VMain present.  In cases where there is no 
    VMAIN present, the boot code will no longer check/wait for a "stable 
    PCI-E Refclk" before continuing.
2. Fixed Link Histogram Issue.

    In DVT testing, Link histogram results seemed to be worsen in bootcode
    version 3.05.
    The change in version 3.05, item#2, removes all Gphy workaround.
    The workaround included hybrid bias change, adc  bias change, and pll 
    startup bandwidth change. The hardware fix still have incorrect PLL
    startup bandwidth value. By removing the workaround, the sympton has
    showed up. 

    Added the adjustment for the PLL startup bandwidth.    
 Version 3.05 ---- 10/18/05
1. Fixed Cable Sense mode

    The Cable Sense mode was not enabled correctly. 
    There was a confusion between SuperAirplane mode and Cable Sense mode.
    SuperAirplane mode with GPHY configuration should be equivalent to 
    Cable Sense mode. The previous, version 3.04, was setting SuperAirplane 
    mode without configuring GPHY. Therefore, it would not function as Cable 
    Sense mode.
    Instead of using SuperAirplane mode (bit 25), now the code will use
    Cable Sense mode (bit 26) so it does not need to program GPHY.
2. Not to apply poor BER performance work around

    The work around for poor BER (Bit Error Rate) with cable length 70m or less
    was causing the problem.
    For 5754/5787 family, the BER problem has been fixed in ASIC already. If the
    work around was applied, by changing hybrid bias current, would yield the
    unwanted current.
    Removed the work around     
 Version 3.04 ---- 10/12/05
1. Fixed Cable Sense mode

    The Cable Sense mode could not be enabled.
    The bit to check for mobile part was wrong. 
    Changed to correct way of detecting mobile part.
2. Move GPIO initialization to Phase1 code

  Problem: CQ#14105
    Unexpected POR was seen at Windows S3/S4 shutdown when using 64k
    Originally, activating VAUX power was done in phase 2 bootcode.
    However, once driver waited for phase1 signature, driver may
    start to configure GPIO for WoL setting. The 2nd phase GPIO
    initialization may destroy driver's setting.
    This problem was worked around by driver by waiting for
    phase2 bootcode to be loaded before the GPIO initialization.
    However, when the NVRAM device is 64K EEPROM, phase 2 takes
    over 500ms to be loaded. To meet the Windows Fast Initiative
    requirement, driver could only wait for 200ms. When driver times
    out, it will proceed with GPIO initialization and later, destroyed
    by 2nd phase bootcode. This caused power glitch and generated POR.
    Moved the GPIO initialization to phase 1.    
 Version 3.03 ---- 10/3/05
1. Worked around unstable PCIE refclk issue

    Device does not come up on some machine platform. (bootcode v3.02)

    In some particular system, the PCIE refclk was not stable for a long 
    period of time. Accessing PCI config. space registers, 0x7d00 and 
    0x7e00 block registers relying on this clock. When the clock is not
    available, all access to those registers will timeout and read will 
    return zero.
    The read-modify-write instruction performed at 0x7d00, reads zero
    (due to unavailable clock and stall for a long time), then clock
    become available (due to long timeout delay) and write modified zero 
    value back to register. As result, destroyed the register content.
    With value zero in 0x7d00 shuts down PCIE bus and hence the device
    become invisible from the bus. 
    Since all access performed to 0x7d00, 0x7e00, and PCI config. space 
    is invalid until the clock is available, many initialization may not 
    be done correctly; or at least it may read incorrect revision ID. 
    Therefore, to ensure the code is executed properly, we need to ensure
    the clock is there first before proceeding with initialization. 
    Put a wait loop until refclk is stable before move on to initialization
2. Disable ClockReq
    The chip will get a GRC_RESET when going from D3Hot to D0 state
    When ClockReq is enabled, the chip will get a GRC_RESET when going 
    from D3Hot to D0 state. The hardware default for mobile part is enabled.
    Disable ClockReq for mobile part.
    The ClockReq is automatically disabled by h/w on a non-M parts; therefore,
    this change does not affect non-M parts.
 Version 3.02 ---- 9/22/05  
1. Fixed PCIE Serdes shutdown routine

    When the bootcode was trying to shutdown device, bootcode has disabled
    PCIE transmitter and receiver; however, other bits in the same register
    was destroyed.
    Absolute write routine was used.
    Changed to read-modify-write.
2. Removed Nvram config1 initialization

    There is address lockout error
    Per design, Nvram config1 register (0x7014) modification is not allowed 
    when address lockout feature is enabled. The original firmware was 
    overriding this register to adjust the NVRAM clock access speed. When 
    write to config1 register is attempt, address lockout error 9 was posted 
    (at reg. 0x7000 [31:28]) 
    Removed the config1 register initialization.
 Version 3.01 ---- 9/7/05 
1. Enabled PCIE transmitter & receiver upon reset

    When WoL is enabled in NIC mode, device disappears after
    turning off power.
    When bootcode detects no VMain, it turns off PCIE transmitter & receiver.
    Those two bits are only reset upon power on reset (POR) but not other
    resets. Therefore, when power it on with power switch, the device getting
    PE reset does not bring PCIE link out of disabled state. As result,
    the device become not visible.
    Enable PCIE transmitter and reciever upon reset.
    When using version 3.00, this problem occured, the only to recover is to
    short jumper J405 and then use Alt-Ctl-Del to restart the computer.  

 Version 3.00 ---- 9/6/05 
1. Initial official release

    Version 2.00, 2nd phase bootcode did not run. 
    The stack pointer was initialized to 0x20000. For Jade, the mbuf memory
    size only has 48k, 0x10000-0x1c000; therefore, the stack pointer should
    be initialized to 0x1c000 instead of 0x20000.
    Fixed the stack pointer   
 Version 2.00 ---- 6/2/05 
1. Initial engineering release

   This is a branch of Stanford v2.01.
   GPIOs will not be changed to output pins for the one not in use.

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