releases.txt Driver File Contents (

             Release Note for Stanford Bootcode Firmware
                           5755, 5755m 

 Version 3.32 ---- 6/20/07
1. Serial number get changed issue 

  The workaround for CQ#28997 in V3.31 only restores 0x164[31:28] and 0x168[7:0] after setting bit 23 of 0x7c04.
  In this release, the entire 32 bits of 0x164 and 0x168 will be restored.

 Version 3.31 ----  6/19/07
1. Serial number get changed issue

  Problem: CQ#28997
    The serial number in offset 0x164/168 get changed after reset. As result, OS will
    treat our device as new device in the system. 
	Under certain corner cases, the Reserved bits of  0x164[31:28] or 0x168[7:0]  may not have default value set correctly.  

    Firmware will write back the hardware default value after setting bit 23 of 0x7c04. 
 Version 3.30 ---- 1/19/07
1. Fixed Timer Prescale value such that the timer tick will be 1us

  Problem: (CQ#27938)
    Currently, one timer tick will take 2us with the default Timer Prescale value in register 6804[7:1].  
    The default Timer Prescale value 0x7f has been used and has not been adjusted correctly.   
    Changed the Timer Prescale value to 65 in register 6804[7:1].

    5705 and newer devices.

 Version 3.29 ---- 12/18/06 
1. Re-visit CQ#27733 fix

  Problem: CQ#27733
    When TPM is enabled, STM45PE20 NVRAM write access intermittently fails
    The fixed was introduced in Version 3.28. There are two lines of code
    are not needed.

    Original fix has set bit 21 of Reg 0x6804 before resetting the flash interface.
    and clear the bit after resetting the flash. These two lines of code are not needed.

    Removing these two lines of code from the fix to save NVRAM space.

2. Re-visit CQ#24820, CQ#27697, CQ#27659 workaround

    Bootcode version 3.27 Item #1 attempts to address CQ#24820, CQ#27697, CQ#27659.  
    The workaround takes about 27ms to shutdown the 5755m device.   
    Any access to the LOM within this window can prevent proper shutdown. 
    This version optimized the shutdown logic and reduces the shutdown time down to less than 3ms.

3. Improved the IEEE Testing performance for 5755M
  Enhancement: CQ#27630, CQ#27832
    The Hybrid Trim value in the GPhy has been adjusted to improve the IEEE Testing performance.

 Version 3.28 ---- 12/6/06 
1. Fixed STM45PE20 NVRAM write issue

  Problem: CQ#27733
    When TPM is enabled, STM45PE20 NVRAM write access intermittently fails
    When TPM is enabled (TPM_EN# tied to GND) and at the PE_RST# transition
    from low to high, the register 0x7028 may come up with a non-default value.
    This issue is seen only when WoL is enabled. WoL routine slows down
    the core clock before putting the device in WoL sleep state. 
    We don't see this issue with WoL disabled. This is because if WoL is 
    disabled, the device is put into Power Down state instead of slow core 
    clock state when the system transitions to a sleep state. 

    To workaround this, bootcode win/lock arbitration first, then reset the 
    NVRAM access block. This operation should be transparent to TPM. 

 Version 3.27 ---- 12/1/06 
1. Fixed A2 GPIO2 powerdown workaround

  Problem: CQ#27697, CQ#27659
    Power was not completely shutdown when GPIO2 powerdown was asserted.
    The workaround requires the PCIE link state to be L1 to work. The code
    was polling for L1 link state but there are two types of L1 stats:
    Normal L1 and ASPM L1. Since the code is only waiting for Normal L1 state, 
    if the system negotiates to ASPM L1 state, the program will loop in 
    infinity loop waiting for link state change.
    The code is changed to wait for both Normal L1 or ASPM L1 state to exit.
    Furthermore, put a two milliseconds time out timer to prevent infinity 

 Version 3.26 ---- 11/27/06 
1. Fixed NVRAM access bug

    Due to other project change, since version 3.24, some NVRAM access 
    were used incorrectly. 
    NVRAM access FIRST/LAST bit can only be used in consecutive addresses.
    Some random address were also using FIRST/LAST access and will return
    incorrect value.
    Fixed incorrect NVRAM read to SINGLE access. 
    The incorrect NVRAM read was:
      1. v3.24: shared_config (NVRAM 0xdc, stored to Shared memory 0xd3c)
      2. v3.25: Power_Budget2 & Power_Budget3 if Power Budget the feature 
         is enabled. (NVRAM 0xf4/0xf8, stored to register 0x184/0x188)
 Version 3.25 ---- 11/27/06 
1. Shorten PXE enable timing

  Enhancement: CQ 27423
    In some systems, enabling PXE and reboot the system, PXE code was not 
    loaded and executed. The reason for this was because the latency was too
    long for bootcode to enable PXE. The enhancement was to move the Expansion
    ROM initialization to earlier stage at Phase1 boot code.
2. Changed GPhy parameter setting
  Ehancement: CQ 27630
    With the external E-switch in some systems, the 5755M-A2 marginally failed 
    IEEE Testing. We needed to change the trim register to allow our device to 
    pass IEEE testing.

    Write to phy register 0x1e with 0x0016. 

    This change only applies to 5755m. There is no change for 5755.  

 Version 3.24 ---- 11/06/06 
1. PCIE Link Polarity

  Enhancement: CQ#27039, CQ#26767, CQ#27105
    Apply PCIE Link polarity workaround only at hardware reset (POR or 

 Version 3.23 ---- 10/13/06 
1. NVRAM parameters to set GPIO initial configuration for LOM designs
  Enhancement: CQ#27111
    The GPIO0 and GPIO2 configuration will be based on NVRAM setting. 
    Need newer b57diag version 10.04 or later to configure this setting.    
    No change for non-Mobile parts.  
    No change for NIC designs.
    For Chip Revision A2, due to the powerdown workaround (CQ24820),
    GPIO2 will be always set as input pin for powerdown control. 
    When upgrading to this version (or any future version) from any previous 
    version, "seprg" command should be used instead of "upgfrm". If "upgfrm" 
    is used, the default configuration setting will configure those GPIO pins 
    as input pins which is not compatible from the old default setting. The 
    old bootcode configure all unused GPIO pins to output and drive it to zero. 
    When "seprg" is used, the default configuration will be the same as older 
    bootcode behavior; configure to output pin and drive it zero.    
 Version 3.22 ---- 10/10/06 
1. L1 exit latency improvement
  Enhancement: CQ#27044
    Improve the L1 exit latency when Clock Request is enabled.
    No change for non-Mobile parts.
 Version 3.21 ---- 10/05/06 
1. Remove Disable Clock Request
  Enhancement: CQ#26951
    The clock request was disabled in version 3.20 for CQ #26629 for Mobile parts. 
    Change to use h/w default setting.
 Version 3.20 ---- 09/15/06 
1. Disable Clock Request
  Enhancement: CQ#26629
    The clock request enabled feature is not fully tested. This feature needs 
    to be disabled for RC 10.0 release.
    The ClockReq is automatically disabled by h/w on a non-Mobile parts; therefore,
    this change does not affect non-Mobile parts.

2. Link speed issue

  Enhancement: CQ26652
    We have compatibility issue with Intel NIC Intel Pro/1000MT based LOM 
    (NDIS5.1 8.5.14, Auto detect for Speed/Duplex parameter, Windows XP 
    Professional SP2 O/S). The symptom shows when WoL is disabled and there
    is no management firmware loaded, after first time power up, the link 
    partner settles at speed 10H where our device settle at 1000F after the 
    link negotiation. To workaround the issue, bootcode is changed to use 
    different method to initialize the phy. 
    This issue exists not only in this device but all NetXtreme I products.  

3. IPMI/ASF traffic fails when LOM is disabled by BIOS
  Problem: CQ#25290
    The IPMI/ASF traffic does not work when LOM is disabled by BIOS.  
    With certain platform, when the device is disabled by BIOS, PERST# is
    asserted and refclk is removed. Under this condition, the workaround 
    implemented for unstable refclk in version 3.52 logic will kick in 
    and cause bootcode to wait for stable refclk. Since the clock will 
    never be available, hence, bootcode is stuck in forever loop and cannot 
    proceed to load IPMI firmware. 
    Added one second timeout when waiting for stable refclk. The bootcode
    will advance when the timeout expires.
    Since there is no refclk is available; furthermore, the PERST# is 
    asserted under this condition, the PCI domain registers become not 
    accessible. Since bootcode has many PCI domain register access after
    exiting the loop, all those register access become invalid and will 
    timeout causing further delay to load IPMI code. The estimated delay is
    about 3 to 4 seconds compare to normal boot under this particular 
    condition. (There is no impact and no delay under normal condition.)

 Version 3.19 ---- 6/26/06 
1. Enabled double Ack bug ASIC fix

  Problem: CQ25115
    LAN traffic may stop under heavy chariot stress in conjunction w/ management SW
    For 5755 a race condition inside the HW could cause the firmware to read bogus
    data from internal chip registers.  The bogus data could cause the firmware to
    issue a GRC reset what causes the HW to return back to its default state.  In its
    default state the 'memory enable bit' will be cleared and the Host device driver
    will no longer be able to communicate with the HW, what causes the LAN traffic
    to stop.
    The 5755 has build-in technology that addresses this underlying HW issue.  All   
    that is required is for firmware to enable this HW fix known as the "double 
    ACK issue" (CQ9987).
    It should be noted that this firmware fix goes along with a Windows and Linux
    device driver change
 Version 3.18 ---- 6/15/06 
1. Implemented workaround for Low_Power_Mode Input Pin

  Problem: CQ#24820
    Stanford TPM Block Gets Reset upon Deassertion of Low_Power_Mode Input Pin
    Hardware behavior
    Using GPIO2 as Low_Power_Mode Input Pin and use firmware to shutdown the
    device when deasserted and power-up the device when it it asserted.
    Only Stanford mobile device, chip revision A2, and LOM configuration will 
    take effect. All others are unaffected by this change.
    If a NIC card is configured as LOM and the GPIO2 is floating, the device will 
    be shut down immidiately. In that case, GPIO2 should be shorted to gound to 
    bring up the device. 
2. Wrong revision.

    The chip revision posted in Shared memory 0xd2c was incorrect.
    Bug introduced in version 3.17. The metal revision mask was changed 
    by other project incorrectly.
    Changed back to the correct mask.
    Any revision sensitive routines or workaround was affected by this.
3. Turn off Cable Sense issue

    Once the Cable Sense was turned on, it could not be turned off until 
    the next power cycle to the chip. 
    The Cable Sense mode was cleared on by POR only. Since the bootcode only
    turns cable sense on when it is enable; assuming any reset would clear
    Cable Sense configuration, it was not clearing the configuration until
    the next power cycle.
    Not just turn on but also turn off the configuration according to the
    NVRAM setting.             
 Version 3.17 ---- 5/15/06 
1. Change phy settings for better link detection.
 Enhancement: CQ24525
  Shut off SMDSP clock after programming the Tab registers.
2. Enabled second phase fastboot feature

    Only the first phase bootcode NVRAM loading is bypassed with the older
    bootcodes. Starting with this version, the second phase is also pre-
    reserved and NVRAM code loading is bypassed. 

    Since the bootcode is no longer reload from NVRAM, the boot time will be
    much faster. Upon reset, there will be only few words of configuration 
    NVRAM access.

 Version 3.16 ---- 4/5/06 
1. Removed reg. 0x7d00 access

  Problem: CQ#23880
    5755 LOM disappears after WoL from S5
    Due to the document error, bit 18 of register 0x7d00, CQ#11011 fix enable 
    bit logic was reversed. When bootcode writes to this register, writing 0
    and disabled the ASIC fix. 
    Removed 0x7d00 access and use hardware default.  
    Since the hardware will automatically shutdown PCIE transmitter and receiver
    in D3 state; therefore, there is no power consumption change in normal OS
    When the system was powered down in D0 state, such as ungraceful/DOS 
    shutdown, we will see more power consumption. From the lab measurement,
    we observed the current draw increased from 172mA to 236mA. 

 Version 3.15 ---- 3/07/06 
1. VPD-R checksum error

  Problem: Related CQ#23565, CQ#23566
    VPD-R checksum was incorrect
    Checksum was calculated from VPD-R to the end of VPD-R region; however,
    the specification indicates that Checksum should be calculated from the
    offset zero.
    Corrected the checksum
 Version 3.14 ---- 2/17/06
1. Fixed revision issue

  Problem: CQ#23294
    For all B step revision were reported as A step revisions
    Revision now is reading from register 2018 instead of 68; However,
    there was a coding error, shifted metal revision incorrectly. 
    Corrected the error 
    Since we don't have B step silicon yet, we should not see any problems
    related to this issue. 
2. Initialized Cardbus pointer register

  Enhancement: CQ#23431
    Since Cardbus support is no longer a requirement, in order to pass
    the plug-fest compliance test, we write zero to register 0x28 to disable
    cardbus feature.     
 Version 3.13 ---- 2/08/06
1. Enable PEReset Mask
      On certain systems, when entering S5 state (with WoL enabled), the 
      LOM current draw on the 1.2V rail can fluctuate between ~90mA and 
      ~150mA from shutdown to shutdown.

      On certain systems (with WoL enabled), the 5754/A1 LOM may disappear 
      during repeated S5 Power-Cycle tests.
    As part of the bootcode f/w logic, the NIC f/w will make access to 
    certain registers (0x00-0xff and 0x7d00-0x7fff) when the firmware 
    detected that the Vmain power goes low.  Due to CQ23039, the register 
    bit that the firmware used for detecting the "Vmain power state" can 
    also toggles between logical '0' and '1', and this leads to f/w to not 
    able to make reliable read/write access to the registers (0x00-0xff and 
    0x7c00-0x7fff), which ultimately causes bad behaviors that is described 
    in CQ22684.
    Firmware now enables the PEReset Mask register bit (0x68a4[16]=1).  By 
    enabling this register bit, the chip exits the reset state after the 
    current fluctuation become stabilized, which eliminates the toggling of 
    the "Vmain power" detection register bit, which ultimately enables 
    successful access to the register (0x00-0xff, 0x7c00-0x7fff) by the f/w.
    Fixes CQ#23039 and CQ#22684.

2. Restored 0x7d00 access
    Since we were able to root cause the reason why we could not access 0x7d00
    correctly in #1 change, this version is putting back the 0x7d00 access
    using absolute write. This is undoing the change in version 3.12, #2.   

 Version 3.12 ---- 1/24/06

1. Enabled ASIC fix for tx Ethernet packet corruption on late collision

  Enhancement: CQ#22908, CQ#14561, CQ#14521
    Since the ASIC is fixed and verified by ASIC team, we are enabling the
    fix in this version.
2. Removed all register 0x7d00 access

  Problem: CQ#22832
    Accessing register 0x7d00 can cause the corruption of content when
    reference clock was not stable in some system. 
    When the device was put into D3 power state, due to the clock issue, the 
    PCIE registers become not accessible. If an access to register may cause
    the content corruption.
    Removed all 0x7d00 register access.
    Since the hardware will automatically shutdown PCIE transmitter and receiver
    in D3 state; therefore, there is no power consumption change in normal OS
    When the system was powered down in D0 state, such as ungraceful/DOS 
    shutdown, we will see more power consumption. From the lab measurement,
    we observed the current draw increased from 172mA to 236mA. 

3. Changed revision reading

    CPU reads incorrect silicon revision id in D3 power state.
    In D3 power state, except OOB, the PCI/PCIE registers are not accessible.
    All reads returns zero. Because of this, the read is not reliable.
    Instead of reading from register 0x68, the code is changed to read the
    revision id from register 0x2018. The register 0x2018 is available at all
 Version 3.11 ---- 12/22/05
1. Enabled Slow Clock for Cable Sense mode

    Enabled slow clock mode for cable sense so when cable is unplug, we
    can conserve more power. 
 Version 3.10 ---- 12/09/05
1. Force PCIE link polarity

  Problem: CQ#22173,CQ#22176,CQ#22178,CQ#22180,CQ#22254
    In some platform, the PCIE link polarity comes up incorrectly. 
    ASIC could not handle all cases correctly.
    Wait until PCIE link comes up. Then based on the link polarity status
    detected by ASIC polarity auto detect, firmware will then force the 
    PCIE link to the correct polarity.
2. Enable refclock auto switching

    The workaround in version 3.07, #1 is not stable. CPU could read "good"
    link indication without REFCLK. 
    Without clock, the interface can timeout and return anything left in
    the data bus. 
    Enable auto clock switching. When enabled, the clock will automatically
    switched to internal clock when there is no ref. clock available.
3. Enable clock request for A1 or new revision

    The clock request was disabled in version 3.06, #3 for A0 issue. Starting
    this version, the clock request will be enabled back for A1 or newer devices.

 Version 3.09 ---- 11/14/05
1. CQ14315
  Problem: CQ14315
    If L0s is enabled on the BRCM chip a "yellow bang", or a system hang 
    condition can occur.
    During the L0s to L0 exit transition, symbol lock can be lost if the 
    system reference clock has not fully stabilized what leads the PCI-E 
    link training state machine to go through the "detect" state.  Going 
    through "detect" causes an internal reset to the BRCM chip what causes 
    "yellow bang" and/or a system hang condition based on the chipset 
    1. Change Serdes RX Timer from 768 ns to 2 uS to make sure the 
       Serdes CDR is stable before it sends data to the Physical Layer.  
    2. Increase FTS Count from 1uS to 2.25 uS to avoid intermittent GRC 
       Reset when L0s is enabled.
    Since RX Timer value and FTS Count change only needed before PCIE link 
    training, bootcode will initialize those values and retrain the PCIE 
    link during cold reset only. When driver reset, this workaround is 
    bypassed to avoid PCIE link retrain. 
    Increasing the amount of FTS required to transition from L0s to L0, 
    will impact the overall, top performance.
2. Enable Frequency Multiplier only for the Mobile Device

    ASIC team has verified this enhancement in ASIC; therefore, this
    version enables the ASIC enhancement for Frequency Multiplier.
    This feature is only available for M-part.
3. Fixed WoL was not working issue.

  Problem: CQ#14614
    WoL was not working on OOB case. 
    Version 3.07 (#1) added workaround for platforms that show an unstable 
    PCIE refclk during power up. Nevertheless, there is a limitation to 
    this workaround as to where it requires VMAIN to be present. In systems 
    where there is no VMAIN present and there is no PCI-E REFCLK at all for 
    the cases outlined above the bootcode will loop forever, therefore not 
    enabling WoL.
    Added a condition to the "unstable PCI-E Refclk" workaround to apply
    this fix only when there is VMain present.  In cases where there is no 
    VMAIN present, the boot code will no longer check/wait for a "stable 
    PCI-E Refclk" before continuing.
4. Fixed Link Histogram Issue.

    In DVT testing, Link histogram results seemed to be worsen in bootcode
    version 3.08.
    The change in version 3.08, item#2, removes all Gphy workaround.
    The workaround included hybrid bias change, adc  bias change, and pll 
    startup bandwidth change. The hardware fix still have incorrect PLL
    startup bandwidth value. By removing the workaround, the sympton has
    showed up. 

    Added the adjustment for the PLL startup bandwidth.    
 Version 3.08 ---- 10/18/05
1. Fixed Cable Sense mode

    The Cable Sense mode was initialized incorrectly
    Initialized to wrong register.
    Fixed the error
2. Not to apply poor BER performance workaround

    The workaround for poor BER (Bit Error Rate) with cable length 70m or less
    was causing the problem.
    For 5755/5755m, the BER problem has been fixed in ASIC already. If the
    workaround was applied, by changing hybrid bias current, would yield the
    unwanted current.
    Removed the workaround
3. Move GPIO initialization to Phase1 code

    Originally, activating VAUX power was done in phase 2 bootcode.
    However, once driver waited for phase1 signature, driver may start to 
    configure GPIO for WoL setting. The 2nd phase GPIO initialization may 
    destroy driver's setting.
    This problem was worked around by driver by waiting for phase2 bootcode
    to be loaded before the GPIO initialization. This change does not 
    affect anything since driver already have the work around. 
 Version 3.07 ---- 9/30/05
1. Worked around unstable PCIE refclk issue

    Device does not come up on some machine platform. (bootcode v3.05)

    In some particular system, the PCIE refclk was not stable for a long 
    period of time. Accessing PCI config. space registers, 0x7d00 and 
    0x7e00 block registers relying on this clock. When the clock is not
    available, all access to those registers will timeout and read will 
    return zero.
    The read-modify-write instruction performed at 0x7d00, reads zero
    (due to unavailable clock and stall for a long time), then clock
    become available (due to long timeout delay) and write modified zero 
    value back to register. As result, destroyed the register content.
    With value zero in 0x7d00 shuts down PCIE bus and hence the device
    become invisible from the bus. 
    The fix in bootcode version 3.06, changing read-modify-write to
    absolute write is not good because basically that write does not go
    through. (Due to unavailable refclk) In this case, it worked 
    because the hardware default value was good enough to bring up the
    device. Since all access performed to 0x7d00, 0x7e00, and
    PCI config. space is invalid until the clock is available, many 
    initialization may not be done correctly; or at least it may reads
    incorrect revision ID. 
    Therefore, to ensure the code is executed properly, we need to ensure
    the clock is there first before proceeding with initialization. 
    Put a wait loop until refclk is stable before move on to initialization
2. Enable L1 support advertizement for M part

    This version enables Link Capability L1 support for M part.   
 Version 3.06 ---- 9/29/05  
1. Fixed PCIE Serdes shutdown routine

  Problem: CQ#14165
    There still a time bootcode will write 0 to PCIE Serdes control register.
    There is a time the register is not readable. Using read-modify-write 
    method may cause reading wrong value and write clear all necessary control 
    Changed to absolute write after reset to initialize PCIE Serdes control 

2. Load ASF with Driver reset

    This is the 2nd phase of rev. A0 workaround. Allowing ASF code to be
    loaded with driver reset.
3. Disable ClockReq
    The chip will get a GRC_RESET when going from D3Hot to D0 state
    When ClockReq is enabled, the chip will get a GRC_RESET when going 
    from D3Hot to D0 state. The hardware default for mobile part is enabled.
    Disable ClockReq for mobile part.
    The ClockReq is automatically disabled by h/w on a non-M parts; therefore,
    this change does not affect non-M parts.
 Version 3.05 ---- 9/22/05  
1. Fixed PCIE Serdes shutdown routine

    When the bootcode was trying to shutdown device, bootcode has disabled
    PCIE transmitter and receiver; however, other bits in the same register
    was destroyed.
    Absolute write routine was used.
    Changed to read-modify-write.
 Version 3.04 ---- 9/21/05  
1. Enabled GPIO

    By hardware default, GPIO function was disabled. Because of
    this, all GPIO function was not working. This was result in NIC
    mode WoL function not to work or system hang for some machine.
    Stanford requires firmware to enable GPIO in order to use it. 
    Enabled GPIO function
 Version 3.03 ---- 9/20/05  
1. Fixed the version 3.02 workaround

    After posting negate of drv/firmware handshake signature, there is still
    a small window of time that register read could be corrupted.
    The second phase of bootcode still accessing NVRAM. (To check/load 
    Management firmware)
    Moved the signature posting right before entering the service loop.
    In case of management firmware is enabled, no negate of signature is 
    posted. (It will be the management firmware's responsibility to post
    the signature)
 Version 3.02 ---- 9/16/05  
1. Applied ASIC bug workaround

  The following is only applied to A0 revision
  a. Post negate of drv/firmwaqw handshake signature at the end of 2nd phase 
     bootcode loading.
  b. Disabled VPD read/write for driver reset. (It returns garbage if read)
  c. Disabled ROM service for driver reset.
  d. Disabled ASF/IPMI/UMP firmware for driver reset.
  e. Added firmware suspension function. 
  f. A value 0 is read after NVRAM access.
 Version 3.01 ---- 9/14/05  
1. Removed Nvram config1 initialization

    There is address lockout error
    Per design, Nvram config1 register (0x7014) modification is not allowed 
    when address lockout feature is enabled. The original firmware was 
    overriding this register to adjust the NVRAM clock access speed. When 
    write to config1 register is attempt, address lockout error 9 was posted 
    (at reg. 0x7000 [31:28]) 
    Removed the config1 register initialization.
 Version 3.00 ---- 9/13/05  
1. Initial official release

    2nd phase bootcode did not run. 
    The stack pointer was initialized to 0x20000. For Stanford, the mbuf memory
    size only has 48k, 0x10000-0x1c000; therefore, the stack pointer should
    be initialized to 0x1c000 instead of 0x20000.
    Fixed the stack pointer   
 Version 2.07 ---- 6/2/05 
1. Changed NVRAM pin straps

    Stanford pin strap is not compatible with Baxter.
    The pin strap mapping needed to be changed. 
    Changed the bin strap to Stanford. 

  Note: Due to b57diag, the version has been skipped from 2.01 to 2.07. (B57diag treat
    version 2.07 smaller number as an old version doesn't support directory structure.)

 Version 2.01 ---- 6/2/05 
1. Firmware does not program revision register 0x8. 
2. The indirect access address registers, 0x78/0x7c will not be cleared by firmware.
3. Set bit 23 of 0x7c04 after programming MAC address 0x410/0x414 to prevent future
   change of register 0x164/0x168.
4. The link capability, register 0xdc is not touched.

 Version 2.00 ---- 4/1/05 
1. Initial engineering release

   This branch of built of Baxter v3.10.

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