Release Note for BCM5702 BOOT Code Firmware ================================================= Version 2.39: 1. Writes firmware id to shared memory rx_cpu_firmware_id field Enhancement: Phase1 & Phase2 code will write the firmware id to rx_cpu_firmware_id. Eng. Notes: bootcode phase1 will write value 0xfefe0008 to shared memory 0xc0c. bootcode phase2 will write value 0xfefe0009 to shared memory 0xc0c. When phase2 executes properly, the value phase1 wrote should be overwritten by phase2 code. Version 2.38: 1. Restored phy type in manufacture data block Problem: PXE code needed this field to determine the phy type Fix: Hard coded this field to be copper type 2. Changed device id from 0x16a6 to 0x16c6 Problem: Device id has been changed from chip rev. A3 or later. Fix: Changed the default device id to rev A3 or later. Version 2.37: 1. Fixed WOL issue Problem: After using restart option in Windows and restart computer to DOS. Then, turn off the power, WOL will not work. Cause: Since there was no power lose from Windows to DOS, the signature deposited by driver was not cleared. Therefore, when power lose from DOS, bootcode sees the WOL signature and was bypassing the WoL initialization. Fix: Changed bootcode to clear WoL signature if the startup does not have driver signature. Version 2.36: 1. Get phy id from phy register instead of NVRAM configuration Enhancement: Get phy id from phy register instead of NVRAM configuration Cause: Originally, the phy id field in shared memory was read from NVRAM configuration. User could changed it any way they wanted and driver cannot rely on the content to perform as correct judgements Change: The phy id in shared memory will be read from phy register instead of NVRAM field. 2. Removed Phy 1.8v option Problem: Earlier bootcode contains 5701 product code which will cause a glitch in the PHY clock and could cause PHY to lock-up. Cause: The code was carry over from 5701 in the old day was not needed in newer product. Fix: Removed unnecessary code that could cause Phy to lock-up. Version 2.35: 1. Fixed Link drop problem in version 2.34 Problem: Link will drop in middle of Windows Certification test Cause: In version 2.34, the device reset indication bit was not passed from phase 1 to phase 2 correctly. As result, the bootcode was performing phy reset from driver reset. Fix: Fixed the software bug. Note: This bug was introduced in version 2.34 Version 2.34: 1. Enable phy in cold reset. Problem: Cannot access MAC register if phy is in powerdown state. Cause: When Windows is restarting, the driver go through the shutdown routine. When WoL is disabled, it turns off phy completely by putting phy to powerdown mode. When it restarts, the main power, 3.3 volt is stable. Only rely on PCI reset, the device does not generating power on reset; thus phy is not reset and still in powerdown state. To access MAC registers, phy clock is required and we need to access the register for MAC address initialization. Fix: If it is cold reset, it will put phy to 10mbps to enable the clock before accessing MAC registers. This also helps to reduce power consumption by putting at lowest speed. The phy will eventually get reset at phase 2 code. Note: This is an extension fix of version 2.25 item 17. Version 2.33: 1. Fixed PXE ROM size bug Problem: The secfg option 29, expansion ROM size was not taking effect. The size was always 64k. Cause: Bootcode did not program the correct value in the register. Fix: Bootcode is changed to program correct expansion ROM size setting in NVRAM configuration into register. Version 2.32: 1. Fixed configuration read bug. Problem: The 2nd phase code was not reading configuration correctly Cause: software bug. Fix: Corrected the bug. Note: This bug was created in version 2.31. Version 2.31: 1. Supports Shared Memory data structure version 1 Problem: Driver need more information from bootcode. Cause: More feature is needed to support in driver. Fix: Changed the shared data structure from version 0 to version 1 to pass new data in new fields. 2. Removed phase 2 image loading failure LED blink feature (to save space) Problem: Image size is growing to 8k limit. We needed to remove the Debug feature out to save space. Effects: If first phase bootcode has failed to load second phase code, the older code will blink both traffic and link LED. This version will no longer blink the LED. Version 2.30: 1. Support Reverse Nway PowerSaving Problem: Needed new Reverse Nway feature. Cause: When Reverse Nway mode is on, bootcode needed to settle at lowest speed possible to save power. Fix: When feature is enabled, put to 10mbps speed. 2. Fixed Rev. A2 Tx Scratchpad code loading problem. Problem: In OOB, the device could not establish LINK when ASF is enabled Cause: For rev A2 or earlier, Tx Scratchpad was disabled and not accessible in OOB mode. When ASF is enabled, the bootcode would load ASF code into TX CPU and cause CPU to hang Fix: Put a sanity check on scratchpad accessiblity. If passes, then it will proceed with code loadding. 3. Changed phy type always to be copper Problem: User could change phy type in NVRAM configuration to serdes and cause the bootcode to misbehave Cause: Originally, the bootcode was shared between copper and Serdes verion; therefore, we needed a configuration field to indicate if this is copper or serdes. Today, we separated the bootcode image already, we don't need to use this configuration any more. Fix: Instead of reading phy type from configuration, it now will always force this field to be copper type. Version 2.29: 1. Support WoL Limit 10 speed Problem: WoL was always 10/100 Cause: We didn't have configuration to allow user to limit the link speed to 10. Fix: Added new configuration WoL Limit 10 for this purpose. This version of bootcode will read the configuration and set the speed accordingly. 2. Added 2nd phase signature. Problem: Driver/Diagnostics could not tell when the 2nd phase bootcode initialization is complete. Cause: We only had 1st phase signature but we didn't have 2nd phase signature. Fix: Added 2nd phase signature. Version 2.28: 1. Improved NVRAM corruption workaround algorithm Problem: The problem described in 2.23 item 2 still exist. Theologically, there is potential problem when PC jumps to NVRAM write routine with invalid register content when losing power. Fix: Enhance the original workaround by not only check of VPD write event, but also construct the command outside of VPD event 'if' check. Thus, if PC happens to be jumping outside of 'if' statement, it is protected by VPD write event. If the PC happens to jump inside of if statement, it will write harmless command since the command is not constructed yet. Also, when power is deteriorating, most likely the address jump will incorrectly jump from high to low address. Therefore, moved the NVRAM write routine to the highest address in the module. Version 2.27: 1. Reversed the NVRAM corruption workaround algorithm to original method Problem: The new workaround method does not work with other firmware Cause: Other firmware, such as ASF or TCP segmentation firmware does not reserve the special register content. Thus, the workaround does not work if other firmware is loaded. Fix: Reversed back to original method. With double check of NVRAM write only if VPD event bit is present. Version 2.26: 1. Use default MAC address for entry 1 to 15 Problem: After we programmed all same MAC address in MAC registers in version 2.22 item 14, we started to fail Microsoft certification test. Cause: The certification test was testing if we program zero MAC address into our MAC address register and make sure we will not accept the packet address to our device; however, even if our MAC register 0 has been programmed with 0, since MAC register 1 to 15 still have our MAC address, it was continuing to receive the packet address to our MAC address. Fix: Initialize all Mac address registers 1-15 with broadcom default MAC address 001018000000. 2. Changed NVRAM corruption workaround algorithm Problem: Theologically, there is potential problem when PC jumps to NVRAM write routine with invalid register content when losing power. Cause: When the device is losing power, the power drains down slowly. In the mean time, internal CPU is still running with deteriorating logic value. Under this condition, PC can jump in invalid NVRAM write routine and issue write command to NVRAM and cause the NVRAM corruption. Fix: Reserved one CPU General Purpose Register to be used for command to write NVRAM. If any jumps should occur, it will write an harmless command into NVRAM command register. Version 2.25: 1. Propagated the ASF enable information to shared memory before signature Problem: Driver was getting incorrect ASF enable status. Cause: ASF enable bit was initialized in shared memory after the signature Fix: Propapated the ASF enable information to shared memory before signature Note: This is also propagated in version 2.21b 2. Fixed a bug where bootcode may fail to cut auxiliary power when WOL is disabled. Problem: Some times, the NIC will not cut auxiliary power even WoL is disabled. Cause: In the phase 1 code, the WoL indication variable was not initialized when checking for necessity of cutting VAUX power. Fix: This is pure software bug. The variable now is initialized currectly before use. Note: This bug is also fixed in version 2.21c 3. Propagated NVRAM setting regarding WOL even on device reset. Problem: NVRAM setting was not propagated to shared memory on device reset. Fix: Propagate NVRAM setting regarding WOL even on device reset Note: This is also propagated in version 2.21c 4. Fix WOL when power down from PXE or DOS driver Problem: When PXE is enabled and BIOS is loading ROM code, if the power is turned off, WoL will not work. Cause: When PXE code is running, it resets the firmware with driver signature. When bootcode sees the signature, it will not enable WoL. Fix: The fix is to check if driver set up any WOL before unloading itself. If it is set (magic or interesting or both), the firmware will not touch the WOL setup. If it is not set, it'll consult wol setting in EEPROM. If WOL is specified to be "enabled" in EEPROM, the firmware will set it up. This allows magic pkt WOL after powering down from PXE or DOS driver. The drawback is that the WOL setting in Windows registry cannot override the EEPROM setting (i.e. if user disables WOL completely in Windows, the firmware will decide whether to set up WOL based on EEPROM setting). Note: This fix is also in version 2.21c 5. Fixed PXE speed Config. bug Problem: PXE speed setting was not taking effect. Cause: The PXE speed was not programmed correctly Fix: Program PXE speed according to secfg setting Note: This is also fixed in version 2.21d 6. Fixed an LED problem with A2 LOM when ASF is enabled. Problem: When ASF code was fail to load, we could not tell the failure from LED indicator. Cause: Original board design, we had all 10M, 100M, 1000M link speed LEDs. When it failed, all LED was turned on. With some board design, we only have one LED for link status. When turning on all link speed cannot tell from having good link connected. Fix: Turn on traffic also when it failed. Thus all LED will be turned when there is failure. Note: Fix is also in version 2.21d 7. Cut aux power when driver goes hibernation without WOL Problem: Vaux power was not cut off from Window hibernation without WOL Fix: Cut the Vaux power when window hibernates. Note: Fix is also in Version 2.21d 8. Added power saving mode support. Problem: To support power saving mode. We needed to default the link speed to 10 mbps to conserve power. Fix: Added new secfg configuration setting and set phy speed to 10 mbps if this featuer is enabled. Note: This is also added in version 2.21d 9. Added new WOL communication with driver Problem: Driver cannot take over the firmware setting to disable WoL. Bootcode was always taking over driver WoL setting. Cause: The scheme implemented in item 4, (version 2.21c), had drawback that When driver wants to disable WoL, it was not able to do so if NVRAM WoL setting is set. There was no communication between driver and firmware. Upon power down, firmware was taking over control for WoL initialization. Fix: Implemented a new WOL scheme that communicate with drivers. For older driver version older than 07/17/02, if WoL is enabled by driver, firmware will not touch anything. For newer driver, it will post signature. And depends on the commands. Firmware will act accordingly. Note: This change is also added in version 2.21e 10. Added NVRAM corruption protection Problem: NVRAM corruption was seen Cause: When powering off, the power drops down slowly. The CPU was still running under deteriorating illegal power and cause to jump to NVRAM write routine and caused NVRAM corruption. Fix: The workaround was to put a VPD write event qualification before actual write command. Notes: This is also added in version 2.21e 11. Changed Phase1/Phase2 parameter passing to void bootcode/driver race condition Problem: Fixed PHY access contention problem with driver Cause: Phase 2 code needed some information requires MII access; however, since the signature has been posted by first phase, the driver already have the ownership of MII access. By reading MII register in 2nd phase code, caused firmware/driver MII read conflict. Fix: The information need by 2nd phase was read in 1st phase and passed the information to 2nd code via shared memory as parameter passing. Note: This is also fixed in version 2.21e 12. Added Phase1 NVRAM access arbitration logic Problem: Phase 1 bootcode was not using arbitration logic accessing NVRAM Fix: Added arbitration logic in NVRAM access. Note: This is also fixed in verision 2.21e 13. Fixed ASF configuration application misreading EEPROM content problem Problem: ASF configuration application read incorrect NVRAM content Cause: ASF configuartion application (running under Windows) resets the device first and then start to read NVRAM content. Since the first phase code didn't have NVRAM arbitration logic, boot code was fighting the NVRAM access with application. Fix: Added arbitration logic in phase 1 bootcode. (Same as Item 10) Note: Fix is also in version 2.21e 14. Fixed NULL MAC address problem Problem: The device was accepting NULL MAC address packets. Cause: Only Mac Address register 0 was programmed. All other Mac was left was default value 0. Fixed: Program all 16 MAC registers with the MacAddress in NVRAM. 15. Improved PXE loading speed Problem: PXE was taking too much time to load and cause system hang Cause: BIOS was reading PXE in byte. Each by access, we needed to Access NVRAM to return data. Fix: Our ASIC design always read data in word (4 bytes) size. For each ROM byte read it will be wasted of time to read the entire 4 byte-word again. Changed algorithm to save the read data in memory, acting as cache. 16. Supports dynamic bootcode location Problem: The bootcode had to be in fixed in address 0x200. When the next application is programmed right after the bootcode image, upgrading larger bootcode image requires bootcode to be allocated to another location. Cause: We never needed dynamic bootcode allocation support until now Fix: Added new algorithm to support dynamic bootcode allocation 17. Fixed zero MAC address problem Problem: The NIC Device driver "sees" zero MAC address when user choose "system restart" under Windows. This only occur when "system restart" and WoL is disabled. It does not occur in system "cold start" (shutdown the system completely, then restart the system by pushing the power switch). Cause: The device is not able to access MAC Address register if PHY is in shutdown mode. When the user choose the "restart" in a Windows system, the OS will perform (a) "shutdown" and then (b) "restart" the system. During the "shutdown" phase, the NIC Device Driver checks to see if the WoL option is enabled or not. If the WoL is disabled, the device driver will program the PHY to powerdown mode in order to reduce power consumption. When system restart, PCI reset is asserted by system. The bootcode restart; however it does not reset the phy. Since the phy was in powerdown mode, and MAC registers requires phy clock to operate, the MAC Address registers becomes inaccessible by the "bootcode". Fix: The MAC address is programmed in SRAM first and let driver to program the MAC address in MAC address regiser after phy reset. Version 2.24a: 1. Fixed intermittent chip CPU crashing in auxiliary power mode (CQ#3763). Version 2.24: 1. Propagate GPIO_1 usage to driver and corrected the usage in a VPD operation. 2. Updated LED modes of operations. Version 2.23: 1. Exploited power state and pci power presence features supported in A2. 2. Included write protect of EEPROM for some LOM design. 3. Increased the bootcode image size to 5kbytes (5120 bytes). 4. Fixed pxe speed initialization (CQ#3488). 5. Restored range check for VPD access. Version 2.22: 1. Support fastboot initiative. 2. PXE and ASF no longer need to be mutually exclusive. 3. Updated Ethernet@WireSpeed setup sequence. Version 2.21: 1. Added CRC checking before loading other firmware (e.g. ASF). All speed LEDs will light up when CRC check fails. 2. Added 5702FE and Ethernet@WireSpeed supports. 3. Uses 0x16A6 as the new device ID in the boot image. Version 2.19: 1. Employed block read method when loading other firmwares (e.g. ASF) from non-volatile memory. 2. Increased the bootcode image size to 4.5kbytes (4608 bytes). This may have impact on boards that already have pxe or other firmware programmed as they need to be reprogrammed. 3. Added CRC checking before loading phase 2 bootcode. All speed LEDs will light up when CRC check fails. 4. Fixed a bug where a system cannot boot up if phase 2 bootcode is corrupted. 5. Fixed a bug where Windows does not wake up from standby due to bootcode cutting off aux power. 6. Eliminated flash interface reset as this may cause non-volatile memory module to become out of sync. Note: PXE and ASF currently must be mutually exclusive. Enabling both may have an undesirable effect. Version 2.18: 1. Employed block read method when loading codes from non-volatile memory. Version 2.17: 1. Fixed a failure of loading PXE when WOL is enabled. Version 2.16: 1. Speed up the PXE loading (CQ#3108). 2. Enable expansion ROM bit in phase one booting to avoid BIOS missing to load PXE when enabled. Version 2.15: (A0 chip is no longer supported) 1. Implemented two-phase loading to speed up the boot process. 2. Firmware stops running after loading ASF to avoid interference. 3. Cut off auxilary power when an OS turns off the device due to absence of driver. 4. Use software arbitration support by the hardware when accessing non-volatile memory. 5. Included cold WOL support. 6. Fixed a problem where the system fails to boot when both PXE and WOL are enabled (CQ#2977). 7. Fixed a bug where the firmware did not clear VPD request after it is serviced. Version 2.14: 1. Moved multiple boot agent codes and fixed uninitialized variable bug. 2. Updated default subsystem device ID. 3. Temporarily remove cold WOL support to ensure proper bootcode execution. Version 2.13: 1. Added new GPIO sequences for WOL. 2. Added cold WOL support. 3. Embedded version string into the executable binary. 4. Support multiple boot agents. 5. Set LED to PHY mode when card first receives auxilary power. 6. Enable PXE loading from flash memory. 7. Disabled the setup for max PCI retry, default to zero. Version 2.12: 1. Added ASF support. Version 2.11: 1. Fixed Non-Buffer VPD write bug Version 2.10: 1. Added flash write support for VPD. 2. Added auto negotiation for 5703S. Version 2.8: 1. Branched bootcode into several versions to be silicon specific. 2. Fixed flash timeout problem. Version 2.7: 1. Added 5703 support. Version 2.6: 1. Added generic loader support. This is a requirement for ASF support. Version 2.5: 1. Fixed the cable unplug/replug problem on PCI-X setting. Version 2.4: 1. Fixed cable unplug/replug problem (CQ#1998). Version 2.3: 1. Added 100Mbps WOL on A3/B5 boards. 2. Fixed zero mac address when enabling WOL on fiber card (CQ#2236). Version 2.2: 1. Initialize PME Status upon the first time power-up. Version 2.1: 1. Fixed bug on WOL. 2. Temporarily disable BCM5703 support. 3. Fixed link loss on fiber card. Version 2.0: 1. Added WOL support 2. Added BCM5703 support Version 1.9: 1. Added features so that neccessary manufacturing information is stored in the shared memory. This allows host driver can query these information. Version 1.8: 1. Fixed a problem where PXE is not operatable in version 1.7. Version 1.7: 1. Added logic for 1.3v and 1.8v voltage source. 2. Added logic forcing PCI mode. Version 1.6: 1. Added BCM5701 support. * Initialize BCM5701 to use PHY LED mode. * Initialize BCM5701's PHY to advertise 10/100/1000. 2. Timer prescaler is now initialized to reflect 66Mhz core clock. Version 1.5: 1. Added BCM5700 Fiber support. Version 1.4: 1. Initialize BAR after first reset. Version 1.3: 1. Changed so that default manufacturing information now has proper power consumption and dissipation. Version 1.2: 1. Fixed a problem where firmware has problem accessing PHY registers during bootup time for NIC rev.12 and above. Version 1.1: 1. Format of ASIC revision ID has been changed. Changed to generate PCI revision ID correctly. ASIC Rev. PCI Revision ID ======== =============== B0 0x10 B1 0x11 Version 1.0: 1. Initialize PHY LED mode based on subsystem vendor ID. * Dell Viper LOM (0x1028) : Triple speed mode (MII 0x10 = 0x0) * Other : link/speed mode (MII 0x10 = 0x2) Version 0.8: 1. Initialize PHY LED mode based on subsystem device ID. * Dell Viper LOM (0x1028) : Triple speed mode (MII 0x10 = 0x2) * Other : link/speed mode (MII 0x10 = 0x0) Version 0.7: 1. Initialize PHY (BCM5401) with scripts so that NIC has link after power-on-reset before driver is loaded. Version 0.6: 1. Initialize Chip Revision ID in PCI configuration space. Version 0.5: 1. Added logic to perform PHY H/W reset. 2. Initialize VPD delay so that BIOS can access VPD. Version 0.4: Initial release.Download Driver Pack
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