Snow Self-boot image without VPD Data For Chip Rev. A2
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BCM5906m
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Version 3.04 --- 12/7/06
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1. Move most of Snow patches to Phase 1.
Problem: CQ#27283:
BCM5906mA2 disappears during the driver load/unload test.
Cause:
After VCPU sets the device_init_done, it executes the bootcode in the
external EEPROM with more patches added later on. One operation to write
SERDES PLL Control register conflicts with the driver configuration. It
caused the data corruption of the SERDES register.
Fix:
Moved most of the patches to the Phase 1.It will avoid the SERDES/PHY
contention.
Version 3.03 --- 11/3/06
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1. Fixed the typo of link polarity patch enhancement (CQ#26585 CQ#27267).
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Version 3.02 --- 10/30/06
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1. Enable link polarity patch only during the hard reset. The patch will
be disabled if driver reset bit (register 0x5104 bit27) is set.
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Version 3.01 --- 10/16/06
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1. Add a patch to fix the link polarity patch corner case during OOB WOL.
Problem: CQ#26937:
Link Polarity patch needs to poll PCIE Link-Up before performing the rest of
bootcode function. It caused the bootcode hangs here for OOB scenario.
Fix:
Read register 0x6804 to Check Vmain_present. If Vmain is present, use the link
polarity patch inside VCPU ROM. Otherwise, read VCPU Configuration Shadow reg
0x5105. Disable link polarity fix. The device init procedure will bypass the
link polarity patch.
2. Increase the Advertise Number of FTS order set to 0xa0.
Problem: CQ#26585:
NMI Error occurred when Loading Driver onto 5906A1 and Boot into O/S
Fix:
Change the Advertise Number of FTS Order-Set from 64 Order-Sets to 160 Order-Sets
to get around noise bus problem in some systems.
3. L1 exit latency improvement
Enhancement: CQ#27042
Improve the L1 exit latency when Clock Request is enabled.
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Version 3.00 --- 9/20/06
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1. Initial ASIC A2 bootcode release
The patch code in v2.04 is moved to VCPU ROM. Change the ASIC revision ID
and bootcode revision ID. Change the L1_PLL_Powerdown_Disable default value
to 1. Add a new configuration bit 10 to disable clkreq advertisement. The default
value of clkreq_enable is 0. Program Regulator Voltage Control register to 0x01f0_0000.
Add a new configuration bit 11 to disable link polarity fix. The default value
of "Link Polarity Fix Disable" is 0. The patch is moved to VCPU ROM.
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