hp StorageWorks enterprise virtual array Event Text Description File
© Copyright 2001-2005 Hewlett-Packard Company
WARNING: Modification of this file may cause
Enterprise Storage Management Software
to improperly translate event information
Model number string: HSV210
Software version number string: 6100
Baselevel build string: CR0EB0
Structure Format: Endian Little
COUPLED CRASH CONTROL CODES:
Coupled Crash Control Code: 0
Other HSV210 controller should not perform a coupled crash.
Coupled Crash Control Code: 1
Other HSV210 controller should perform a coupled crash.
DUMP/RESTART CONTROL CODES:
Dump/Restart Control Code: 0
Perform crash dump then restart.
Dump/Restart Control Code: 1
Do not perform crash dump, just restart.
Dump/Restart Control Code: 2
Perform crash dump and do not restart.
Dump/Restart Control Code: 3
Do not perform crash dump and do not restart.
SEVERITY LEVEL CODES:
Severity Level Code: 0
Normal -- informational in nature.
Severity Level Code: 1
Critical -- failure or failure imminent.
Severity Level Code: 2
Warning -- not failed but attention recommended or required.
Severity Level Code: 3
Undetermined -- more information needed to determine severity.
CORRECTIVE ACTION CODES:
Corrective Action Code: 0
No action necessary.
Corrective Action Code: 1
An unrecoverable hardware detected fault occurred or an unrecoverable software inconsistency was detected, proceed with HSV210 controller support avenues.
Corrective Action Code: 2
Inconsistent/erroneous information received from the operating system. Proceed with operating system software support avenues.
Corrective Action Code: 3
Follow the recommended corrective action shown in the termination corrective action code of this event's detailed information. The cause of the controller termination associated with this controller event can only be determined by obtaining the detailed information of the associated termination event. To obtain that information follow Corrective Action [[06]].
Corrective Action Code: 4
Follow the recommended corrective action described in the recursing termination event. Perform these steps to obtain that termination event's information:
<UL>
<LI>View the termination events of the HSV210 controller shown in this termination event's detailed information. NOTE: If that controller is not currently operating, the event of interest will not be available for viewing.
<LI>Locate the termination event that occurred closest to the date and time shown in this termination event's detailed information and obtain that termination event's detailed information. NOTE: The termination event of interest will show termination location, termination code and termination parameters that are identical to the recursive event termination location, recursive event termination code and recursive event termination parameters 0 through 28 shown in this termination event.
</UL>
Corrective Action Code: 5
Follow the recommended corrective action described in the termination event reported by the other controller that caused this termination event to occur. Perform these steps to obtain that termination event's information:
<UL>
<LI>View the termination events of the other HSV210 controller (i.e., the controller NOT shown in this termination event's detailed information). NOTE: If that controller is not currently operating, the event of interest will not be available for viewing.
<LI>Locate the termination event that occurred closest to the date and time shown in this termination event's detailed information and obtain that termination event's detailed information. NOTE: The termination event of interest will show a termination location and termination code that are identical to the other controller termination location and other controller termination code shown in this termination event.
</UL>
Corrective Action Code: 6
Perform these steps to obtain the termination information associated with this controller event:
<UL>
<LI>View the termination events of the HSV210 controller shown in this event's detailed information. NOTE: If that controller is not currently operating, the event of interest will not be available for viewing.
<LI>Locate the termination event that occurred closest to the date and time shown in this event's detailed information and obtain that termination event's detailed information. NOTE: The termination event of interest will show software version, baselevel ID, and uptime information identical to that shown in this event's detailed information for the terminating controller.
</UL>
Corrective Action Code: 7
A significant hardware detected fault occurred or a significant software inconsistency was detected. Accumulate information to report to HSV210 controller engineering.
Corrective Action Code: 8
A significant hardware detected fault occurred or a significant software inconsistency was detected. Accumulate information to report to HSV210 controller engineering.
Corrective Action Code: 9
Determine power loss cause and take appropriate action to ensure power is restored and maintained.
Corrective Action Code: a
A portion of low memory is purposely set to produce an uncorrectable memory error in order to detect low memory access violations made by the HSV210 controller's software (e.g., access to memory address zero through an uninitialized pointer, etc.). Unfortunately, there is no method available for immediately distinguishing a low memory access violation from an uncorrectable memory error that occurs elsewhere in memory. However, the memory diagnostics that are executed following controller restart will immediately terminate HSV210 controller operation if any portion of memory is found defective. In that case perform corrective action [[20]]. If defective memory is not found during HSV210 controller restart and this termination event is again reported, the most likely cause is a software induced low memory access violation. In that case perform corrective action [[01]].
Corrective Action Code: b
The GLUE eeprom on this HSV210 controller has been reprogrammed with new GLUE chip code. This HSV210 controller must be power cycled to complete the GLUE chip code update procedure. <P> In addition, this HSV210 controller's functional code has been updated. Controller operations will continue with the old functional code until the power cycle necessary to complete the GLUE chip code update is performed. NOTE: If a spontaneous termination of controller operations occurs before the controller's power is cycled, this HSV210 controller will be running new functional code with old GLUE code after the controller restarts which will result in a termination of controller operation. To recover from that situation this HSV210 controller must be power cycled. After doing so, this HSV210 controller will be running new functional code with new GLUE code after the controller restarts which will allow normal controller operations to resume.
Corrective Action Code: 20
Replace the HSV210 controller Field Replaceable Unit (FRU). Note that the FRU must be a single power supply type if so indicated in this event's detailed information.
Corrective Action Code: 22
Replace the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly closest to the cache battery door hinge. CAUTION: The information described in corrective action [[38]] must be understood before attempting a cache battery replacement.
Corrective Action Code: 23
Replace the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly farthest from the cache battery door hinge. CAUTION: The information described in corrective action [[38]] must be understood before attempting a cache battery replacement.
Corrective Action Code: 24
Replace the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower farthest from the blower door hinge.
Corrective Action Code: 25
Replace the "2" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower closest to the blower door hinge.
Corrective Action Code: 26
Replace the "1" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply closest to the cache battery door hinge.
Corrective Action Code: 27
Replace the "2" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply farthest from the cache battery door hinge.
Corrective Action Code: 28
Reinstall the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly closest to the cache battery door hinge.
Corrective Action Code: 29
Reinstall the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the battery assembly farthest from the cache battery door hinge.
Corrective Action Code: 2a
Reinstall the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower farthest from the blower door hinge.
Corrective Action Code: 2b
Reinstall the "2" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the blower closest to the blower door hinge.
Corrective Action Code: 2c
Reinstall the "1" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply closest to the cache battery door hinge, or restore AC power.
Corrective Action Code: 2d
Reinstall the "2" Blower/Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the blower/power supply farthest from the cache battery door hinge, or restore AC power.
Corrective Action Code: 2e
Reduce the ambient temperature in the vicinity of the indicated HSV210 controller.
Corrective Action Code: 2f
Ensure that both batteries in the indicated HSV210 controller are installed and functioning normally. A cache battery failure will be indicated by the red battery status LED located on the OCP display. If that LED is on, open the battery compartment door and check for the amber status LED in the lower right corner of each battery assembly. If the amber status LED is ONLY on in the battery assembly closest to the battery compartment door hinge, perform corrective action [[22]]. If the amber status LED is ONLY on in the battery assembly farthest from the cache battery door hinge, perform corrective action [[23]]. If the amber status LED is on in BOTH battery assemblies, perform [[22]] and [[23]] simultaneously.
Corrective Action Code: 30
GBIC SFF Serial ID Data check code failure. Corrective action: Try re-seating the GBIC, if failure persists, replace the GBIC, lastly perform corrective action [[20]].
Corrective Action Code: 36
The temperature on the HSV210 controller has become critical. Proceed with corrective action [[2e]] and restart the controller.
Corrective Action Code: 37
The temperature on the HSV210 controller could not be accurately determined possibly due to faulty operation of a temperature sensor or the temperature acquisition communication path. If the problem persists, perform Corrective Action [[20]].
Corrective Action Code: 38
Before performing cache battery replacement the following must be understood:
<UL>
<LI>CAUTION: Never remove batteries from the controller while it is powered down. Replace a cache battery only when the controller power is on.
<LI>CAUTION: If the amber status LED is on in both battery assemblies, both batteries must be removed before installing either of the new batteries. If one of the batteries is replaced while the other failed battery is still in the enclosure, the original failure may be propagated to the newly installed battery. To ensure there is no propagated failure, wait a minimum of 15 seconds after the removal of both batteries before inserting the new batteries.
<LI>CAUTION: Never install a battery that was previously failed by any controller.
<LI>NOTE: When installing a cache battery, the amber status LED will initially be on. The LED may remain on for up to two minutes, after which time it will turn off.
<LI>NOTE: It will take several hours for the EVA controller to recognize a new battery as fully charged. If a pair of batteries has been replaced, this period will be noticeably longer.
</UL>
Corrective Action Code: 39
If this event is an isolated occurrence, then no further action is necessary. If this event occurs more than once in a three month period, perform Corrective Action [[20]].
Corrective Action Code: 3a
Insert and re-seat the GBIC. If failure persists, replace the GBIC, or lastly perform Corrective Action [[20]].
Corrective Action Code: 3b
Isolated occurrences of this event may be safely ignored. If this event occurs more than once in a three month period, perform Corrective Action [[20]].
Corrective Action Code: 40
Replace the indicated physical disk drive.
Corrective Action Code: 41
Reinstall the indicated physical disk drive or install a drive blank.
Corrective Action Code: 42
Perform these steps in an attempt to clear the error:
<UL>
<LI>Remove and reinstall the indicated physical disk drive.
<LI>Observe the drive's status LEDs to ensure that the drive is operational.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure the error no longer exists.
</UL>If the error persists, perform Corrective Action [[40]].
Corrective Action Code: 43
Perform these steps in an attempt to clear the error:
<UL>
<LI>Remove and reinstall the indicated physical disk drive into the leftmost empty bay, preferably in a different Drive Enclosure.
<LI>If the error persists, perform Corrective Action [[89]].
<LI>If the error still persists, perform Corrective Action [[40]].
</UL>
Corrective Action Code: 44
A Fibre Channel port has failed. This may be caused by a failure on the indicated HSV210 controller, or the coprresponding Fibre Channel Switch. Proceed with corrective action [[01]].
Corrective Action Code: 46
Numerous failures have occurred while attempting to communicate with a particular Physical Disk Drive on a particular Fibre Channel port. The HSV210 controller will attempt to use an alternate Fibre Channel port to communicate with that Physical Disk Drive. If communication fails on the alternate Fibre Channel port, that Physical Disk Drive will be rendered inoperable. This is a preemptive action warning, no immediate action is necessary.
Corrective Action Code: 47
Dropped frames are potential indications of an impending Fibre Channel port or physical disk drive failure when they occur excessively. If frame drop becomes excessive, the indicated Fibre Channel port or the indicated physical disk drive will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary.
Corrective Action Code: 48
Unexpected work from a physical disk drive is an indication of an impending drive failure. If unexpected work becomes excessive, the indicated physical disk drive will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary.
Corrective Action Code: 49
Bad ALPAs are indications of an impending physical disk drive failure. If the number of bad ALPAs becomes excessive, the indicated physical disk drive will be placed in the inoperative state. This is a preemptive action warning, no immediate action is necessary.
Corrective Action Code: 4a
Unable to communicate through a Fibre Channel link to a Fibre Channel port. This may be caused by a missing Fibre connection to an HSV210 controller Host Port or Drive Enclosure, faulty GBIC, faulty Drive Enclosure, faulty Fibre Channel Cable, faulty Drive Enclosure I/O module, or faulty Fibre Channel Switch. This is a preemptive action warning, no immediate action is necessary.
Corrective Action Code: 4c
This event is probably a symptom of another problem. Check for failed Fibre Channel ports and multiple instances of this event. Also check for patterns, such as multiple occurrences of this event pertaining to physical disk drives on the same rack or loop. If this is an isolated occurrence of this event, ungroup the indicated physical disk drive and remove it from the system.
Corrective Action Code: 4d
Load the latest physical disk drive firmware superfile for the physical disk drive type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be ungrouped and removed. Using a superfile that updates the controller approved firmware table may be sufficient to correct the problem.
Corrective Action Code: 4e
This event is probably a symptom of another problem. Check for failed Fibre Channel ports and multiple instances of this event. Also check for patterns, such as multiple occurrences of this event pertaining to physical disk drives on the same rack or loop.
Corrective Action Code: 4f
Remove the indicated physical disk drive and install a drive blank.
Corrective Action Code: 50
Delete the indicated inoperative Snapshot Logical Disk.
Corrective Action Code: 51
Evaluate previously reported Physical Device, Device Enclosure, and Logical Disk events to determine root cause and corrective action.
Corrective Action Code: 52
Delete the indicated inoperative Logical Disk, unless an instant restore operation is possible.
Corrective Action Code: 5f
Unable to communicate to the destination controllers, or through a specific path to the destination. Check to see if the destination controllers have malfunctioned, and perform the repair actions indicated in event reports found for the destination controllers. In addition, check for a malfunction that may have occurred in the Fibre Channel fabric between the sites.
Corrective Action Code: 60
Unable to communicate to the indicated source virtual disk, because the virtual disk or another member in the Data Replication Group malfunctioned. Perform the repair actions indicated in event reports found for that source virtual disk or another virtual disk member in that Data Replication Group.
Corrective Action Code: 61
Unable to communicate to the indicated destination virtual disk on the remote Storage System because the virtual disk malfunctioned. Perform the repair actions indicated in event reports found for that destination virtual disk on the remote Storage System.
Corrective Action Code: 62
The Data Replication Log for the specified Data Replication Group has insufficient space to grow the log. A copy resynchronization will be started when data replication can resume. Evaluate whether sufficient disk storage has been made available for the log to grow in capacity. If necessary, add new volumes to the Disk Group.
Corrective Action Code: 63
The Data Replication Source Site and the Data Replication Destination Site cannot communicate because the software versions are incompatible. Communication will automatically continue when both sites are at compatible software levels.
Corrective Action Code: 64
Check the Data Replication Destination Site for problems with physical disk drives or fibre channel loops. The Data Replication Destination Site may also be temporarily experiencing higher than usual levels of disk related activity.
Corrective Action Code: 65
Check the Data Replication Destination Site for slow or no response for this Data Replication Group. If this is not the case then restart the Data Replication Destination Site controllers. Then restart the Data Replication Source Site controllers.
Corrective Action Code: 66
Check both the Data Replication Source Site and the Data Replication Destination Site for slow or no response for this Data Replication Group. If this is not the case then restart the Data Replication Source Site controllers. IF you have already taken this action and are receiving this event for a second time then restart the Data Replication Destination Site controllers instead.
Corrective Action Code: 67
Check link speed and quality between the Data Replication Source Site controllers and the Data Replication Destination Site controllers.
Corrective Action Code: 68
Reduce the number of controller pairs on the fabric to the supported maximum.
Corrective Action Code: 69
Check fabric switch settings and inter site link quality between the Data Replication Source Site controllers and the Data Replication Destination Site controllers.
Corrective Action Code: 80
Perform these steps in an attempt to clear the error:
<UL>
<LI>Remove and reinstall the indicated drive enclosure power supply.
<LI>Observe the power supply/blower status LED to ensure that the power supply is operational.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure that the error no longer exists.
</UL>If the error persists, immediately (within 7 minutes) perform Corrective Action [[81]]. If that action cannot be performed immediately, perform Corrective Action [[85]] immediately.
Corrective Action Code: 81
Replace the indicated drive enclosure power supply. Hewlett-Packard recommends not removing a defective drive enclosure power supply until a replacement drive enclosure power supply is available.
Corrective Action Code: 82
Perform these steps in an attempt to clear the error:
<UL>
<LI>Remove and reinstall the indicated drive enclosure blower.
<LI>Observe the power supply/blower status LED to ensure that the blower is operational.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure that the error no longer exists.
</UL>If the error persists, perform Corrective Action [[83]].
Corrective Action Code: 83
Replace the indicated drive enclosure blower. CAUTION: Removing a blower automatically closes flaps over the power supply blower opening. However, the air flow within the enclosure changes and can cause an over temperature condition. Hewlett-Packard recommends not removing a defective blower until a replacement blower is available.
Corrective Action Code: 84
Immediately replace one of the missing drive enclosure blowers. The other blower should be replaced as soon as possible. If a blower is not available for immediate replacement, perform Corrective Action [[85]] immediately.
Corrective Action Code: 85
If the problem cannot be corrected, the Enterprise Virtual Array should be shut down to:
<UL>
<LI>Flush data from the controllers.
<LI>Shut down the drive enclosures.
<LI>Shut down the controllers.
</UL>CAUTION: This is a drastic measure that will stop all Enterprise Virtual Array operations. Hewlett-Packard recommends using this procedure only when necessary to protect a drive enclosure from overheating or to clear drive enclosure errors that cannot otherwise be cleared.
Corrective Action Code: 86
If the indicated drive enclosure element's temperature sensor is high, follow these steps to correct the over temperature condition:
<UL>
<LI>Ensure that all elements are properly installed to maintain proper air flow.
<LI>Ensure that nothing is obstructing the air flow at either the front of the enclosure or the rear of the blower.
<LI>Ensure that both blowers are operating properly (the LEDs are on) and neither blower is operating at high speed. If a blower appears to be defective, perform Corrective Action [[83]].
<LI>Verify that the ambient temperature is within the range +10C to +35C (+50F to +95F). Adjust as necessary.
</UL>If the indicated drive enclosure element's temperature sensor is low, follow this step to correct the below temperature condition:
<UL>
<LI>Verify that the ambient temperature is within the range +10C to +35C (+50F to +95F). Adjust as necessary.
</UL>After performing the actions described above observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure that the error no longer exists.
Corrective Action Code: 87
Immediately perform Corrective Action [[86]]. If the problem persists after performing those actions, perform Corrective Action [[85]] immediately.
Corrective Action Code: 88
Reset the indicated Drive Enclosure Environmental Monitoring Unit using the following procedure:
<UL>
<LI>Firmly grasp the Drive Enclosure Environmental Monitoring Unit mounting handle and pull the Drive Enclosure Environmental Monitoring Unit partially out of the enclosure. <P> IMPORTANT: You do not need to remove the Drive Enclosure Environmental Monitoring Unit from the enclosure, nor to disconnect the cables. You must avoid putting any strain on the cables or connectors.
<LI>Wait 30 seconds, and then push the Drive Enclosure Environmental Monitoring Unit in and fully seat the element in the backplane. The Drive Enclosure Environmental Monitoring Unit should display any enclosure condition report within two minutes.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure that the error no longer exists.
</UL>If the problem persists, perform Corrective Action [[89]].
Corrective Action Code: 89
Replace the indicated Drive Enclosure Environmental Monitoring Unit.
Corrective Action Code: 8a
The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[89]].
Corrective Action Code: 8b
Perform these steps in an attempt to clear the error:
<UL>
<LI>Perform Corrective Action [[88]] with the exception of performing Corrective Action [[89]] if the problem persists.
<LI>If resetting the Drive Enclosure Environmental Monitoring Unit did not correct the problem, perform Corrective Action [[8d]] to initialize the drive enclosure.
</UL>If the problem still persists, then perform Corrective Action [[89]].
Corrective Action Code: 8c
The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[8b]].
Corrective Action Code: 8d
Initialize the indicated drive enclosure by:
<UL>
<LI>Disconnecting the AC power cords from both power supplies. CAUTION: This is a dramatic measure that will result in data being unavailable until power is reapplied.
<LI>Reconnecting the AC power cords to both power supplies.
</UL>
Corrective Action Code: 8e
This error may be caused by a defective drive enclosure address bus cable, an incorrectly connected cable, or a defective enclosure address bus junction box. Perform these steps in an attempt to clear the error:
<UL>
<LI>Remove and reconnect the cable between the address bus junction box and the Drive Enclosure Environmental Monitoring Unit.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit to ensure the error is corrected.
<LI>If the problem is not corrected, remove and reinstall the bottom and top terminators, and all the junction box-to-junction box cables.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit to ensure the error is corrected.
<LI>If the problem is not corrected, perform Corrective Action [[88]].
</UL>
Corrective Action Code: 8f
Perform these steps in an attempt to clear the error:
<UL>
<LI>If one of the drive enclosure power supplies has remained powered on, replace the power supply that remains on.
<LI>If both power supplies remain on, check Drive Enclosure Environmental Monitoring Unit communications with all drive enclosure components.
<LI>If the Drive Enclosure Environmental Monitoring Unit is unable to communicate, individually replace drive enclosure power supplies, I/O modules, and the Drive Enclosure Environmental Monitoring Unit until the problem is resolved.
<LI>If component replacement does not resolve the problem, replace the drive enclosure.
</UL>
Corrective Action Code: 90
Perform these steps in an attempt to clear the error:
<UL>
<LI>Check if one of the HSV210 controllers has suffered a power failure. If so, perform Corrective Action [[09]].
<LI>Check all the transceivers and cables to ensure they are properly connected. Reseat any that are not properly connected.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit to ensure the error is corrected.
<LI>If the problem is not corrected, check all the transceivers on the loop to ensure that they are drive enclosure I/O module compatible. Replace any transceivers that are found to be incompatible.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit to ensure the error is corrected.
<LI>If the problem is not corrected, replace the input cable connected to the indicated transceiver.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit to ensure the error is corrected.
<LI>If the problem is not corrected, replace both transceivers attached to the cable that is connected to the indicated transceiver.
</UL>
Corrective Action Code: 91
Replace the indicated drive enclosure.
Corrective Action Code: 92
The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[91]].
Corrective Action Code: 93
Replace the indicated drive enclosure I/O module.
Corrective Action Code: 94
The Drive Enclosure Environmental Monitoring Unit attempts to automatically correct this type of error. If the problem persists after one minute has elapsed, perform Corrective Action [[93]].
Corrective Action Code: 95
Reset the indicated device enclosure I/O module using the following procedure:
<UL>
<LI>Remove the I/O module.
<LI>Reinsert the I/O module.
<LI>Observe the Drive Enclosure Environmental Monitoring Unit alphanumeric display to ensure that the error no longer exists.
</UL>If the problem persists, perform Corrective Action [[93]].
Corrective Action Code: 96
The Drive Enclosure Environmental Monitoring Unit has requested new Drive Enclosure Environmental Monitoring Unit code. The code could not be found. Upgrade with the latest revision of the Drive Enclosure Environmental Monitoring Unit code update.
Corrective Action Code: 97
Ensure all HSV210 controllers are connected to the enclosure address bus. If all controllers are connected, then replace the Y-cable and restart the controllers.
Corrective Action Code: 98
Reduce the number of drive enclosures.
Corrective Action Code: 99
Ensure that each drive enclosure I/O module is connected to the correct Fibre Channel port.
Corrective Action Code: 9a
Ensure A/C input to the rack PDU is intact, otherwise perform [[81]].
Corrective Action Code: 9b
If the element is not redetected within 10 minutes, the indicated Drive Enclosure Environmental Monitoring Unit may need to be replaced. The problem may be caused by the controller not being able to communicate with the drives in this enclosure for reasons that are unrelated to the Drive Enclosure Environmental Monitoring Unit.
Corrective Action Code: 9c
Ungroup and replace the physical disk drive. If this does not correct the problem, replace the Drive Enclosure Environmental Monitoring Unit and power cycle the physical disk drive. If the problem is persistent, replace Device Enclosure.
Corrective Action Code: b4
Add new volumes to the Disk Group or increase the Disk Group occupancy alarm level threshold.
Corrective Action Code: b5
Add new volumes to the Disk Group or delete unwanted logical disks from Disk Group.
Corrective Action Code: b6
To restore the Disk Group to a Single Point of Failure Robust Configuration add more physical disk drives or rearrange the existing Single Point of Failure Robust Configuration to ensure the physical disk drives members are on different Fibre Channel device enclosures.
Corrective Action Code: b9
Evaluate previously reported events associated with this HSV210 controller to determine root cause and corrective action.
Corrective Action Code: ba
Check to see if this HSV210 controller has suffered a power failure. If so, perform Corrective Action [[09]]. Otherwise, perform Corrective Action [[b9]].
Corrective Action Code: bf
Evaluate previously reported Device or Device Enclosure events that related to the Physical Disk Drive that is associated with this Volume to determine root cause and corrective action.
Corrective Action Code: c3
Evaluate previously reported Device, Device Enclosure, and Host events to determine root cause and corrective action. If the problem persists, follow Corrective Action [[20]].
Corrective Action Code: c4
Load the latest physical disk drive firmware superfile for the physical disk drive type shown in the SCSI Product ID of this event's detailed information. If no such superfile exists, the physical disk drive is unsupported, and should be ungrouped and removed. Using a superfile that updates the controller approved firmware table may be sufficient to correct the problem.
Corrective Action Code: c5
Check enclosure address bus cable connections between Drive Enclosure Environmental Monitoring Unit and nodes. If cabling is not the problem, the node or Drive Enclosure Environmental Monitoring Unit may need to be replaced.
Corrective Action Code: c8
Replace the "0" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper left battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement.
Corrective Action Code: c9
Replace the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower left battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement.
Corrective Action Code: ca
Replace the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper right battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement.
Corrective Action Code: cb
Replace the "3" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower right battery assembly. CAUTION: The information described in corrective action [[d1]] must be understood before attempting a cache battery replacement.
Corrective Action Code: cc
Reinstall the "0" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper left battery assembly.
Corrective Action Code: cd
Reinstall the "1" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower left battery assembly.
Corrective Action Code: ce
Reinstall the "2" Battery Assembly Field Replaceable Unit (FRU)--i.e., the upper right battery assembly.
Corrective Action Code: cf
Reinstall the "3" Battery Assembly Field Replaceable Unit (FRU)--i.e., the lower right battery assembly.
Corrective Action Code: d0
Ensure the required number of batteries in the indicated HSV210 controller are installed and functioning normally. Each battery assembly has a green LED located to the side of a battery symbol label and an amber LED located to the side of a caution symbol label. A cache battery failure will be indicated when the amber LED is on and the green LED is off. If the upper left battery assembly is failed, perform corrective action [[c8]]. If the lower left battery assembly is failed, perform corrective action [[c9]]. If the upper right battery assembly is failed, perform corrective action [[ca]]. If the lower right battery assembly is failed, perform corrective action [[cb]].
Corrective Action Code: d1
Before performing cache battery replacement the following must be understood:
<UL>
<LI>CAUTION: Never remove batteries from the controller while it is powered down. Replace a cache battery only when the controller power is on.
<LI>CAUTION: Never install a battery that was previously failed by any controller.
<LI>NOTE: When installing a cache battery, the amber status LED will initially be on after insertion. It will remain on for several seconds while initial battery integrity is checked, after which time it will turn off.
<LI>NOTE: It will take several hours for the EVA controller to recognize a new battery as fully charged.
</UL>
Corrective Action Code: d2
Replace the "0" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top blower.
Corrective Action Code: d3
Replace the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the bottom blower.
Corrective Action Code: d4
Reinstall the "0" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the top blower.
Corrective Action Code: d5
Reinstall the "1" Blower Assembly Field Replaceable Unit (FRU)-- i.e., the bottom blower.
Corrective Action Code: d6
Verify AC connection integrity of "0" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the left power supply. Replace assembly if AC connection is good and malfunction persists.
Corrective Action Code: d7
Verify AC connection integrity of "1" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the right power supply. Replace assembly if AC connection is good and malfunction persists.
Corrective Action Code: d8
Reinstall the "0" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the left power supply.
Corrective Action Code: d9
Reinstall the "1" Power Supply Assembly Field Replaceable Unit (FRU)-- i.e., the right power supply.
Corrective Action Code: da
If this event is an isolated occurrence, then no further action is necessary. Perform these steps in an attempt to clear persistent occurrences:
<UL>
<LI>If this event persistently occurs for each installed battery brick in the controller, then verify the correct SDC version is installed.
<LI>If this event persistently occurs for the "0" Battery Assembly, perform Corrective Action [[c8]].
<LI>If this event persistently occurs for the "1" Battery Assembly, perform Corrective Action [[c9]].
<LI>If this event persistently occurs for the "2" Battery Assembly, perform Corrective Action [[ca]].
<LI>If this event persistently occurs for the "3" Battery Assembly, perform Corrective Action [[cb]].
<LI>If all previous steps fail to stop event from occurring, perform Corrective Action [[01]]
</UL>
Corrective Action Code: db
This event indicates a SLAVE ROHS compliant controller is being force loaded from the MASTER with code that is inappropriate for this hardware. This will continue until this controller is made MASTER or the current master is upgraded to the appropriate level of code that will run on both controllers.
SOFTWARE COMPONENT ID CODES:
Software Component ID Code: 1
Executive Services
Software Component ID Code: 2
Cache Management Component
Software Component ID Code: 3
Storage System State Services
Software Component ID Code: 4
Fault Manager
Software Component ID Code: 6
Fibre Channel Services
Software Component ID Code: 7
Container Services
Software Component ID Code: 8
Raid Services
Software Component ID Code: 9
Storage System Management Interface
Software Component ID Code: b
System Services (DFP, XMFC, etc. processing)
Software Component ID Code: c
Data Replication Manager Component
Software Component ID Code: d
Disk Enclosure Environmental Monitoring Unit Services
Software Component ID Code: e
System Data Center
Software Component ID Code: 42
Host Port
Software Component ID Code: 83
Diagnostic Operations Generator
Software Component ID Code: 84
Diagnostic Runtime Services (Scrubbing, UPS, temp/battery/voltage monitoring, etc.)
EVENT CODES:
Event Code: 0102000d
Severity: Normal -- informational in nature. A time change occurred.
Event Code: 0300200a
Severity: Critical -- failure or failure imminent. An HSV210 controller has failed in communicating with the Cabinet (Rack) Bus Interface Controller.
Event Code: 0301400b
Severity: Critical -- failure or failure imminent. A physical disk drive has been rendered inoperable.
Event Code: 03024f0b
Severity: Warning -- not failed but attention recommended or required. A physical disk drive will not be used because the maximum number of physical disk drives already exist in the current Storage System.
Event Code: 0303000a
Severity: Normal -- informational in nature. An HSV210 controller has begun booting.
Event Code: 0304000a
Severity: Normal -- informational in nature. An HSV210 controller has finished the process of bringing the Storage System online.
Event Code: 0305000a
Severity: Normal -- informational in nature. An HSV210 controller has been joined into the Storage System.
Event Code: 0306000a
Severity: Normal -- informational in nature. An HSV210 controller has been ousted from the Storage System.
Event Code: 0307000a
Severity: Normal -- informational in nature. An HSV210 controller is now the Storage System Master.
Event Code: 0308000a
Severity: Normal -- informational in nature. An HSV210 controller has been brought into the Storage System.
Event Code: 03090018
Severity: Normal -- informational in nature. The Redundant Storage Set has started migrating members.
Event Code: 030a0018
Severity: Normal -- informational in nature. The Redundant Storage Set has finished migrating members.
Event Code: 030b4f0b
Severity: Warning -- not failed but attention recommended or required. A physical disk drive has failed during Storage System realization.
Event Code: 030c001e
Severity: Normal -- informational in nature. The DebugFlags and/or PrintFlags have changed.
Event Code: 030d001e
Severity: Normal -- informational in nature. Process with work during CSM reset:
Event Code: 030e070b
Severity: Warning -- not failed but attention recommended or required. About to write ID block to wrong physical disk drive.
Event Code: 030f001e
Severity: Normal -- informational in nature. RoHS Status of the HSV210 controller has been determined.
Event Code: 0310001f
Severity: Normal -- informational in nature. A Storage System Virtual Disk has changed controller mastership.
Event Code: 03114420
Severity: Critical -- failure or failure imminent. A Fibre Channel Switch responded to a fabric port login. The corresponding device Fibre Channel port on the specified HSV210 controller has been failed.
Event Code: 03120021
Severity: Normal -- informational in nature. A Logical Disk attach operation has completed. Refer to event details for completion status.
Event Code: 03130021
Severity: Normal -- informational in nature. A snapclone Logical Disk has completed the unsharing operation.
Event Code: 03140021
Severity: Normal -- informational in nature. A mirror clone Logical Disk has completed the detach operation.
Event Code: 03150021
Severity: Normal -- informational in nature. A mirror clone Logical Disk has completed the fracture operation.
Event Code: 03160021
Severity: Normal -- informational in nature. A mirror clone Logical Disk has completed the synchronization operation.
Event Code: 03170021
Severity: Normal -- informational in nature. A Logical Disk has completed the instant restore operation.
Event Code: 0400031c
Severity: Undetermined -- more information needed to determine severity. HSV210 controller operation was terminated due to an unrecoverable event detected by either software or hardware or due to an action initiated via the Storage System Management Interface.
Event Code: 0401031c
Severity: Undetermined -- more information needed to determine severity. This HSV210 controller has received a last gasp message from another HSV210 controller prior to it terminating operation.
Event Code: 04020101
Severity: Critical -- failure or failure imminent. A machine check occurred while a termination event was being processed.
Event Code: 04030102
Severity: Critical -- failure or failure imminent. An unexpected event occurred while a termination event was being processed.
Event Code: 04040003
Severity: Normal -- informational in nature. The Storage System Event Log validation completed successfully.
Event Code: 04050003
Severity: Normal -- informational in nature. The Storage System Event Log validation failed.
Event Code: 04060803
Severity: Normal -- informational in nature. Local event reports were lost due to an insufficient supply of Event Log Packets on this HSV210 controller.
Event Code: 04070803
Severity: Normal -- informational in nature. Remote event reports were lost due to an insufficient supply of Event Log Packets on this HSV210 controller.
Event Code: 04080003
Severity: Normal -- informational in nature. The Storage System Termination Event Log has become inaccessible.
Event Code: 04090003
Severity: Normal -- informational in nature. The Storage System Termination Event Log validation completed successfully.
Event Code: 040a0003
Severity: Normal -- informational in nature. The Storage System Termination Event Log validation failed.
Event Code: 040b0003
Severity: Normal -- informational in nature. The Storage System Termination Event Log has been updated with the termination event information obtained from the HSV210 controller that is not the Storage System Master.
Event Code: 040c0803
Severity: Normal -- informational in nature. The Fault Manager on the Storage System Master received an invalid Event Information Packet from the remote Fault Manager.
Event Code: 040d0003
Severity: Normal -- informational in nature. The Fault Manager operation was made quiescent.
Event Code: 040e031c
Severity: Undetermined -- more information needed to determine severity. An HSV210 controller sent a last gasp message prior to terminating operation with an indication that both HSV210 controllers should terminate operation.
Event Code: 040f0003
Severity: Normal -- informational in nature. This HSV210 controller sent its termination event information to the HSV210 controller that is the Storage System Master.
Event Code: 04100803
Severity: Normal -- informational in nature. Event reports were lost due to an insufficient supply of ISR Event Log Packets on the HSV210 controller that is the Storage System Master.
Event Code: 04110803
Severity: Normal -- informational in nature. Event reports were lost due to an insufficient supply of ISR Event Log Packets on the HSV210 controller that is not the Storage System Master.
Event Code: 04120003
Severity: Normal -- informational in nature. The last event reporting interval has changed or last event reporting has been enabled or disabled.
Event Code: 04130003
Severity: Normal -- informational in nature. Storage System event reporting is still active.
Event Code: 0414031d
Severity: Undetermined -- more information needed to determine severity. HSV210 controller operation was terminated due to an unrecoverable event detected by either software or hardware or due to an action initiated via the Storage System Management Interface.
Event Code: 0415031d
Severity: Undetermined -- more information needed to determine severity. This HSV210 controller has received a last gasp message from another HSV210 controller prior to it terminating operation.
Event Code: 0416031d
Severity: Undetermined -- more information needed to determine severity. An HSV210 controller sent a last gasp message prior to terminating operation with an indication that both HSV210 controllers should terminate operation.
Event Code: 04180003
Severity: Normal -- informational in nature. The Manufacturing Event Analysis Log validation completed successfully.
Event Code: 04190003
Severity: Normal -- informational in nature. The Manufacturing Event Analysis Log validation failed.
Event Code: 041a031c
Severity: Undetermined -- more information needed to determine severity. An error condition was encountered while this HSV210 controller's Last Termination Event information was being processed.
Event Code: 041b031d
Severity: Undetermined -- more information needed to determine severity. An error condition was encountered while this HSV210 controller's Last Termination Event information was being processed.
Event Code: 06000009
Severity: Normal -- informational in nature. A physical disk drive has reported that it has exceeded its failure prediction threshold.
Event Code: 06014a08
Severity: Warning -- not failed but attention recommended or required. A Fibre Channel port on the HSV210 controller has failed to respond.
Event Code: 06020009
Severity: Normal -- informational in nature. A physical disk drive has reported a check condition error.
Event Code: 06034713
Severity: Warning -- not failed but attention recommended or required. An exchange sent to a physical disk drive or another HSV210 controller via the mirror port or a Fibre Channel port has timed out.
Event Code: 06044812
Severity: Warning -- not failed but attention recommended or required. Work was unexpectedly sent to this HSV210 controller by a physical disk drive or another HSV210 controller.
Event Code: 06054909
Severity: Warning -- not failed but attention recommended or required. Work has been sent to a physical disk drive or another HSV210 controller via the mirror port but it did not respond.
Event Code: 06074709
Severity: Warning -- not failed but attention recommended or required. A Target Discovery Service Descriptor exchange sent to a physical disk drive has timed out.
Event Code: 06080007
Severity: Normal -- informational in nature. An excessive number of link errors were detected on a HSV210 controller's Fibre Channel port. This informational event is triggered by the occurrence of an excessive number of Tachyon chip link status errors detected within a particular link status error type.
Event Code: 06090013
Severity: Normal -- informational in nature. A physical disk drive has reported numerous failure prediction threshold exceeded errors.
Event Code: 060a0013
Severity: Normal -- informational in nature. A physical disk drive has reported numerous check condition errors.
Event Code: 060b4709
Severity: Warning -- not failed but attention recommended or required. A non-data exchange sent to a physical disk drive has timed out.
Event Code: 060c0013
Severity: Normal -- informational in nature. A loop switch has been detected on a Fibre Channel port.
Event Code: 060d0013
Severity: Normal -- informational in nature. The location of a physical disk drive previously reported as unknown is now known.
Event Code: 060e9613
Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit requested a code update but the code update could not be found, so the update was not performed.
Event Code: 060f4013
Severity: Critical -- failure or failure imminent. The Drive Enclosure Environmental Monitoring Unit is able to communicate with a physical disk drive but this HSV210 controller is unable to communicate with that physical disk drive on the Fibre Channel bus.
Event Code: 06109b13
Severity: Undetermined -- more information needed to determine severity. An HSV210 controller is unable to communicate with this Drive Enclosure Environmental Monitoring Unit.
Event Code: 06120008
Severity: Normal -- informational in nature. The retry count for a task assigned to a Drive Enclosure Environmental Monitoring Unit has been exhausted.
Event Code: 06130013
Severity: Normal -- informational in nature. A Drive Enclosure Environmental Monitoring Unit is able to communicate with this HSV210 controller.
Event Code: 06149813
Severity: Critical -- failure or failure imminent. There are too many drive enclosures attached to a Fibre Channel port.
Event Code: 06159913
Severity: Critical -- failure or failure imminent. The cable connected to the I/O module is attached to the wrong Fibre Channel port.
Event Code: 06169713
Severity: Critical -- failure or failure imminent. An HSV210 controller does not have an address on the enclosure address bus.
Event Code: 06180013
Severity: Normal -- informational in nature. A Drive Enclosure Environmental Monitoring Unit has begun updating its code. Do not power down this drive enclosure until the code update has completed.
Event Code: 06190013
Severity: Normal -- informational in nature. A Drive Enclosure Environmental Monitoring Unit has completed updating its code. It is now safe to power down this drive enclosure.
Event Code: 061a0009
Severity: Normal -- informational in nature. A physical disk drive has exceeded its soft error threshold.
Event Code: 061b0013
Severity: Normal -- informational in nature. An HSV210 controller now has an address on the enclosure address bus.
Event Code: 061c4709
Severity: Warning -- not failed but attention recommended or required. An outbound frame targeted to a physical disk drive has timed out.
Event Code: 061d4709
Severity: Warning -- not failed but attention recommended or required. A Fibre Channel exchange to a physical disk drive has completed but is missing data.
Event Code: 061e4c13
Severity: Critical -- failure or failure imminent. An HSV210 controller has detected only one port of a Fibre Channel device.
Event Code: 061f0013
Severity: Normal -- informational in nature. A previously reported Fibre Channel device with only one port has been corrected and redundancy has been restored.
Event Code: 06204013
Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel device has been detected. The device has been failed to prevent possible data corruption or system instability.
Event Code: 06210013
Severity: Normal -- informational in nature. A Fibre Channel device with incorrect block size has been detected.
Event Code: 06230013
Severity: Normal -- informational in nature. An HSV210 controller is about to retry a failed port.
Event Code: 06240013
Severity: Normal -- informational in nature. An HSV210 controller has successfully retried a failed port.
Event Code: 06254313
Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has failed to assign a hard address to a physical disk drive on the loop.
Event Code: 06268913
Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has failed to assign an address to a physical disk drive on the loop. This has occurred because another physical disk drive has already obtained this AL_PA.
Event Code: 06270113
Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has failed to assign address(s) to a physical disk drive on the loop. Soft addressing was detected for this enclosure.
Event Code: 06280008
Severity: Normal -- informational in nature. The retry count for an OB task assigned to a Drive Enclosure Environmental Monitoring Unit has been exhausted.
Event Code: 06290009
Severity: Normal -- informational in nature. The HSV210 controller has sent a Basic Link Service command Abort Sequence Frame.
Event Code: 062a0009
Severity: Normal -- informational in nature. The HSV210 controller has sent an Extended Link Service command Reinstate Recovery Qualifier.
Event Code: 062b4004
Severity: Critical -- failure or failure imminent. A physical disk drive was bypassed rendering it unusable.
Event Code: 062c0012
Severity: Normal -- informational in nature. One or more media defects were detected on a physical disk drive.
Event Code: 062d0012
Severity: Normal -- informational in nature. An HSV210 controller issued a directed LIP to an arbitrated loop physical address.
Event Code: 062e0012
Severity: Normal -- informational in nature. An HSV210 controller has detected loop receiver failures.
Event Code: 06304e13
Severity: Critical -- failure or failure imminent. An HSV210 controller has detected only one port of all Fibre Channel devices in an enclosure.
Event Code: 06310013
Severity: Normal -- informational in nature. A previously reported Fibre Channel device enclosure with only one port has been corrected and redundancy has been restored.
Event Code: 06324e13
Severity: Critical -- failure or failure imminent. An HSV210 controller has detected only one port of all Fibre Channel devices on a loop.
Event Code: 06330013
Severity: Normal -- informational in nature. A previously reported Fibre Channel loop with only one port has been corrected and redundancy has been restored.
Event Code: 06340013
Severity: Normal -- informational in nature. An HSV210 controller has been told to enable a device port, and that device port was not disabled during boot diagnostics.
Event Code: 06354d04
Severity: Critical -- failure or failure imminent. An unrecognized Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process.
Event Code: 06364d04
Severity: Critical -- failure or failure imminent. An unsupported Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process.
Event Code: 0637c404
Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process that is later than the latest known supported revision.
Event Code: 0638c404
Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware revision has been detected by the physical disk drive firmware load process that has a newer supported revision available.
Event Code: 06394008
Severity: Critical -- failure or failure imminent. The HSV210 controller bypassed a device bay in an attempt to restore loop operability. Replace this drive only if the Loop Recovery algorithm did not abort.
Event Code: 063a0008
Severity: Normal -- informational in nature. The HSV210 controller is attempting to recover devices on the indicated ports.
Event Code: 063b0008
Severity: Normal -- informational in nature. The HSV210 controller has finished error recovery attempts on the indicated ports.
Event Code: 063c0008
Severity: Normal -- informational in nature. The HSV210 controller been requested to unbypass device bays on the indicated port. Loop recovery incomplete.
Event Code: 063d9b09
Severity: Undetermined -- more information needed to determine severity. The HSV210 controller has detected a enclosure on the enclosure address bus that does not have a Fibre Channel connection.
Event Code: 063ec513
Severity: Critical -- failure or failure imminent. The HSV210 controller has detected an enclosure on the Fibre Channel but is unable to communicate with the Drive Enclosure Environmental Monitoring Unit on the enclosure address bus or the Drive Enclosure Environmental Monitoring Unit is reporting an invalid enclosure number.
Event Code: 063f9c13
Severity: Warning -- not failed but attention recommended or required. A physical disk drive is using an improper protocol to attempt communication with an Drive Enclosure Environmental Monitoring Unit. The physical disk drive identified in the device field has stopped communicating with the HSV210 controller.
Event Code: 06404d04
Severity: Critical -- failure or failure imminent. A Fibre Channel physical disk drive that has new capabilities has been detected. The physical disk drive has properties that may or may not be compatible with this release of Enterprise Virtual Array firmware -- the drive will be prevented from being used until the Approved Drive Firmware table has been updated to allow it.
Event Code: 06410017
Severity: Normal -- informational in nature. The device loop configuration has changed on a HSV210 controller's Fibre Channel port. This informational event contains a page of the newly genereated fibre channel loop map. Devices are listed in loop order using their ALPAs.
Event Code: 06420009
Severity: Normal -- informational in nature. A user command has been sent to a physical disk drive.
Event Code: 06440008
Severity: Normal -- informational in nature. An HSV210 controller is evaluating the next drive enclosure in the Loop Recovery Process.
Event Code: 06450008
Severity: Normal -- informational in nature. An HSV210 controller has identified a starting point for the Loop Recovery Process. It does not mean this drive is defective.
Event Code: 06460008
Severity: Normal -- informational in nature. An HSV210 controller has determined the CAB bus is not usable at this time. A loop recovery operation will not be intitated.
Event Code: 06480008
Severity: Normal -- informational in nature. An HSV210 controller experienced the failure of an EMU unbypass operation during loop recovery. User should evaluate any bypassed drives that were not identified as loop disrupters during the recovery for possible re-introduction into the system.
Event Code: 06490008
Severity: Normal -- informational in nature. The HSV210 controller is attempting to recover devices in the indicated enclosure.
Event Code: 064a0008
Severity: Normal -- informational in nature. The HSV210 controller has finished error recovery attempts in the indicated enclosure.
Event Code: 064b0008
Severity: Normal -- informational in nature. The HSV210 controller has been instructed to Enable or Disable Loop Recovery Operations.
Event Code: 064c0004
Severity: Normal -- informational in nature. Device Fibre Channel physical disk drive was placed on the Drive Suspect List (DSL) Look at events around this one to help determine what has happened. Fibre Channel port number used to communicate with the physical disk drive is contained in the port field. The arbitrated loop physical address of the physical disk drive is contained in the al_pa field. Note that the content of the rack_num field will not be valid until
Event Code: 064d0008
Severity: Normal -- informational in nature. The HSV210 controller has finished attempts to codeload all Drive Enclosure Environmental Monitoring Unit hardware requiring updates, and has completed staggered codeload if necessary.
Event Code: 064e0009
Severity: Normal -- informational in nature. A physical disk drive has reported a non-zero RSP_CODE. in response to an I/O. This is not interesting by itself, as the I/O will be retried if retries remain and are allowed for the particular type of I/O.
Event Code: 0700b515
Severity: Warning -- not failed but attention recommended or required. Allocation of a Virtual Disk has stalled due to insufficient space in the Disk Group caused by the failure or pulling of a physical disk drive.
Event Code: 0701b515
Severity: Warning -- not failed but attention recommended or required. Expansion of a Virtual Disk has stalled due to insufficient space in the Disk Group caused by the failure or pulling of a physical disk drive.
Event Code: 07020015
Severity: Normal -- informational in nature. Leveling of capacity in a Disk Group has started.
Event Code: 07030015
Severity: Normal -- informational in nature. Leveling of capacity in a Disk Group has finished.
Event Code: 07040015
Severity: Normal -- informational in nature. A member management operation has started due to the appearance or disappearance of a physical disk drive.
Event Code: 07050015
Severity: Normal -- informational in nature. A member management operation has finished.
Event Code: 07060015
Severity: Normal -- informational in nature. A Disk Group has started changing its internal structure due to the appearance or disappearance of a Volume.
Event Code: 07070015
Severity: Normal -- informational in nature. A Disk Group has finished changing its internal structure due to the appearance or disappearance of a Volume.
Event Code: 07080015
Severity: Normal -- informational in nature. Deallocation of a Virtual Disk has failed after three attempts due to unknown circumstances. This will more than likely be caused by failing physical drives. The deletion will be restarted when a resync/reboot occurs.
Event Code: 0709b515
Severity: Warning -- not failed but attention recommended or required. A member management operation has stalled due to insufficient space in the Disk Group.
Event Code: 070a0015
Severity: Normal -- informational in nature. A stalled member management operation is being restarted.
Event Code: 070b0015
Severity: Normal -- informational in nature. Unexpected metadata utility event. If available, the tag1 field contains the identity of the Volume, and tag2 field contains the identity of the Logical Disk.
Event Code: 070d0015
Severity: Normal -- informational in nature. A member management operation encounter an error while processing a Logical Disk. Processing on this logical disk will be retried again.
Event Code: 09010005
Severity: Normal -- informational in nature. A physical disk drive has transitioned to the NORMAL state.
Event Code: 09020005
Severity: Normal -- informational in nature. The state of a Volume has changed.
Event Code: 09030005
Severity: Normal -- informational in nature. The state of a Logical Disk has changed.
Event Code: 09040005
Severity: Normal -- informational in nature. An HSV210 controller has transitioned to the NORMAL state.
Event Code: 09050005
Severity: Normal -- informational in nature. The state of a battery assembly has changed.
Event Code: 0906bf05
Severity: Undetermined -- more information needed to determine severity. A Volume has transitioned to the MISSING state.
Event Code: 09070005
Severity: Normal -- informational in nature. A Fibre Channel port has transitioned to the NORMAL state.
Event Code: 0908b405
Severity: Warning -- not failed but attention recommended or required. A Disk Group's occupancy alarm level threshold has been reached.
Event Code: 09090005
Severity: Normal -- informational in nature. The resource availability state of a Volume has transitioned to the SUFFICIENT state.
Event Code: 090a0005
Severity: Normal -- informational in nature. The data availability state of an internal Logical Disk has transitioned to the NORMAL state.
Event Code: 090c0005
Severity: Normal -- informational in nature. A snapclone Logical Disk has completed the unsharing operation.
Event Code: 090d0005
Severity: Normal -- informational in nature. The state of the quorum disk flag of a Volume has changed.
Event Code: 090e3605
Severity: Critical -- failure or failure imminent. The temperature trip point for a temperature sensor located within an HSV210 controller has been reached.
Event Code: 090f2e05
Severity: Warning -- not failed but attention recommended or required. The temperature within an HSV210 controller is approaching its trip point.
Event Code: 09110005
Severity: Normal -- informational in nature. An HSV210 controller's blower "1" is now present.
Event Code: 09122405
Severity: Critical -- failure or failure imminent. An HSV210 controller's blower "1" is running slower than the lowest acceptable speed.
Event Code: 09132005
Severity: Critical -- failure or failure imminent. A voltage sensor has reported a voltage that is out of range.
Event Code: 0914bf05
Severity: Undetermined -- more information needed to determine severity. A Volume has transitioned to the FAILED state.
Event Code: 0915b905
Severity: Undetermined -- more information needed to determine severity. An HSV210 controller has failed.
Event Code: 09160005
Severity: Normal -- informational in nature. The temperature within an HSV210 controller has returned to its normal operating range.
Event Code: 09172805
Severity: Critical -- failure or failure imminent. An HSV210 controller's battery assembly "1" has been removed.
Event Code: 09180005
Severity: Normal -- informational in nature. An HSV210 controller's battery assembly "1" is now in use.
Event Code: 09190005
Severity: Normal -- informational in nature. A voltage sensor has returned to a normal range.
Event Code: 091a2005
Severity: Critical -- failure or failure imminent. The battery assembly voltage regulator located within an HSV210 controller is offline.
Event Code: 091b0005
Severity: Normal -- informational in nature. A Disk Group has transitioned to the NORMAL state.
Event Code: 091c0005
Severity: Normal -- informational in nature. The occupancy alarm level for a Disk Group has returned to the normal range.
Event Code: 091d2205
Severity: Critical -- failure or failure imminent. An HSV210 controller's battery assembly "1" has malfunctioned.
Event Code: 091e0005
Severity: Normal -- informational in nature. An HSV210 controller's battery assembly "1" is now present.
Event Code: 091f2905
Severity: Critical -- failure or failure imminent. An HSV210 controller's battery assembly "2" has been removed.
Event Code: 09200005
Severity: Normal -- informational in nature. An HSV210 controller's battery assembly "2" is now present.
Event Code: 09210005
Severity: Normal -- informational in nature. An HSV210 controller's battery assembly "2" is now functioning properly.
Event Code: 09222305
Severity: Critical -- failure or failure imminent. An HSV210 controller's battery assembly has malfunctioned.
Event Code: 09232b05
Severity: Critical -- failure or failure imminent. An HSV210 controller's blower "2" has been removed.
Event Code: 09240005
Severity: Normal -- informational in nature. An HSV210 controller's blower assembly "2" is now present.
Event Code: 09252505
Severity: Critical -- failure or failure imminent. An HSV210 controller's blower assembly "2" is running slower than the lowest acceptable speed.
Event Code: 09262c05
Severity: Critical -- failure or failure imminent. An HSV210 controller's "1" blower/power supply assembly has been removed or AC power has been removed from the power supply.
Event Code: 09270005
Severity: Normal -- informational in nature. An HSV210 controller's "1" blower/power supply assembly has been reinstalled or AC power has been restored to the power supply.
Event Code: 09282d05
Severity: Critical -- failure or failure imminent. An HSV210 controller's "2" blower/power supply assembly has been removed or AC power has been removed from the power supply.
Event Code: 09290005
Severity: Normal -- informational in nature. An HSV210 controller's "2" blower/power supply assembly has been reinstalled or AC power has been restored to the power supply.
Event Code: 092a2605
Severity: Critical -- failure or failure imminent. An HSV210 controller's "1" blower/power supply is running slower than the lowest acceptable speed.
Event Code: 092b2705
Severity: Critical -- failure or failure imminent. An HSV210 controller's "2" blower/power supply is running slower than the lowest acceptable speed.
Event Code: 092c2f05
Severity: Warning -- not failed but attention recommended or required. An HSV210 controller's battery assembly has transitioned to the "Battery System Hold-up Time is zero hours" state.
Event Code: 092dbf05
Severity: Undetermined -- more information needed to determine severity. The resource availability state of a Volume has transitioned to the INSUFFICIENT state.
Event Code: 092e0005
Severity: Normal -- informational in nature. An HSV210 controller has rejected a login attempt.
Event Code: 092f0005
Severity: Normal -- informational in nature. An HSV210 controller has processed a Storage System Management Interface command with the result of non-success return code.
Event Code: 09300005
Severity: Normal -- informational in nature. An HSV210 controller has updated the physical disk drive map for a loop pair.
Event Code: 09314205
Severity: Critical -- failure or failure imminent. A physical disk drive has transitioned to the DEGRADED state.
Event Code: 09324005
Severity: Critical -- failure or failure imminent. A physical disk drive has transitioned to the FAILED state.
Event Code: 0933000e
Severity: Normal -- informational in nature. A Derived Unit was created.
Event Code: 0934000e
Severity: Normal -- informational in nature. A Logical Disk was created.
Event Code: 0935000e
Severity: Normal -- informational in nature. A Disk Group was created.
Event Code: 0936000e
Severity: Normal -- informational in nature. A physical disk drive was discovered.
Event Code: 0937000e
Severity: Normal -- informational in nature. A Presented Unit was created.
Event Code: 0938000e
Severity: Normal -- informational in nature. A Storage System Host Path was created.
Event Code: 0939000e
Severity: Normal -- informational in nature. A Storage System Virtual Disk was created.
Event Code: 093a000e
Severity: Normal -- informational in nature. A Volume was created.
Event Code: 093b000e
Severity: Normal -- informational in nature. A Derived Unit was deleted.
Event Code: 093c000e
Severity: Normal -- informational in nature. A Logical Disk was deleted.
Event Code: 093d000e
Severity: Normal -- informational in nature. A Disk Group was deleted.
Event Code: 093e420e
Severity: Critical -- failure or failure imminent. A physical disk drive has disappeared.
Event Code: 093f000e
Severity: Normal -- informational in nature. A Presented Unit was deleted.
Event Code: 0940000e
Severity: Normal -- informational in nature. A Storage System Host Path was deleted.
Event Code: 0941000e
Severity: Normal -- informational in nature. A Storage System Virtual Disk was deleted.
Event Code: 0943000e
Severity: Normal -- informational in nature. An HSV210 controller has joined the Storage System.
Event Code: 0944ba0e
Severity: Undetermined -- more information needed to determine severity. An HSV210 controller has left the Storage System.
Event Code: 0945000e
Severity: Normal -- informational in nature. The Storage System has been deleted by an HSV210 controller.
Event Code: 0946000e
Severity: Normal -- informational in nature. A Data Replication Group was created.
Event Code: 0947000e
Severity: Normal -- informational in nature. A Data Replication Group was deleted.
Event Code: 0948000e
Severity: Normal -- informational in nature. An internal Logical Disk associated with a snapshot Virtual Disk was created.
Event Code: 0949000e
Severity: Normal -- informational in nature. An internal Logical Disk associated with a copy of a Virtual Disk was created.
Event Code: 094a000e
Severity: Normal -- informational in nature. Destination Data Replication Group not deleted due to inoperative members.
Event Code: 094b000e
Severity: Normal -- informational in nature. A Volume was removed from a LDAD.
Event Code: 094c000e
Severity: Normal -- informational in nature. A new Remote Node has been discovered.
Event Code: 094d000e
Severity: Normal -- informational in nature. The Remote Node object has been discarded.
Event Code: 094e000e
Severity: Normal -- informational in nature. The Remote Node Storage System UUID has changed.
Event Code: 0965000f
Severity: Normal -- informational in nature. A host operating system mode has changed.
Event Code: 0966000f
Severity: Normal -- informational in nature. Time was set on a Storage System.
Event Code: 0967000f
Severity: Normal -- informational in nature. The LUN of a Presented Unit has changed.
Event Code: 0968000f
Severity: Normal -- informational in nature. The device addition policy of a Storage System has changed.
Event Code: 0969000f
Severity: Normal -- informational in nature. The quiescent state of a Storage System Virtual Disk has changed.
Event Code: 096a000f
Severity: Normal -- informational in nature. The enabled/disabled state of a Storage System Virtual Disk has changed.
Event Code: 096b000f
Severity: Normal -- informational in nature. The cache policy of a Storage System Virtual Disk has changed.
Event Code: 096c000f
Severity: Normal -- informational in nature. The usage state of a Volume changed.
Event Code: 096d000f
Severity: Normal -- informational in nature. The disk failure protection level of a Disk Group has changed.
Event Code: 096e000f
Severity: Normal -- informational in nature. The write protected state of a Derived Unit has changed.
Event Code: 0970460f
Severity: Warning -- not failed but attention recommended or required. A physical disk drive has experienced numerous communication failures on a particular Fibre Channel port.
Event Code: 0971000f
Severity: Normal -- informational in nature. An HSV210 controller has received a request to shutdown.
Event Code: 0972000f
Severity: Normal -- informational in nature. An HSV210 controller has completed its shutdown preparations.
Event Code: 0973000f
Severity: Normal -- informational in nature. The failsafe state of a Data Replication Group has changed.
Event Code: 0974000f
Severity: Normal -- informational in nature. The mode of a Data Replication Group has changed.
Event Code: 0975000f
Severity: Normal -- informational in nature. The synchronous/asynchronous operational state of a Data Replication Group has changed.
Event Code: 0976000f
Severity: Normal -- informational in nature. The read only attribute of a Data Replication Group has changed.
Event Code: 0977000f
Severity: Normal -- informational in nature. A Data Replication Group failover has occurred.
Event Code: 0978000f
Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed.
Event Code: 0979000f
Severity: Normal -- informational in nature. A Storage System Virtual Disk was added to a Data Replication Group.
Event Code: 097a000f
Severity: Normal -- informational in nature. A Storage System Virtual Disk was removed from a Data Replication Group.
Event Code: 097b000f
Severity: Normal -- informational in nature. The auto suspend attribute of a Data Replication Group has changed.
Event Code: 097c000f
Severity: Normal -- informational in nature. The destination presentation attribute of a Data Replication Group has changed.
Event Code: 097d000f
Severity: Normal -- informational in nature. The flags of a physical disk drive have changed because of a maintenance mode change.
Event Code: 097e000f
Severity: Normal -- informational in nature. The defer_copy attribute of a Data Replication Group has changed.
Event Code: 097f000f
Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed.
Event Code: 0980000f
Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed.
Event Code: 0981000f
Severity: Normal -- informational in nature. A Data Replication Group has been suspended or resumed.
Event Code: 09c85105
Severity: Undetermined -- more information needed to determine severity. An internal Logical Disk has transitioned to the DATA LOST state.
Event Code: 09c95105
Severity: Undetermined -- more information needed to determine severity. A Disk Group has transitioned to an INOPERATIVE state.
Event Code: 09ca5105
Severity: Undetermined -- more information needed to determine severity. An internal Logical Disk has transitioned to the FAILED state.
Event Code: 09cb5005
Severity: Critical -- failure or failure imminent. An internal Logical Disk has transitioned to the SNAPSHOT OVERCOMMIT state.
Event Code: 09cc5105
Severity: Undetermined -- more information needed to determine severity. An internal Logical Disk has transitioned to the DEVICE DATA LOST state.
Event Code: 09cdc305
Severity: Undetermined -- more information needed to determine severity. A Fibre Channel port has transitioned to the FAILED state.
Event Code: 09ce0005
Severity: Normal -- informational in nature. A Disk Group has transitioned to an INOPERATIVE MARKED state.
Event Code: 09cf4105
Severity: Warning -- not failed but attention recommended or required. A physical disk drive has transitioned to the NOT PRESENT state.
Event Code: 09d00005
Severity: Normal -- informational in nature. An HSV210 controller no longer needs attention.
Event Code: 09d1b905
Severity: Undetermined -- more information needed to determine severity. An HSV210 controller needs attention.
Event Code: 09d22a05
Severity: Critical -- failure or failure imminent. An HSV210 controller's blower "1" has been removed.
Event Code: 09d35105
Severity: Undetermined -- more information needed to determine severity. At least one Virtual Disk associated with a Data Replication Group has transitioned to the INOPERATIVE state. The remaining Virtual Disks associated with this Data Replication Group have been forced INOPERATIVE.
Event Code: 09d40005
Severity: Normal -- informational in nature. All the Virtual Disks associated with a Data Replication Group have transitioned to the OPERATIVE state.
Event Code: 09d50005
Severity: Normal -- informational in nature. The state of a physical disk drive has transitioned to the Single Port on Fibre state.
Event Code: 09d63705
Severity: Warning -- not failed but attention recommended or required. An HSV210 controller has been powered off because the temperature sensors do not agree and the system temperature can not be accurately determined.
Event Code: 09d73705
Severity: Warning -- not failed but attention recommended or required. An HSV210 controller has been powered off because the temperature sensors can not be accessed and the system temperature can not be accurately determined.
Event Code: 09d8b605
Severity: Undetermined -- more information needed to determine severity. A Redundant Storage Set has two members on the same Fibre Channel device enclosure causing a Disk Group to lose its Single Point of Failure Robust Configuration.
Event Code: 09d90005
Severity: Normal -- informational in nature. A Disk Group has attained a Single Point of Failure Robust Configuration.
Event Code: 09da0005
Severity: Normal -- informational in nature. An HSV210 controller's blower "1" is running at normal speed.
Event Code: 09db0005
Severity: Normal -- informational in nature. An HSV210 controller's blower "2" is running at normal speed.
Event Code: 09dc0b05
Severity: Warning -- not failed but attention recommended or required. An HSV210 controller's glue eeprom has been programmed. A controller reset is going to be initiated to finish the glue part programming. This will take longer than the resync that normally occurs after a codeload.
Event Code: 09dd0005
Severity: Normal -- informational in nature. An HSV210 controller receives a maintenance invoke call from the user
Event Code: 09de5205
Severity: Critical -- failure or failure imminent. An internal Logical Disk has transitioned to the INVALIDATED state.
Event Code: 0b000010
Severity: Normal -- informational in nature. An HSV210 controller has begun a resynchronization operation. This is a restart of the HSV210 controller in a manner that has little or no impact on host system connectivity.
Event Code: 0b01b515
Severity: Warning -- not failed but attention recommended or required. A migrate method drive codeload has stalled due to insufficient space in the Disk Group.
Event Code: 0b020004
Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware version has been loaded into memory in preparation for codeload.
Event Code: 0b040004
Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload begun.
Event Code: 0b050004
Severity: Normal -- informational in nature. A Fibre Channel physical disk drive firmware codeload has finished.
Event Code: 0b06001a
Severity: Normal -- informational in nature. An HSV210 controller has begun/finished a code load, code use, or code burn operation as indicated, in a manner that has little or no impact on host system connectivity.
Event Code: 0b070b1a
Severity: Warning -- not failed but attention recommended or required. An HSV210 controller has finished a code load to the GLUE eeprom.
Event Code: 0b09001e
Severity: Normal -- informational in nature. Process with work, eg. during CSM Hang and Unit Stalled Too Long.
Event Code: 0c03000c
Severity: Normal -- informational in nature. The specified Data Replication Group has transitioned to the Merging state, because the Data Replication Destination Storage System is now accessible or resumed.
Event Code: 0c045f0c
Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state because the Data Replication Destination Storage System is inaccessible.
Event Code: 0c05610c
Severity: Critical -- failure or failure imminent. A Data Replication Group has entered the Failsafe Locked state due to an inaccessible Destination Virtual Disk.
Event Code: 0c06600c
Severity: Critical -- failure or failure imminent. A Full Copy was terminated prior to completion: An unrecoverable read error occurred on the specified Source Virtual Disk during the Full Copy.
Event Code: 0c075f0c
Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible alternate Storage System; The Full Copy will continue when the Data Replication Destination is restored.
Event Code: 0c08610c
Severity: Critical -- failure or failure imminent. A Full Copy terminated prior to completion: A remote copy error occurred due to an inaccessible Destination Virtual Disk; The Full Copy will continue when the Destination Virtual Disk is restored.
Event Code: 0c09620c
Severity: Warning -- not failed but attention recommended or required. A Data Replication Log has been reset due to insufficient Disk Group capacity; The Data Replication Destination has been marked for a Full Copy.
Event Code: 0c0a000c
Severity: Normal -- informational in nature. A Data Replication Log has been reset due to a Data Replication Group failover.
Event Code: 0c0c000c
Severity: Normal -- informational in nature. A Destination Data Replication Group has successfully completed a Merge.
Event Code: 0c0f000c
Severity: Normal -- informational in nature. A Data Replication Group is no longer in a Failsafe Locked state.
Event Code: 0c10000c
Severity: Normal -- informational in nature. A Destination Data Replication Group has been marked for a Full Copy.
Event Code: 0c11000c
Severity: Normal -- informational in nature. This Data Replication Group is transitioning from a Data Replication Source role to a Data Replication Destination role.
Event Code: 0c12000c
Severity: Normal -- informational in nature. This Data Replication Group is transitioning from a Data Replication Destination role to a Data Replication Source role.
Event Code: 0c160016
Severity: Normal -- informational in nature. An HSV210 controller has sent a time report message to this HSV210 controller.
Event Code: 0c17630c
Severity: Critical -- failure or failure imminent. The Data Replication Manager communications protocol version between the Data Replication Source Storage System and a Data Replication Destination Storage System is mismatched.
Event Code: 0c18640c
Severity: Critical -- failure or failure imminent. Conditions on the Data Replication Destination Storage System are preventing acceptable replication throughput: Initiating temporary logging on the affected Data Replication Group that is failsafe mode disabled.
Event Code: 0c19020c
Severity: Critical -- failure or failure imminent. Overlapping concurrent host writes to an Active/Active Peer Storage System violate a Data Replication Manager architectural requirement, resulting in a reparative resynchronization operation for the master Storage System and a Full Copy operation.
Event Code: 0c1a000c
Severity: Normal -- informational in nature. The specified Destination Virtual Disk has successfully completed a Full Copy.
Event Code: 0c1b5f0c
Severity: Critical -- failure or failure imminent. A Data Replication Group has transitioned to the Logging state because the alternate Storage System is not accessible.
Event Code: 0c1c610c
Severity: Critical -- failure or failure imminent. The specified Source Data Replication Group has transitioned to the (not merging) Logging state because a Destination Virtual Disk is not accessible.
Event Code: 0c1d000c
Severity: Normal -- informational in nature. Inconsistency was found in the group log: A Full Copy of the affected Data Replication Group will be initiated.
Event Code: 0c1e5f0c
Severity: Critical -- failure or failure imminent. The members of the specified Source Data Replication Group have not been presented to the host because the remote Storage System is not accessible: Suspend Source Data Replication Group to override this behavior, which will present the members.
Event Code: 0c1f000c
Severity: Normal -- informational in nature. The members of the specified Source Data Replication Group have been presented to the host because the remote Storage System is now accessible or source group is now suspended.
Event Code: 0c20650c
Severity: Critical -- failure or failure imminent. Conditions on the Data Replication Destination Storage System are preventing replication processing: The specified Source Data Replication Group will remain in the Logging or the Failsafe Locked state until corrective action is performed.
Event Code: 0c21660c
Severity: Critical -- failure or failure imminent. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed.
Event Code: 0c22000c
Severity: Normal -- informational in nature. A Data Replication Path between this Storage System and the Peer Storage System has been opened.
Event Code: 0c23670c
Severity: Warning -- not failed but attention recommended or required. Conditions on the inter site link are preventing acceptable replication throughput: Initiating temporary logging on the affected Data Replication Group that is failsafe mode disabled.
Event Code: 0c24000c
Severity: Normal -- informational in nature. The specified Source Data Replication Group has transitioned to the (not merging) Logging state because a Destination Virtual Disk is momentarily inaccessible.
Event Code: 0c25000c
Severity: Normal -- informational in nature. A Full Copy terminated prior to completion: A remote copy error occurred due to a momentarily inaccessible Destination Virtual Disk; The Full Copy will continue when the Destination Virtual Disk is restored.
Event Code: 0c26000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has been opened due to simultaneous requests from each Storage System
Event Code: 0c27000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has been opened by the Peer Storage System.
Event Code: 0c285f0c
Severity: Critical -- failure or failure imminent. A Data Replication Path to the Peer Storage System is not currently available.
Event Code: 0c29000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed in order to force Data Replication Manager traffic to the controller's Preferred Port.
Event Code: 0c2a000c
Severity: Normal -- informational in nature. A Data Replication Path to a Peer Storage System has been found.
Event Code: 0c2b600c
Severity: Critical -- failure or failure imminent. A Merge was terminated prior to completion: An unrecoverable read error occurred on the log unit of the specified Data Replication Group during the Merge.
Event Code: 0c2c660c
Severity: Critical -- failure or failure imminent. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed.
Event Code: 0c2d000c
Severity: Normal -- informational in nature. The Peer Storage System port name that was incorrectly associated with a host has been deleted from the specified client object.
Event Code: 0c2e680c
Severity: Warning -- not failed but attention recommended or required. Insufficient resources exist to discover additional remote nodes.
Event Code: 0c2f000c
Severity: Normal -- informational in nature. Sufficient resources now exist to allow discovery of additional remote nodes.
Event Code: 0c30000c
Severity: Normal -- informational in nature. A replication operation on the Data Replication Source Storage System or Data Replication Destination Storage System has stalled which will prevent replication processing for the specified Data Replication Group until corrective action is performed.
Event Code: 0c31000c
Severity: Normal -- informational in nature. A stalled Full Copy has been restarted.
Event Code: 0c325f0c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the host port connection has failed.
Event Code: 0c335f0c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the link or the Storage System has become unresponsive.
Event Code: 0c345f0c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, due to slow response on the connection between the specified host port and the Peer Storage System.
Event Code: 0c35070c
Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has closed, because a Data Replication Group configuration change lock was not released in a timely manner.
Event Code: 0c365f0c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, due to thrashing of the connection between the specified host port and the Peer Storage System.
Event Code: 0c375f0c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the maximum ping retry count has been exceeded.
Event Code: 0c38630c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the Data Replication Path protocol version is not supported by the controller firmware.
Event Code: 0c39000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the Data Replication Path is not being used.
Event Code: 0c3a5f0c
Severity: Critical -- failure or failure imminent. A Data Replication Path between this Storage System and the Peer Storage System could not be created, possibly due to a connection failure between the specified host port and the Peer Storage System.
Event Code: 0c3b000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed, because the Peer Storage System requested the creation of a new Data Replication Path.
Event Code: 0c3c000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because the Peer Storage System tried to open a Data Replication Path to a different host port.
Event Code: 0c3d5f0c
Severity: Critical -- failure or failure imminent. The Data Replication Path between this Storage System and the Peer Storage System has closed because of a frame retransmit limit was reached.
Event Code: 0c3e000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System was closed by the Peer Storage System.
Event Code: 0c3f000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because the NPortID of the remote port changed.
Event Code: 0c40690c
Severity: Warning -- not failed but attention recommended or required. The Data Replication Path between this Storage System and the Peer Storage System has closed because an out of order frame sequence number was detected.
Event Code: 0c41000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed to allow creation of a Data Replication Path that requires a lower protocol version.
Event Code: 0c42000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because Peer Storage System no longer exists.
Event Code: 0c43000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has been closed by user request.
Event Code: 0c49000c
Severity: Normal -- informational in nature. The Data Replication Path between this Storage System and the Peer Storage System has closed because the corresponding connection data was deleted. This is typically due to a change in the fabric.
Event Code: 0c4a000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the Storage System is re-starting.
Event Code: 0c4b000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the Storage System is not active.
Event Code: 0c4c000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the firmware has not completed Data Replication Path discovery.
Event Code: 0c4d000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the firmware is performing Data Replication Path discovery on the path.
Event Code: 0c4e000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the remote port is not associated with a Enterprise Virtual Array.
Event Code: 0c4f000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the remote port world wide identifier is associated with a host system.
Event Code: 0c50000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the supplied UUID does not match the UUID for this Storage System.
Event Code: 0c51000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the requested protocol version is not compatible with the existing Data Replication Path.
Event Code: 0c52000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the requested port was disabled by the user.
Event Code: 0c53000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected because the insufficient resources exist to create the Data Replication Path.
Event Code: 0c54000c
Severity: Normal -- informational in nature. A request to create a Data Replication Path was rejected to force the use of a lower protocol version on the Data Replication Path.
Event Code: 0c550016
Severity: Normal -- informational in nature. A time synchronization message has been sent to a Alternate Site.
Event Code: 0c56000c
Severity: Normal -- informational in nature. The DRM Forced Logging Timeout value has been changed.
Event Code: 0c57000c
Severity: Normal -- informational in nature. The DRM Forced Logging Timeout value has been reset to the default value.
Event Code: 0c58690c
Severity: Warning -- not failed but attention recommended or required. Excessive data exchange retry rate on the inter site link is preventing acceptable replication throughput: Reducing data exchange resources.
Event Code: 0c59690c
Severity: Warning -- not failed but attention recommended or required. Excessive out of order message rate on the inter site link is impacting replication throughput.
Event Code: 0c5a670c
Severity: Warning -- not failed but attention recommended or required. Excessive PING response time on the inter site link is preventing acceptable replication throughput: Reducing data exchange resources.
Event Code: 0c5b670c
Severity: Warning -- not failed but attention recommended or required. Replication data exchange write resources on the inter site link have been reduced to the minimum allowed value.
Event Code: 0c5c670c
Severity: Warning -- not failed but attention recommended or required. Replication data exchange copy resources on the inter site link have been reduced to the minimum allowed value.
Event Code: 0c5d000c
Severity: Normal -- informational in nature. Quality of service on the inter site link has improved: Increasing data exchange resources to improve replication throughput.
Event Code: 0c5e000c
Severity: Normal -- informational in nature. A Replication Write History Log Shrink is in progress.
Event Code: 0c5f000c
Severity: Normal -- informational in nature. A Replication Write History Log Shrink has completed.
Event Code: 0c60000c
Severity: Normal -- informational in nature. Excessive Vdisk response time at the Data Replication Destination has been detected: Reducing data exchange copy resources on the inter site link to limit replication throughput.
Event Code: 0d000111
Severity: Critical -- failure or failure imminent. An unrecognized event was reported by a Drive Enclosure Environmental Monitoring Unit.
Event Code: 0d014011
Severity: Critical -- failure or failure imminent. A physical disk drive was detected that is not Fibre Channel compatible or cannot operate at the link rate established by the drive enclosure I/O modules.
Event Code: 0d024111
Severity: Warning -- not failed but attention recommended or required. A physical disk drive is improperly installed or missing. This could affect the drive enclosure air flow and cause an over temperature condition.
Event Code: 0d034111
Severity: Warning -- not failed but attention recommended or required. A physical disk drive was removed while software-activated drive locking was enabled on a drive enclosure that does not support drive locking.
Event Code: 0d044211
Severity: Critical -- failure or failure imminent. A physical disk drive that is capable of operating at the loop link rate established by the drive enclosure I/O module was found to be running at a different rate.
Event Code: 0d330911
Severity: Warning -- not failed but attention recommended or required. The AC input to a drive enclosure power supply has been lost. Note that the remaining power supply has become a single point of failure.
Event Code: 0d348011
Severity: Critical -- failure or failure imminent. A drive enclosure power supply is improperly installed or missing. This could affect the drive enclosure air flow and cause an over temperature condition. The operational power supply will automatically shut down after a short period of time, thereby disabling the drive enclosure. This condition remains active until either the problem is corrected, or the operational power supply shuts down, whichever occurs first.
Event Code: 0d359a11
Severity: Critical -- failure or failure imminent. A drive enclosure power supply component has failed.
Event Code: 0d478311
Severity: Critical -- failure or failure imminent. A drive enclosure blower is not operating properly. This could affect the drive enclosure air flow and cause an over temperature condition. A single blower operating at high speed can provide sufficient air flow to cool an enclosure and the elements for up to 100 hours. However, operating an enclosure at temperatures approaching an overheating threshold can damage elements and may reduce the mean time before failure of a specific element.
Event Code: 0d4b8211
Severity: Critical -- failure or failure imminent. A drive enclosure blower is improperly installed or missing. This affects the drive enclosure air flow and can cause an over temperature condition.
Event Code: 0d4c8411
Severity: Critical -- failure or failure imminent. Both drive enclosure blowers are missing. This severely affects the drive enclosure air flow and can cause an over temperature condition. The operational power supply(s) will automatically shut down after a short period of time, thereby disabling the drive enclosure. This condition remains active until either the problem is corrected, or the operational power supply(s) shut down, whichever occurs first.
Event Code: 0d5b8611
Severity: Warning -- not failed but attention recommended or required. A drive enclosure temperature sensor out of range condition has been reported by one of the drive enclosure elements.
Event Code: 0d5f8711
Severity: Critical -- failure or failure imminent. The average temperature of two of the three temperature sensor groups (i.e., Drive Enclosure Environmental Monitoring Unit, Disk Drives, and Power Supplies) exceeds the CRITICAL level. The operational power supply(s) will automatically shut down after a short period of time, thereby disabling the drive enclosure. This condition remains active until either the problem is corrected, or the operational power supply(s) shut down, whichever occurs first. Refer to the HSV element manager GUI for the temperature threshold values.
Event Code: 0d6f8811
Severity: Warning -- not failed but attention recommended or required. An internal Drive Enclosure Environmental Monitoring Unit error has occurred.
Event Code: 0d710011
Severity: Normal -- informational in nature. An internal Drive Enclosure Environmental Monitoring Unit error has occurred.
Event Code: 0d728a11
Severity: Warning -- not failed but attention recommended or required. A Drive Enclosure Environmental Monitoring Unit is unable to collect data for the SCSI-3 Enclosure Services (SES) page.
Event Code: 0d7e8c11
Severity: Warning -- not failed but attention recommended or required. Invalid data was read from a Drive Enclosure Environmental Monitoring Unit NVRAM.
Event Code: 0d7f8b11
Severity: Warning -- not failed but attention recommended or required. An internal Drive Enclosure Environmental Monitoring Unit error has occurred.
Event Code: 0d828e11
Severity: Warning -- not failed but attention recommended or required. A drive enclosure's address is incorrect or the enclosure has no address.
Event Code: 0d838911
Severity: Critical -- failure or failure imminent. A Drive Enclosure Environmental Monitoring Unit has experienced a hardware failure.
Event Code: 0d858f11
Severity: Warning -- not failed but attention recommended or required. A drive enclosure power supply failed to respond to a shut down command.
Event Code: 0d8d9011
Severity: Critical -- failure or failure imminent. A drive enclosure transceiver error has been detected.
Event Code: 0da18111
Severity: Critical -- failure or failure imminent. A drive enclosure power supply voltage sensor out-of-range condition has been reported.
Event Code: 0db58111
Severity: Critical -- failure or failure imminent. A drive enclosure power supply current sensor out of range condition has been reported.
Event Code: 0dd89211
Severity: Warning -- not failed but attention recommended or required. A drive enclosure backplane invalid NVRAM read error has occurred.
Event Code: 0dd99111
Severity: Critical -- failure or failure imminent. A drive enclosure backplane error has occurred.
Event Code: 0ddd9311
Severity: Critical -- failure or failure imminent. A drive enclosure I/O module error has occurred.
Event Code: 0dde9511
Severity: Warning -- not failed but attention recommended or required. A drive enclosure I/O module is unable to communicate with the Drive Enclosure Environmental Monitoring Unit.
Event Code: 0dec9411
Severity: Warning -- not failed but attention recommended or required. A drive enclosure I/O module invalid NVRAM read error has occurred.
Event Code: 0df00011
Severity: Normal -- informational in nature. The status has changed on one or more of the drive enclosures. This informational event is generated for the HSV element manager GUI and contains no user information.
Event Code: 0df68811
Severity: Warning -- not failed but attention recommended or required. An Drive Enclosure Environmental Monitoring Unit has detected missing receive interrupts on its Com Port.
Event Code: 0df70011
Severity: Normal -- informational in nature. An Drive Enclosure Environmental Monitoring Unit has rebooted following the detection of missing receive interrupts on its Com Port.
Event Code: 0df80011
Severity: Normal -- informational in nature. An Drive Enclosure Environmental Monitoring Unit has initialized its Com Port following the detection of an overrun condition.
Event Code: 0e000019
Severity: Normal -- informational in nature. Battery subsystem boot time status.
Event Code: 0e010019
Severity: Normal -- informational in nature. Battery assembly "0" is now present.
Event Code: 0e02cc19
Severity: Critical -- failure or failure imminent. Battery assembly "0" has been removed.
Event Code: 0e030019
Severity: Normal -- informational in nature. The status of battery assembly "0" has changed.
Event Code: 0e04c819
Severity: Critical -- failure or failure imminent. Battery assembly "0" has malfunctioned.
Event Code: 0e050019
Severity: Normal -- informational in nature. Battery assembly "1" is now present.
Event Code: 0e06cd19
Severity: Critical -- failure or failure imminent. Battery assembly "1" has been removed.
Event Code: 0e070019
Severity: Normal -- informational in nature. The status of battery assembly "1" has changed.
Event Code: 0e08c919
Severity: Critical -- failure or failure imminent. Battery assembly "1" has malfunctioned.
Event Code: 0e090019
Severity: Normal -- informational in nature. Battery assembly "2" is now present.
Event Code: 0e0ace19
Severity: Critical -- failure or failure imminent. Battery assembly "2" has been removed.
Event Code: 0e0b0019
Severity: Normal -- informational in nature. The status of battery assembly "2" has changed.
Event Code: 0e0cca19
Severity: Critical -- failure or failure imminent. Battery assembly "2" has malfunctioned.
Event Code: 0e0d0019
Severity: Normal -- informational in nature. Battery assembly "3" is now present.
Event Code: 0e0ecf19
Severity: Critical -- failure or failure imminent. Battery assembly "3" has been removed.
Event Code: 0e0f0019
Severity: Normal -- informational in nature. The status of battery assembly "3" has changed.
Event Code: 0e10cb19
Severity: Critical -- failure or failure imminent. Battery assembly "3" has malfunctioned.
Event Code: 0e110019
Severity: Normal -- informational in nature. The battery subsystem has transitioned to the good state.
Event Code: 0e120019
Severity: Normal -- informational in nature. The battery subsystem has transitioned to the low state.
Event Code: 0e13d019
Severity: Warning -- not failed but attention recommended or required. The battery subsystem has transitioned to the bad state.
Event Code: 0e140019
Severity: Normal -- informational in nature. Blower subsystem boot time status.
Event Code: 0e150019
Severity: Normal -- informational in nature. Blower assembly "0" is now present.
Event Code: 0e16d419
Severity: Critical -- failure or failure imminent. Blower assembly "0" has been removed.
Event Code: 0e170019
Severity: Normal -- informational in nature. The status of blower assembly "0" has changed.
Event Code: 0e18d219
Severity: Critical -- failure or failure imminent. Blower assembly "0" has malfunctioned.
Event Code: 0e190019
Severity: Normal -- informational in nature. Blower assembly "1" is now present.
Event Code: 0e1ad519
Severity: Critical -- failure or failure imminent. Blower assembly "1" has been removed.
Event Code: 0e1b0019
Severity: Normal -- informational in nature. The status of blower assembly "1" has changed.
Event Code: 0e1cd319
Severity: Critical -- failure or failure imminent. Blower assembly "1" has malfunctioned.
Event Code: 0e1dda19
Severity: Warning -- not failed but attention recommended or required. Battery read memory failure has occurred.
Event Code: 0e1e0019
Severity: Normal -- informational in nature. Temperature subsystem boot time status.
Event Code: 0e1f0019
Severity: Normal -- informational in nature. The temperature within an HSV210 controller has returned to its normal operating range.
Event Code: 0e202e19
Severity: Warning -- not failed but attention recommended or required. The temperature within an HSV210 controller is approaching its trip point.
Event Code: 0e213619
Severity: Critical -- failure or failure imminent. The temperature trip point for a temperature sensor located within an HSV210 controller has been reached.
Event Code: 0e220019
Severity: Normal -- informational in nature. Power Supply subsystem boot time status.
Event Code: 0e230019
Severity: Normal -- informational in nature. Power Supply assembly "0" is now present.
Event Code: 0e24d819
Severity: Critical -- failure or failure imminent. Power Supply assembly "0" has been removed.
Event Code: 0e250019
Severity: Normal -- informational in nature. The status of power supply assembly "0" has changed.
Event Code: 0e26d619
Severity: Critical -- failure or failure imminent. Power supply assembly "0" lost AC connection or has malfunctioned.
Event Code: 0e270019
Severity: Normal -- informational in nature. Power Supply assembly "1" is now present.
Event Code: 0e28d919
Severity: Critical -- failure or failure imminent. Power Supply assembly "1" has been removed.
Event Code: 0e290019
Severity: Normal -- informational in nature. The status of power supply assembly "1" has changed.
Event Code: 0e2ad719
Severity: Critical -- failure or failure imminent. Power supply assembly "1" lost AC connection or has malfunctioned.
Event Code: 42000008
Severity: Normal -- informational in nature. A host Fibre Channel port transitioned to the link down state.
Event Code: 42010008
Severity: Normal -- informational in nature. A host Fibre Channel port transitioned to the link failed state.
Event Code: 42030007
Severity: Normal -- informational in nature. An excessive number of link errors were detected on a host Fibre Channel port.
Event Code: 42044a08
Severity: Warning -- not failed but attention recommended or required. A host Fibre Channel port has failed to respond.
Event Code: 42050008
Severity: Normal -- informational in nature. A host Fibre Channel port has transitioned to a deadlocked state.
Event Code: 4206001b
Severity: Normal -- informational in nature. Indicated Virtual Disk has transitioned to Stalled Too Long.
Event Code: 4207001b
Severity: Normal -- informational in nature. Indicated Virtual Disk has transitioned to ownership by the other HSV210 controller.
Event Code: 42080008
Severity: Normal -- informational in nature. A host Fibre Channel port has been reissued a freeze command.
Event Code: 42090008
Severity: Normal -- informational in nature. A host Fibre Channel port has been issued a soft reset.
Event Code: 420a001b
Severity: Normal -- informational in nature. Indicated Virtual Disk that previously entered into Stalled Too Long has now been unstalled and resumed.
Event Code: 83002014
Severity: Critical -- failure or failure imminent. A failure was detected during the execution of this HSV210 controller's on-board diagnostics.
Event Code: 83013014
Severity: Warning -- not failed but attention recommended or required. A GBIC SFF Serial ID Data check code failure was detected during the execution of this HSV210 controller's on-board diagnostics.
Event Code: 83073a14
Severity: Warning -- not failed but attention recommended or required. A GBIC SFF was determined to be not present during the execution of this HSV210 controller's on-board diagnostics.
Event Code: 83083b14
Severity: Warning -- not failed but attention recommended or required. A failure was detected during testing of this HSV210 controller's SRAM.
Event Code: 83093b14
Severity: Warning -- not failed but attention recommended or required. A parity error was detected during testing of this HSV210 controller's SRAM.
Event Code: 830a3b14
Severity: Warning -- not failed but attention recommended or required. Force parity generation failed during test of this HSV210 controller's SRAM.
TERMINATION CODES:
Termination Code: 0101011f
Severity: Critical -- failure or failure imminent. Unknown fault type reported by EXEC.
Termination Code: 0102011f
Severity: Critical -- failure or failure imminent. DLQ entry not properly linked.
Termination Code: 0103011f
Severity: Critical -- failure or failure imminent. Timer not expired as expected.
Termination Code: 0104011f
Severity: Critical -- failure or failure imminent. Structure not a timer as expected.
Termination Code: 0105011f
Severity: Critical -- failure or failure imminent. DLQ entry doubly linked.
Termination Code: 0106011f
Severity: Critical -- failure or failure imminent. DLQ head not properly linked.
Termination Code: 0107011f
Severity: Critical -- failure or failure imminent. SQ entry doubly linked.
Termination Code: 0108011f
Severity: Critical -- failure or failure imminent. Structure not a BQUE as expected.
Termination Code: 0109011f
Severity: Critical -- failure or failure imminent. Structure not a SEM as expected.
Termination Code: 010a011f
Severity: Critical -- failure or failure imminent. Function not yet implemented.
Termination Code: 010b011f
Severity: Critical -- failure or failure imminent. ILF invocation not from SC.
Termination Code: 010c011f
Severity: Critical -- failure or failure imminent. Too many performance log instances.
Termination Code: 010d011f
Severity: Critical -- failure or failure imminent. Undefined performance log call.
Termination Code: 010e011f
Severity: Critical -- failure or failure imminent. Structure not AQUE as expected.
Termination Code: 010f011f
Severity: Critical -- failure or failure imminent. Waiter queue not empty as expected.
Termination Code: 0110011f
Severity: Critical -- failure or failure imminent. Structure not GATE as expected.
Termination Code: 0111011f
Severity: Critical -- failure or failure imminent. Receiver queue not empty as expected.
Termination Code: 0112011f
Severity: Critical -- failure or failure imminent. BQUE has unexpected items.
Termination Code: 0113011f
Severity: Critical -- failure or failure imminent. Structure not ASEM as expected.
Termination Code: 0114011f
Severity: Critical -- failure or failure imminent. Unknown system trap routine.
Termination Code: 0115011f
Severity: Critical -- failure or failure imminent. Active DMA list is empty.
Termination Code: 0116011f
Severity: Critical -- failure or failure imminent. CDB address not as expected.
Termination Code: 0117011f
Severity: Critical -- failure or failure imminent. Attempt to allocate a buffer that is already in use.
Termination Code: 0118011f
Severity: Critical -- failure or failure imminent. Attempt to free a buffer that is already free.
Termination Code: 0119011f
Severity: Critical -- failure or failure imminent. Interrupts unexpectedly disabled.
Termination Code: 011a011f
Severity: Critical -- failure or failure imminent. Page zero corrupted.
Termination Code: 011b011f
Severity: Critical -- failure or failure imminent. DCBZ not cache line aligned.
Termination Code: 011c0140
Severity: Critical -- failure or failure imminent. Console requested crash with dump (not coupled).
Termination Code: 011d01c0
Severity: Critical -- failure or failure imminent. Console requested crash with dump (coupled).
Termination Code: 011e0120
Severity: Critical -- failure or failure imminent. Console requested restart without dump (not coupled).
Termination Code: 011f01a0
Severity: Critical -- failure or failure imminent. Console requested restart without dump (coupled).
Termination Code: 01220105
Severity: Critical -- failure or failure imminent. Unknown SMI interrupt occurred.
Termination Code: 01400100
Severity: Critical -- failure or failure imminent. Expiration queue not BQUE.
Termination Code: 015a0100
Severity: Critical -- failure or failure imminent. exc_do_preempt_high called with empty subprocess queue
Termination Code: 02000100
Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory.
Termination Code: 02010100
Severity: Critical -- failure or failure imminent. CACHE$GET_DATA called with bad get data.
Termination Code: 02020100
Severity: Critical -- failure or failure imminent. Cannot allocate BQ.
Termination Code: 02030100
Severity: Critical -- failure or failure imminent. Duplicate dirty data found in Buffer Metadata Array.
Termination Code: 02040100
Severity: Critical -- failure or failure imminent. Invalid Primary Mirror Operation state.
Termination Code: 02050100
Severity: Critical -- failure or failure imminent. Invalid Unit Cache state.
Termination Code: 02070100
Severity: Critical -- failure or failure imminent. Mirror data structure inconsistency.
Termination Code: 02080100
Severity: Critical -- failure or failure imminent. Mirror UUID Changed.
Termination Code: 02090100
Severity: Critical -- failure or failure imminent. Invalid call to CACHE$LOCK_META.
Termination Code: 020a0100
Severity: Critical -- failure or failure imminent. Cannot align parity and user data.
Termination Code: 020b0100
Severity: Critical -- failure or failure imminent. Invalid Pullover Memory Operation state.
Termination Code: 020c0100
Severity: Critical -- failure or failure imminent. Invalid Group Cache Operation state.
Termination Code: 020d0100
Severity: Critical -- failure or failure imminent. Process NV Data NCA corrupted.
Termination Code: 020e0100
Severity: Critical -- failure or failure imminent. Process NV Data Freeing Diag Buffer.
Termination Code: 020f0100
Severity: Critical -- failure or failure imminent. Improper MWB Recovery data sent.
Termination Code: 02100100
Severity: Critical -- failure or failure imminent. Mnode & MFC NCAE Difference.
Termination Code: 02110100
Severity: Critical -- failure or failure imminent. Improper MWBF Recovery data sent.
Termination Code: 02120100
Severity: Critical -- failure or failure imminent. WRITE HOLE COLLISION IN RS_CRITICAL.c
Termination Code: 02150100
Severity: Critical -- failure or failure imminent. Unable to obtain free cache nodes.
Termination Code: 02160100
Severity: Critical -- failure or failure imminent. Unable to obtain free volatile cache buffers.
Termination Code: 02180102
Severity: Critical -- failure or failure imminent. Invalid Proxy Write Mirror Operation state.
Termination Code: 02190102
Severity: Critical -- failure or failure imminent. Invalid Proxy Read Mirror Operation state.
Termination Code: 021a0102
Severity: Critical -- failure or failure imminent. Invalid Proxy Verify Mirror Operation state.
Termination Code: 021b0100
Severity: Critical -- failure or failure imminent. Not enough XDs for RSTORE flush
Termination Code: 021c0102
Severity: Critical -- failure or failure imminent. Invalid Flush Node Detected
Termination Code: 03010104
Severity: Critical -- failure or failure imminent. Logic inconsistency detected; one HSV210 controller is suspect.
Termination Code: 03020184
Severity: Critical -- failure or failure imminent. Logic inconsistency detected; both HSV210 controllers are suspect.
Termination Code: 03030102
Severity: Critical -- failure or failure imminent. Invalid value in switch statement.
Termination Code: 03040102
Severity: Critical -- failure or failure imminent. The minimum number of quorum disks is no longer accessible. Backend hardware failure, backend configuration problems, or HSV210 controller hardware failure are all possible causes.
Termination Code: 03060184
Severity: Critical -- failure or failure imminent. An error for which no recovery is possible occurred.
Termination Code: 030a0102
Severity: Critical -- failure or failure imminent. Index out of bounds in scsscsdb_get_scsdb_ds call.
Termination Code: 030b0101
Severity: Critical -- failure or failure imminent. Area offset unknown in scsscsdb_get_scsdb_ds call.
Termination Code: 030c0100
Severity: Critical -- failure or failure imminent. All SCSDB cache pages in use.
Termination Code: 030d0101
Severity: Critical -- failure or failure imminent. scsscsdb_free_scsdb_page cache inconsistency.
Termination Code: 030e0102
Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not.
Termination Code: 030f0101
Severity: Critical -- failure or failure imminent. Call to commit SCSDB while cache page dirty or in use.
Termination Code: 03100102
Severity: Critical -- failure or failure imminent. Index out of bounds in scscvmdb_get_cvmdb_ds call.
Termination Code: 03110101
Severity: Critical -- failure or failure imminent. Area offset unknown in scscvmdb_get_cvmdb_ds call.
Termination Code: 03120100
Severity: Critical -- failure or failure imminent. All CVMDB cache pages in use.
Termination Code: 03130101
Severity: Critical -- failure or failure imminent. scscvmdb_free_cvmdb_page cache inconsistency.
Termination Code: 03140102
Severity: Critical -- failure or failure imminent. Caller believes cache page is dirty and in use, but cache does not.
Termination Code: 03150101
Severity: Critical -- failure or failure imminent. Call to commit CVMDB while cache page dirty or in use.
Termination Code: 03160100
Severity: Critical -- failure or failure imminent. Unable to allocate login maps.
Termination Code: 031f0100
Severity: Critical -- failure or failure imminent. Unable to allocate tdsd pool.
Termination Code: 032a0000
Severity: Normal -- informational in nature. Both HSV210 controllers registered as Storage System Master.
Termination Code: 033c0106
Severity: Critical -- failure or failure imminent. Invalid port login state in remote port object.
Termination Code: 033d0105
Severity: Critical -- failure or failure imminent. Remote port logged_in timer expired in inappropriate login state.
Termination Code: 03500020
Severity: Normal -- informational in nature. Crash forced by maintenance invoke CRASH or SCS_DEBUG command.
Termination Code: 03510141
Severity: Critical -- failure or failure imminent. Crash forced by other HSV210 controller.
<UL>
<LI>TP[0] contains the reason code for the kill.
</UL>
Termination Code: 03520140
Severity: Critical -- failure or failure imminent. This controller killed other controller and CPLD_CRASH_ALWAYS set.
Termination Code: 03640020
Severity: Normal -- informational in nature. This HSV210 controller was requested to terminate operation and then restart.
Termination Code: 03650060
Severity: Normal -- informational in nature. This HSV210 controller was requested to terminate operation and then not restart.
Termination Code: 03660060
Severity: Normal -- informational in nature. This HSV210 controller was requested to terminate operation and then power off.
Termination Code: 03670000
Severity: Normal -- informational in nature. This HSV210 controller was requested to terminate operation, perform a crash dump and then restart.
Termination Code: 03680040
Severity: Normal -- informational in nature. This HSV210 controller was requested to terminate operation, perform a crash dump and then not restart.
Termination Code: 03690080
Severity: Normal -- informational in nature. Both HSV210 controllers were requested to terminate operation, perform a crash dump and then restart.
Termination Code: 036a00c0
Severity: Normal -- informational in nature. Both HSV210 controllers were requested to terminate operation, perform a crash dump and then not restart.
Termination Code: 036b0001
Severity: Normal -- informational in nature. This controller was requested to terminate operation as a result of a unit having cache data that could not fail over.
Termination Code: 036c01c8
Severity: Critical -- failure or failure imminent. This special termination event is for engineering debug purpose.
Termination Code: 03780101
Severity: Critical -- failure or failure imminent. Unable to realize the CVMDB or SCSDB during Storage System Master failover. Backend hardware failure, backend configuration problems, or HSV210 controller hardware failure are all possible causes.
Termination Code: 03790020
Severity: Normal -- informational in nature. This HSV210 controller is restarting in order to use a new version of firmware.
Termination Code: 0400011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap (i.e., SIMM operand of twi instruction not a recognized FM_TRAP_TYPE_xxx variant or tw instruction executed).
Termination Code: 0401011f
Severity: Critical -- failure or failure imminent. Machine Check Interrupt Vector Service Routine (MCIVSR) entered; termination processing interrupted before fm_decode_machine_check could be performed.
Termination Code: 0402011f
Severity: Critical -- failure or failure imminent. DEBUG statement executed.
Termination Code: 0403047f
Severity: Undetermined -- more information needed to determine severity. Termination event is recursive -- i.e., the Termination Event Information contained in multiple recent Termination Events array entries is identical and the terminations occurred within a short interval of time.
Termination Code: 04050101
Severity: Critical -- failure or failure imminent. Out of range event data block index encountered in fm_update_scelaba_entry.
Termination Code: 0406017f
Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad. Either the EDC was not updated due to premature termination of post-termination operations or the memory area was corrupted in an unexplained manner. A power supply internal failure could cause this termination. Note: The in progress event information may not describe the event that caused the HSV210 controller to terminate operation depending on how far termination processing got before the event occurred.
Termination Code: 0407016a
Severity: Critical -- failure or failure imminent. An unexpected event array entry indicated that post-termination operations were terminated prematurely before or during the event report block load.
Termination Code: 04080582
Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV210 controller with the coupled crash flag set.
Termination Code: 040905a2
Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV210 controller with the coupled crash flag set.
Termination Code: 040a05c2
Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV210 controller with the coupled crash flag set.
Termination Code: 040b05e2
Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV210 controller with the coupled crash flag set.
Termination Code: 040c0582
Severity: Undetermined -- more information needed to determine severity. A last gasp message was received from the other HSV210 controller with the coupled crash flag set and an unrecognized Dump/Restart code.
Termination Code: 040d0101
Severity: Critical -- failure or failure imminent. Unrecognized fm_update_scelaba_entry operation code encountered.
Termination Code: 040e0100
Severity: Critical -- failure or failure imminent. This HSV210 controller is not the Storage System Master when conditions dictate that it should be.
Termination Code: 040f0100
Severity: Critical -- failure or failure imminent. This HSV210 controller is the Storage System Master when conditions dictate that it should not be.
Termination Code: 04100182
Severity: Critical -- failure or failure imminent. The Storage System Termination Event Log or Storage System Event Log is not active when conditions dictate that it should be.
Termination Code: 04110181
Severity: Critical -- failure or failure imminent. The Storage System Termination Event Log or Storage System Event Log is inaccessible.
Termination Code: 04120123
Severity: Critical -- failure or failure imminent. An invalid entry or an inconsistency between entries was found in the Last Termination Event array following a controller resynchronization operation; all entries in the array were reset.
Termination Code: 04130107
Severity: Critical -- failure or failure imminent. Structure type is not as expected.
Termination Code: 04140104
Severity: Critical -- failure or failure imminent. Event Information Packet type is out of range.
Termination Code: 04150104
Severity: Critical -- failure or failure imminent. Event Information Packet size is too big.
Termination Code: 04160103
Severity: Critical -- failure or failure imminent. Event Information Packet size is not a longword multiple.
Termination Code: 04170107
Severity: Critical -- failure or failure imminent. Invalid Storage System Termination Event Log or Storage System Event Log I/O request, no data mapped (unallocated) or object is unknown.
Termination Code: 04180107
Severity: Critical -- failure or failure imminent. Unrecognized status returned following a Storage System Termination Event Log or Storage System Event Log I/O request.
Termination Code: 04190100
Severity: Critical -- failure or failure imminent. The restartdebug routine was invoked without a termination having been performed.
Termination Code: 041a0100
Severity: Critical -- failure or failure imminent. The Fault Manager's active queue is unexpectedly empty.
Termination Code: 041b0105
Severity: Critical -- failure or failure imminent. The Fault Manager detected that the correct event data block was not cached.
Termination Code: 041c0100
Severity: Critical -- failure or failure imminent. Calling process is not the Storage System Management Interface or Host Port SCSI as it should be.
Termination Code: 041d0100
Severity: Critical -- failure or failure imminent. Calling process is not the Storage System Management Interface as it should be.
Termination Code: 041e0102
Severity: Critical -- failure or failure imminent. Termination Event Information Store Packet content is not as expected.
Termination Code: 041f0a1f
Severity: Critical -- failure or failure imminent. Either a low memory access violation made by the HSV210 controller's software (e.g., access to memory address zero through an uninitialized pointer, etc.) or an uncorrectable memory error was detected.
Termination Code: 0420011f
Severity: Critical -- failure or failure imminent. The HSV210 controller inactivity watchdog timer expired.
Termination Code: 04210107
Severity: Critical -- failure or failure imminent. Drive Broken status returned following a Storage System Termination Event Log or Storage System Event Log I/O request.
Termination Code: 04220102
Severity: Critical -- failure or failure imminent. The Software Component ID specified in an Event Code is illegal.
Termination Code: 04240960
Severity: Warning -- not failed but attention recommended or required. Power failed.
Termination Code: 043f011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 0, Reserved exception.
Termination Code: 0440011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 100, System Reset exception.
Termination Code: 0441011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 200, Machine Check exception.
Termination Code: 0442011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 300, DSI exception (i.e., a data memory access cannot be performed).
Termination Code: 0443011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 400, ISI exception (i.e., an attempt to fetch the next instruction to be executed failed).
Termination Code: 0444011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 500, External Interrupt exception.
Termination Code: 0445011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 600, Alignment exception (i.e., a memory access cannot be performed because the address alignment or mode is incompatible for the instruction that was about to be executed).
Termination Code: 0446011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 700, Program exception (i.e., execution of an illegal or privileged instruction was attempted).
Termination Code: 0447011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 800, Floating-Point Unavailable exception (i.e., an attempt was made to execute a floating-point instruction and the floating-point available bit in the MSR was cleared).
Termination Code: 0448011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 900, Decrementer exception.
Termination Code: 0449011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector A00, Reserved exception.
Termination Code: 044a011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector B00, Reserved exception.
Termination Code: 044b011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector C00, System Call exception.
Termination Code: 044c011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector D00, Trace exception.
Termination Code: 044d011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector E00, Floating-Point Assist exception.
Termination Code: 044e011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector F00, Reserved exception.
Termination Code: 044f011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1000, Instruction Translation Miss exception.
Termination Code: 0450011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1100, Data Load Translation Miss exception.
Termination Code: 0451011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1200, Data Store Translation Miss exception.
Termination Code: 0452011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1300, Instruction Address Break exception.
Termination Code: 0453011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1400, System Management exception.
Termination Code: 04540101
Severity: Critical -- failure or failure imminent. Event data block count unexpected.
Termination Code: 04550101
Severity: Critical -- failure or failure imminent. FM_locate_event_info received unexpected event retrieval status.
Termination Code: 04560102
Severity: Critical -- failure or failure imminent. FM_activeq_read_event was unable to satisfy an active queue event request due to an internal inconsistency.
Termination Code: 04570105
Severity: Critical -- failure or failure imminent. A direct call to FM_x_terminate_ctl was made. FM_terminate_ctl_user or FM_terminate_ctl_isr must be used instead.
Termination Code: 0458011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1500, Reserved exception.
Termination Code: 0459011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1600, Altivec exception.
Termination Code: 045a011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1700, Reserved exception.
Termination Code: 045b011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1800, Reserved exception.
Termination Code: 045c011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1900, Reserved exception.
Termination Code: 045d011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1A00, Reserved exception.
Termination Code: 045e011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1B00, Reserved exception.
Termination Code: 045f011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1C00, Reserved exception.
Termination Code: 0460011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1D00, Reserved exception.
Termination Code: 0461011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1E00, Reserved exception.
Termination Code: 0462011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 1F00, Reserved exception.
Termination Code: 0463011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2000, Reserved exception.
Termination Code: 0464011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2100, Reserved exception.
Termination Code: 0465011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2200, Reserved exception.
Termination Code: 0466011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2300, Reserved exception.
Termination Code: 0467011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2400, Reserved exception.
Termination Code: 0468011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2500, Reserved exception.
Termination Code: 0469011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2600, Reserved exception.
Termination Code: 046a011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2700, Reserved exception.
Termination Code: 046b011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2800, Reserved exception.
Termination Code: 046c011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2900, Reserved exception.
Termination Code: 046d011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2A00, Reserved exception.
Termination Code: 046e011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2B00, Reserved exception.
Termination Code: 046f011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2C00, Reserved exception.
Termination Code: 0470011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2D00, Reserved exception.
Termination Code: 0471011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2E00, Reserved exception.
Termination Code: 0472011f
Severity: Critical -- failure or failure imminent. Program Interrupt Vector Service Routine (PIVSR) entered with unhandled trap at Exception Vector 2F00, Reserved exception.
Termination Code: 04730167
Severity: Critical -- failure or failure imminent. Error encountered while building ADDRESS_MAP.
Termination Code: 04740160
Severity: Critical -- failure or failure imminent. Fault Manager Event Log Packet Management Area not allocated.
Termination Code: 0476013f
Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; termination processing was completed.
Termination Code: 0477013f
Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; termination processing was initiated but not completed.
Termination Code: 0478393f
Severity: Warning -- not failed but attention recommended or required. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; termination processing was not initiated, the HSV210 controller's PowerPC was spontaneously reset.
Termination Code: 04790020
Severity: Normal -- informational in nature. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; manufacturing full memory test was executed.
Termination Code: 047a013f
Severity: Critical -- failure or failure imminent. The EDC used to test the validity of the Last Termination Event area in nonvolatile memory was bad; unexpected termination processing state.
Termination Code: 047b0022
Severity: Normal -- informational in nature. The HSV210 controller has been requested to be uninitialize by the user.
Termination Code: 04810130
Severity: Critical -- failure or failure imminent. The HSV210 controller inactivity watchdog timer expired.
Termination Code: 0482206f
Severity: Critical -- failure or failure imminent. Cache Memory VTT Voltage Failure.
Termination Code: 0483206f
Severity: Critical -- failure or failure imminent. Non-Volatile Cache Memory Voltage Failure.
Termination Code: 0484206f
Severity: Critical -- failure or failure imminent. Volatile Cache Memory Voltage Failure.
Termination Code: 0485200f
Severity: Critical -- failure or failure imminent. PowerPC Bus Data Parity Error.
Termination Code: 04862010
Severity: Critical -- failure or failure imminent. PowerPC Bus Address Parity Error.
Termination Code: 0487390e
Severity: Warning -- not failed but attention recommended or required. PowerPC L1 Instruction Cache Error.
Termination Code: 0488390e
Severity: Warning -- not failed but attention recommended or required. PowerPC L1 Data Cache Error.
Termination Code: 0489390e
Severity: Warning -- not failed but attention recommended or required. PowerPC L2 Cache Tag Parity or L2 Cache Data Parity Error.
Termination Code: 048a2015
Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer TimeOut Error.
Termination Code: 048b0030
Severity: Normal -- informational in nature. Killed by Other Controller.
Termination Code: 048c0030
Severity: Normal -- informational in nature. Software Restart.
Termination Code: 048d0030
Severity: Normal -- informational in nature. Button Reset.
Termination Code: 048e0114
Severity: Critical -- failure or failure imminent. Atlantis CPU Address Out of Range Error.
Termination Code: 048f2015
Severity: Critical -- failure or failure imminent. Atlantis Transfer Type/Initial Value Violation Error.
Termination Code: 04900114
Severity: Critical -- failure or failure imminent. Atlantis Access to a Protected Region Error.
Termination Code: 04913915
Severity: Warning -- not failed but attention recommended or required. Atlantis Integrated SRAM Parity Error.
Termination Code: 04922015
Severity: Critical -- failure or failure imminent. Uncorrectable Policy Memory ECC Error.
Termination Code: 04930112
Severity: Critical -- failure or failure imminent. Atlantis Device Burst Violation Error.
Termination Code: 04942013
Severity: Critical -- failure or failure imminent. Atlantis Device Ready Timeout Error.
Termination Code: 04952013
Severity: Critical -- failure or failure imminent. Atlantis Device Address or Data Parity Error.
Termination Code: 04960112
Severity: Critical -- failure or failure imminent. Atlantis DMA Failure to Decode Address Error.
Termination Code: 04970112
Severity: Critical -- failure or failure imminent. Atlantis DMA Access Protection Violation Error.
Termination Code: 04980112
Severity: Critical -- failure or failure imminent. Atlantis DMA Write Protect Violation Error.
Termination Code: 04990112
Severity: Critical -- failure or failure imminent. Atlantis DMA Attempt to Access the Descriptor Owned by the CPU.
Termination Code: 049a010f
Severity: Critical -- failure or failure imminent. Sprite PowerPC Transfer Timeout on PCIX Error.
Termination Code: 049b2010
Severity: Critical -- failure or failure imminent. Sprite PowerPC Last Entry Error.
Termination Code: 049c2010
Severity: Critical -- failure or failure imminent. Sprite PowerPC Alignment Error.
Termination Code: 049d3910
Severity: Warning -- not failed but attention recommended or required. Sprite Queue Read Data Parity Error.
Termination Code: 049e010f
Severity: Critical -- failure or failure imminent. Sprite PCIX Access Error - Not a 4-Byte Access.
Termination Code: 049f2011
Severity: Critical -- failure or failure imminent. Sprite Queue Detected an Invalid Destination Error.
Termination Code: 04a0011b
Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - TimeOut Error.
Termination Code: 04a1011b
Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Start Frame Error.
Termination Code: 04a2011b
Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - End Frame Error.
Termination Code: 04a3391c
Severity: Warning -- not failed but attention recommended or required. Sprite XOR-DMA - Parity Error.
Termination Code: 04a4011b
Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Invalid Opcode Error.
Termination Code: 04a5011b
Severity: Critical -- failure or failure imminent. Sprite XOR-DMA - Count Error.
Termination Code: 04a62011
Severity: Critical -- failure or failure imminent. Sprite Bad Write Data Error.
Termination Code: 04a73911
Severity: Warning -- not failed but attention recommended or required. Sprite Command/Data Parity Error.
Termination Code: 04a82011
Severity: Critical -- failure or failure imminent. Sprite New Command Bad Error.
Termination Code: 04a92016
Severity: Critical -- failure or failure imminent. Uncorrectable Cache Memory ECC Error.
Termination Code: 04aa2012
Severity: Critical -- failure or failure imminent. Sprite No Beginning-Of-Frame or Invalid Single Destination Error.
Termination Code: 04ab2012
Severity: Critical -- failure or failure imminent. Sprite Transaction Length MisMatch Error.
Termination Code: 04ac3912
Severity: Warning -- not failed but attention recommended or required. Sprite Transaction Entry Read Parity Error.
Termination Code: 04ad0111
Severity: Critical -- failure or failure imminent. Sprite Bite-Count (BC) MisMatch Error (Transaction BC != BC in FIFO).
Termination Code: 04ae0111
Severity: Critical -- failure or failure imminent. Sprite Target Retry-Count Exceeded Error.
Termination Code: 04af0111
Severity: Critical -- failure or failure imminent. Sprite Initiator Retry-Count Exceeded Error.
Termination Code: 04b00111
Severity: Critical -- failure or failure imminent. Sprite Split-Completion Count Exceeded Error.
Termination Code: 04b10111
Severity: Critical -- failure or failure imminent. Sprite Split-Completion Error Message Received Error.
Termination Code: 04b20111
Severity: Critical -- failure or failure imminent. Sprite UnExpected Split-Completion Error.
Termination Code: 04b30111
Severity: Critical -- failure or failure imminent. Sprite Split-Completion Invalid Termination Error.
Termination Code: 04b40111
Severity: Critical -- failure or failure imminent. Sprite Split-Completion Without a Previous Split-Response Error.
Termination Code: 04b52012
Severity: Critical -- failure or failure imminent. Sprite PCIX PERR Asserted Error.
Termination Code: 04b60112
Severity: Critical -- failure or failure imminent. Sprite performed a Master Abort Error.
Termination Code: 04b72012
Severity: Critical -- failure or failure imminent. Sprite received a Target Abort Error.
Termination Code: 04b82012
Severity: Critical -- failure or failure imminent. Sprite asserted SERR.
Termination Code: 04b92012
Severity: Critical -- failure or failure imminent. Sprite detected SERR.
Termination Code: 04ba011b
Severity: Critical -- failure or failure imminent. Tachyon Unsupported Byte Enable Error.
Termination Code: 04bb391b
Severity: Warning -- not failed but attention recommended or required. Tachyon Outbound Parity Error.
Termination Code: 04bc391b
Severity: Warning -- not failed but attention recommended or required. Tachyon Inbound Parity Error.
Termination Code: 04bd201c
Severity: Critical -- failure or failure imminent. Tachyon Detected Parity Error.
Termination Code: 04be201c
Severity: Critical -- failure or failure imminent. Tachyon Signaled System Error (SERR).
Termination Code: 04bf011b
Severity: Critical -- failure or failure imminent. Tachyon Received Master Abort Error.
Termination Code: 04c0201c
Severity: Critical -- failure or failure imminent. Tachyon Received Target Abort Error.
Termination Code: 04c1201c
Severity: Critical -- failure or failure imminent. Tachyon Signaled Target Abort Error.
Termination Code: 04c2201c
Severity: Critical -- failure or failure imminent. Tachyon Master Data Parity Error.
Termination Code: 04c3011b
Severity: Critical -- failure or failure imminent. Tachyon Unexpected Split-Completion Error.
Termination Code: 04c4011b
Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Discarded Error.
Termination Code: 04c5391c
Severity: Warning -- not failed but attention recommended or required. Tachyon Parity Error on Split Related Transaction.
Termination Code: 04c6391c
Severity: Warning -- not failed but attention recommended or required. Tachyon Parity Error on Incoming Data.
Termination Code: 04c7391c
Severity: Warning -- not failed but attention recommended or required. Tachyon Parity Error on Outgoing Data.
Termination Code: 04c8201c
Severity: Critical -- failure or failure imminent. Tachyon Attribute Parity Error.
Termination Code: 04c9011b
Severity: Critical -- failure or failure imminent. Tachyon Split-Completion Byte Count Excessive.
Termination Code: 04ca011b
Severity: Critical -- failure or failure imminent. Tachyon Read Byte Count Excessive Error.
Termination Code: 04cb011b
Severity: Critical -- failure or failure imminent. Tachyon Read FIFO Parity Error.
Termination Code: 04cc011b
Severity: Critical -- failure or failure imminent. Tachyon Write FIFO Parity Error.
Termination Code: 04cd011b
Severity: Critical -- failure or failure imminent. Tachyon Reserved Region Access Error.
Termination Code: 04ce010d
Severity: Critical -- failure or failure imminent. Tachyon Parity Error on Split Completion Error.
Termination Code: 04cf011a
Severity: Critical -- failure or failure imminent. Undecoded machine check.
Termination Code: 04d00180
Severity: Critical -- failure or failure imminent. Manufacturing Event Analysis Log Commit Packet unexpectedly in use.
Termination Code: 04f6013f
Severity: Critical -- failure or failure imminent. User termination test all parameters.
Termination Code: 04f70000
Severity: Normal -- informational in nature. Console requested restart with dump (not coupled) via CTRL-Z.
Termination Code: 04f9017f
Severity: Critical -- failure or failure imminent. Poweroff test.
Termination Code: 04fa0100
Severity: Critical -- failure or failure imminent. User termination test no parameters.
Termination Code: 04fb011f
Severity: Critical -- failure or failure imminent. User termination test all parameters.
Termination Code: 04fc0100
Severity: Critical -- failure or failure imminent. ISR termination test no parameters.
Termination Code: 04fd011f
Severity: Critical -- failure or failure imminent. ISR termination test all parameters.
Termination Code: 04fe0100
Severity: Critical -- failure or failure imminent. Function not yet implemented.
Termination Code: 04ff011f
Severity: Critical -- failure or failure imminent. EXEC_BUGCHECK statement executed.
Termination Code: 06040100
Severity: Critical -- failure or failure imminent. Failed memory allocation for SFQ.
Termination Code: 06150100
Severity: Critical -- failure or failure imminent. Failed memory allocation for Fibre Channel Services Crash Dump structure.
Termination Code: 061c0100
Severity: Critical -- failure or failure imminent. Failed memory allocation for IBQ.
Termination Code: 061d0100
Severity: Critical -- failure or failure imminent. Failed memory allocation for MFC copy buffer.
Termination Code: 06200100
Severity: Critical -- failure or failure imminent. Invalid Completion Message type.
Termination Code: 06230100
Severity: Critical -- failure or failure imminent. Class 2 Failure for outbound sequence.
Termination Code: 0624011f
Severity: Critical -- failure or failure imminent. Host Programming error.
Termination Code: 06280100
Severity: Critical -- failure or failure imminent. Invalid Port Event Type.
Termination Code: 06290100
Severity: Critical -- failure or failure imminent. Unknown FED type found.
Termination Code: 062a0100
Severity: Critical -- failure or failure imminent. Unknown FED found during Link Down cleanup.
Termination Code: 062b0100
Severity: Critical -- failure or failure imminent. Fail status returned for timer start.
Termination Code: 062c0100
Severity: Critical -- failure or failure imminent. Unexpected loop state.
Termination Code: 062e0100
Severity: Critical -- failure or failure imminent. SEST programming error.
Termination Code: 062f0100
Severity: Critical -- failure or failure imminent. SEST programming error.
Termination Code: 06320100
Severity: Critical -- failure or failure imminent. Port chip failed to go Offline.
Termination Code: 06330100
Severity: Critical -- failure or failure imminent. Out of Reserved FEDs.
Termination Code: 06340100
Severity: Critical -- failure or failure imminent. Unsupported ELS requested.
Termination Code: 06360100
Severity: Critical -- failure or failure imminent. Unsupported drive initialization sequence command.
Termination Code: 06380100
Severity: Critical -- failure or failure imminent. Unsupported TDS requested.
Termination Code: 063c0100
Severity: Critical -- failure or failure imminent. Command issued to an illegal LBA.
Termination Code: 06410100
Severity: Critical -- failure or failure imminent. Unknown SCSI status byte.
Termination Code: 06420100
Severity: Critical -- failure or failure imminent. No backend ports were available for a mirror cache transfer
Termination Code: 06460100
Severity: Critical -- failure or failure imminent. Unsupported SES page for Receive Diagnostic Results.
Termination Code: 06470100
Severity: Critical -- failure or failure imminent. Unsupported SES String In subpage for Receive Diagnostic Results.
Termination Code: 06500080
Severity: Normal -- informational in nature. Unsupported SES page for Receive Diagnostic Results.
Termination Code: 0651011f
Severity: Critical -- failure or failure imminent. FED for handling MFC ACK was not on the In-process Queue as expected.
Termination Code: 07000100
Severity: Critical -- failure or failure imminent. Initialization failed due to insufficient memory.
Termination Code: 07010100
Severity: Critical -- failure or failure imminent. LMAP allocation failed.
Termination Code: 07020100
Severity: Critical -- failure or failure imminent. LMAP allocation failed.
Termination Code: 07030100
Severity: Critical -- failure or failure imminent. Invalid RAID type.
Termination Code: 07070100
Severity: Critical -- failure or failure imminent. Failed reading QS.
Termination Code: 070a0100
Severity: Critical -- failure or failure imminent. RSD allocation failed.
Termination Code: 070b0100
Severity: Critical -- failure or failure imminent. LDSB ref_count is off
Termination Code: 070c0100
Severity: Critical -- failure or failure imminent. Invalid Object Class for I/O request.
Termination Code: 070d0100
Severity: Critical -- failure or failure imminent. Invalid I/O range for given object.
Termination Code: 07110100
Severity: Critical -- failure or failure imminent. Invalid RAID type.
Termination Code: 07130100
Severity: Critical -- failure or failure imminent. Invalid RAID type.
Termination Code: 07140100
Severity: Critical -- failure or failure imminent. Invalid structure - Zero process.
Termination Code: 07150100
Severity: Critical -- failure or failure imminent. Invalid structure - Zero process.
Termination Code: 07160100
Severity: Critical -- failure or failure imminent. Invalid structure - ODWORK process.
Termination Code: 07170100
Severity: Critical -- failure or failure imminent. Program buffer leak detected.
Termination Code: 07180100
Severity: Critical -- failure or failure imminent. Buffer pool leak detected.
Termination Code: 07190100
Severity: Critical -- failure or failure imminent. Code not yet implemented.
Termination Code: 071a0100
Severity: Critical -- failure or failure imminent. Wrong LDSB returned to waiting abort requester.
Termination Code: 071b0100
Severity: Critical -- failure or failure imminent. Wrong LDAD returned to waiting abort requester.
Termination Code: 071c0100
Severity: Critical -- failure or failure imminent. Bad map type for read merge.
Termination Code: 071d0100
Severity: Critical -- failure or failure imminent. Cache hit occurred while performing read merge.
Termination Code: 071e0100
Severity: Critical -- failure or failure imminent. PSAR indicates invalid usage.
Termination Code: 071f0100
Severity: Critical -- failure or failure imminent. Bad object class in Regen/Replace.
Termination Code: 07200100
Severity: Critical -- failure or failure imminent. No Free CMAPs.
Termination Code: 07220100
Severity: Critical -- failure or failure imminent. Invalid CS Drive Request.
Termination Code: 07240100
Severity: Critical -- failure or failure imminent. No Free CS Req items.
Termination Code: 07260100
Severity: Critical -- failure or failure imminent. Invalid Volnoid encountered.
Termination Code: 07290100
Severity: Critical -- failure or failure imminent. Multiple Metadata Transactions Detected.
Termination Code: 072a0100
Severity: Critical -- failure or failure imminent. I/O Failed in CS$RECOVER_TRANSACTIONS.
Termination Code: 072b0100
Severity: Critical -- failure or failure imminent. Invalid Transaction type.
Termination Code: 072d0100
Severity: Critical -- failure or failure imminent. No Transaction was found.
Termination Code: 072f0100
Severity: Critical -- failure or failure imminent. Member State not supported in zero_rsdm.
Termination Code: 07300100
Severity: Critical -- failure or failure imminent. Regen of Member should be complete, but is not.
Termination Code: 07340100
Severity: Critical -- failure or failure imminent. Bad CS Req Object Class in handle CS Req.
Termination Code: 07350100
Severity: Critical -- failure or failure imminent. Invalid CS Req Operation in handle CS Req.
Termination Code: 07370100
Severity: Critical -- failure or failure imminent. Invalid Volnoid in Sparing Process.
Termination Code: 07380100
Severity: Critical -- failure or failure imminent. No XDs available for cs_req operation
Termination Code: 07390100
Severity: Critical -- failure or failure imminent. Invalid Raid Type in Regen/Reassign.
Termination Code: 073b0100
Severity: Critical -- failure or failure imminent. Unknown CS Transaction type for Journaling.
Termination Code: 073c0100
Severity: Critical -- failure or failure imminent. CS Journal Transaction inconsistency.
Termination Code: 073d0100
Severity: Critical -- failure or failure imminent. Invalid CS Transaction type for Journaling operation.
Termination Code: 073e0100
Severity: Critical -- failure or failure imminent. Invalid structure - LD Leveling process.
Termination Code: 073f0100
Severity: Critical -- failure or failure imminent. Invalid structure - RStore Sparing process.
Termination Code: 07400100
Severity: Critical -- failure or failure imminent. Invalid structure - CS Req process.
Termination Code: 07410100
Severity: Critical -- failure or failure imminent. Invalid structure - PLDMC process.
Termination Code: 07420100
Severity: Critical -- failure or failure imminent. No Free RLBs (RSD Lock Blocks).
Termination Code: 07430100
Severity: Critical -- failure or failure imminent. RLB List is inconsistent.
Termination Code: 07440100
Severity: Critical -- failure or failure imminent. RLB state is inconsistent.
Termination Code: 07450100
Severity: Critical -- failure or failure imminent. Invalid structure - CS CSLD process.
Termination Code: 07460100
Severity: Critical -- failure or failure imminent. Invalid structure - CS E-bit handler.
Termination Code: 07480100
Severity: Critical -- failure or failure imminent. Illegal QS I/O by Non Storage System Master.
Termination Code: 07490100
Severity: Critical -- failure or failure imminent. Illegal CSLD I/O by Non Storage System Master.
Termination Code: 074a0100
Severity: Critical -- failure or failure imminent. Invalid structure - ACBW process.
Termination Code: 074b0100
Severity: Critical -- failure or failure imminent. Invalid ACBW Opcode.
Termination Code: 074c0100
Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process.
Termination Code: 074f0100
Severity: Critical -- failure or failure imminent. Invalid structure - RSS Migration process.
Termination Code: 07500100
Severity: Critical -- failure or failure imminent. Invalid structure - RStore Migration process.
Termination Code: 07510100
Severity: Critical -- failure or failure imminent. Member State not supported.
Termination Code: 07520100
Severity: Critical -- failure or failure imminent. Metadata is inaccessible; an inoperative condition has occurred.
Termination Code: 07530100
Severity: Critical -- failure or failure imminent. An invalid structure was encountered on an ALB list.
Termination Code: 07540100
Severity: Critical -- failure or failure imminent. LMAP does not point to RStore, and RStore not being allocated.
Termination Code: 07550100
Severity: Critical -- failure or failure imminent. Invalid structure - LD Allocation work process.
Termination Code: 07570100
Severity: Critical -- failure or failure imminent. Realize or realize_temp failed.
Termination Code: 07580100
Severity: Critical -- failure or failure imminent. Unrealize or unrealize_temp failed.
Termination Code: 07590100
Severity: Critical -- failure or failure imminent. Unit realized before initial allocation completed
Termination Code: 075b0100
Severity: Critical -- failure or failure imminent. An I/O that should NOT fail, did.
Termination Code: 075d0100
Severity: Critical -- failure or failure imminent. Invalid structure - CS C-bit handler.
Termination Code: 075e0100
Severity: Critical -- failure or failure imminent. Invalid structure - OD bg aloc process.
Termination Code: 075f0100
Severity: Critical -- failure or failure imminent. DUB and RSS do not agree with each other.
Termination Code: 07600100
Severity: Critical -- failure or failure imminent. Invalid LD type
Termination Code: 07610100
Severity: Critical -- failure or failure imminent. Invalid DIP State in LD
Termination Code: 07620100
Severity: Critical -- failure or failure imminent. Deallocation failed
Termination Code: 07630100
Severity: Critical -- failure or failure imminent. Failure to validate reserved capacity on each rss member
Termination Code: 07640100
Severity: Critical -- failure or failure imminent. Invalid structure - REBUILD PARITY MAIN
Termination Code: 07680100
Severity: Critical -- failure or failure imminent. An RSS member has been removed unexpectedly.
Termination Code: 07690102
Severity: Critical -- failure or failure imminent. An unsupported member manager state has occurred.
Termination Code: 076a0100
Severity: Critical -- failure or failure imminent. No Quorum Disks have been discovered.
Termination Code: 076b0100
Severity: Critical -- failure or failure imminent. Invalid/unknown pseg allocation type
Termination Code: 076c0100
Severity: Critical -- failure or failure imminent. XMFC Failure - other controller gone during communication with it.
Termination Code: 076d0100
Severity: Critical -- failure or failure imminent. Invalid XMFC operation.
Termination Code: 076e0100
Severity: Critical -- failure or failure imminent. Invalid type in RSDM.
Termination Code: 07700105
Severity: Critical -- failure or failure imminent. CHKDSK test failed
Termination Code: 07710100
Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process.
Termination Code: 07720100
Severity: Critical -- failure or failure imminent. Invalid structure - Unsharing process.
Termination Code: 07730100
Severity: Critical -- failure or failure imminent. The RSD pointer should have been NULL but wasn't
Termination Code: 07740100
Severity: Critical -- failure or failure imminent. Shadow initial synchronization encountered bad data
Termination Code: 07750100
Severity: Critical -- failure or failure imminent. The LD should have not been realized but was
Termination Code: 08010100
Severity: Critical -- failure or failure imminent. Bad status from CS$SET_EBIT
Termination Code: 08020100
Severity: Critical -- failure or failure imminent. An abnormal member's member_state is not supported
Termination Code: 08030100
Severity: Critical -- failure or failure imminent. A request was made to do I/O for an undefined RAID type.
Termination Code: 08040100
Severity: Critical -- failure or failure imminent. Drive rewrite function is not supported
Termination Code: 08050100
Severity: Critical -- failure or failure imminent. A sprite DMA transaction completed with an interrupt but the DMA context queue was empty
Termination Code: 08060100
Severity: Critical -- failure or failure imminent. Unable to save DMA context because the Queue is full
Termination Code: 08070100
Severity: Critical -- failure or failure imminent. Cannot dynamically allocate enough memory to store waiters for ptr 9687 fix.
Termination Code: 08080100
Severity: Critical -- failure or failure imminent. Unsupported structure type passed into RS function
Termination Code: 08090100
Severity: Critical -- failure or failure imminent. Sprite CDB memory has been corrupted
Termination Code: 080a0100
Severity: Critical -- failure or failure imminent. Sprite returned an error that we don't know how to handle yet
Termination Code: 080f0100
Severity: Critical -- failure or failure imminent. Sprite DMA context queue is out of sync with interrupts
Termination Code: 09010100
Severity: Critical -- failure or failure imminent. EXEC_init_bque failed.
Termination Code: 09020100
Severity: Critical -- failure or failure imminent. Memory allocation failed for Storage System Management Interface CP/RP (task block).
Termination Code: 09040100
Severity: Critical -- failure or failure imminent. Storage System Management Interface detected an internal inconsistency.
Termination Code: 09060100
Severity: Critical -- failure or failure imminent. Memory allocation failed for return buffer.
Termination Code: 09080100
Severity: Critical -- failure or failure imminent. Insufficient resources available for SCMI Command Lock dynamic allocation.
Termination Code: 09090100
Severity: Critical -- failure or failure imminent. Insufficient resources available for SCMI Command Lock initial allocation.
Termination Code: 0b000100
Severity: Critical -- failure or failure imminent. Invalid XMFC Response Packet.
Termination Code: 0b010100
Severity: Critical -- failure or failure imminent. Invalid MFC Vector (Index).
Termination Code: 0b020100
Severity: Critical -- failure or failure imminent. Invalid System Activity Collection state.
Termination Code: 0b040100
Severity: Critical -- failure or failure imminent. Invalid System Utility (Code Load or Resynchronization) state.
Termination Code: 0b052001
Severity: Critical -- failure or failure imminent. Attempt to access EEPROM for UUID Range failed.
Termination Code: 0b062001
Severity: Critical -- failure or failure imminent. UUID Range overflow.
Termination Code: 0b080100
Severity: Critical -- failure or failure imminent. A resynchronization was requested at an inappropriate time.
Termination Code: 0b092003
Severity: Critical -- failure or failure imminent. Attempt to access Operator Control Panel failed.
Termination Code: 0b0a0100
Severity: Critical -- failure or failure imminent. Invalid XMFC State.
Termination Code: 0b100021
Severity: Normal -- informational in nature. New glue code available, attempting a force load which requires a restart after the load is successful.
Termination Code: 0b110020
Severity: Normal -- informational in nature. New boot code available, attempting a force load following restart.
Termination Code: 0b12db60
Severity: Warning -- not failed but attention recommended or required. Attempt to load Non-ROHS compliant firmware onto a ROHS complaint controller or Non-CR2 firmware onto a CR2 controller was prevented.
Termination Code: 0c010102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command.
Termination Code: 0c03010c
Severity: Critical -- failure or failure imminent. Invalid state exists for deleting a Group State Block.
Termination Code: 0c040101
Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The group sequence number node already exists.
Termination Code: 0c050106
Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery write data was not in cache as expected.
Termination Code: 0c060106
Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: The recovery write data found in cache was not marked dirty write-back cached data as expected.
Termination Code: 0c070106
Severity: Critical -- failure or failure imminent. A software problem was found in processing a recovery write upon controller start or failover: Lookup of group sequence number node failed.
Termination Code: 0c080106
Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: A recovery write was found, but its associated RIE was not marked free as expected.
Termination Code: 0c090106
Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the mirror cache when the mirror was declared invalid: Not all group members were processed.
Termination Code: 0c0a0106
Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the primary was declared invalid: A recovery write was found, but its associated RIE was not marked free as expected.
Termination Code: 0c0b0106
Severity: Critical -- failure or failure imminent. A software problem was found in cleaning Data Replication Manager context in the primary cache when the primary was declared invalid: Not all group members were processed.
Termination Code: 0c0c0104
Severity: Critical -- failure or failure imminent. A software problem was found when deleting the Group State Block: Transfers were not completely run down.
Termination Code: 0c0d0104
Severity: Critical -- failure or failure imminent. A software problem was found when inserting a Group State Block into the active list: A Group State Block with this same Universal Unique Identifier is already on the active list.
Termination Code: 0c0e0106
Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected in the transfer path upon remote write completion after the mirror controller was updated; A Full Copy of the affected Data Replication Group may be initiated upon the next controller restart.
Termination Code: 0c0f0105
Severity: Critical -- failure or failure imminent. Setting the e-bit failed for a write long command on the destination unit.
Termination Code: 0c100104
Severity: Critical -- failure or failure imminent. An attempt was made to acquire the Data Replication Manager Remote Response Waiter, but it was unexpectedly already in use.
Termination Code: 0c110105
Severity: Critical -- failure or failure imminent. A Group Sequence Number Node was lost during mirror synchronization.
Termination Code: 0c130105
Severity: Critical -- failure or failure imminent. An unexpected I/O failure occurred: Container Services was unable to write to the PLDMC on media.
Termination Code: 0c140106
Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected in the transfer path on the mirror side upon remote write completion; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c150106
Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected upon controller restart or failover when building the list of incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c160106
Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected upon controller restart or failover when completing previously incomplete writes; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c170106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the received group sequence number was detected after a controller restarted, when synchonizing the group sequence numbers with the mirror side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c180106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use and sent group sequence numbers was detected after a controller restarted, when synchronizing the group sequence numbers with the mirror side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c190106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the received group sequence number was detected after a controller restarted, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c1a0106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use and sent group sequence number was detected after a controller restart, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c1b0106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected after a controller restart, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c1c0107
Severity: Critical -- failure or failure imminent. A group sequence number out of order was detected after a controller restart when synchronizing the mirror writes with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c200106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected after a controller restart, when synchronizing the group sequence numbers with the primary side; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c210106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too high; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c220108
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too low; A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c230105
Severity: Critical -- failure or failure imminent. A Data Replication Group member was detected to be in an unexpected cache state.
Termination Code: 0c240107
Severity: Critical -- failure or failure imminent. Secondary controller selection failed.
Termination Code: 0c270106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too low. A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c280106
Severity: Critical -- failure or failure imminent. A group sequence number out of order with the use group sequence number was detected to be too low. A Full Copy of the affected Data Replication Group may be initiated upon controller restart.
Termination Code: 0c290105
Severity: Critical -- failure or failure imminent. Data Replication Manager Dual State was not idle for MFC communication between the dual controllers during an add member operation.
Termination Code: 0c2a0106
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management ADD SOURCE command.
Termination Code: 0c2b0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command when a process is waiting for the ACK.
Termination Code: 0c2c0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command when a process is waiting for a DONE response.
Termination Code: 0c2d0105
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating an ADD SOURCE dual controller management command.
Termination Code: 0c2e0105
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating an SITE FAILOVER dual controller management command.
Termination Code: 0c2f0106
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management command requiring a DRRW response.
Termination Code: 0c300105
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating a multi-destinaton dual controller management command.
Termination Code: 0c310105
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while creating a dual controller management command that has only an ACK as a response and passes a group object as a parameter.
Termination Code: 0c320101
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found in the main dispatch function for dual controller management commands.
Termination Code: 0c330103
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found in the main processing function for dual controller management commands.
Termination Code: 0c340101
Severity: Critical -- failure or failure imminent. An EETB resource needed for a Data Replication Manager Mirror Request dual controller management command is already in use by another command.
Termination Code: 0c350101
Severity: Critical -- failure or failure imminent. An EETB resource expected in response to a Data Replication Manager Mirror Request dual controller management command is missing.
Termination Code: 0c360102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while issuing a simple dual controller management command.
Termination Code: 0c370102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing the response to a simple dual controller management command.
Termination Code: 0c380102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a simple dual controller management command.
Termination Code: 0c390102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a dual controller management command which uses an SCVD object.
Termination Code: 0c3a0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a unit related dual controller management command that does not require an additional response.
Termination Code: 0c3b0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a unit related dual controller management command that requires an additional response.
Termination Code: 0c3c0102
Severity: Critical -- failure or failure imminent. An unexpected response to a dual controller management command was received during mirror controller crash cleanup.
Termination Code: 0c3d0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a mirror request dual controller management command.
Termination Code: 0c3e0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a dual controller management command to be sent to the mirror controller.
Termination Code: 0c3f0102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management mirror response.
Termination Code: 0c400102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while building a dual controller management response to be sent to the mirror controller.
Termination Code: 0c410102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while initiating a site failover.
Termination Code: 0c420102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management synchronize buffers command.
Termination Code: 0c430102
Severity: Critical -- failure or failure imminent. Invalid Data Replication Manager Dual State was found while processing an ACK for a dual controller management MDW command.
Termination Code: 0c450100
Severity: Critical -- failure or failure imminent. We should not have gone down this path.
Termination Code: 0c460103
Severity: Critical -- failure or failure imminent. MFC frame corruption detected.
Termination Code: 0c470104
Severity: Critical -- failure or failure imminent. Invalid attempt to associate host adapter ACB with Data Replication Manager destination DDCB.
Termination Code: 0c480100
Severity: Critical -- failure or failure imminent. Insufficient free memory available to allocate required DDCB structures.
Termination Code: 0c490100
Severity: Critical -- failure or failure imminent. Insufficient free memory available to allocate required RNSB structures.
Termination Code: 0c4a0104
Severity: Critical -- failure or failure imminent. Invalid attempt to associate a temporary ACB with Data Replication Manager destination DDCB.
Termination Code: 0e000020
Severity: Normal -- informational in nature. Found invalid battery subsystem state.
Termination Code: 0e010020
Severity: Normal -- informational in nature. Found invalid battery system hold up time.
Termination Code: 0e020020
Severity: Normal -- informational in nature. Found invalid battery brick number.
Termination Code: 0e030020
Severity: Normal -- informational in nature. Found invalid battery brick state.
Termination Code: 0e050020
Severity: Normal -- informational in nature. Found invalid blower number.
Termination Code: 0e060020
Severity: Normal -- informational in nature. Found invalid blower state.
Termination Code: 0e080020
Severity: Normal -- informational in nature. Found invalid temperature subsystem state.
Termination Code: 0e090020
Severity: Normal -- informational in nature. Found invalid power supply number.
Termination Code: 0e0a0020
Severity: Normal -- informational in nature. Found invalid power supply state.
Termination Code: 0e0b0020
Severity: Normal -- informational in nature. A command was sent to the SDC microcontroller while it was still busy processing a previous command.
Termination Code: 42000101
Severity: Critical -- failure or failure imminent. No memory for HP_init.
Termination Code: 42050103
Severity: Critical -- failure or failure imminent. Unexpected Cache Node lock state for WRITE LONG.
Termination Code: 42060105
Severity: Critical -- failure or failure imminent. Unexpected outstanding SCSI command on unit.
Termination Code: 42070123
Severity: Critical -- failure or failure imminent. DD CDB function 0X42 received.
Termination Code: 420801a3
Severity: Critical -- failure or failure imminent. DD CDB function 0X43 received.
Termination Code: 420901c3
Severity: Critical -- failure or failure imminent. DD CDB function 0X86 received.
Termination Code: 420c0184
Severity: Critical -- failure or failure imminent. Unknown build context received in remote SCSI MFC build routine.
Termination Code: 420d0182
Severity: Critical -- failure or failure imminent. Unknown context received in remote SCSI MFC receive routine.
Termination Code: 420e0181
Severity: Critical -- failure or failure imminent. ICOPS could not allocate necessary memory.
Termination Code: 420f0182
Severity: Critical -- failure or failure imminent. Unknown build context in the ICOPS build routine.
Termination Code: 42100182
Severity: Critical -- failure or failure imminent. Unknown receive context in the ICOPS receive routine.
Termination Code: 42120104
Severity: Critical -- failure or failure imminent. Illegal structure on in process queue.
Termination Code: 42130101
Severity: Critical -- failure or failure imminent. No host port command HTBs.
Termination Code: 42140102
Severity: Critical -- failure or failure imminent. Invalid Context in hp_call_get_scsi_data.
Termination Code: 42150102
Severity: Critical -- failure or failure imminent. HP_change_host_mode ACB-- not found.
Termination Code: 42160102
Severity: Critical -- failure or failure imminent. HP_present_lun-- ACB not found.
Termination Code: 42190104
Severity: Critical -- failure or failure imminent. CCB either already in use or improperly marked not used.
Termination Code: 421b0102
Severity: Critical -- failure or failure imminent. A work request has an invalid type.
Termination Code: 421c0101
Severity: Critical -- failure or failure imminent. Work request resources have run out.
Termination Code: 421e0102
Severity: Critical -- failure or failure imminent. Allocated command HTB is already in use.
Termination Code: 42230102
Severity: Critical -- failure or failure imminent. HP_unpresent_lun ACB not found.
Termination Code: 42250104
Severity: Critical -- failure or failure imminent. Could not delete the ACB.
Termination Code: 42260104
Severity: Critical -- failure or failure imminent. Did not have a Unit Attention table and units are presented.
Termination Code: 42270108
Severity: Critical -- failure or failure imminent. Port event handler had an unknown port event.
Termination Code: 42280102
Severity: Critical -- failure or failure imminent. Unknown completion message from the Tachyon.
Termination Code: 42290103
Severity: Critical -- failure or failure imminent. Received an illegal SEST id.
Termination Code: 422a0103
Severity: Critical -- failure or failure imminent. Received a bad AL_PA from the Tachyon on a point to point topology.
Termination Code: 422b0103
Severity: Critical -- failure or failure imminent. Received an unknown error idle status from the Tachyon.
Termination Code: 422c0003
Severity: Normal -- informational in nature. Received an unknown error idle status from the Tachyon.
Termination Code: 422d010a
Severity: Critical -- failure or failure imminent. Received an unknown I/O error value.
Termination Code: 422e0104
Severity: Critical -- failure or failure imminent. Had a LUN with write only access.
Termination Code: 422f0103
Severity: Critical -- failure or failure imminent. Received an unknown FCP inbound completion status.
Termination Code: 42300103
Severity: Critical -- failure or failure imminent. Received an illegal script response.
Termination Code: 42310102
Severity: Critical -- failure or failure imminent. Received an illegal error status in the error routine.
Termination Code: 42320104
Severity: Critical -- failure or failure imminent. Requested to present a LUN that is already in existence or is illegal
Termination Code: 4233010a
Severity: Critical -- failure or failure imminent. An internal request was made to return a status of Not Ready for work created in the controller.
Termination Code: 42340104
Severity: Critical -- failure or failure imminent. The state for a command with the Immed bit set in the CDB is incorrect.
Termination Code: 42350104
Severity: Critical -- failure or failure imminent. A unit unquiesce was called without the corresponding quiesce.
Termination Code: 42360102
Severity: Critical -- failure or failure imminent. A call to notify of new ELP encountered an invalid CSEL state.
Termination Code: 42370183
Severity: Critical -- failure or failure imminent. Gap in Sequence Numbers for Event Logs.
Termination Code: 4238011f
Severity: Critical -- failure or failure imminent. The host port has detected a CSM reset after 60 minutes.
Termination Code: 42390184
Severity: Critical -- failure or failure imminent. Invalid proxy io operation state
Termination Code: 423a0102
Severity: Critical -- failure or failure imminent. Logical port number out of range to access S_pcb[]
Termination Code: 423b0102
Severity: Critical -- failure or failure imminent. The tachyon chip is not responding. The controller will be restarted so that diagnostics can be executed.
Termination Code: 423c0306
Severity: Undetermined -- more information needed to determine severity. An attempt was made to create a client using the remote port world wide name of a Data Replication Path.The controller will be restarted so this condition can be cleared.
Termination Code: 83002061
Severity: Critical -- failure or failure imminent. DOG cannot branch to this routine.
Termination Code: 83012079
Severity: Critical -- failure or failure imminent. DOG unexpected vector to error.
Termination Code: 8302206b
Severity: Critical -- failure or failure imminent. DOG non-fault tolerant hard error.
Termination Code: 84032069
Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in cache memory.
Termination Code: 84042065
Severity: Critical -- failure or failure imminent. Excessive correctable errors have been seen in policy memory.
EVENT INFORMATION PACKETS:
Event Information Packet Type: 1
EIP01 - Fault Manager Termination Processing Recursive Entry Event
A machine check occurred while a termination event was being processed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
union hdu Termination Event Information Header
<byte 72>
{lteihd (Active if Termination Event Information Header revision is greater than 3)}
<byte 72>
{flags (Last Termination Event flags)}
<byte 72>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 rsvd Pad to fill byte
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 73>
utiny revision Structure revision number
<byte 74>
ushort size Structure size
{}
or hdu Termination Event Information Header
<byte 72>
{lteihd0 (Active if Termination Event Information Header revision is less than or equal to 3)}
<byte 72>
{flags (Last Termination Event flags)}
<byte 72>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
{}
<byte 73>
utiny revision Structure revision number
<byte 74>
ushort size Structure size
{}
endunion hdu Termination Event Information Header
<byte 76>
union ru Termination Event Reporting Information
<byte 76>
{lter (Active if Termination Event Information Header revision greater than 3)}
<byte 76>
ulong seq Sequence number assigned to the termination event
<byte 80>
char[4] sw_version HSV210 controller software version number string
<byte 84>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 96>
char[8] ctrlr_model_id HSV210 controller model string
<byte 104>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 124>
scmitim termination_time Time termination event occurred
<byte 132>
{termination_event (Termination event information)}
<byte 132>
ulong termination_location Location of termination event report call
<byte 136>
union u Termination Code Union
<byte 136>
{code (Termination Code)}
<byte 136>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 137>
cacode cac Corrective Action Code
<byte 138>
utiny evnum Event Number
<byte 139>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 136>
ulong value Termination Code Value
endunion u Termination Code Union
{}
<byte 140>
utiny[2] reserved Reserved
<byte 142>
{flags (Other Last Termination Event flags)}
<byte 142>
tbits:1 lg_send_sts Last Gasp send status
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
tbits:3 rsvd Pad to fill byte
{}
<byte 143>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 144>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
or ru Termination Event Reporting Information
<byte 76>
{lter0 (Active if Termination Event Information Header revision is less than or equal to 3)}
<byte 76>
ulong seq Sequence number assigned to the termination event
<byte 80>
char[4] sw_version HSV210 controller software version number string
<byte 84>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 96>
char[8] ctrlr_model_id HSV210 controller model string
<byte 104>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 124>
scmitim termination_time Time termination event occurred
<byte 132>
{termination_event (Termination event information)}
<byte 132>
ulong termination_location Location of termination event report call
<byte 136>
union u Termination Code Union
<byte 136>
{code (Termination Code)}
<byte 136>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 137>
cacode cac Corrective Action Code
<byte 138>
utiny evnum Event Number
<byte 139>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 136>
ulong value Termination Code Value
endunion u Termination Code Union
{}
<byte 140>
utiny[2] reserved Reserved
<byte 142>
utiny lg_send_sts Last Gasp send status
<byte 143>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 144>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
endunion ru Termination Event Reporting Information
<byte 152>
{rei (Recursive Entry Event Information)}
<byte 152>
ulong tt Trap type
<byte 156>
ulong tc Termination code
<byte 160>
ulong srr0 SRR0 register
<byte 164>
ulong lr LR register
<byte 168>
ulong exception Exception code
{}
{}
Event Information Packet Type: 2
EIP02 - Fault Manager Termination Processing Unexpected Event
An unexpected event occurred while a termination event was being processed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
union hdu Termination Event Information Header
<byte 72>
{lteihd (Active if Termination Event Information Header revision is greater than 3)}
<byte 72>
{flags (Last Termination Event flags)}
<byte 72>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 rsvd Pad to fill byte
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 73>
utiny revision Structure revision number
<byte 74>
ushort size Structure size
{}
or hdu Termination Event Information Header
<byte 72>
{lteihd0 (Active if Termination Event Information Header revision is less than or equal to 3)}
<byte 72>
{flags (Last Termination Event flags)}
<byte 72>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
{}
<byte 73>
utiny revision Structure revision number
<byte 74>
ushort size Structure size
{}
endunion hdu Termination Event Information Header
<byte 76>
union ru Termination Event Reporting Information
<byte 76>
{lter (Active if Termination Event Information Header revision greater than 3)}
<byte 76>
ulong seq Sequence number assigned to the termination event
<byte 80>
char[4] sw_version HSV210 controller software version number string
<byte 84>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 96>
char[8] ctrlr_model_id HSV210 controller model string
<byte 104>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 124>
scmitim termination_time Time termination event occurred
<byte 132>
{termination_event (Termination event information)}
<byte 132>
ulong termination_location Location of termination event report call
<byte 136>
union u Termination Code Union
<byte 136>
{code (Termination Code)}
<byte 136>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 137>
cacode cac Corrective Action Code
<byte 138>
utiny evnum Event Number
<byte 139>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 136>
ulong value Termination Code Value
endunion u Termination Code Union
{}
<byte 140>
utiny[2] reserved Reserved
<byte 142>
{flags (Other Last Termination Event flags)}
<byte 142>
tbits:1 lg_send_sts Last Gasp send status
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
tbits:3 rsvd Pad to fill byte
{}
<byte 143>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 144>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
or ru Termination Event Reporting Information
<byte 76>
{lter0 (Active if Termination Event Information Header revision is less than or equal to 3)}
<byte 76>
ulong seq Sequence number assigned to the termination event
<byte 80>
char[4] sw_version HSV210 controller software version number string
<byte 84>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 96>
char[8] ctrlr_model_id HSV210 controller model string
<byte 104>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 124>
scmitim termination_time Time termination event occurred
<byte 132>
{termination_event (Termination event information)}
<byte 132>
ulong termination_location Location of termination event report call
<byte 136>
union u Termination Code Union
<byte 136>
{code (Termination Code)}
<byte 136>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 137>
cacode cac Corrective Action Code
<byte 138>
utiny evnum Event Number
<byte 139>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 136>
ulong value Termination Code Value
endunion u Termination Code Union
{}
<byte 140>
utiny[2] reserved Reserved
<byte 142>
utiny lg_send_sts Last Gasp send status
<byte 143>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 144>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
endunion ru Termination Event Reporting Information
<byte 152>
{uei (Unexpected Event Information)}
<byte 152>
ulong type Unexpected event type
<byte 156>
ulong pto Post-Termination Operation Indicator
<byte 160>
ulong[5] param Unexpected event parameters
{}
{}
Event Information Packet Type: 3
EIP03 - Fault Manager Management Event
An event that affects Fault Manager operation occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
union ainfo Ancillary Information Union
<byte 72>
ulong events_not_reported Number of events not reported
<byte 76>
do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!)
or ainfo Ancillary Information Union
<byte 72>
ulong quiesce_type Quiesce type
<byte 76>
do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!)
or ainfo Ancillary Information Union
<byte 72>
{remote_event (Remote event header information)}
<byte 72>
union u Event Code Union
<byte 72>
{ec (Event Code)}
<byte 72>
utiny eiptype Event Information Packet Type Code
<byte 73>
cacode cac Corrective Action Code
<byte 74>
utiny evnum Event Number
<byte 75>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 72>
ulong value Event Code Value
endunion u Event Code Union
<byte 76>
utiny revision Packet revision number
<byte 77>
utiny type Packet type
<byte 78>
ushort count Number of bytes in packet
{}
endunion ainfo Ancillary Information Union
<byte 80>
union cinfo Control Block Information Union
<byte 80>
{scelcbi (Storage System Event Log Control Block Information)}
<byte 80>
ushort current_offset Current offset within event buffer
<byte 82>
{flags (Flags)}
<byte 82>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Sequence number reset occurred
tbits:1 wrapped All event data blocks in use
tbits:4 rsvd Pad to fill byte
{}
<byte 83>
utiny status Maintenance status
<byte 84>
ulong current_edbn Current event data block number
<byte 88>
ulong start_edbn Storage System State Logical Disk-Storage System Event Log starting event data block number
<byte 92>
ulong end_edbn Storage System State Logical Disk-Storage System Event Log ending event data block number
<byte 96>
ulong seq_reset_edbn Event data block number where sequence number reset occurred
<byte 100>
ulong event_count Number of events contained in Storage System State Logical Disk-Storage System Event Log
<byte 104>
ulong event_count_wraps Event count overflow
<byte 108>
ulong sequence_number Last event sequence number used
{}
<byte 112>
do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!)
or cinfo Control Block Information Union
<byte 80>
{sctelcbi (Storage System Termination Event Log Control Block Information)}
<byte 80>
ushort reserved Reserved for future use
<byte 82>
{flags (Flags)}
<byte 82>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 bctrlr_wrapped All termination event data blocks in use for "B" HSV210 controller
tbits:1 bctrlr_valid "B" HSV210 controller's Storage System State Logical Disk-Storage System Termination Event Log information is valid
tbits:1 actrlr_wrapped All termination event data blocks in use for "A" HSV210 controller
tbits:1 actrlr_valid "A" HSV210 controller's Storage System State Logical Disk-Storage System Termination Event Log information is valid
tbits:2 rsvd Pad to fill byte
{}
<byte 83>
utiny status Maintenance status
<byte 84>
uuid actrlr_id "A" HSV210 controller's UUID
<byte 100>
ulong actrlr_mru_edbn "A" HSV210 controller's Storage System State Logical Disk-Storage System Termination Event Log most recently used event data block number
<byte 104>
uuid bctrlr_id "B" HSV210 controller's UUID
<byte 120>
ulong bctrlr_mru_edbn "B" HSV210 controller's Storage System State Logical Disk-Storage System Termination Event Log most recently used event data block number
{}
or cinfo Control Block Information Union
<byte 80>
{stats30 (Last 30 seconds activity summary)}
<byte 80>
{host (Host Activity,)}
<byte 80>
ulong rps Requests Per Second,
<byte 84>
ulong kbs KB/Second.
{}
<byte 88>
{mirror (Mirror Activity,)}
<byte 88>
ulong rps Requests Per Second,
<byte 92>
ulong kbs KB/Second.
{}
<byte 96>
{backend (Backend Activity,)}
<byte 96>
ulong rps Requests Per Second,
<byte 100>
ulong kbs KB/Second.
{}
<byte 104>
{total (Total Activity,)}
<byte 104>
ulong rps Requests Per Second,
<byte 108>
ulong kbs KB/Second.
{}
<byte 112>
{background (Background Activity.)}
<byte 112>
ulong rps Requests Per Second,
<byte 116>
ulong kbs KB/Second.
{}
{}
<byte 120>
do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!)
or cinfo Control Block Information Union
<byte 80>
{mealcbi (Manufacturing Event Analysis Log Control Block information)}
<byte 80>
ushort current_offset Current offset within event buffer
<byte 82>
{flags (Flags)}
<byte 82>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Sequence number reset occurred
tbits:1 wrapped All event data blocks in use
tbits:4 rsvd Pad to fill byte
{}
<byte 83>
utiny status Maintenance status
<byte 84>
ulong current_edbn Current event data block number
<byte 88>
ulong start_edbn Manufacturing Event Analysis Log starting event data block number
<byte 92>
ulong end_edbn Manufacturing Event Analysis Log ending event data block number
<byte 96>
ulong seq_reset_edbn Event data block number where sequence number reset occurred
<byte 100>
ulong event_count Number of events contained in Manufacturing Event Analysis Log
<byte 104>
ulong event_count_wraps Event count overflow
<byte 108>
ulong sequence_number Last event sequence number used
{}
<byte 112>
do_not_display[12] union_pad Union Element Padding (DO NOT DISPLAY!)
endunion cinfo Control Block Information Union
<byte 124>
union minfo Maintenance Information Union
<byte 124>
{scelmi (Storage System Event Log Maintenance Information)}
<byte 124>
ulong index Loop index
<byte 128>
*ptr *utp Zero test buffer pointer
<byte 132>
ulong current_eventp Pointer to the current event
<byte 136>
ulong current_edbn Current event data block number
<byte 140>
ulong current_seqn Current sequence number
<byte 144>
ushort previous_offset Previous event buffer offset
<byte 146>
ushort current_offset Current event buffer offset
<byte 148>
ulong previous_edbn Previous event data block number
<byte 152>
ulong previous_seqn Previous sequence number
<byte 156>
ulong end_found End of Storage System State Logical Disk-Storage System Event Log found flag
<byte 160>
ulong accept_new_to_old New to old transition acceptable flag
<byte 164>
ulong unequal_found Sequence number not as expected flag
<byte 168>
ulong iostatus I/O status
{}
or minfo Maintenance Information Union
<byte 124>
{sctelmi (Storage System Termination Event Log Maintenance Information)}
<byte 124>
ulong index Loop index
<byte 128>
ulong current_edbn Current event data block number
<byte 132>
ulong end_edbn End event data block number
<byte 136>
ulong actrlr If "A" HSV210 controller, TRUE
<byte 140>
ulong iostatus I/O status
<byte 144>
ulong hold_offset Hold buffer current offset
{}
<byte 148>
do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!)
or minfo Maintenance Information Union
<byte 124>
{lerinfo (Last Event Reported Information)}
<byte 124>
ulong reporting_interval Last event reporting interval
<byte 128>
ulong sequence_number Sequence number assigned to the event
<byte 132>
scmitim report_time Time event was reported
<byte 140>
{header (Event Header)}
<byte 140>
union u Event Code Union
<byte 140>
{ec (Event Code)}
<byte 140>
utiny eiptype Event Information Packet Type Code
<byte 141>
cacode cac Corrective Action Code
<byte 142>
utiny evnum Event Number
<byte 143>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 140>
ulong value Event Code Value
endunion u Event Code Union
<byte 144>
utiny revision Packet revision number
<byte 145>
utiny type Packet type
<byte 146>
ushort count Number of bytes in packet
{}
{}
<byte 148>
do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!)
or minfo Maintenance Information Union
<byte 124>
{mealmi (Manufacturing Event Analysis Log Maintenance Information)}
<byte 124>
ulong index Loop index
<byte 128>
*ptr *utp Zero test buffer pointer
<byte 132>
ulong current_eventp Pointer to the current event
<byte 136>
ulong current_edbn Current event data block number
<byte 140>
ulong current_seqn Current sequence number
<byte 144>
ushort previous_offset Previous event buffer offset
<byte 146>
ushort current_offset Current event buffer offset
<byte 148>
ulong previous_edbn Previous event data block number
<byte 152>
ulong previous_seqn Previous sequence number
<byte 156>
ulong end_found End of Manufacturing Event Analysis Log found flag
<byte 160>
ulong accept_new_to_old New to old transition acceptable flag
<byte 164>
ulong unequal_found Sequence number not as expected flag
<byte 168>
ulong first_seqn First sequence number
{}
endunion minfo Maintenance Information Union
{}
Event Information Packet Type: 4
EIP04 - Fibre Channel Services Physical Disk Drive Error
An error was encountered while accessing a physical disk drive.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag device UUID of physical disk drive associated with the event
<byte 88>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port
<byte 96>
ulong al_pa AL_PA of the physical disk drive or mirror port
<byte 100>
ushort dencl_num Enclosure where the physical disk drive is located
<byte 102>
ushort port HSV210 controller internal Fibre Channel port number attached to the physical disk drive or mirror port
<byte 104>
ushort rack_num Rack where physical disk drive is located
<byte 106>
ushort bay Enclosure bay where the physical disk drive is located
<byte 108>
char[16] pid Physical disk drive product identification string
<byte 124>
char[4] rev Current firmware level of physical disk drive
<byte 128>
{enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 128>
utiny rack_num Rack were enclosure is located
<byte 129>
utiny dencl_num Enclosure number
{}
<byte 130>
{enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 130>
utiny rack_num Rack were enclosure is located
<byte 131>
utiny dencl_num Enclosure number
{}
<byte 132>
{enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 132>
utiny rack_num Rack were enclosure is located
<byte 133>
utiny dencl_num Enclosure number
{}
<byte 134>
{enclosures[2] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 134>
utiny rack_num Rack were enclosure is located
<byte 135>
utiny dencl_num Enclosure number
{}
<byte 136>
{enclosures[5] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 136>
utiny rack_num Rack were enclosure is located
<byte 137>
utiny dencl_num Enclosure number
{}
<byte 138>
{enclosures[4] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 138>
utiny rack_num Rack were enclosure is located
<byte 139>
utiny dencl_num Enclosure number
{}
<byte 140>
{enclosures[7] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 140>
utiny rack_num Rack were enclosure is located
<byte 141>
utiny dencl_num Enclosure number
{}
<byte 142>
{enclosures[6] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 142>
utiny rack_num Rack were enclosure is located
<byte 143>
utiny dencl_num Enclosure number
{}
<byte 144>
{enclosures[9] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 144>
utiny rack_num Rack were enclosure is located
<byte 145>
utiny dencl_num Enclosure number
{}
<byte 146>
{enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 146>
utiny rack_num Rack were enclosure is located
<byte 147>
utiny dencl_num Enclosure number
{}
<byte 148>
ulong bypass_reason Reason the physical disk drive at this location has been bypassed
<byte 152>
char[4] new_rev Latest known firmware level of physical disk drive
<byte 156>
ushort bypassb Mask showing bypass state for each slot in a shelf
<byte 158>
ushort bypassa Mask showing bypass state for each slot in a shelf
{}
Event Information Packet Type: 5
EIP05 - Storage System Management Interface Entity State Change
The state of a Storage System Management Interface entity has changed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{event_type (Entity and Event type)}
<byte 72>
ushort scmi_object_type Entity type
<byte 74>
ushort scmi_object_event_type Event Information Packet type
{}
<byte 76>
{value (New entity state)}
<byte 76>
ulong ul1 Additional information longword 1
<byte 80>
ulong ul2 Additional information longword 2
{}
<byte 84>
scmi_obj_hnd handle Storage System Management Interface Handle of affected entity
<byte 104>
ulong secondary_id Alternate entity identification
<byte 108>
{attribute (Entity attributes)}
<byte 108>
ulong type Datatype used
<byte 112>
union value SCMI Attribute Union
<byte 112>
ushort[12] u16 As 16 bit words,
or value SCMI Attribute Union
<byte 112>
ulong[6] u32 As 32 bit words,
or value SCMI Attribute Union
<byte 112>
double_word[3] u64 As 64 bit words,
or value SCMI Attribute Union
<byte 112>
{obj (As typed Storage System Management Interface object handle,)}
<byte 112>
ulong value
<byte 116>
scmi_obj_hnd handle
{}
or value SCMI Attribute Union
<byte 112>
char[24] str As character string
endunion value SCMI Attribute Union
{}
<byte 136>
scmi_obj_hnd add_handle Additional entity identification (Storage System Management Interface Handle)
<byte 156>
ulong[6] add_data Additional Data
{}
Event Information Packet Type: 7
EIP07 - Fibre Channel Services Fibre Channel Port Link Error
Excessive link errors were detected on a Fibre Channel port.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port
<byte 80>
ushort reserved Reserved
<byte 82>
ushort port HSV210 controller internal Fibre Channel port number
<byte 84>
ulong loss_of_signal Number of times a loss of signal was detected
<byte 88>
ulong bad_rx_char Bad received character count
<byte 92>
ulong loss_of_sync Loss of synchronization count
<byte 96>
ulong link_fail Link failure count
<byte 100>
ulong rx_eofa The number of frames that have been received with an EOFa delimiter
<byte 104>
ulong dis_frm The number of frames that have been received and then discarded
<byte 108>
ulong bad_crc The number of frames that have been received with a Bad_CRC and a valid EOF
<byte 112>
ulong proto_err The number of N_Port protocol errors detected
<byte 116>
ulong exp_frm The number of outbound frames that have expired and therefore were discarded.
{}
Event Information Packet Type: 8
EIP08 - Fibre Channel Services Fibre Channel Port Link Failure
A Fibre Channel port link has failed or a Drive Enclosure Environmental Monitoring Unit task has failed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port
<byte 80>
char[8] other_cerp_id HSV210 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port
<byte 88>
{peb[0] (Fibre Channel port Event Blocks)}
<byte 88>
ulong type Error type code
<byte 92>
ulong context Error context
{}
<byte 96>
{peb[1] (Fibre Channel port Event Blocks)}
<byte 96>
ulong type Error type code
<byte 100>
ulong context Error context
{}
<byte 104>
{peb[2] (Fibre Channel port Event Blocks)}
<byte 104>
ulong type Error type code
<byte 108>
ulong context Error context
{}
<byte 112>
{peb[3] (Fibre Channel port Event Blocks)}
<byte 112>
ulong type Error type code
<byte 116>
ulong context Error context
{}
<byte 120>
{peb[4] (Fibre Channel port Event Blocks)}
<byte 120>
ulong type Error type code
<byte 124>
ulong context Error context
{}
<byte 128>
{peb[5] (Fibre Channel port Event Blocks)}
<byte 128>
ulong type Error type code
<byte 132>
ulong context Error context
{}
<byte 136>
{peb[6] (Fibre Channel port Event Blocks)}
<byte 136>
ulong type Error type code
<byte 140>
ulong context Error context
{}
<byte 144>
{peb[7] (Fibre Channel port Event Blocks)}
<byte 144>
ulong type Error type code
<byte 148>
ulong context Error context
{}
<byte 152>
ushort peq_prod_index Producer index
<byte 154>
ushort peq_frz_prod_index Error idle or freeze producer index
<byte 156>
ushort failure_cause Code indicating path to link failure
<byte 158>
ushort peq_cons_index Consumer index
<byte 160>
utiny reserved1 Reserved
<byte 161>
utiny time Used to represent a retry time or other time based element in the event.
<byte 162>
utiny other_port HSV210 controller internal Fibre Channel port number
<byte 163>
utiny port HSV210 controller internal Fibre Channel port number
<byte 164>
{recovery (Loop Recovery Operations)}
<byte 164>
ulong progress EWE Step for recovery process
<byte 168>
ulong shelf Physical Shelf being evaluated.
<byte 172>
ulong slot Physical Slot being evaluated.
<byte 176>
ulong cab Cabinet rack being evaluated.
{}
{}
Event Information Packet Type: 9
EIP09 - Fibre Channel Services Physical Disk Drive/Mirror Port Error
An error was encountered while attempting to access a physical disk drive or the mirror port.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag device UUID of physical disk drive associated with the event
<byte 88>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port
<byte 96>
ushort exch_type Frame exchange type
<byte 98>
ushort port HSV210 controller internal Fibre Channel port number attached to the physical disk drive or mirror port
<byte 100>
ulong al_pa AL_PA of the physical disk drive or mirror port
<byte 104>
ushort dencl_num Enclosure where the physical disk drive is located
<byte 106>
ushort reserved Reserved
<byte 108>
ushort rack_num Rack where physical disk drive is located
<byte 110>
ushort bay Enclosure bay where the physical disk drive is located
<byte 112>
ulong fed_class Fibre Channel Exchange Descriptor class
<byte 116>
union cmd Command Descriptor Block issued
<byte 116>
utiny[16] bytes CDB as bytes
or cmd Command Descriptor Block issued
<byte 116>
ulong[4] lw CDB as longwords
or cmd Command Descriptor Block issued
<byte 116>
{cdb6 (6 Byte CDB by field)}
<byte 116>
utiny opcode Offset 0 -- Operation Code
<byte 117>
tbits:5 lba0 Offset 1, Bits 0-4 -- Logical Block Address[0]
tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused)
<byte 118>
utiny lba1 Offset 2 -- Logical Block Address[1]
<byte 119>
utiny lba2 Offset 3 -- Logical Block Address[2]
<byte 120>
utiny length Offset 4 -- Length
<byte 121>
utiny control Offset 5 -- Control
<byte 122>
ushort padding Offsets 6-7 -- Pad to longword align
{}
<byte 124>
do_not_display[8] union_pad Union Element Padding (DO NOT DISPLAY!)
or cmd Command Descriptor Block issued
<byte 116>
{cdb10 (10 Byte CDB by field)}
<byte 116>
utiny opcode Offset 0 -- Operation Code
<byte 117>
tbits:5 reserved Offset 1, Bits 0-4 -- Reserved
tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused)
<byte 118>
utiny lba0 Offset 2 -- Logical Block Address[0]
<byte 119>
utiny lba1 Offset 3 -- Logical Block Address[1]
<byte 120>
utiny lba2 Offset 4 -- Logical Block Address[2]
<byte 121>
utiny lba3 Offset 5 -- Logical Block Address[3]
<byte 122>
utiny reserved6 Offset 6 -- Reserved
<byte 123>
utiny length0 Offset 7 -- Length[0]
<byte 124>
utiny length1 Offset 8 -- Length[1]
<byte 125>
utiny control Offset 9 -- Control
<byte 126>
ushort padding Offsets 10-11 -- Pad to longword align
{}
<byte 128>
do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!)
or cmd Command Descriptor Block issued
<byte 116>
{cdb12 (12 Byte CDB by field)}
<byte 116>
utiny opcode Offset 0 -- Operation Code
<byte 117>
tbits:5 reserved Offset 1, Bits 0-4 -- Reserved
tbits:3 lun Offset 1, Bits 5-7 -- Logical Unit Number (obsolete method -- unused)
<byte 118>
utiny lba0 Offset 2 -- Logical Block Address[0]
<byte 119>
utiny lba1 Offset 3 -- Logical Block Address[1]
<byte 120>
utiny lba2 Offset 4 -- Logical Block Address[2]
<byte 121>
utiny lba3 Offset 5 -- Logical Block Address[3]
<byte 122>
utiny length0 Offset 6 -- Length[0]
<byte 123>
utiny length1 Offset 7 -- Length[1]
<byte 124>
utiny length2 Offset 8 -- Length[2]
<byte 125>
utiny length3 Offset 9 -- Length[3]
<byte 126>
utiny reserved10 Offset 10 -- Reserved
<byte 127>
utiny control Offset 11 -- Control
{}
<byte 128>
do_not_display[4] union_pad Union Element Padding (DO NOT DISPLAY!)
or cmd Command Descriptor Block issued
<byte 116>
{cdb16 (16 Byte CDB by field)}
<byte 116>
utiny opcode Offset 0 -- Operation Code
<byte 117>
utiny parameter Offset 1 -- Command specific parameters
<byte 118>
utiny lba0 Offset 2 -- Logical Block Address[0]
<byte 119>
utiny lba1 Offset 3 -- Logical Block Address[1]
<byte 120>
utiny lba2 Offset 4 -- Logical Block Address[2]
<byte 121>
utiny lba3 Offset 5 -- Logical Block Address[3]
<byte 122>
utiny lba4 Offset 6 -- Logical Block Address[4] or Operation Length[0]
<byte 123>
utiny lba5 Offset 7 -- Logical Block Address[5] or Operation Length[1]
<byte 124>
utiny lba6 Offset 8 -- Logical Block Address[6] or Operation Length[2]
<byte 125>
utiny lba7 Offset 9 -- Logical Block Address[7] or Operation Length[3]
<byte 126>
utiny length0 Offset 10 -- Length[0]
<byte 127>
utiny length1 Offset 11 -- Length[1]
<byte 128>
utiny length2 Offset 12 -- Length[2]
<byte 129>
utiny length3 Offset 13 -- Length[3]
<byte 130>
utiny reserved Offsets 14 -- Reserved
<byte 131>
utiny control Offset 15 -- Control
{}
endunion cmd Command Descriptor Block issued
<byte 132>
union error Sense data reported by the physical disk drive
<byte 132>
utiny[20] bytes Sense data as bytes
or error Sense data reported by the physical disk drive
<byte 132>
ulong[5] lw Sense data as longwords
or error Sense data reported by the physical disk drive
<byte 132>
{sense_data (Sense data by field)}
<byte 132>
tbits:7 error_code Offset 0, Bits 0-6 -- Error Code
tbits:1 valid Offset 0, Bit 7 -- Valid
<byte 133>
utiny segment Offset 1 -- Segment
<byte 134>
tbits:4 sense_key Offset 2, Bits 0-3 -- Sense Key
tbits:1 reserved_1 Offset 2, Bit 4 -- Reserved
tbits:1 ili Offset 2, Bit 5 -- Incorrect Length Indicator
tbits:1 eom Offset 2, Bit 6 -- End of Medium
tbits:1 filemark Offset 2, Bit 7 -- Filemark
<byte 135>
utiny info_0 Offset 3 -- Information[0]
<byte 136>
utiny info_1 Offset 4 -- Information[1]
<byte 137>
utiny info_2 Offset 5 -- Information[2]
<byte 138>
utiny info_3 Offset 6 -- Information[3]
<byte 139>
utiny add_length Offset 7 -- Additional Sense Length
<byte 140>
utiny[4] cmd_specific Offsets 8-11 -- Command Specific Information
<byte 144>
union asc_ascq ASC/ASCQ Union
<byte 144>
{asc_ascqb (Offsets 12-13 -- Additional Sense Code (ASC)/Additional Sense Code Qualifier (ASCQ))}
<byte 144>
utiny asc Offset 12 -- ASC
<byte 145>
utiny asq Offset 13 -- ASCQ
{}
or asc_ascq ASC/ASCQ Union
<byte 144>
ushort asc_ascqw Offsets 12-13 -- Combined ASC/ASCQ
endunion asc_ascq ASC/ASCQ Union
<byte 146>
utiny fru_code Offset 14 -- Field Replaceable Unit Code
<byte 147>
tbits:7 sks_0 Offset 15, Bits 0-6 -- Sense Key Specific[0]
tbits:1 sksv Offset 15, Bit 7 -- Sense Key Specific Valid
<byte 148>
utiny[2] sks Offsets 16-17 -- Sense Key Specific[1-2]
<byte 150>
ushort padding Offsets 18-19 -- Pad to longword align
{}
endunion error Sense data reported by the physical disk drive
<byte 152>
{enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 152>
utiny rack_num Rack were enclosure is located
<byte 153>
utiny dencl_num Enclosure number
{}
<byte 154>
{enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 154>
utiny rack_num Rack were enclosure is located
<byte 155>
utiny dencl_num Enclosure number
{}
<byte 156>
{enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 156>
utiny rack_num Rack were enclosure is located
<byte 157>
utiny dencl_num Enclosure number
{}
<byte 158>
{enclosures[2] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 158>
utiny rack_num Rack were enclosure is located
<byte 159>
utiny dencl_num Enclosure number
{}
<byte 160>
{enclosures[5] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 160>
utiny rack_num Rack were enclosure is located
<byte 161>
utiny dencl_num Enclosure number
{}
<byte 162>
{enclosures[4] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 162>
utiny rack_num Rack were enclosure is located
<byte 163>
utiny dencl_num Enclosure number
{}
<byte 164>
{enclosures[7] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 164>
utiny rack_num Rack were enclosure is located
<byte 165>
utiny dencl_num Enclosure number
{}
<byte 166>
{enclosures[6] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 166>
utiny rack_num Rack were enclosure is located
<byte 167>
utiny dencl_num Enclosure number
{}
<byte 168>
{enclosures[9] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 168>
utiny rack_num Rack were enclosure is located
<byte 169>
utiny dencl_num Enclosure number
{}
<byte 170>
{enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 170>
utiny rack_num Rack were enclosure is located
<byte 171>
utiny dencl_num Enclosure number
{}
<byte 172>
ushort bypassb Mask showing bypass state for each slot in a shelf
<byte 174>
ushort bypassa Mask showing bypass state for each slot in a shelf
{}
Event Information Packet Type: a
EIP0A - Storage System State Services State Change
A Storage System state change occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{node_name (World Wide Name of HSV210 controller)}
<byte 72>
ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type
<byte 76>
ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port
{}
<byte 80>
tag scell_tag UUID of Storage System
<byte 96>
ulong dimm_size Size of this HSV210 controller's DIMM in megabytes
<byte 100>
ulong debug_flags DebugFlags of HSV210 controller
<byte 104>
ulong print_flags PrintFlags of HSV210 controller
{}
Event Information Packet Type: b
EIP0B - Storage System State Services Physical Disk Drive State Change
A physical disk drive state change occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
uuid device UUID of physical disk drive
<byte 88>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port attached to the physical disk drive
<byte 96>
ushort reason_code Code identifying cause of the physical disk drive being marked inoperative or why event is being reported
<byte 98>
ushort port HSV210 controller internal Fibre Channel port number attached to the physical disk drive or mirror port
<byte 100>
ushort dencl_num Enclosure where the physical disk drive is located
<byte 102>
{rss_flags (Redundant Storage Set member state flags)}
<byte 102>
tbits:1 member_migrating Migrating
tbits:1 member_missing Missing or never existed
tbits:1 member_abnormal Abnormal
tbits:5 reserved Reserved for future use
{}
<byte 103>
{flags (Information validity flags)}
<byte 103>
tbits:1 inq_state SCSI INQUIRY data is valid
tbits:1 quorum_disk Is Storage System quorum disk
tbits:6 reserved Reserved for future use
{}
<byte 104>
ushort rack_num Rack where the physical disk drive is located
<byte 106>
ushort bay Enclosure bay where the physical disk drive is located
<byte 108>
{inq_data (Last SCSI INQUIRY data read during discovery (Note: The inquiry data is truncated after the Version Descriptor 1 field.))}
<byte 108>
tbits:5 per_dev_typ Peripheral Device-type
tbits:3 per_qual Peripheral Qualifier
<byte 109>
tbits:7 reserved_1 Reserved
tbits:1 rmb Removable Medium bit
<byte 110>
tbits:8 version Version
<byte 111>
tbits:4 response_data Response data format ( 1 = SCSI-1, 2 = SCSI-2, 3 = SCSI-3)
tbits:1 hisup Hierarchical Support bit
tbits:1 normaca Normal ACA bit
tbits:1 obsolete Obsolete
tbits:1 aerc Asynchronous Event Reporting Capability bit
<byte 112>
utiny add_length Additional Length
<byte 113>
tbits:7 reserved_3 Reserved
tbits:1 sccs SCC Supported bit
<byte 114>
tbits:1 addr16 Address 16 bit
tbits:2 obsolete_1 Reserved
tbits:1 mchngr Medium Changer bit
tbits:1 multip Multiport bit
tbits:1 vs_1 Vendor Specific
tbits:1 encserv Enclosure Services bit
tbits:1 bque Basic Queuing bit
<byte 115>
tbits:1 vs Vendor Specific
tbits:1 cmdque Command Queuing bit
tbits:1 reserved_2 Reserved
tbits:1 linked Linked Command bit
tbits:1 sync Synchronous Transfer bit
tbits:1 wbus16 Wide Bus 16 bit
tbits:1 wbus32 Wide Bus 32 bit
tbits:1 reladr Relative Addressing bit
<byte 116>
char[8] vendor_id Vendor Identification
<byte 124>
char[16] product_id Product Identification
<byte 140>
char[4] product_rev Product Revision Level
<byte 144>
ulong[5] vendor_36_55 Vendor-specific
<byte 164>
ushort reserved_56_57 Reserved
<byte 166>
ushort vd1 Version Descriptor 1
{}
<byte 168>
ulong quorum_sequence Quorum Space Write Sequence (i.e., quorum disk 1, 2, or 3)
<byte 172>
ulong capacity LUN capacity (blocks)
<byte 176>
ulong member_state Redundant Storage Set member state
<byte 180>
uuid second_device UUID of other physical disk drive
<byte 196>
ulong second_fnb_ptr Address of fnb for other physical disk drive
<byte 200>
ushort volnoid Volume of other physical disk drive
<byte 202>
ushort poid NOID of other physical disk drive
{}
Event Information Packet Type: c
EIP0C - Data Replication Manager State Change
A Data Replication Manager state change occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag group_name_uuid Group Name UUID
<byte 88>
tag peer_scell_uuid Peer Storage System UUID
<byte 104>
tag group_uuid Data Replication Group UUID
<byte 120>
tag source_scvd_uuid Source Storage System Virtual Disk UUID
<byte 136>
tag dest_scvd_uuid If eip0c.flags.remote_adapter_wwn is set equal to 1, this field contains the WWN of the remote adapter. Otherwise, this field contains the Destination Storage System Virtual Disk UUID.
<byte 152>
ushort blocks Number of blocks in error
<byte 154>
ushort status Error status value
<byte 156>
ulong vda Virtual Disk Address in error
<byte 160>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port
<byte 168>
utiny reserved Reserved for future use
<byte 169>
{flags (Field use flags)}
<byte 169>
tbits:7 reserved Reserved for future use
tbits:1 remote_adapter_wwn dest_scvd_uuid contains remote adapter WWN
{}
<byte 170>
utiny side Remote HSV210 controller used by Data Replication Manager tunnel: 0 => A; 1 => B
<byte 171>
utiny port HSV210 controller internal Fibre Channel port number
<byte 172>
ulong[2] reserved1 Reserved for future use
{}
Event Information Packet Type: d
EIP0D - Executive Services System Time Change
A change in system time occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
utiny[3] unused Unused
<byte 75>
utiny action Action code
<byte 76>
ulong[2] reserved Reserved
<byte 84>
scmitim ctime Current time value
<byte 92>
scmitim ptime Previous time value
{}
Event Information Packet Type: e
EIP0E - Storage System Management Interface Entity Creation or Deletion
A Storage System Management Interface entity was created or deleted.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{event_type (Entity and Event type)}
<byte 72>
ushort scmi_object_type Entity type
<byte 74>
ushort scmi_object_event_type Event Information Packet type
{}
<byte 76>
scmi_obj_hnd handle Storage System Management Interface Handle of affected entity
<byte 96>
scmi_obj_hnd add_handle Additional entity identification (Storage System Management Interface Handle)
<byte 116>
{attribute (Entity attributes)}
<byte 116>
ulong type Datatype used
<byte 120>
union value SCMI Attribute Union
<byte 120>
ushort[12] u16 As 16 bit words,
or value SCMI Attribute Union
<byte 120>
ulong[6] u32 As 32 bit words,
or value SCMI Attribute Union
<byte 120>
double_word[3] u64 As 64 bit words,
or value SCMI Attribute Union
<byte 120>
{obj (As typed Storage System Management Interface object handle,)}
<byte 120>
ulong value
<byte 124>
scmi_obj_hnd handle
{}
or value SCMI Attribute Union
<byte 120>
char[24] str As character string
endunion value SCMI Attribute Union
{}
<byte 144>
scmi_obj_hnd add_handle2 Additional SCMI object handle (2)
<byte 164>
ulong[4] add_data Additional Data
{}
Event Information Packet Type: f
EIP0F - Storage System Management Interface Entity Attribute Change
An attribute of a Storage System Management Interface entity has changed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{event_type (Entity and Event type)}
<byte 72>
ushort scmi_object_type Entity type
<byte 74>
ushort scmi_object_event_type Event Information Packet type
{}
<byte 76>
union secondary_id Secondary identification
<byte 76>
ulong Id Alternate entity identification
or secondary_id Secondary identification
<byte 76>
{rss_data (Redundant Storage Set information)}
<byte 76>
ushort Id Redundant Storage Set identification
<byte 78>
ushort Index Redundant Storage Set index
{}
endunion secondary_id Secondary identification
<byte 80>
{old_attr (Old attribute information)}
<byte 80>
ulong type Datatype used
<byte 84>
union value SCMI Attribute Union
<byte 84>
ushort[12] u16 As 16 bit words,
or value SCMI Attribute Union
<byte 84>
ulong[6] u32 As 32 bit words,
or value SCMI Attribute Union
<byte 84>
double_word[3] u64 As 64 bit words,
or value SCMI Attribute Union
<byte 84>
{obj (As typed Storage System Management Interface object handle,)}
<byte 84>
ulong value
<byte 88>
scmi_obj_hnd handle
{}
or value SCMI Attribute Union
<byte 84>
char[24] str As character string
endunion value SCMI Attribute Union
{}
<byte 108>
{new_attr (New attribute information)}
<byte 108>
ulong type Datatype used
<byte 112>
union value SCMI Attribute Union
<byte 112>
ushort[12] u16 As 16 bit words,
or value SCMI Attribute Union
<byte 112>
ulong[6] u32 As 32 bit words,
or value SCMI Attribute Union
<byte 112>
double_word[3] u64 As 64 bit words,
or value SCMI Attribute Union
<byte 112>
{obj (As typed Storage System Management Interface object handle,)}
<byte 112>
ulong value
<byte 116>
scmi_obj_hnd handle
{}
or value SCMI Attribute Union
<byte 112>
char[24] str As character string
endunion value SCMI Attribute Union
{}
<byte 136>
scmi_obj_hnd handle Storage System Management Interface Handle of affected entity
<byte 156>
scmi_obj_hnd add_handle Additional entity identification (Storage System Management Interface
<byte 176>
ulong reserved reserved for future use
{}
Event Information Packet Type: 10
EIP10 - System Services HSV210 Controller State Change
A controller state change occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{node_name (World Wide Name of HSV210 controller)}
<byte 72>
ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type
<byte 76>
ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port
{}
<byte 80>
{information (State change information)}
<byte 80>
ulong pc Program counter
<byte 84>
ulong flags Flags
<byte 88>
ulong code Code
{}
{}
Event Information Packet Type: 11
EIP11 - Disk Enclosure Environmental Monitoring Unit Services Status Change.
Status of a disk enclosure element has changed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{event_type (Entity and Event type)}
<byte 72>
ushort scmi_object_type Entity type
<byte 74>
ushort scmi_object_event_type Event Information Packet type
{}
<byte 76>
scmi_obj_hnd handle Storage System Management Interface Handle of affected disk enclosure
<byte 96>
ulong rack_num Rack number
<byte 100>
ulong dencl_num Disk enclosure number
<byte 104>
union alarm_error_code Alarm code
<byte 104>
ulong value As longword
or alarm_error_code Alarm code
<byte 104>
{field (By field)}
<byte 104>
utiny reserved Reserved for future use
<byte 105>
utiny ec Error code
<byte 106>
utiny en Element number
<byte 107>
utiny et Element type code
{}
endunion alarm_error_code Alarm code
<byte 108>
utiny[3] rsvd1 Reserved for future use
<byte 111>
utiny loop Loop number
<byte 112>
{enclosures[1] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 112>
utiny rack_num Rack were enclosure is located
<byte 113>
utiny dencl_num Enclosure number
{}
<byte 114>
{enclosures[0] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 114>
utiny rack_num Rack were enclosure is located
<byte 115>
utiny dencl_num Enclosure number
{}
<byte 116>
{enclosures[3] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 116>
utiny rack_num Rack were enclosure is located
<byte 117>
utiny dencl_num Enclosure number
{}
<byte 118>
{enclosures[2] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 118>
utiny rack_num Rack were enclosure is located
<byte 119>
utiny dencl_num Enclosure number
{}
<byte 120>
{enclosures[5] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 120>
utiny rack_num Rack were enclosure is located
<byte 121>
utiny dencl_num Enclosure number
{}
<byte 122>
{enclosures[4] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 122>
utiny rack_num Rack were enclosure is located
<byte 123>
utiny dencl_num Enclosure number
{}
<byte 124>
{enclosures[7] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 124>
utiny rack_num Rack were enclosure is located
<byte 125>
utiny dencl_num Enclosure number
{}
<byte 126>
{enclosures[6] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 126>
utiny rack_num Rack were enclosure is located
<byte 127>
utiny dencl_num Enclosure number
{}
<byte 128>
{enclosures[9] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 128>
utiny rack_num Rack were enclosure is located
<byte 129>
utiny dencl_num Enclosure number
{}
<byte 130>
{enclosures[8] (Enclosure available on the Fibre Channel loop pair identified in the loop field)}
<byte 130>
utiny rack_num Rack were enclosure is located
<byte 131>
utiny dencl_num Enclosure number
{}
<byte 132>
ulong[12] rsvd Reserved for future use
{}
Event Information Packet Type: 12
EIP12 - Fibre Channel Services Physical Disk Drive/Mirror Port Unexpected Work Encountered
Unexpected work was received from a physical disk drive or the mirror port.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag device UUID of the physical disk drive or HSV210 controller associated with the event
<byte 88>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port
<byte 96>
ulong al_pa AL_PA of the physical disk drive or the mirror port
<byte 100>
ushort dencl_num Enclosure where the physical disk drive is located
<byte 102>
ushort port HSV210 controller internal Fibre Channel port number attached to the physical disk drive or mirror port
<byte 104>
ushort rack_num Rack where the physical disk drive is located
<byte 106>
ushort bay Enclosure bay where the physical disk drive is located
<byte 108>
ulong[14] hdr_cdb Command Descriptor Block issued and Fibre Channel Header
<byte 164>
ushort bypassb Mask showing bypass state for each slot in a shelf
<byte 166>
ushort bypassa Mask showing bypass state for each slot in a shelf
{}
Event Information Packet Type: 13
EIP13 - Fibre Channel Services Physical Disk Drive/Mirror Port/Drive Enclosure Environmental Monitoring Unit Error summary.
Summary of errors encountered while attempting to access a physical disk drive, the mirror port, or a Drive Enclosure Environmental Monitoring Unit.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag device UUID of the physical disk drive, HSV210 controller, or Drive Enclosure Environmental Monitoring Unit associated with the event
<byte 88>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port attached to the physical disk drive or mirror port
<byte 96>
ulong al_pa AL_PA of the physical disk drive or the mirror port
<byte 100>
ushort dencl_num Enclosure where the physical disk drive is located
<byte 102>
ushort port HSV210 controller internal Fibre Channel port number attached to the physical disk drive or mirror port
<byte 104>
ushort rack_num Rack where the physical disk drive is located
<byte 106>
ushort bay Enclosure bay where the physical disk drive is located
<byte 108>
ulong fed_class Fibre Channel Exchange Descriptor class
<byte 112>
ulong num_times Number of occurrences of the error.
<byte 116>
{enclosures[1] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 116>
utiny rack_num Rack were enclosure is located
<byte 117>
utiny dencl_num Enclosure number
{}
<byte 118>
{enclosures[0] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 118>
utiny rack_num Rack were enclosure is located
<byte 119>
utiny dencl_num Enclosure number
{}
<byte 120>
{enclosures[3] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 120>
utiny rack_num Rack were enclosure is located
<byte 121>
utiny dencl_num Enclosure number
{}
<byte 122>
{enclosures[2] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 122>
utiny rack_num Rack were enclosure is located
<byte 123>
utiny dencl_num Enclosure number
{}
<byte 124>
{enclosures[5] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 124>
utiny rack_num Rack were enclosure is located
<byte 125>
utiny dencl_num Enclosure number
{}
<byte 126>
{enclosures[4] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 126>
utiny rack_num Rack were enclosure is located
<byte 127>
utiny dencl_num Enclosure number
{}
<byte 128>
{enclosures[7] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 128>
utiny rack_num Rack were enclosure is located
<byte 129>
utiny dencl_num Enclosure number
{}
<byte 130>
{enclosures[6] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 130>
utiny rack_num Rack were enclosure is located
<byte 131>
utiny dencl_num Enclosure number
{}
<byte 132>
{enclosures[9] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 132>
utiny rack_num Rack were enclosure is located
<byte 133>
utiny dencl_num Enclosure number
{}
<byte 134>
{enclosures[8] (Enclosure available on the Fibre Channel port identified in the cerp_id and port fields)}
<byte 134>
utiny rack_num Rack were enclosure is located
<byte 135>
utiny dencl_num Enclosure number
{}
<byte 136>
char[8] missing_cerp_id HSV210 controller enclosure rear panel Fibre Channel port that cannot connect to physical disk drive or mirror port
<byte 144>
ushort bypassa Mask showing bypass state for each slot in a shelf
<byte 146>
ushort missing_port HSV210 controller internal Fibre Channel port number that cannont connect to the physical disk drive or mirror port
<byte 148>
ushort switch_type Used to represent the type of switch detected (SES or non-SES compliant)
<byte 150>
ushort bypassb Mask showing bypass state for each slot in a shelf
{}
Event Information Packet Type: 14
EIP14 - Diagnostic Operations Generator Detected Failure.
A failure was detected during the execution of a diagnostic.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{eep_error (Diagnostic error EEPROM data)}
<byte 72>
utiny padding Pad to longword align this structure
<byte 73>
utiny count Duplicate error count
<byte 74>
utiny test_num Test number
<byte 75>
utiny TE_num TE number
<byte 76>
ulong Z_code Z's code
<byte 80>
ulong error_code Error code
<byte 84>
ulong address Address of Error
<byte 88>
ulong expected Expected Data
<byte 92>
ulong actual Actual Data
<byte 96>
ulonglong uptime Uptime of error
{}
<byte 104>
ulong dimm_size Size of this HSV210 controller's DIMM in megabytes
{}
Event Information Packet Type: 15
EIP15 - Container Services Management Operation has started or completed.
An operation on a Disk Group has started or completed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag tag1 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event
<byte 88>
tag tag2 UUID of the Virtual Disk, physical disk drive, or Disk Group associated with the event
<byte 104>
ulong state Event-specific state value
<byte 108>
ulong status Event-specific operation status
{}
Event Information Packet Type: 16
EIP16 - Data Replication Manager Time Report.
An Data Replication Manager time synchronization event has occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
uuid sender Enterprise Virtual Array controller initiating time report message
<byte 88>
uuid receiver Peer controller receiving time report message
<byte 104>
uuid receiver_partner Other controller in sending or receiving Storage System
<byte 120>
scmitim sent_time Time message was sent
<byte 128>
scmitim received_time Time message was received
{}
Event Information Packet Type: 17
EIP17 - Fibre Channel Services Fibre Channel Port Loop Config
A new device map has been generated on a Fibre Channel port.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
char[8] cerp_id HSV210 controller enclosure rear panel Fibre Channel port
<byte 80>
ulong map_id Multi-page map identifier (all pages containing this identifier comprise this map)
<byte 84>
utiny entries Number of map entries (AL_PAs) in this map
<byte 85>
utiny total_pages Total pages containing portions of this map
<byte 86>
utiny page Page number of this loop map event
<byte 87>
utiny port HSV210 controller internal Fibre Channel port number
<byte 88>
utiny[92] loop_map Loop configuration information
{}
Event Information Packet Type: 18
EIP18 - Storage System State Services Redundant Storage Set State Change
A Redundant Storage Set state change occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag ldad_tag Tag of the Disk Group associated with the event
<byte 88>
ushort target_rss Migration target
<byte 90>
ushort source_rss Migration source
<byte 92>
ushort target_migr Migration flags for target
<byte 94>
ushort source_migr Migration flags for source
<byte 96>
utiny[16] smembers Volumes in source
<byte 112>
utiny[16] tmembers Volumes in target
{}
Event Information Packet Type: 19
EIP19 - System Data Center Services Status Change
Status of a System Data Center element has changed.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{event_type (Entity and Event type)}
<byte 72>
ushort scmi_object_type Entity type
<byte 74>
ushort scmi_object_event_type Event Information Packet type
{}
<byte 76>
scmi_obj_hnd handle Storage System Management Interface
<byte 96>
{state (State of SDC monitored component)}
<byte 96>
ulong old Previous State
<byte 100>
ulong cur Current State
{}
<byte 104>
{status_code (Status code of SDC monitored component)}
<byte 104>
ulong old Previous Status Code
<byte 108>
ulong cur Current Status Code
{}
<byte 112>
{status_data (Status data of SDC monitored component)}
<byte 112>
ulong old Previous Additional Status Data
<byte 116>
ulong cur Current Additional Status Data
{}
<byte 120>
ulong[4] comp_states States of SDC monitored components
<byte 136>
ulong[4] comp_status_codes Status codes of SDC monitored components
<byte 152>
ulong[4] comp_status_data Status data of SDC monitored components
{}
Event Information Packet Type: 1a
EIP1A - System Services Code Load Operation Update
A code load operation has occurred.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
char[40] state State information
<byte 112>
char[36] hardware Hardware information
<byte 148>
char[32] versions Version information
{}
Event Information Packet Type: 1b
EIP1B - Host Port Event
A Host Port Event Occurred
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag ld_tag Virtual Disk UUID
<byte 88>
tag scvd_tag Associated Storage System Virtual Disk UUID
{}
Event Information Packet Type: 1c
EIP1C - Fault Manager Termination Event
HSV210 controller operation terminated event report.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{lteihd (Last Termination Event Information Header)}
<byte 72>
{flags (Last Termination Event flags)}
<byte 72>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 rsvd Pad to fill byte
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 73>
utiny revision Structure revision number
<byte 74>
ushort size Structure size
{}
<byte 76>
{lter (Last Termination Event Report Block)}
<byte 76>
ulong seq Sequence number assigned to the termination event
<byte 80>
char[4] sw_version HSV210 controller software version number string
<byte 84>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 96>
char[8] ctrlr_model_id HSV210 controller model string
<byte 104>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 124>
scmitim termination_time Time termination event occurred
<byte 132>
{termination_event (Termination event information)}
<byte 132>
ulong termination_location Location of termination event report call
<byte 136>
union u Termination Code Union
<byte 136>
{code (Termination Code)}
<byte 136>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 137>
cacode cac Corrective Action Code
<byte 138>
utiny evnum Event Number
<byte 139>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 136>
ulong value Termination Code Value
endunion u Termination Code Union
<byte 140>
{params (Termination Parameters)}
<byte 140>
ulong[31] param Termination Parameters
{}
{}
<byte 264>
utiny[2] reserved Reserved
<byte 266>
{flags (Other Last Termination Event flags)}
<byte 266>
tbits:1 lg_send_sts Last Gasp send status
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
tbits:3 rsvd Pad to fill byte
{}
<byte 267>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 268>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
{}
Event Information Packet Type: 1d
EIP1D - Fault Manager Termination Event (old Termination Event Information Header)
HSV210 controller operation terminated event report.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{lteihd (Last Termination Event Information Header)}
<byte 72>
{flags (Last Termination Event flags)}
<byte 72>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
{}
<byte 73>
utiny revision Structure revision number
<byte 74>
ushort size Structure size
{}
<byte 76>
{lter (Nonstandard Last Termination Event Report Block)}
<byte 76>
ulong seq Sequence number assigned to the termination event
<byte 80>
char[4] sw_version HSV210 controller software version number string
<byte 84>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 96>
char[8] ctrlr_model_id HSV210 controller model string
<byte 104>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 124>
scmitim termination_time Time termination event occurred
<byte 132>
{termination_event (Termination event information)}
<byte 132>
ulong termination_location Location of termination event report call
<byte 136>
union u Termination Code Union
<byte 136>
{code (Termination Code)}
<byte 136>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 137>
cacode cac Corrective Action Code
<byte 138>
utiny evnum Event Number
<byte 139>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 136>
ulong value Termination Code Value
endunion u Termination Code Union
{}
<byte 140>
utiny[2] reserved Reserved
<byte 142>
utiny lg_send_sts Last Gasp send status
<byte 143>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 144>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
{}
Event Information Packet Type: 1e
EIP1E - General Storage System State Services State Information Event
General Storage System state information to be reported.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
char[12] info Informational String
<byte 84>
ulong[24] data Informational Data
{}
Event Information Packet Type: 1f
EIP1F - A Storage System Virtual Disk has changed controller mastership.
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag ld_tag Logical disk
<byte 88>
tag du_tag Derived unit
<byte 104>
tag scvd_tag Storage System Virtual Disk
<byte 120>
{prev_wwn (Previous Controller)}
<byte 120>
ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type
<byte 124>
ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port
{}
<byte 128>
{current_wwn (Current Controller)}
<byte 128>
ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type
<byte 132>
ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port
{}
{}
Event Information Packet Type: 20
EIP20 - Storage System State Services Controller FC Port event
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
{node_name (World Wide Name of HSV210 controller)}
<byte 72>
ulong hi (Bits 31:28) Network Address Authority Code, (Bits 27:4) Company ID, (Bits 3:0) Type
<byte 76>
ulong lo (Bits 31:4) Node Number, (Bits 3:0) Port
{}
<byte 80>
ulong port Loop port number
<byte 84>
ulong data Event-specific data
{}
Event Information Packet Type: 21
EIP21 - General purpose SCS Logical Disk synchronization event
{Event Log Packet Event Specific Information}
<byte 0>
{flags (Flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Event sequence number reset occurred
tbits:1 outofsequence Event reported out of sequence due to Final Event Block reconciliation or lost host event
tbits:1 requeued Event requeued following restart or resynchronization
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort count Event specific information size in bytes
<byte 4>
ulong sequence_number Sequence number assigned to the event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd reporting_ctrlr Storage System Management Interface Handle of HSV210 controller that reported the event
<byte 52>
scmitim report_time Time event was reported
<byte 60>
ulong report_location Location of event report call
<byte 64>
{header (Header Information)}
<byte 64>
union u Event Code Union
<byte 64>
{ec (Event Code)}
<byte 64>
utiny eiptype Event Information Packet Type Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Event Code Union
<byte 64>
ulong value Event Code Value
endunion u Event Code Union
<byte 68>
utiny revision Packet revision number
<byte 69>
utiny type Packet type
<byte 70>
ushort count Number of bytes in packet
{}
<byte 72>
tag target_tag Target Tag
<byte 88>
tag parent_tag Parent Tag
<byte 104>
ulong operation Operation
<byte 108>
ulong status Status
<byte 112>
ulong prev_state Previous State
<byte 116>
ulong new_state New State
<byte 120>
ulong redundancy Redundancy Type
<byte 124>
double_word size LD Size
<byte 132>
tag aux_tag Auxillary Tag
{}
TERMINATION EVENT BLOCK:
{Termination Event Block}
<byte 0>
union u Last Termination Event Block Union
<byte 0>
{data (Termination Event Block Data)}
<byte 0>
{ltei (Last Termination Event Information)}
<byte 0>
{lteihd (Last Termination Event Information Header)}
<byte 0>
{flags (Last Termination Event flags)}
<byte 0>
tbits:1 time_set Time has been set on this HSV210 controller
tbits:1 time_synched Time has been synchronized with all HSV210 controllers in the Storage System
tbits:1 seq_reset Termination event sequence number reset occurred
tbits:1 cccc_forced Coupled crash forced
tbits:1 rsvd Pad to fill byte
tbits:1 labcode Event reported using LAB code
tbits:1 prictrlr Event reported by primary HSV210 controller (Note: Not valid until Storage System primary HSV210 controller is elected)
tbits:1 spsctrlr Single power supply HSV210 controller
{}
<byte 1>
utiny revision Structure revision number
<byte 2>
ushort size Structure size
{}
<byte 4>
{lter (Last Termination Event Report Block)}
<byte 4>
ulong seq Sequence number assigned to the termination event
<byte 8>
char[4] sw_version HSV210 controller software version number string
<byte 12>
char[12] baselevel_id HSV210 controller baselevel build string
<byte 24>
char[8] ctrlr_model_id HSV210 controller model string
<byte 32>
scmi_obj_hnd terminating_ctrlr Storage System Management Interface Handle of HSV210 controller that terminated operation
<byte 52>
scmitim termination_time Time termination event occurred
<byte 60>
{termination_event (Termination event information)}
<byte 60>
ulong termination_location Location of termination event report call
<byte 64>
union u Termination Code Union
<byte 64>
{code (Termination Code)}
<byte 64>
tbits:5 parc Parameter Count
tbits:2 drcc Dump/Restart Control Code
tbits:1 cccc Coupled Crash Control Code
<byte 65>
cacode cac Corrective Action Code
<byte 66>
utiny evnum Event Number
<byte 67>
utiny scid HSV210 Controller Software Component Identification
{}
or u Termination Code Union
<byte 64>
ulong value Termination Code Value
endunion u Termination Code Union
<byte 68>
{params (Termination Parameters)}
<byte 68>
ulong[31] param Termination Parameters
{}
{}
<byte 192>
utiny[2] reserved Reserved
<byte 194>
{flags (Other Last Termination Event flags)}
<byte 194>
tbits:1 lg_send_sts Last Gasp send status
tbits:1 stack_bad Stack contains pointer outside stack area
tbits:1 stack_guard_bad System or process stack guard value(s) overwritten
tbits:1 short_term_path Short termination path taken
tbits:1 feb_saved Final Event Block saved
tbits:3 rsvd Pad to fill byte
{}
<byte 195>
utiny reuea_index Termination Processing Recursive Entry Event or Unexpected Event array index
<byte 196>
ulonglong uptime Number of seconds HSV210 controller has run functional code
{}
<byte 204>
{sa (Exception save area)}
<byte 204>
ulong[32] registers R0-R31
<byte 332>
ulong srr0 SRR0
<byte 336>
ulong srr1 SRR1
<byte 340>
ulong cr CR
<byte 344>
ulong xer XER
<byte 348>
ulong ctr CTR
<byte 352>
ulong lr LR
<byte 356>
ulong exception Exception Code
<byte 360>
union optional Machine check or DSI exception values
<byte 360>
{mcp (Machine check values)}
<byte 360>
ulong mc_count Exception Count
<byte 364>
ulong msssr0 MSSSR0 Register
{}
or optional Machine check or DSI exception values
<byte 360>
{dsi (DSI exception values)}
<byte 360>
ulong dsisr DSISR Register
<byte 364>
ulong dar DAR Register
{}
endunion optional Machine check or DSI exception values
{}
<byte 368>
char[8] current_process Current process name
<byte 376>
{stack (Stack information)}
<byte 376>
ulong stack_depth Total calls made
<byte 380>
{stack[0] (Stack entries)}
<byte 380>
ulong bc Back chain (old stack pointer)
<byte 384>
ulong slr Saved link register
{}
<byte 388>
{stack[1] (Stack entries)}
<byte 388>
ulong bc Back chain (old stack pointer)
<byte 392>
ulong slr Saved link register
{}
<byte 396>
{stack[2] (Stack entries)}
<byte 396>
ulong bc Back chain (old stack pointer)
<byte 400>
ulong slr Saved link register
{}
<byte 404>
{stack[3] (Stack entries)}
<byte 404>
ulong bc Back chain (old stack pointer)
<byte 408>
ulong slr Saved link register
{}
<byte 412>
{stack[4] (Stack entries)}
<byte 412>
ulong bc Back chain (old stack pointer)
<byte 416>
ulong slr Saved link register
{}
<byte 420>
{stack[5] (Stack entries)}
<byte 420>
ulong bc Back chain (old stack pointer)
<byte 424>
ulong slr Saved link register
{}
<byte 428>
{stack[6] (Stack entries)}
<byte 428>
ulong bc Back chain (old stack pointer)
<byte 432>
ulong slr Saved link register
{}
<byte 436>
{stack[7] (Stack entries)}
<byte 436>
ulong bc Back chain (old stack pointer)
<byte 440>
ulong slr Saved link register
{}
<byte 444>
{stack[8] (Stack entries)}
<byte 444>
ulong bc Back chain (old stack pointer)
<byte 448>
ulong slr Saved link register
{}
<byte 452>
{stack[9] (Stack entries)}
<byte 452>
ulong bc Back chain (old stack pointer)
<byte 456>
ulong slr Saved link register
{}
<byte 460>
{stack[10] (Stack entries)}
<byte 460>
ulong bc Back chain (old stack pointer)
<byte 464>
ulong slr Saved link register
{}
<byte 468>
{stack[11] (Stack entries)}
<byte 468>
ulong bc Back chain (old stack pointer)
<byte 472>
ulong slr Saved link register
{}
<byte 476>
{stack[12] (Stack entries)}
<byte 476>
ulong bc Back chain (old stack pointer)
<byte 480>
ulong slr Saved link register
{}
<byte 484>
{stack[13] (Stack entries)}
<byte 484>
ulong bc Back chain (old stack pointer)
<byte 488>
ulong slr Saved link register
{}
<byte 492>
{stack[14] (Stack entries)}
<byte 492>
ulong bc Back chain (old stack pointer)
<byte 496>
ulong slr Saved link register
{}
<byte 500>
{stack[15] (Stack entries)}
<byte 500>
ulong bc Back chain (old stack pointer)
<byte 504>
ulong slr Saved link register
{}
<byte 508>
{stack[16] (Stack entries)}
<byte 508>
ulong bc Back chain (old stack pointer)
<byte 512>
ulong slr Saved link register
{}
<byte 516>
{stack[17] (Stack entries)}
<byte 516>
ulong bc Back chain (old stack pointer)
<byte 520>
ulong slr Saved link register
{}
<byte 524>
{stack[18] (Stack entries)}
<byte 524>
ulong bc Back chain (old stack pointer)
<byte 528>
ulong slr Saved link register
{}
<byte 532>
{stack[19] (Stack entries)}
<byte 532>
ulong bc Back chain (old stack pointer)
<byte 536>
ulong slr Saved link register
{}
<byte 540>
{stack[20] (Stack entries)}
<byte 540>
ulong bc Back chain (old stack pointer)
<byte 544>
ulong slr Saved link register
{}
<byte 548>
{stack[21] (Stack entries)}
<byte 548>
ulong bc Back chain (old stack pointer)
<byte 552>
ulong slr Saved link register
{}
<byte 556>
{stack[22] (Stack entries)}
<byte 556>
ulong bc Back chain (old stack pointer)
<byte 560>
ulong slr Saved link register
{}
<byte 564>
{stack[23] (Stack entries)}
<byte 564>
ulong bc Back chain (old stack pointer)
<byte 568>
ulong slr Saved link register
{}
<byte 572>
{stack[24] (Stack entries)}
<byte 572>
ulong bc Back chain (old stack pointer)
<byte 576>
ulong slr Saved link register
{}
<byte 580>
{stack[25] (Stack entries)}
<byte 580>
ulong bc Back chain (old stack pointer)
<byte 584>
ulong slr Saved link register
{}
<byte 588>
{stack[26] (Stack entries)}
<byte 588>
ulong bc Back chain (old stack pointer)
<byte 592>
ulong slr Saved link register
{}
<byte 596>
{stack[27] (Stack entries)}
<byte 596>
ulong bc Back chain (old stack pointer)
<byte 600>
ulong slr Saved link register
{}
<byte 604>
{stack[28] (Stack entries)}
<byte 604>
ulong bc Back chain (old stack pointer)
<byte 608>
ulong slr Saved link register
{}
<byte 612>
{stack[29] (Stack entries)}
<byte 612>
ulong bc Back chain (old stack pointer)
<byte 616>
ulong slr Saved link register
{}
<byte 620>
{stack[30] (Stack entries)}
<byte 620>
ulong bc Back chain (old stack pointer)
<byte 624>
ulong slr Saved link register
{}
<byte 628>
{stack[31] (Stack entries)}
<byte 628>
ulong bc Back chain (old stack pointer)
<byte 632>
ulong slr Saved link register
{}
<byte 636>
*ptr *bad_stack_ptr Bad stack address
<byte 640>
ulong system_stack_guard System stack guard intact flags (set to 1 if not intact)
<byte 644>
ulong[16] stack_guard Process stack guard intact flags (set to 1 if not intact)
{}
<byte 708>
{hardware (Hardware registers)}
<byte 708>
{flags (Hardware registers gathered flags)}
<byte 708>
lbits:1 uartdrd SC28L194 Quad UART d data registers gathered
lbits:1 uartdrc SC28L194 Quad UART c data registers gathered
lbits:1 uartdrb SC28L194 Quad UART b data registers gathered
lbits:1 uartdra SC28L194 Quad UART a data registers gathered
lbits:1 uartcrd SC28L194 Quad UART d control registers gathered
lbits:1 uartcrc SC28L194 Quad UART c control registers gathered
lbits:1 uartcrb SC28L194 Quad UART b control registers gathered
lbits:1 uartcra SC28L194 Quad UART a control registers gathered
lbits:1 sprite_csr Sprite Chip CSR registers gathered
lbits:1 glue_csr Glue Chip CSR registers gathered
lbits:1 toyclock DS1557 4MEG NV Y2KC Timekeeping RAM registers gathered
lbits:1 decoder_csr Decoder
lbits:1 atlantis_csr Atlantis (Crash Dump only)
lbits:1 atlantis_mcs Atlantis machine check specific registers (Termination event only)
lbits:1 atlantis_a1 Atlantis Area 1 miscellaneous registers (Termination event only)
lbits:1 aa2 Atlantis registers--Area 2 (Termination event only)
lbits:1 aa3 Atlantis registers--Area 3 (Termination event only)
lbits:15 rsvd Reserved
{}
<byte 712>
{tach_flags (Tachyon registers gathered flags)}
<byte 712>
lbits:1 tachyon9_csr Tachyon 9 CSR registers gathered
lbits:1 tachyon9_pcicfg Tachyon 9 PCI Configuration
lbits:1 tachyon9_gbic Tachyon 9 GBIC Small Form Factor ID
lbits:1 tachyon8_csr Tachyon 8 CSR registers gathered
lbits:1 tachyon8_pcicfg Tachyon 8 PCI Configuration
lbits:1 tachyon8_gbic Tachyon 8 GBIC Small Form Factor ID
lbits:1 tachyon7_csr Tachyon 7 CSR registers gathered
lbits:1 tachyon7_pcicfg Tachyon 7 PCI Configuration
lbits:1 tachyon7_gbic Tachyon 7 GBIC Small Form Factor ID
lbits:1 tachyon6_csr Tachyon 6 CSR registers gathered
lbits:1 tachyon6_pcicfg Tachyon 6 PCI Configuration
lbits:1 tachyon6_gbic Tachyon 6 GBIC Small Form Factor ID
lbits:1 tachyon5_csr Tachyon 5 CSR registers gathered
lbits:1 tachyon5_pcicfg Tachyon 5 PCI Configuration
lbits:1 tachyon5_gbic Tachyon 5 GBIC Small Form Factor ID
lbits:1 tachyon4_csr Tachyon 4 CSR registers gathered
lbits:1 tachyon4_pcicfg Tachyon 4 PCI Configuration
lbits:1 tachyon4_gbic Tachyon 4 GBIC Small Form Factor ID
lbits:1 tachyon3_csr Tachyon 3 CSR registers gathered
lbits:1 tachyon3_pcicfg Tachyon 3 PCI Configuration
lbits:1 tachyon3_gbic Tachyon 3 GBIC Small Form Factor ID
lbits:1 tachyon2_csr Tachyon 2 CSR registers gathered
lbits:1 tachyon2_pcicfg Tachyon 2 PCI Configuration
lbits:1 tachyon2_gbic Tachyon 2 GBIC Small Form Factor ID
lbits:1 tachyon1_csr Tachyon 1 CSR registers gathered
lbits:1 tachyon1_pcicfg Tachyon 1 PCI Configuration
lbits:1 tachyon1_gbic Tachyon 1 GBIC Small Form Factor ID
lbits:1 tachyon0_csr Tachyon 0 CSR registers gathered
lbits:1 tachyon0_pcicfg Tachyon 0 PCI Configuration
lbits:1 tachyon0_gbic Tachyon 0 GBIC Small Form Factor ID
lbits:2 rsvd Reserved
{}
<byte 716>
{tach_ncfg_flags (Tachyon non-configuration registers gathered flags)}
<byte 716>
lbits:1 tachyon9_ncfghi Tachyon 9 Non-configuration--high registers gathered
lbits:1 tachyon9_ncfglo Tachyon 9 Non-configuration--low registers gathered
lbits:1 tachyon8_ncfghi Tachyon 8 Non-configuration--high registers gathered
lbits:1 tachyon8_ncfglo Tachyon 8 Non-configuration--low registers gathered
lbits:1 tachyon7_ncfghi Tachyon 7 Non-configuration--high registers gathered
lbits:1 tachyon7_ncfglo Tachyon 7 Non-configuration--low registers gathered
lbits:1 tachyon6_ncfghi Tachyon 6 Non-configuration--high registers gathered
lbits:1 tachyon6_ncfglo Tachyon 6 Non-configuration--low registers gathered
lbits:1 tachyon5_ncfghi Tachyon 5 Non-configuration--high registers gathered
lbits:1 tachyon5_ncfglo Tachyon 5 Non-configuration--low registers gathered
lbits:1 tachyon4_ncfghi Tachyon 4 Non-configuration--high registers gathered
lbits:1 tachyon4_ncfglo Tachyon 4 Non-configuration--low registers gathered
lbits:1 tachyon3_ncfghi Tachyon 3 Non-configuration--high registers gathered
lbits:1 tachyon3_ncfglo Tachyon 3 Non-configuration--low registers gathered
lbits:1 tachyon2_ncfghi Tachyon 2 Non-configuration--high registers gathered
lbits:1 tachyon2_ncfglo Tachyon 2 Non-configuration--low registers gathered
lbits:1 tachyon1_ncfghi Tachyon 1 Non-configuration--high registers gathered
lbits:1 tachyon1_ncfglo Tachyon 1 Non-configuration--low registers gathered
lbits:1 tachyon0_ncfghi Tachyon 0 Non-configuration--high registers gathered
lbits:1 tachyon0_ncfglo Tachyon 0 Non-configuration--low registers gathered
lbits:12 rsvd Reserved
{}
<byte 720>
{aa3 (Atlantis registers--Area3)}
<byte 720>
ulong[518] reserved Reserved for future use
{}
<byte 2792>
{aa2 (Atlantis registers--Area2)}
<byte 2792>
ulong[200] reserved Reserved for future use
{}
<byte 3592>
{atlantis_a1 (Atlantis Area 1 miscellaneous registers)}
<byte 3592>
union cpu_configuration (Offset 0x0000) CPU Configuration
<byte 3592>
{field (By field)}
<byte 3592>
lbits:8 nomatchcnt RW CPU Address Miss Counter
lbits:1 nomatchcnten RW CPU Address Miss Counter Enable
lbits:1 nomatchcntext RW CPU address miss counter MSB
lbits:1 reserved4 RES Reserved
lbits:1 singlecpu RW 0 = Dual CPU. 1 = Single CPU
lbits:1 endianess RW CPU Bus Byte Orientation. Must be 0
lbits:1 pipeline RW Pipeline Enable
lbits:3 reserved3 RES Reserved
lbits:1 stopretry RW Stop to retry transactions from PCI
lbits:1 multigtdec RW Multi-GT Address Decode
lbits:1 dpvalid RW CPU DP[0-7] Connection
lbits:2 reserved2 RES Reserved
lbits:1 perrprop RW Parity Error Propagation
lbits:2 reserved1 RES Reserved
lbits:1 aackdelay2 RW AACK# earliest assertion following TS#
lbits:1 apvalid RW CPU AP[0-3] Connection
lbits:1 remapwrdis RW Address Remap Registers Write Control
lbits:4 reserved0 RES Reserved
{}
or cpu_configuration (Offset 0x0000) CPU Configuration
<byte 3592>
ulong value As longword
endunion cpu_configuration (Offset 0x0000) CPU Configuration
<byte 3596>
union cs_0_base_address (Offset 0x0008) CS[0]# Base Address
<byte 3596>
{field (By field)}
<byte 3596>
lbits:20 base RW Base Address
lbits:12 reserved0 RES Reserved
{}
or cs_0_base_address (Offset 0x0008) CS[0]# Base Address
<byte 3596>
ulong value As longword
endunion cs_0_base_address (Offset 0x0008) CS[0]# Base Address
<byte 3600>
union cs_0_size (Offset 0x0010) CS[0]# Size
<byte 3600>
{field (By field)}
<byte 3600>
lbits:16 size RW Bank Size
lbits:16 reserved0 RES Reserved
{}
or cs_0_size (Offset 0x0010) CS[0]# Size
<byte 3600>
ulong value As longword
endunion cs_0_size (Offset 0x0010) CS[0]# Size
<byte 3604>
union cs_2_base_address (Offset 0x0018) CS[2]# Base Address
<byte 3604>
{field (By field)}
<byte 3604>
lbits:20 base RW Base Address
lbits:12 reserved0 RES Reserved
{}
or cs_2_base_address (Offset 0x0018) CS[2]# Base Address
<byte 3604>
ulong value As longword
endunion cs_2_base_address (Offset 0x0018) CS[2]# Base Address
<byte 3608>
union cs_2_size (Offset 0x0020) CS[2]# Size
<byte 3608>
{field (By field)}
<byte 3608>
lbits:16 size RW Bank Size
lbits:16 reserved0 RES Reserved
{}
or cs_2_size (Offset 0x0020) CS[2]# Size
<byte 3608>
ulong value As longword
endunion cs_2_size (Offset 0x0020) CS[2]# Size
<byte 3612>
union cs_1_base_address (Offset 0x0208) CS[1]# Base Address
<byte 3612>
{field (By field)}
<byte 3612>
lbits:20 base RW Base Address
lbits:12 reserved0 RES Reserved
{}
or cs_1_base_address (Offset 0x0208) CS[1]# Base Address
<byte 3612>
ulong value As longword
endunion cs_1_base_address (Offset 0x0208) CS[1]# Base Address
<byte 3616>
union cs_1_size (Offset 0x0210) CS[1]# Size
<byte 3616>
{field (By field)}
<byte 3616>
lbits:16 size RW Bank Size
lbits:16 reserved0 RES Reserved
{}
or cs_1_size (Offset 0x0210) CS[1]# Size
<byte 3616>
ulong value As longword
endunion cs_1_size (Offset 0x0210) CS[1]# Size
<byte 3620>
union cs_3_base_address (Offset 0x0218) CS[3]# Base Address
<byte 3620>
{field (By field)}
<byte 3620>
lbits:20 base RW Base Address
lbits:12 reserved0 RES Reserved
{}
or cs_3_base_address (Offset 0x0218) CS[3]# Base Address
<byte 3620>
ulong value As longword
endunion cs_3_base_address (Offset 0x0218) CS[3]# Base Address
<byte 3624>
union cs_3_size (Offset 0x0220) CS[3]# Size
<byte 3624>
{field (By field)}
<byte 3624>
lbits:16 size RW Bank Size
lbits:16 reserved0 RES Reserved
{}
or cs_3_size (Offset 0x0220) CS[3]# Size
<byte 3624>
ulong value As longword
endunion cs_3_size (Offset 0x0220) CS[3]# Size
<byte 3628>
union base_address_enable (Offset 0x0278) Base Address Enable
<byte 3628>
{field (By field)}
<byte 3628>
lbits:1 encs_0 RW CS[0] base address enable
lbits:1 encs_1 RW CS[1] base address enable
lbits:1 encs_2 RW CS[2] base address enable
lbits:1 encs_3 RW CS[3] base address enable
lbits:1 endevcs_0 RW DevCS[0] base address enable
lbits:1 endevcs_1 RW DevCS[1] base address enable
lbits:1 endevcs_2 RW DevCS[2] base address enable
lbits:1 endevcs_3 RW DevCS[3] base address enable
lbits:1 enbootcs RW BootCS base address enable
lbits:1 enpci_0_io RW PCI_0 I/O base address enable
lbits:1 enpci_0_mem0 RW PCI_0 Mem0 base address enable
lbits:1 enpci_0_mem1 RW PCI_0 Mem1 base address enable
lbits:1 enpci_0_mem2 RW PCI_0 Mem2 base address enable
lbits:1 enpci_0_mem3 RW PCI_0 Mem3 base address enable
lbits:1 enpci_1_io RW PCI_1 I/O base address enable
lbits:1 enpci_1_mem0 RW PCI_1 Mem0 base address enable
lbits:1 enpci_1_mem1 RW PCI_1 Mem1 base address enable
lbits:1 enpci_1_mem2 RW PCI_1 Mem2 base address enable
lbits:1 enpci_1_mem3 RW PCI_1 Mem3 base address enable
lbits:1 enintegr_sram RW Integrated SRAM base address enable
lbits:1 eninter_space RW Internal Space base address enable
lbits:11 reserved0 RES Reserved
{}
or base_address_enable (Offset 0x0278) Base Address Enable
<byte 3628>
ulong value As longword
endunion base_address_enable (Offset 0x0278) Base Address Enable
<byte 3632>
union idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count
<byte 3632>
{field (By field)}
<byte 3632>
lbits:24 bytecnt RW Number of bytes left for the DMA to transfer
lbits:6 reserved0 RES Reserved
lbits:1 bcleft RW Left Byte Count
lbits:1 own RW Ownership Bit
{}
or idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count
<byte 3632>
ulong value As longword
endunion idma_channel_0_dma_byte_count (Offset 0x0800) IDMA Channel 0 DMA Byte Count
<byte 3636>
union idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count
<byte 3636>
{field (By field)}
<byte 3636>
lbits:24 bytecnt RW Number of bytes left for the DMA to transfer
lbits:6 reserved0 RES Reserved
lbits:1 bcleft RW Left Byte Count
lbits:1 own RW Ownership Bit
{}
or idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count
<byte 3636>
ulong value As longword
endunion idma_channel_1_dma_byte_count (Offset 0x0804) IDMA Channel 1 DMA Byte Count
<byte 3640>
union idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count
<byte 3640>
{field (By field)}
<byte 3640>
lbits:24 bytecnt RW Number of bytes left for the DMA to transfer
lbits:6 reserved0 RES Reserved
lbits:1 bcleft RW Left Byte Count
lbits:1 own RW Ownership Bit
{}
or idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count
<byte 3640>
ulong value As longword
endunion idma_channel_2_dma_byte_count (Offset 0x0808) IDMA Channel 2 DMA Byte Count
<byte 3644>
union idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count
<byte 3644>
{field (By field)}
<byte 3644>
lbits:24 bytecnt RW Number of bytes left for the DMA to transfer
lbits:6 reserved0 RES Reserved
lbits:1 bcleft RW Left Byte Count
lbits:1 own RW Ownership Bit
{}
or idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count
<byte 3644>
ulong value As longword
endunion idma_channel_3_dma_byte_count (Offset 0x080C) IDMA Channel 3 DMA Byte Count
<byte 3648>
union idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source Address
<byte 3648>
{field (By field)}
<byte 3648>
lbits:32 srcadd RW Bits[31:0] of the DMA source address
{}
or idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source Address
<byte 3648>
ulong value As longword
endunion idma_channel_0_dma_source_address (Offset 0x0810) IDMA Channel 0 DMA Source Address
<byte 3652>
union idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source Address
<byte 3652>
{field (By field)}
<byte 3652>
lbits:32 srcadd RW Bits[31:0] of the DMA source address
{}
or idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source Address
<byte 3652>
ulong value As longword
endunion idma_channel_1_dma_source_address (Offset 0x0814) IDMA Channel 1 DMA Source Address
<byte 3656>
union idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source Address
<byte 3656>
{field (By field)}
<byte 3656>
lbits:32 srcadd RW Bits[31:0] of the DMA source address
{}
or idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source Address
<byte 3656>
ulong value As longword
endunion idma_channel_2_dma_source_address (Offset 0x0818) IDMA Channel 2 DMA Source Address
<byte 3660>
union idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source Address
<byte 3660>
{field (By field)}
<byte 3660>
lbits:32 srcadd RW Bits[31:0] of the DMA source address
{}
or idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source Address
<byte 3660>
ulong value As longword
endunion idma_channel_3_dma_source_address (Offset 0x081C) IDMA Channel 3 DMA Source Address
<byte 3664>
union idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address
<byte 3664>
{field (By field)}
<byte 3664>
lbits:32 destadd RW Bits[31:0] of the DMA destination address
{}
or idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address
<byte 3664>
ulong value As longword
endunion idma_channel_0_dma_destination_address (Offset 0x0820) IDMA Channel 0 DMA Destination Address
<byte 3668>
union idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address
<byte 3668>
{field (By field)}
<byte 3668>
lbits:32 destadd RW Bits[31:0] of the DMA destination address
{}
or idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address
<byte 3668>
ulong value As longword
endunion idma_channel_1_dma_destination_address (Offset 0x0824) IDMA Channel 1 DMA Destination Address
<byte 3672>
union idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address
<byte 3672>
{field (By field)}
<byte 3672>
lbits:32 destadd RW Bits[31:0] of the DMA destination address
{}
or idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address
<byte 3672>
ulong value As longword
endunion idma_channel_2_dma_destination_address (Offset 0x0828) IDMA Channel 2 DMA Destination Address
<byte 3676>
union idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address
<byte 3676>
{field (By field)}
<byte 3676>
lbits:32 destadd RW Bits[31:0] of the DMA destination address
{}
or idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address
<byte 3676>
ulong value As longword
endunion idma_channel_3_dma_destination_address (Offset 0x082C) IDMA Channel 3 DMA Destination Address
<byte 3680>
union idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer
<byte 3680>
{field (By field)}
<byte 3680>
lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address
{}
or idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer
<byte 3680>
ulong value As longword
endunion idma_channel_0_next_descriptor_pointer (Offset 0x0830) IDMA Channel 0 Next Descriptor Pointer
<byte 3684>
union idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer
<byte 3684>
{field (By field)}
<byte 3684>
lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address
{}
or idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer
<byte 3684>
ulong value As longword
endunion idma_channel_1_next_descriptor_pointer (Offset 0x0834) IDMA Channel 1 Next Descriptor Pointer
<byte 3688>
union idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer
<byte 3688>
{field (By field)}
<byte 3688>
lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address
{}
or idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer
<byte 3688>
ulong value As longword
endunion idma_channel_2_next_descriptor_pointer (Offset 0x0838) IDMA Channel 2 Next Descriptor Pointer
<byte 3692>
union idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer
<byte 3692>
{field (By field)}
<byte 3692>
lbits:32 nextdescptr RW Bits[31:0] of the DMA next descriptor address
{}
or idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer
<byte 3692>
ulong value As longword
endunion idma_channel_3_next_descriptor_pointer (Offset 0x083C) IDMA Channel 3 Next Descriptor Pointer
<byte 3696>
union idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low)
<byte 3696>
{field (By field)}
<byte 3696>
lbits:3 dstburstlimit RW Destination burst limit in each DMA access
lbits:1 srchold RW Source Hold
lbits:1 dmaack_width RW DMA ack width
lbits:1 desthold RW Destination Hold
lbits:3 srcburstlimit RW Source burst limit in each DMA access
lbits:1 chainmode RW Chained Mode
lbits:1 intmode RW Interrupt Mode
lbits:1 demandmode RW Demand Mode Enable
lbits:1 chanen RW Channel Enable
lbits:1 fetchnd RWC Fetch Next Descriptor
lbits:1 chanact RO DMA Channel Active
lbits:1 dmareqdir RW DMAReq Direction
lbits:1 dmareqmode RW DMAReq# Mode
lbits:1 cden RW Close Descriptor Enable
lbits:1 eoten RW End Of Transfer Enable
lbits:1 eotmode RW End of Transfer Affect
lbits:1 abr RW Channel Abort
lbits:2 saddrovr RW Override Source Address
lbits:2 daddrovr RW Override Destination Address
lbits:2 naddrovr RW Override Next Descriptor Address
lbits:1 dmaackmode RW DMA Acknowledge Mode
lbits:1 timerreq RW Timer DMA Request Enable
lbits:2 dmaackdir RW DMA Acknowledge Direction
lbits:1 descmode RW Descriptor Mode
{}
or idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low)
<byte 3696>
ulong value As longword
endunion idma_channel_0_control_low (Offset 0x0840) IDMA Channel 0 Control (Low)
<byte 3700>
union idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low)
<byte 3700>
{field (By field)}
<byte 3700>
lbits:3 dstburstlimit RW Destination burst limit in each DMA access
lbits:1 srchold RW Source Hold
lbits:1 dmaack_width RW DMA ack width
lbits:1 desthold RW Destination Hold
lbits:3 srcburstlimit RW Source burst limit in each DMA access
lbits:1 chainmode RW Chained Mode
lbits:1 intmode RW Interrupt Mode
lbits:1 demandmode RW Demand Mode Enable
lbits:1 chanen RW Channel Enable
lbits:1 fetchnd RWC Fetch Next Descriptor
lbits:1 chanact RO DMA Channel Active
lbits:1 dmareqdir RW DMAReq Direction
lbits:1 dmareqmode RW DMAReq# Mode
lbits:1 cden RW Close Descriptor Enable
lbits:1 eoten RW End Of Transfer Enable
lbits:1 eotmode RW End of Transfer Affect
lbits:1 abr RW Channel Abort
lbits:2 saddrovr RW Override Source Address
lbits:2 daddrovr RW Override Destination Address
lbits:2 naddrovr RW Override Next Descriptor Address
lbits:1 dmaackmode RW DMA Acknowledge Mode
lbits:1 timerreq RW Timer DMA Request Enable
lbits:2 dmaackdir RW DMA Acknowledge Direction
lbits:1 descmode RW Descriptor Mode
{}
or idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low)
<byte 3700>
ulong value As longword
endunion idma_channel_1_control_low (Offset 0x0844) IDMA Channel 1 Control (Low)
<byte 3704>
union idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low)
<byte 3704>
{field (By field)}
<byte 3704>
lbits:3 dstburstlimit RW Destination burst limit in each DMA access
lbits:1 srchold RW Source Hold
lbits:1 dmaack_width RW DMA ack width
lbits:1 desthold RW Destination Hold
lbits:3 srcburstlimit RW Source burst limit in each DMA access
lbits:1 chainmode RW Chained Mode
lbits:1 intmode RW Interrupt Mode
lbits:1 demandmode RW Demand Mode Enable
lbits:1 chanen RW Channel Enable
lbits:1 fetchnd RWC Fetch Next Descriptor
lbits:1 chanact RO DMA Channel Active
lbits:1 dmareqdir RW DMAReq Direction
lbits:1 dmareqmode RW DMAReq# Mode
lbits:1 cden RW Close Descriptor Enable
lbits:1 eoten RW End Of Transfer Enable
lbits:1 eotmode RW End of Transfer Affect
lbits:1 abr RW Channel Abort
lbits:2 saddrovr RW Override Source Address
lbits:2 daddrovr RW Override Destination Address
lbits:2 naddrovr RW Override Next Descriptor Address
lbits:1 dmaackmode RW DMA Acknowledge Mode
lbits:1 timerreq RW Timer DMA Request Enable
lbits:2 dmaackdir RW DMA Acknowledge Direction
lbits:1 descmode RW Descriptor Mode
{}
or idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low)
<byte 3704>
ulong value As longword
endunion idma_channel_2_control_low (Offset 0x0848) IDMA Channel 2 Control (Low)
<byte 3708>
union idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low)
<byte 3708>
{field (By field)}
<byte 3708>
lbits:3 dstburstlimit RW Destination burst limit in each DMA access
lbits:1 srchold RW Source Hold
lbits:1 dmaack_width RW DMA ack width
lbits:1 desthold RW Destination Hold
lbits:3 srcburstlimit RW Source burst limit in each DMA access
lbits:1 chainmode RW Chained Mode
lbits:1 intmode RW Interrupt Mode
lbits:1 demandmode RW Demand Mode Enable
lbits:1 chanen RW Channel Enable
lbits:1 fetchnd RWC Fetch Next Descriptor
lbits:1 chanact RO DMA Channel Active
lbits:1 dmareqdir RW DMAReq Direction
lbits:1 dmareqmode RW DMAReq# Mode
lbits:1 cden RW Close Descriptor Enable
lbits:1 eoten RW End Of Transfer Enable
lbits:1 eotmode RW End of Transfer Affect
lbits:1 abr RW Channel Abort
lbits:2 saddrovr RW Override Source Address
lbits:2 daddrovr RW Override Destination Address
lbits:2 naddrovr RW Override Next Descriptor Address
lbits:1 dmaackmode RW DMA Acknowledge Mode
lbits:1 timerreq RW Timer DMA Request Enable
lbits:2 dmaackdir RW DMA Acknowledge Direction
lbits:1 descmode RW Descriptor Mode
{}
or idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low)
<byte 3708>
ulong value As longword
endunion idma_channel_3_control_low (Offset 0x084C) IDMA Channel 3 Control (Low)
<byte 3712>
union idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control
<byte 3712>
{field (By field)}
<byte 3712>
lbits:2 arb0 RW Slice 0 of 'pizza arbiter'
lbits:2 arb1 RW Slice 1 of 'pizza arbiter'
lbits:2 arb2 RW Slice 2 of 'pizza arbiter'
lbits:2 arb3 RW Slice 3 of 'pizza arbiter'
lbits:2 arb4 RW Slice 4 of 'pizza arbiter'
lbits:2 arb5 RW Slice 5 of 'pizza arbiter'
lbits:2 arb6 RW Slice 6 of 'pizza arbiter'
lbits:2 arb7 RW Slice 7 of 'pizza arbiter'
lbits:2 arb8 RW Slice 8 of 'pizza arbiter'
lbits:2 arb9 RW Slice 9 of 'pizza arbiter'
lbits:2 arb10 RW Slice 10 of 'pizza arbiter'
lbits:2 arb11 RW Slice 11 of 'pizza arbiter'
lbits:2 arb12 RW Slice 12 of 'pizza arbiter'
lbits:2 arb13 RW Slice 13 of 'pizza arbiter'
lbits:2 arb14 RW Slice 14 of 'pizza arbiter'
lbits:2 arb15 RW Slice 15 of 'pizza arbiter'
{}
or idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control
<byte 3712>
ulong value As longword
endunion idma_arbiter_control (Offset 0x0860) IDMA Arbiter Control
<byte 3716>
union idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0
<byte 3716>
{field (By field)}
<byte 3716>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3716>
union attr Target specific attributes
<byte 3720>
{dramti (DRAM Target Interface)}
<byte 3720>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3716>
{dbti (Device Bus Target Interface)}
<byte 3716>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3716>
{pci01ti (PCI0/1 Target Interface)}
<byte 3716>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3716>
utiny value As byte
endunion attr Target specific attributes
<byte 3717>
lbits:16 base RW Base Address
{}
or idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0
<byte 3716>
ulong value As longword
endunion idma_base_address_register_0 (Offset 0x0A00) IDMA Base Address Register 0
<byte 3720>
union idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0
<byte 3720>
{field (By field)}
<byte 3720>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0
<byte 3720>
ulong value As longword
endunion idma_size_register_0 (Offset 0x0A04) IDMA Size Register 0
<byte 3724>
union idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1
<byte 3724>
{field (By field)}
<byte 3724>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3724>
union attr Target specific attributes
<byte 3728>
{dramti (DRAM Target Interface)}
<byte 3728>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3724>
{dbti (Device Bus Target Interface)}
<byte 3724>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3724>
{pci01ti (PCI0/1 Target Interface)}
<byte 3724>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3724>
utiny value As byte
endunion attr Target specific attributes
<byte 3725>
lbits:16 base RW Base Address
{}
or idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1
<byte 3724>
ulong value As longword
endunion idma_base_address_register_1 (Offset 0x0A08) IDMA Base Address Register 1
<byte 3728>
union idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1
<byte 3728>
{field (By field)}
<byte 3728>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1
<byte 3728>
ulong value As longword
endunion idma_size_register_1 (Offset 0x0A0C) IDMA Size Register 1
<byte 3732>
union idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2
<byte 3732>
{field (By field)}
<byte 3732>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3732>
union attr Target specific attributes
<byte 3736>
{dramti (DRAM Target Interface)}
<byte 3736>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3732>
{dbti (Device Bus Target Interface)}
<byte 3732>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3732>
{pci01ti (PCI0/1 Target Interface)}
<byte 3732>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3732>
utiny value As byte
endunion attr Target specific attributes
<byte 3733>
lbits:16 base RW Base Address
{}
or idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2
<byte 3732>
ulong value As longword
endunion idma_base_address_register_2 (Offset 0x0A10) IDMA Base Address Register 2
<byte 3736>
union idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2
<byte 3736>
{field (By field)}
<byte 3736>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2
<byte 3736>
ulong value As longword
endunion idma_size_register_2 (Offset 0x0A14) IDMA Size Register 2
<byte 3740>
union idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3
<byte 3740>
{field (By field)}
<byte 3740>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3740>
union attr Target specific attributes
<byte 3744>
{dramti (DRAM Target Interface)}
<byte 3744>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3740>
{dbti (Device Bus Target Interface)}
<byte 3740>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3740>
{pci01ti (PCI0/1 Target Interface)}
<byte 3740>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3740>
utiny value As byte
endunion attr Target specific attributes
<byte 3741>
lbits:16 base RW Base Address
{}
or idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3
<byte 3740>
ulong value As longword
endunion idma_base_address_register_3 (Offset 0x0A18) IDMA Base Address Register 3
<byte 3744>
union idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3
<byte 3744>
{field (By field)}
<byte 3744>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3
<byte 3744>
ulong value As longword
endunion idma_size_register_3 (Offset 0x0A1C) IDMA Size Register 3
<byte 3748>
union idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4
<byte 3748>
{field (By field)}
<byte 3748>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3748>
union attr Target specific attributes
<byte 3752>
{dramti (DRAM Target Interface)}
<byte 3752>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3748>
{dbti (Device Bus Target Interface)}
<byte 3748>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3748>
{pci01ti (PCI0/1 Target Interface)}
<byte 3748>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3748>
utiny value As byte
endunion attr Target specific attributes
<byte 3749>
lbits:16 base RW Base Address
{}
or idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4
<byte 3748>
ulong value As longword
endunion idma_base_address_register_4 (Offset 0x0A20) IDMA Base Address Register 4
<byte 3752>
union idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4
<byte 3752>
{field (By field)}
<byte 3752>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4
<byte 3752>
ulong value As longword
endunion idma_size_register_4 (Offset 0x0A24) IDMA Size Register 4
<byte 3756>
union idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5
<byte 3756>
{field (By field)}
<byte 3756>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3756>
union attr Target specific attributes
<byte 3760>
{dramti (DRAM Target Interface)}
<byte 3760>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3756>
{dbti (Device Bus Target Interface)}
<byte 3756>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3756>
{pci01ti (PCI0/1 Target Interface)}
<byte 3756>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3756>
utiny value As byte
endunion attr Target specific attributes
<byte 3757>
lbits:16 base RW Base Address
{}
or idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5
<byte 3756>
ulong value As longword
endunion idma_base_address_register_5 (Offset 0x0A28) IDMA Base Address Register 5
<byte 3760>
union idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5
<byte 3760>
{field (By field)}
<byte 3760>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5
<byte 3760>
ulong value As longword
endunion idma_size_register_5 (Offset 0x0A2C) IDMA Size Register 5
<byte 3764>
union idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6
<byte 3764>
{field (By field)}
<byte 3764>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3764>
union attr Target specific attributes
<byte 3768>
{dramti (DRAM Target Interface)}
<byte 3768>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3764>
{dbti (Device Bus Target Interface)}
<byte 3764>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3764>
{pci01ti (PCI0/1 Target Interface)}
<byte 3764>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3764>
utiny value As byte
endunion attr Target specific attributes
<byte 3765>
lbits:16 base RW Base Address
{}
or idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6
<byte 3764>
ulong value As longword
endunion idma_base_address_register_6 (Offset 0x0A30) IDMA Base Address Register 6
<byte 3768>
union idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6
<byte 3768>
{field (By field)}
<byte 3768>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6
<byte 3768>
ulong value As longword
endunion idma_size_register_6 (Offset 0x0A34) IDMA Size Register 6
<byte 3772>
union idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7
<byte 3772>
{field (By field)}
<byte 3772>
lbits:4 target RW Specifies the target interface associated with this window
lbits:4 reserved0 RES Reserved
<byte 3772>
union attr Target specific attributes
<byte 3776>
{dramti (DRAM Target Interface)}
<byte 3776>
tbits:4 bank DRAM bank select
tbits:2 ccoh Cache coherency
tbits:2 reserved Reserved
{}
or attr Target specific attributes
<byte 3772>
{dbti (Device Bus Target Interface)}
<byte 3772>
tbits:5 bank Device bank select
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3772>
{pci01ti (PCI0/1 Target Interface)}
<byte 3772>
tbits:2 swaptype Data swap type
tbits:1 snoopns PCI-X No Snoop (NS) attribute
tbits:1 space PCI I/O or memory space
tbits:1 req64 PCI REQ64# control
tbits:3 reserved Reserved
{}
or attr Target specific attributes
<byte 3772>
utiny value As byte
endunion attr Target specific attributes
<byte 3773>
lbits:16 base RW Base Address
{}
or idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7
<byte 3772>
ulong value As longword
endunion idma_base_address_register_7 (Offset 0x0A38) IDMA Base Address Register 7
<byte 3776>
union idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7
<byte 3776>
{field (By field)}
<byte 3776>
lbits:16 reserved0 RO Reserved, read only
lbits:16 size RW Window Size
{}
or idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7
<byte 3776>
ulong value As longword
endunion idma_size_register_7 (Offset 0x0A3C) IDMA Size Register 7
<byte 3780>
union idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable
<byte 3780>
{field (By field)}
<byte 3780>
lbits:1 en0 RW Address window 0 enable
lbits:1 en1 RW Address window 1 enable
lbits:1 en2 RW Address window 2 enable
lbits:1 en3 RW Address window 3 enable
lbits:1 en4 RW Address window 4 enable
lbits:1 en5 RW Address window 5 enable
lbits:1 en6 RW Address window 6 enable
lbits:1 en7 RW Address window 7 enable
lbits:24 reserved0 RO Reserved, read only
{}
or idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable
<byte 3780>
ulong value As longword
endunion idma_base_address_enable (Offset 0x0A80) IDMA Base Address Enable
<byte 3784>
union sdram_configuration (Offset 0x1400) SDRAM Configuration
<byte 3784>
{field (By field)}
<byte 3784>
lbits:14 refresh Refresh rate of DIMM
lbits:1 pinter Physical interleaving
lbits:1 vinter Virtual interleaving
lbits:1 reserved1 Reserved
lbits:1 regdram Registered DRAM
lbits:1 ecc Enable ECC
lbits:1 reserved2 Reserved
lbits:2 dqs # DQS pins
lbits:4 reserved3 Reserved
lbits:6 rdbuff Read Buffer assignment
{}
or sdram_configuration (Offset 0x1400) SDRAM Configuration
<byte 3784>
ulong value As longword
endunion sdram_configuration (Offset 0x1400) SDRAM Configuration
<byte 3788>
union dunit_control_low (Offset 0x1404) Dunit Control (Low)
<byte 3788>
{field (By field)}
<byte 3788>
lbits:1 clksync RW Clock Domains Synchronization
lbits:1 rdsyncsel RW Read Data Synchronization Select
lbits:1 rdctrltdel RW Read Control Logic Delay
lbits:1 rddatadel RW Read Data Delay
lbits:2 ctrlpipe RW Number of pipeline stages in the Dunit control path
lbits:1 ctrlpos RW Address/Control Output Timing
lbits:1 rdpipe RW Number of pipeline stages in the read data path
lbits:1 rdsyncen RW Read Data Path Synchronization
lbits:1 rmwsyncen RW RMW Path Synchronization
lbits:1 cpupriority RW CPU priority assignment
lbits:1 pci_0priority RW PCI_0 priority assignment
lbits:1 pci_1priority RW PCI_1 priority assignment
lbits:1 mpscpriority RW MPSC priority assignment
lbits:1 idmapriority RW IDMA priority assignment
lbits:1 gbpriority RW Gb priority assignment
lbits:4 lcnt RW Arbiter Low Priority Counter
lbits:4 hcnt RW Arbiter High Priority Counter
lbits:3 stburstdel RW Number of sample stages on StartBurstIn
lbits:1 stburstneg RW StartBurstIn is first sampled on the falling edge of clock
lbits:1 stburstsrc RW StartBurst source
lbits:1 rddataneg RW Read data is first sampled with falling edge of clock
lbits:2 reserved0 RES Reserved
{}
or dunit_control_low (Offset 0x1404) Dunit Control (Low)
<byte 3788>
ulong value As longword
endunion dunit_control_low (Offset 0x1404) Dunit Control (Low)
<byte 3792>
union atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low)
<byte 3792>
{field (By field)}
<byte 3792>
lbits:4 Tdqss Write to DQS
lbits:4 Trcd Activate to command
lbits:4 Trp Precharge command period
lbits:4 Twr Write command to precharge
lbits:4 Twtr Write command to read command
lbits:4 Tras Minimum row active time
lbits:4 Trrd Activate bank A to activate bank B
lbits:4 reserved Reserved
{}
or atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low)
<byte 3792>
ulong value As longword
endunion atlantis_sdram_timing_l (Offset 0x1408) SDRAM Timing (Low)
<byte 3796>
union atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High)
<byte 3796>
{field (By field)}
<byte 3796>
lbits:4 Trfc Refresh command period
lbits:2 Trd2rd Minimum gap between DRAM read accesses
lbits:2 Trd2wr Minimum gap between DRAM read and write accesses
lbits:24 reserved Write command to precharge
{}
or atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High)
<byte 3796>
ulong value As longword
endunion atlantis_sdram_timing_h (Offset 0x140C) SDRAM Timing (High)
<byte 3800>
union sdram_address_control (Offset 0x1410) SDRAM Address Control
<byte 3800>
{field (By field)}
<byte 3800>
lbits:4 addrsel RW SDRAM Address Select
lbits:2 dcfg RW SDRAM Device Configuration
lbits:26 reserved0 RES Reserved
{}
or sdram_address_control (Offset 0x1410) SDRAM Address Control
<byte 3800>
ulong value As longword
endunion sdram_address_control (Offset 0x1410) SDRAM Address Control
<byte 3804>
union sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control
<byte 3804>
{field (By field)}
<byte 3804>
lbits:1 ope0 RW Open Page Enable CS[0]# bank0
lbits:1 ope1 RW Open Page Enable CS[0]# bank1
lbits:1 ope2 RW Open Page Enable CS[0]# bank2
lbits:1 ope3 RW Open Page Enable CS[0]# bank3
lbits:1 ope4 RW Open Page Enable CS[1]# bank0
lbits:1 ope5 RW Open Page Enable CS[1]# bank1
lbits:1 ope6 RW Open Page Enable CS[1]# bank2
lbits:1 ope7 RW Open Page Enable CS[1]# bank3
lbits:1 ope8 RW Open Page Enable CS[2]# bank0
lbits:1 ope9 RW Open Page Enable CS[2]# bank1
lbits:1 ope10 RW Open Page Enable CS[2]# bank2
lbits:1 ope11 RW Open Page Enable CS[2]# bank3
lbits:1 ope12 RW Open Page Enable CS[3]# bank0
lbits:1 ope13 RW Open Page Enable CS[3]# bank1
lbits:1 ope14 RW Open Page Enable CS[3]# bank2
lbits:1 ope15 RW Open Page Enable CS[3]# bank3
lbits:16 reserved0 RES Reserved
{}
or sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control
<byte 3804>
ulong value As longword
endunion sdram_open_pages_control (Offset 0x1414) SDRAM Open Pages Control
<byte 3808>
union sdram_operation (Offset 0x1418) SDRAM Operation
<byte 3808>
{field (By field)}
<byte 3808>
lbits:3 cmd RW DRAM Mode Select
lbits:29 reserved0 RES Reserved
{}
or sdram_operation (Offset 0x1418) SDRAM Operation
<byte 3808>
ulong value As longword
endunion sdram_operation (Offset 0x1418) SDRAM Operation
<byte 3812>
union sdram_mode (Offset 0x141C) SDRAM Mode
<byte 3812>
{field (By field)}
<byte 3812>
lbits:3 bl RW Burst Length
lbits:1 bt RW Burst Type/Init Val
lbits:3 cl RW CAS Latency
lbits:7 om RW Operation Mode
lbits:18 reserved0 RES Reserved
{}
or sdram_mode (Offset 0x141C) SDRAM Mode
<byte 3812>
ulong value As longword
endunion sdram_mode (Offset 0x141C) SDRAM Mode
<byte 3816>
union extsdram_mode (Offset 0x1420) Extended SDRAM Mode
<byte 3816>
{field (By field)}
<byte 3816>
lbits:1 dll RW DRAM DLL Enable
lbits:1 ds RW DRAM Drive Strength
lbits:1 qfc RW QFC Signal Enable
lbits:11 om RW Operation Mode
lbits:18 reserved0 RES Reserved
{}
or extsdram_mode (Offset 0x1420) Extended SDRAM Mode
<byte 3816>
ulong value As longword
endunion extsdram_mode (Offset 0x1420) Extended SDRAM Mode
<byte 3820>
union dunit_control_high (Offset 0x1424) Dunit Control (High)
<byte 3820>
{field (By field)}
<byte 3820>
lbits:4 wrbuff RW Reserved
lbits:4 rdbuff RW Reserved
lbits:4 txque RW Reserved
lbits:4 wrtrig RW Reserved
lbits:4 rdtrig RW Reserved
lbits:4 rmwtrig RW Reserved
lbits:1 snooppipe RW Snoops pipeline enable
lbits:4 snoopdepth RW Reserved
lbits:3 reserved0 RES Reserved
{}
or dunit_control_high (Offset 0x1424) Dunit Control (High)
<byte 3820>
ulong value As longword
endunion dunit_control_high (Offset 0x1424) Dunit Control (High)
<byte 3824>
union sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low)
<byte 3824>
{field (By field)}
<byte 3824>
lbits:4 arb0 RW Slice 0 of the device controller 'pizza' arbiter
lbits:4 arb1 RW Slice 1 of the device controller 'pizza' arbiter
lbits:4 arb2 RW Slice 2 of the device controller 'pizza' arbiter
lbits:4 arb3 RW Slice 3 of the device controller 'pizza' arbiter
lbits:4 arb4 RW Slice 4 of the device controller 'pizza' arbiter
lbits:4 arb5 RW Slice 5 of the device controller 'pizza' arbiter
lbits:4 arb6 RW Slice 6 of the device controller 'pizza' arbiter
lbits:4 arb7 RW Slice 7 of the device controller 'pizza' arbiter
{}
or sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low)
<byte 3824>
ulong value As longword
endunion sdram_interface_crossbar_control_low (Offset 0x1430) SDRAM Interface Crossbar Control (Low)
<byte 3828>
union sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossbar Control (High)
<byte 3828>
{field (By field)}
<byte 3828>
lbits:4 arb8 RW Slice 8 of the device controller 'pizza' arbiter
lbits:4 arb9 RW Slice 9 of the device controller 'pizza' arbiter
lbits:4 arb10 RW Slice 10 of the device controller 'pizza' arbiter
lbits:4 arb11 RW Slice 11 of the device controller 'pizza' arbiter
lbits:4 arb12 RW Slice 12 of the device controller 'pizza' arbiter
lbits:4 arb13 RW Slice 13 of the device controller 'pizza' arbiter
lbits:4 arb14 RW Slice 14 of the device controller 'pizza' arbiter
lbits:4 arb15 RW Slice 15 of the device controller 'pizza' arbiter
{}
or sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossbar Control (High)
<byte 3828>
ulong value As longword
endunion sdram_interface_crossbar_control_high (Offset 0x1434) SDRAM Interface Crossbar Control (High)
<byte 3832>
union sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout
<byte 3832>
{field (By field)}
<byte 3832>
lbits:8 timeout RW CrossBar Arbiter Timeout Preset Value
lbits:8 reserved1 RES Reserved
lbits:1 timeouten RW CrossBar Arbiter Timer Enable
lbits:15 reserved0 RES Reserved
{}
or sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout
<byte 3832>
ulong value As longword
endunion sdram_interface_crossbar_timeout (Offset 0x1438) SDRAM Interface Crossbar Timeout
<byte 3836>
union dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0
<byte 3836>
{field (By field)}
<byte 3836>
lbits:8 updwin RW The window size, after the refresh command, in which DFCDL update is allowed
lbits:5 reserved1 RES Reserved
lbits:1 forceupdsync RW Forces the delay line update as soon as DFCDL is synchronized
lbits:1 forceupdw RW Forces delay line update as soon as update window arrives
lbits:1 blockupd RW Disables delay line update (unless using ForceUpdSync or ForceUpdW bits)
lbits:1 updnosync RW Enables dynamic update without reaching sync condition
lbits:1 updnowin RW Enables dynamic update without reaching update window
lbits:1 forceacc RW Forces the filter state machine to accept bad values
lbits:9 maxdiff RW Maximum difference between consecutive updates Filtering is performed on values multiplied by 4
lbits:4 reserved0 RES Reserved
{}
or dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0
<byte 3836>
ulong value As longword
endunion dfcdl_configuration0 (Offset 0x1480) DFCDL Configuration0
<byte 3840>
union dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1
<byte 3840>
{field (By field)}
<byte 3840>
lbits:6 delpval RW Delay counter preset value
lbits:1 fourcell RW Delay unit selects
lbits:1 isense RW Multiply by two the value found by the search machine
lbits:6 phased RW Delay Counter Phase Delta
lbits:1 singlephase RW Search machine only searches for first phase
lbits:1 reserved1 RES Reserved
lbits:1 phasemode RW Phase Mode Jump
lbits:1 reserved0 RES Reserved
lbits:2 avg RW Average Value Calculation for Filter Process
lbits:2 goodhits RW For the sync machine to enter the previous sync state, the number of times the good value must be received after the bad value
lbits:2 goodsync RW For the sync machine to enter sync state, the number of times the good value must be received after loss of sync
lbits:1 forcesync RW Forces the sync machine to enter the sync state
lbits:1 holdsync RW Forces the sync machine to maintain this state
lbits:1 resync RW Forces the sync machine to enter a loss of sync state
lbits:2 avgrd RW Average used for read address of the SRAM
lbits:1 stopimid RW Forces the filter machine to enter stop state
lbits:1 stopsync RW Forces it to enter stop state, if there is sync condition
lbits:1 goinit RW Forces it to remain in this state
{}
or dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1
<byte 3840>
ulong value As longword
endunion dfcdl_configuration1 (Offset 0x1484) DFCDL Configuration1
<byte 3844>
union sram_address (Offset 0x1490) SRAM Address
<byte 3844>
{field (By field)}
<byte 3844>
lbits:32 addr RW SRAM address
{}
or sram_address (Offset 0x1490) SRAM Address
<byte 3844>
ulong value As longword
endunion sram_address (Offset 0x1490) SRAM Address
<byte 3848>
union sram_data0 (Offset 0x1494) SRAM Data0
<byte 3848>
{field (By field)}
<byte 3848>
lbits:32 data RW SRAM Write Data to initialize the DFCDL SRAM
{}
or sram_data0 (Offset 0x1494) SRAM Data0
<byte 3848>
ulong value As longword
endunion sram_data0 (Offset 0x1494) SRAM Data0
<byte 3852>
union dfcdl_probe (Offset 0x14A0) DFCDL Probe
<byte 3852>
{field (By field)}
<byte 3852>
lbits:4 bussel RW Select DFCDL bus to be probed
lbits:1 proben RW Probe Enabled
lbits:27 reserved0 RES Reserved
{}
or dfcdl_probe (Offset 0x14A0) DFCDL Probe
<byte 3852>
ulong value As longword
endunion dfcdl_probe (Offset 0x14A0) DFCDL Probe
<byte 3856>
union sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration
<byte 3856>
{field (By field)}
<byte 3856>
lbits:5 drvn RW Pad Nchannel Driving Strength
lbits:5 drvp RW Pad Pchannel Driving Strength
lbits:6 reserved1 RES Reserved, read only
lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength
lbits:5 lockn RO Final locked value of the Nchannel Driving Strength
lbits:5 lockp RO Final locked value of the Pchannel Driving Strength
lbits:4 reserved0 RES Reserved, read only
lbits:1 wren RW Write Enable CPU Pads Calibration register
{}
or sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration
<byte 3856>
ulong value As longword
endunion sdram_address_control_pads_calibration (Offset 0x14C0) SDRAM Address/Control Pads Calibration
<byte 3860>
union sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration
<byte 3860>
{field (By field)}
<byte 3860>
lbits:5 drvn RW Pad Nchannel Driving Strength
lbits:5 drvp RW Pad Pchannel Driving Strength
lbits:6 reserved1 RES Reserved, read only
lbits:1 tuneen RW Enables the dynamic tuning of pad driving strength
lbits:5 lockn RO Final locked value of the Nchannel Driving Strength
lbits:5 lockp RO Final locked value of the Pchannel Driving Strength
lbits:4 reserved0 RES Reserved, read only
lbits:1 wren RW Write Enable CPU Pads Calibration register
{}
or sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration
<byte 3860>
ulong value As longword
endunion sdram_data_pads_calibration (Offset 0x14C4) SDRAM Data Pads Calibration
<byte 3864>
union twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address
<byte 3864>
{field (By field)}
<byte 3864>
lbits:1 gce RW General Call Enable
lbits:7 saddr RW Slave address
lbits:24 reserved0 RES Reserved
{}
or twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address
<byte 3864>
ulong value As longword
endunion twsi_slave_address (Offset 0xC000) Two-Wire Serial Interface Slave Address
<byte 3868>
union twsi_data (Offset 0xC004) Two-Wire Serial Interface Data
<byte 3868>
{field (By field)}
<byte 3868>
lbits:8 data RW Data/Address byte to be transmitted by the TWSI master or slave, or data byte received
lbits:24 reserved0 RES Reserved
{}
or twsi_data (Offset 0xC004) Two-Wire Serial Interface Data
<byte 3868>
ulong value As longword
endunion twsi_data (Offset 0xC004) Two-Wire Serial Interface Data
<byte 3872>
union twsi_control (Offset 0xC008) Two-Wire Serial Interface Control
<byte 3872>
{field (By field)}
<byte 3872>
lbits:2 reserved1 RES Reserved, read only
lbits:1 ack RW Acknowledge
lbits:1 iflg RW Interrupt Flag
lbits:1 stop RW Stop
lbits:1 start RW Start
lbits:1 twsien RW TWSI enable
lbits:1 inten RW Interrupt Enable
lbits:24 reserved0 RES Reserved
{}
or twsi_control (Offset 0xC008) Two-Wire Serial Interface Control
<byte 3872>
ulong value As longword
endunion twsi_control (Offset 0xC008) Two-Wire Serial Interface Control
<byte 3876>
union twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate
<byte 3876>
{status (Status value)}
<byte 3876>
lbits:8 stat RO TWSI Status
lbits:24 reserved0 RES Reserved
{}
or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate
<byte 3876>
{br (Baud rate)}
<byte 3876>
lbits:3 n WO SCL frequency power of 2
lbits:4 m WO SCL frequency multiplier
lbits:25 reserved0 RES Reserved
{}
or twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate
<byte 3876>
ulong value As longword
endunion twsi_status_baud_rate (Offset 0xC00C) Two-Wire Serial Interface Status/Baud Rate
<byte 3880>
union twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extended Slave Address
<byte 3880>
{field (By field)}
<byte 3880>
lbits:8 saddr RW Bits[7:0] of the 10-bit slave address
lbits:24 reserved0 RES Reserved
{}
or twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extended Slave Address
<byte 3880>
ulong value As longword
endunion twsi_extended_slave_address (Offset 0xC010) Two-Wire Serial Interface Extended Slave Address
<byte 3884>
union twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset
<byte 3884>
{field (By field)}
<byte 3884>
lbits:32 rst WO Write to this register resets the TWSI logic and sets all TWSI registers to their reset values
{}
or twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset
<byte 3884>
ulong value As longword
endunion twsi_soft_reset (Offset 0xC01C) Two-Wire Serial Interface Soft Reset
{}
<byte 3888>
{atlantis_mcs (Atlantis machine check specific registers)}
<byte 3888>
union main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low)
<byte 3888>
{field (By field)}
<byte 3888>
lbits:1 reserved2 R Reserved
lbits:1 deverr R/CLL Device Bus Error
lbits:1 dmaerr R/CLL DMA Error
lbits:1 cpuerr R/CLL CPU Error
lbits:1 idma0 R/CLL IDMA Channel0 Completion
lbits:1 idma1 R/CLL IDMA Channel1 Completion
lbits:1 idma2 R/CLL IDMA Channel2 Completion
lbits:1 idma3 R/CLL IDMA Channel3 Completion
lbits:1 timer0 R/CLL Timer0
lbits:1 timer1 R/CLL Timer1
lbits:1 timer2 R/CLL Timer2
lbits:1 timer3 R/CLL Timer3
lbits:1 pci0 R/CLL PCI0
lbits:1 sramerr R/CLL SRAM Parity Error
lbits:1 gbeerr R/CLL Gb Ethernet Error
lbits:1 cerr R/CLL Serial Ports Error
lbits:1 pci1 R/CLL PCI1
lbits:1 dramerr R/CLL DRAM ECC Error
lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold
lbits:1 wde R/CLL WatchDog Reached Terminal Cnt
lbits:1 pci0in R/CLL PCI0 Inbound
lbits:1 pci0out R/CLL PCI0 Outbound
lbits:1 pci1in R/CLL PCI1 Inbound
lbits:1 pci1out R/CLL PCI1 Outbound
lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt
lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt
lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt
lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt
lbits:1 p1_cpu_db R/CLL CPU1 Doorbell
lbits:3 reserved1 R Reserved
{}
or main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low)
<byte 3888>
ulong value As longword
endunion main_interrupt_cause_low (Offset 0x0004) Main Interrupt Cause (Low)
<byte 3892>
union main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High)
<byte 3892>
{field (By field)}
<byte 3892>
lbits:1 ge0 R/CLL Gb Ethernet0
lbits:1 ge1 R/CLL Gb Ethernet1
lbits:1 ge2 R/CLL Gb Ethernet2
lbits:1 reserved3 R Reserved
lbits:1 sdma0 R/CLL MPSC0 SDMA
lbits:1 twsi R/CLL TWSI (I2C)
lbits:1 sdma1 R/CLL MPSC1 SDMA
lbits:1 brg R/CLL BRG
lbits:1 mpsc0 R/CLL MPSC0
lbits:1 mpsc1 R/CLL MPSC1
lbits:1 g0rx R/CLL Gb Ethernet0 Rx
lbits:1 g0tx R/CLL Gb Ethernet0 Tx
lbits:1 g0misc R/CLL Gb Ethernet0 Misc
lbits:1 g1rx R/CLL Gb Ethernet1 Rx
lbits:1 g1tx R/CLL Gb Ethernet1 Tx
lbits:1 g1misc R/CLL Gb Ethernet1 Misc
lbits:1 g2rx R/CLL Gb Ethernet2 Rx
lbits:1 g2tx R/CLL Gb Ethernet2 Tx
lbits:1 g2misc R/CLL Gb Ethernet2 Misc
lbits:5 reserved2 R Reserved
lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt
lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt
lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt
lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt
lbits:1 p0_cpu_db R/CLL CPU0 Doorbell
lbits:3 reserved1 R Reserved
{}
or main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High)
<byte 3892>
ulong value As longword
endunion main_interrupt_cause_high (Offset 0x000C) Main Interrupt Cause (High)
<byte 3896>
union cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low)
<byte 3896>
{field (By field)}
<byte 3896>
lbits:1 reserved2 R Reserved
lbits:1 deverr R/CLL Device Bus Error
lbits:1 dmaerr R/CLL DMA Error
lbits:1 cpuerr R/CLL CPU Error
lbits:1 idma0 R/CLL IDMA Channel0 Completion
lbits:1 idma1 R/CLL IDMA Channel1 Completion
lbits:1 idma2 R/CLL IDMA Channel2 Completion
lbits:1 idma3 R/CLL IDMA Channel3 Completion
lbits:1 timer0 R/CLL Timer0
lbits:1 timer1 R/CLL Timer1
lbits:1 timer2 R/CLL Timer2
lbits:1 timer3 R/CLL Timer3
lbits:1 pci0 R/CLL PCI0
lbits:1 sramerr R/CLL SRAM Parity Error
lbits:1 gbeerr R/CLL Gb Ethernet Error
lbits:1 cerr R/CLL Serial Ports Error
lbits:1 pci1 R/CLL PCI1
lbits:1 dramerr R/CLL DRAM ECC Error
lbits:1 wdnmi R/CLL WatchDog Reached NMI Threshold
lbits:1 wde R/CLL WatchDog Reached Terminal Cnt
lbits:1 pci0in R/CLL PCI0 Inbound
lbits:1 pci0out R/CLL PCI0 Outbound
lbits:1 pci1in R/CLL PCI1 Inbound
lbits:1 pci1out R/CLL PCI1 Outbound
lbits:1 p1_gpp0_7 R/CLL CPU1 GPP[7:0] Interrupt
lbits:1 p1_gpp8_15 R/CLL CPU1 GPP[15:8] Interrupt
lbits:1 p1_gpp16_23 R/CLL CPU1 GPP[23:16] Interrupt
lbits:1 p1_gpp24_31 R/CLL CPU1 GPP[24:31] Interrupt
lbits:1 p1_cpu_db R/CLL CPU1 Doorbell
lbits:3 reserved1 R Reserved
{}
or cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low)
<byte 3896>
ulong value As longword
endunion cpuint_0_mask_low (Offset 0x0014) CPUInt[0]# Mask (Low)
<byte 3900>
union cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High)
<byte 3900>
{field (By field)}
<byte 3900>
lbits:1 ge0 R/CLL Gb Ethernet0
lbits:1 ge1 R/CLL Gb Ethernet1
lbits:1 ge2 R/CLL Gb Ethernet2
lbits:1 reserved3 R Reserved
lbits:1 sdma0 R/CLL MPSC0 SDMA
lbits:1 twsi R/CLL TWSI (I2C)
lbits:1 sdma1 R/CLL MPSC1 SDMA
lbits:1 brg R/CLL BRG
lbits:1 mpsc0 R/CLL MPSC0
lbits:1 mpsc1 R/CLL MPSC1
lbits:1 g0rx R/CLL Gb Ethernet0 Rx
lbits:1 g0tx R/CLL Gb Ethernet0 Tx
lbits:1 g0misc R/CLL Gb Ethernet0 Misc
lbits:1 g1rx R/CLL Gb Ethernet1 Rx
lbits:1 g1tx R/CLL Gb Ethernet1 Tx
lbits:1 g1misc R/CLL Gb Ethernet1 Misc
lbits:1 g2rx R/CLL Gb Ethernet2 Rx
lbits:1 g2tx R/CLL Gb Ethernet2 Tx
lbits:1 g2misc R/CLL Gb Ethernet2 Misc
lbits:5 reserved2 R Reserved
lbits:1 p0_gpp0_7 R/CLL CPU0 GPP[7:0] Interrupt
lbits:1 p0_gpp8_15 R/CLL CPU0 GPP[15:8] Interrupt
lbits:1 p0_gpp16_23 R/CLL CPU0 GPP[23:16] Interrupt
lbits:1 p0_gpp24_31 R/CLL CPU0 GPP[24:31] Interrupt
lbits:1 p0_cpu_db R/CLL CPU0 Doorbell
lbits:3 reserved1 R Reserved
{}
or cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High)
<byte 3900>
ulong value As longword
endunion cpuint_0_mask_high (Offset 0x001C) CPUInt[0]# Mask (High)
<byte 3904>
union cpu_error_address_low (Offset 0x0070) CPU Error Address (Low)
<byte 3904>
{field (By field)}
<byte 3904>
lbits:32 erraddr RO Latched address bits [31:0] of a CPU transaction: illegal address (failed address decoding), access protection violation, bad data parity, bad address parity
{}
or cpu_error_address_low (Offset 0x0070) CPU Error Address (Low)
<byte 3904>
ulong value As longword
endunion cpu_error_address_low (Offset 0x0070) CPU Error Address (Low)
<byte 3908>
union cpu_error_address_high (Offset 0x0078) CPU Error Address (High)
<byte 3908>
{field (By field)}
<byte 3908>
lbits:4 erraddr_h R Error Address bits [35:32]
lbits:5 errpar R Address Parity bits
lbits:1 hit R 1=HIT# asserted (cached)
lbits:22 reserved R Reserved
{}
or cpu_error_address_high (Offset 0x0078) CPU Error Address (High)
<byte 3908>
ulong value As longword
endunion cpu_error_address_high (Offset 0x0078) CPU Error Address (High)
<byte 3912>
union cpu_error_data_low (Offset 0x0128) CPU Error Data (Low)
<byte 3912>
{field (By field)}
<byte 3912>
lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus
{}
or cpu_error_data_low (Offset 0x0128) CPU Error Data (Low)
<byte 3912>
ulong value As longword
endunion cpu_error_data_low (Offset 0x0128) CPU Error Data (Low)
<byte 3916>
union cpu_error_data_high (Offset 0x0130) CPU Error Data (High)
<byte 3916>
{field (By field)}
<byte 3916>
lbits:32 perrdata RO Latched data bits in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus
{}
or cpu_error_data_high (Offset 0x0130) CPU Error Data (High)
<byte 3916>
ulong value As longword
endunion cpu_error_data_high (Offset 0x0130) CPU Error Data (High)
<byte 3920>
union cpu_error_parity (Offset 0x0138) CPU Error Parity
<byte 3920>
{field (By field)}
<byte 3920>
lbits:8 perrpar RO Latched data parity bus in case of bad data parity sampled on write transactions or on master read transactions on the 60x bus
lbits:2 gronk ?? Atlantis spec. error, Table 273--these bits are not defined!!!
lbits:22 reserved0 RES Reserved
{}
or cpu_error_parity (Offset 0x0138) CPU Error Parity
<byte 3920>
ulong value As longword
endunion cpu_error_parity (Offset 0x0138) CPU Error Parity
<byte 3924>
union cpu_error_cause (Offset 0x0140) CPU Error Cause
<byte 3924>
{field (By field)}
<byte 3924>
lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs
lbits:1 addrperr R/W0C Bad Address Parity Detected
lbits:1 tterr R/W0C Transfer Type/Init Val Violation
lbits:1 accerr R/W0C Access to a Protected Region
lbits:1 wrerr R/W0C Write to a Wrt Protectd Region
lbits:1 cacheerr R/W0C Cache Rd, Caching Protected
lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected
lbits:1 rddataperr R/W0C Bad Read Data Parity Detected
lbits:19 reserved R Reserved
lbits:5 sel R Type of above error captured
{}
or cpu_error_cause (Offset 0x0140) CPU Error Cause
<byte 3924>
ulong value As longword
endunion cpu_error_cause (Offset 0x0140) CPU Error Cause
<byte 3928>
union cpu0_error_mask (Offset 0x0148) CPU0 Error Mask
<byte 3928>
{field (By field)}
<byte 3928>
lbits:1 addrout R/W0C CPU Address Out of Range in Addr, Data, Parity Err Regs
lbits:1 addrperr R/W0C Bad Address Parity Detected
lbits:1 tterr R/W0C Transfer Type/Init Val Violation
lbits:1 accerr R/W0C Access to a Protected Region
lbits:1 wrerr R/W0C Write to a Wrt Protectd Region
lbits:1 cacheerr R/W0C Cache Rd, Caching Protected
lbits:1 wrdataperr R/W0C Bad Write Data Parity Detected
lbits:1 rddataperr R/W0C Bad Read Data Parity Detected
lbits:19 reserved R Reserved
lbits:5 sel R Type of above error captured
{}
or cpu0_error_mask (Offset 0x0148) CPU0 Error Mask
<byte 3928>
ulong value As longword
endunion cpu0_error_mask (Offset 0x0148) CPU0 Error Mask
<byte 3932>
union sram_configuration (Offset 0x0380) SRAM Configuration
<byte 3932>
{field (By field)}
<byte 3932>
lbits:2 ccen R/W Cache Coherency Enable
lbits:2 reserved2 R Reserved
lbits:1 paren R/W Parity Enable (gen. & check)
lbits:1 perrpropen R/W Parity Error Propagate Enable
lbits:1 forceparen R/W Force Parity Enable (debug)
lbits:1 park R/W Arbiter Park on cross bar
lbits:8 forcepar R/W Forced Parity Byte Value
lbits:3 rtc R Reserved by Marvell (0x6)
lbits:2 wtc R Reserved by Marvell (0x2)
lbits:11 reserved1 R Reserved
{}
or sram_configuration (Offset 0x0380) SRAM Configuration
<byte 3932>
ulong value As longword
endunion sram_configuration (Offset 0x0380) SRAM Configuration
<byte 3936>
union sram_error_cause (Offset 0x0388) SRAM Error Cause
<byte 3936>
{field (By field)}
<byte 3936>
lbits:1 perr0_7 R/W0C Parity Error Byte [7:0]
lbits:1 perr8_15 R/W0C Parity Error Byte [15:8]
lbits:1 perr16_23 R/W0C Parity Error Byte [23:16]
lbits:1 perr24_31 R/W0C Parity Error Byte [31:24]
lbits:1 perr32_39 R/W0C Parity Error Byte [39:32]
lbits:1 perr40_47 R/W0C Parity Error Byte [47:40]
lbits:1 perr48_55 R/W0C Parity Error Byte [55:48]
lbits:1 perr56_63 R/W0C Parity Error Byte [63:56]
lbits:24 reserved R Reserved
{}
or sram_error_cause (Offset 0x0388) SRAM Error Cause
<byte 3936>
ulong value As longword
endunion sram_error_cause (Offset 0x0388) SRAM Error Cause
<byte 3940>
union sram_error_address (Offset 0x0390) SRAM Error Address
<byte 3940>
{field (By field)}
<byte 3940>
lbits:32 addr RW Error Address bits[31:0]
{}
or sram_error_address (Offset 0x0390) SRAM Error Address
<byte 3940>
ulong value As longword
endunion sram_error_address (Offset 0x0390) SRAM Error Address
<byte 3944>
union sram_error_data_low (Offset 0x0398) SRAM Error Data (Low)
<byte 3944>
{field (By field)}
<byte 3944>
lbits:32 data RW Error data
{}
or sram_error_data_low (Offset 0x0398) SRAM Error Data (Low)
<byte 3944>
ulong value As longword
endunion sram_error_data_low (Offset 0x0398) SRAM Error Data (Low)
<byte 3948>
union sram_error_data_high (Offset 0x03A0) SRAM Error Data (High)
<byte 3948>
{field (By field)}
<byte 3948>
lbits:32 data RW Error data
{}
or sram_error_data_high (Offset 0x03A0) SRAM Error Data (High)
<byte 3948>
ulong value As longword
endunion sram_error_data_high (Offset 0x03A0) SRAM Error Data (High)
<byte 3952>
union sram_error_parity (Offset 0x03A8) SRAM Error Parity
<byte 3952>
{field (By field)}
<byte 3952>
lbits:8 par RW Error parity
lbits:24 reserved0 RES Reserved
{}
or sram_error_parity (Offset 0x03A8) SRAM Error Parity
<byte 3952>
ulong value As longword
endunion sram_error_parity (Offset 0x03A8) SRAM Error Parity
<byte 3956>
union sram_error_address_high (Offset 0x03F8) SRAM Error Address (High)
<byte 3956>
{field (By field)}
<byte 3956>
lbits:4 addr RW Error Address bits[35:32] Latched upon SRAM parity error detection
lbits:28 reserved0 RES Reserved
{}
or sram_error_address_high (Offset 0x03F8) SRAM Error Address (High)
<byte 3956>
ulong value As longword
endunion sram_error_address_high (Offset 0x03F8) SRAM Error Address (High)
<byte 3960>
union device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause
<byte 3960>
{field (By field)}
<byte 3960>
lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs
lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug)
lbits:1 perr0 R/W0C Parity Error 0
lbits:1 perr1 R/W0C Parity Error 1
lbits:1 perr2 R/W0C Parity Error 2
lbits:1 perr3 R/W0C Parity Error 3
lbits:21 reserved R Reserved
lbits:5 sel R Type of above error captured
{}
or device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause
<byte 3960>
ulong value As longword
endunion device_interrupt_cause (Offset 0x04D0) Device Interrupt Cause
<byte 3964>
union device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask
<byte 3964>
{field (By field)}
<byte 3964>
lbits:1 dbursterr R/W0C Forced ECC Byte Value in Addr, Data, Parity Err Regs
lbits:1 drdyerr R/W0C Write 'forceecc' Enable (debug)
lbits:1 perr0 R/W0C Parity Error 0
lbits:1 perr1 R/W0C Parity Error 1
lbits:1 perr2 R/W0C Parity Error 2
lbits:1 perr3 R/W0C Parity Error 3
lbits:21 reserved R Reserved
lbits:5 sel R Type of above error captured
{}
or device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask
<byte 3964>
ulong value As longword
endunion device_interrupt_mask (Offset 0x04D4) Device Interrupt Mask
<byte 3968>
union device_error_address (Offset 0x04D8) Device Error Address
<byte 3968>
{field (By field)}
<byte 3968>
lbits:32 addr RW Latched Address Upon Device Error Condition
{}
or device_error_address (Offset 0x04D8) Device Error Address
<byte 3968>
ulong value As longword
endunion device_error_address (Offset 0x04D8) Device Error Address
<byte 3972>
union device_error_data (Offset 0x04DC) Device Error Data
<byte 3972>
{field (By field)}
<byte 3972>
lbits:32 data RW Latched data upon parity error detection
{}
or device_error_data (Offset 0x04DC) Device Error Data
<byte 3972>
ulong value As longword
endunion device_error_data (Offset 0x04DC) Device Error Data
<byte 3976>
union device_error_parity (Offset 0x04E0) Device Error Parity
<byte 3976>
{field (By field)}
<byte 3976>
lbits:4 par RW Latched parity upon parity error detection
lbits:28 reserved0 RES Reserved, read only
{}
or device_error_parity (Offset 0x04E0) Device Error Parity
<byte 3976>
ulong value As longword
endunion device_error_parity (Offset 0x04E0) Device Error Parity
<byte 3980>
union idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause
<byte 3980>
{field (By field)}
<byte 3980>
lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete
lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode
lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation
lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation
lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation
lbits:3 reserved0 R Reserved
lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete
lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode
lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation
lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation
lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation
lbits:3 reserved1 R Reserved
lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete
lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode
lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation
lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation
lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation
lbits:3 reserved2 R Reserved
lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete
lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode
lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation
lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation
lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation
lbits:3 reserved3 R Reserved
{}
or idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause
<byte 3980>
ulong value As longword
endunion idma_interrupt_cause (Offset 0x08C0) IDMA Interrupt Cause
<byte 3984>
union idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask
<byte 3984>
{field (By field)}
<byte 3984>
lbits:1 dmacmplt0 R/W0C Channel 0 DMA Complete
lbits:1 addrmiss0 R/W0C Channel 0 Address Miss, Failed Decode
lbits:1 accprot0 R/W0C Channel 0 Access Protect Violation
lbits:1 wrprot0 R/W0C Channel 0 Write Protect Violation
lbits:1 own0 R/W0C Channel 0 Descriptor Ownership Violation
lbits:3 reserved0 R Reserved
lbits:1 dmacmplt1 R/W0C Channel 1 DMA Complete
lbits:1 addrmiss1 R/W0C Channel 1 Address Miss, Failed Decode
lbits:1 accprot1 R/W0C Channel 1 Access Protect Violation
lbits:1 wrprot1 R/W0C Channel 1 Write Protect Violation
lbits:1 own1 R/W0C Channel 1 Descriptor Ownership Violation
lbits:3 reserved1 R Reserved
lbits:1 dmacmplt2 R/W0C Channel 2 DMA Complete
lbits:1 addrmiss2 R/W0C Channel 2 Address Miss, Failed Decode
lbits:1 accprot2 R/W0C Channel 2 Access Protect Violation
lbits:1 wrprot2 R/W0C Channel 2 Write Protect Violation
lbits:1 own2 R/W0C Channel 2 Descriptor Ownership Violation
lbits:3 reserved2 R Reserved
lbits:1 dmacmplt3 R/W0C Channel 3 DMA Complete
lbits:1 addrmiss3 R/W0C Channel 3 Address Miss, Failed Decode
lbits:1 accprot3 R/W0C Channel 3 Access Protect Violation
lbits:1 wrprot3 R/W0C Channel 3 Write Protect Violation
lbits:1 own3 R/W0C Channel 3 Descriptor Ownership Violation
lbits:3 reserved3 R Reserved
{}
or idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask
<byte 3984>
ulong value As longword
endunion idma_interrupt_mask (Offset 0x08C4) IDMA Interrupt Mask
<byte 3988>
union idma_error_address (Offset 0x08C8) IDMA Error Address
<byte 3988>
{field (By field)}
<byte 3988>
lbits:32 erraddr RW Bits[31:0] of Error Address
{}
or idma_error_address (Offset 0x08C8) IDMA Error Address
<byte 3988>
ulong value As longword
endunion idma_error_address (Offset 0x08C8) IDMA Error Address
<byte 3992>
union sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High)
<byte 3992>
{field (By field)}
<byte 3992>
lbits:32 eccdata RW Sampled 32 high bits of the last data with ECC error
{}
or sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High)
<byte 3992>
ulong value As longword
endunion sdram_error_data_high (Offset 0x1440) SDRAM Error Data (High)
<byte 3996>
union sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low)
<byte 3996>
{field (By field)}
<byte 3996>
lbits:32 eccdata RW Sampled 32 low bits of the last data with ECC error
{}
or sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low)
<byte 3996>
ulong value As longword
endunion sdram_error_data_low (Offset 0x1444) SDRAM Error Data (Low)
<byte 4000>
union sdram_received_ecc (Offset 0x1448) SDRAM Received ECC
<byte 4000>
{field (By field)}
<byte 4000>
lbits:8 eccreg RW ECC code being read from SDRAM
lbits:24 reserved0 RES Reserved
{}
or sdram_received_ecc (Offset 0x1448) SDRAM Received ECC
<byte 4000>
ulong value As longword
endunion sdram_received_ecc (Offset 0x1448) SDRAM Received ECC
<byte 4004>
union sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC
<byte 4004>
{field (By field)}
<byte 4004>
lbits:8 ecccalc RW ECC code calculated by Dunit
lbits:24 reserved0 RES Reserved
{}
or sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC
<byte 4004>
ulong value As longword
endunion sdram_calculated_ecc (Offset 0x144C) SDRAM Calculated ECC
<byte 4008>
union sdram_error_address (Offset 0x1450) SDRAM Error Address
<byte 4008>
{field (By field /* NOTE: WOC just clears the dramerr)}
<byte 4008>
lbits:1 errtype R/W0C Err Type (0=CDEs>limit, 1=UDE)
lbits:2 bank R/W0C DIMM Bank (0-3)
lbits:29 eccaddr R/W0C Address of Error [31:3] (NOTE: Atlantis spec. error, Table 303--indicates this field is 30 bits [31:2]; changed to 29 bits [31:3])
{}
or sdram_error_address (Offset 0x1450) SDRAM Error Address
<byte 4008>
ulong value As longword /* bit in the lower cause reg.
endunion sdram_error_address (Offset 0x1450) SDRAM Error Address
<byte 4012>
union sdram_ecc_control (Offset 0x1454) SDRAM ECC Control
<byte 4012>
{field (By field)}
<byte 4012>
lbits:8 forceecc R/W Forced ECC Byte Value
lbits:1 forceeccen R/W Write 'forceecc' Enable (debug)
lbits:1 perrpropen R/W Propagate PERR to ECC mem. Err
lbits:6 reserved2 R Reserved
lbits:8 threcc R/W Threshold for reporting CDEs
lbits:8 reserved1 R Reserved
{}
or sdram_ecc_control (Offset 0x1454) SDRAM ECC Control
<byte 4012>
ulong value As longword
endunion sdram_ecc_control (Offset 0x1454) SDRAM ECC Control
<byte 4016>
union sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter
<byte 4016>
{field (By field)}
<byte 4016>
lbits:32 count R Number of single bit ECC errors detected
{}
or sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter
<byte 4016>
ulong value As longword
endunion sdram_ecc_counter (Offset 0x1458) SDRAM ECC Counter
{}
<byte 4020>
{decoder (Decoder)}
<byte 4020>
{rsvd (03 Reserved)}
<byte 4020>
utiny value
{}
<byte 4021>
union gpo_c 02 GPO C: Enet Card Reset..
<byte 4021>
{field (By field)}
<byte 4021>
tbits:7 rsvd R Reserved
tbits:1 enet_card_rst R/W Ethernet Card Reset
{}
or gpo_c 02 GPO C: Enet Card Reset..
<byte 4021>
utiny value As utiny
endunion gpo_c 02 GPO C: Enet Card Reset..
<byte 4022>
union gpi 01 GPI B: Module Type..
<byte 4022>
{field (By field)}
<byte 4022>
tbits:4 mod_type R Module Type
tbits:3 rsvd R Reserved
tbits:1 enet_gpi R/W Ethernet Card GPI
{}
or gpi 01 GPI B: Module Type..
<byte 4022>
utiny value As utiny
endunion gpi 01 GPI B: Module Type..
<byte 4023>
union mod_rev 00 GPI A: Module Revision
<byte 4023>
{field (By field)}
<byte 4023>
tbits:3 rev R Revision
tbits:5 eco_level R ECO Level
{}
or mod_rev 00 GPI A: Module Revision
<byte 4023>
utiny value As utiny
endunion mod_rev 00 GPI A: Module Revision
<byte 4024>
{rsvd1[1] (06-FC Reserved)}
<byte 4024>
utiny value
{}
<byte 4025>
{rsvd1[0] (06-FC Reserved)}
<byte 4025>
utiny value
{}
<byte 4026>
union gpo_bstat1 05 GPO E: Boot Status LEDs..
<byte 4026>
{field (By field)}
<byte 4026>
tbits:1 led8 R/W Boot Status LED 8
tbits:1 led9 R/W Boot Status LED 9
tbits:6 rsvd R Reserved
{}
or gpo_bstat1 05 GPO E: Boot Status LEDs..
<byte 4026>
utiny value As utiny
endunion gpo_bstat1 05 GPO E: Boot Status LEDs..
<byte 4027>
union bstat0 04 GPO D: Boot Status LEDs
<byte 4027>
{field (By field)}
<byte 4027>
tbits:1 led0 R/W Boot Status LED 8
tbits:1 led1 R/W Boot Status LED 9
tbits:1 led2 R/W Boot Status LED 9
tbits:1 led3 R/W Boot Status LED 9
tbits:1 led4 R/W Boot Status LED 9
tbits:1 led5 R/W Boot Status LED 9
tbits:1 led6 R/W Boot Status LED 9
tbits:1 led7 R/W Boot Status LED 9
{}
or bstat0 04 GPO D: Boot Status LEDs
<byte 4027>
utiny value As utiny
endunion bstat0 04 GPO D: Boot Status LEDs
<byte 4028>
{rsvd1[5] (06-FC Reserved)}
<byte 4028>
utiny value
{}
<byte 4029>
{rsvd1[4] (06-FC Reserved)}
<byte 4029>
utiny value
{}
<byte 4030>
{rsvd1[3] (06-FC Reserved)}
<byte 4030>
utiny value
{}
<byte 4031>
{rsvd1[2] (06-FC Reserved)}
<byte 4031>
utiny value
{}
<byte 4032>
{rsvd1[9] (06-FC Reserved)}
<byte 4032>
utiny value
{}
<byte 4033>
{rsvd1[8] (06-FC Reserved)}
<byte 4033>
utiny value
{}
<byte 4034>
{rsvd1[7] (06-FC Reserved)}
<byte 4034>
utiny value
{}
<byte 4035>
{rsvd1[6] (06-FC Reserved)}
<byte 4035>
utiny value
{}
<byte 4036>
{rsvd1[13] (06-FC Reserved)}
<byte 4036>
utiny value
{}
<byte 4037>
{rsvd1[12] (06-FC Reserved)}
<byte 4037>
utiny value
{}
<byte 4038>
{rsvd1[11] (06-FC Reserved)}
<byte 4038>
utiny value
{}
<byte 4039>
{rsvd1[10] (06-FC Reserved)}
<byte 4039>
utiny value
{}
<byte 4040>
{rsvd1[17] (06-FC Reserved)}
<byte 4040>
utiny value
{}
<byte 4041>
{rsvd1[16] (06-FC Reserved)}
<byte 4041>
utiny value
{}
<byte 4042>
{rsvd1[15] (06-FC Reserved)}
<byte 4042>
utiny value
{}
<byte 4043>
{rsvd1[14] (06-FC Reserved)}
<byte 4043>
utiny value
{}
<byte 4044>
{rsvd1[21] (06-FC Reserved)}
<byte 4044>
utiny value
{}
<byte 4045>
{rsvd1[20] (06-FC Reserved)}
<byte 4045>
utiny value
{}
<byte 4046>
{rsvd1[19] (06-FC Reserved)}
<byte 4046>
utiny value
{}
<byte 4047>
{rsvd1[18] (06-FC Reserved)}
<byte 4047>
utiny value
{}
<byte 4048>
{rsvd1[25] (06-FC Reserved)}
<byte 4048>
utiny value
{}
<byte 4049>
{rsvd1[24] (06-FC Reserved)}
<byte 4049>
utiny value
{}
<byte 4050>
{rsvd1[23] (06-FC Reserved)}
<byte 4050>
utiny value
{}
<byte 4051>
{rsvd1[22] (06-FC Reserved)}
<byte 4051>
utiny value
{}
<byte 4052>
{rsvd1[29] (06-FC Reserved)}
<byte 4052>
utiny value
{}
<byte 4053>
{rsvd1[28] (06-FC Reserved)}
<byte 4053>
utiny value
{}
<byte 4054>
{rsvd1[27] (06-FC Reserved)}
<byte 4054>
utiny value
{}
<byte 4055>
{rsvd1[26] (06-FC Reserved)}
<byte 4055>
utiny value
{}
<byte 4056>
{rsvd1[33] (06-FC Reserved)}
<byte 4056>
utiny value
{}
<byte 4057>
{rsvd1[32] (06-FC Reserved)}
<byte 4057>
utiny value
{}
<byte 4058>
{rsvd1[31] (06-FC Reserved)}
<byte 4058>
utiny value
{}
<byte 4059>
{rsvd1[30] (06-FC Reserved)}
<byte 4059>
utiny value
{}
<byte 4060>
{rsvd1[37] (06-FC Reserved)}
<byte 4060>
utiny value
{}
<byte 4061>
{rsvd1[36] (06-FC Reserved)}
<byte 4061>
utiny value
{}
<byte 4062>
{rsvd1[35] (06-FC Reserved)}
<byte 4062>
utiny value
{}
<byte 4063>
{rsvd1[34] (06-FC Reserved)}
<byte 4063>
utiny value
{}
<byte 4064>
{rsvd1[41] (06-FC Reserved)}
<byte 4064>
utiny value
{}
<byte 4065>
{rsvd1[40] (06-FC Reserved)}
<byte 4065>
utiny value
{}
<byte 4066>
{rsvd1[39] (06-FC Reserved)}
<byte 4066>
utiny value
{}
<byte 4067>
{rsvd1[38] (06-FC Reserved)}
<byte 4067>
utiny value
{}
<byte 4068>
{rsvd1[45] (06-FC Reserved)}
<byte 4068>
utiny value
{}
<byte 4069>
{rsvd1[44] (06-FC Reserved)}
<byte 4069>
utiny value
{}
<byte 4070>
{rsvd1[43] (06-FC Reserved)}
<byte 4070>
utiny value
{}
<byte 4071>
{rsvd1[42] (06-FC Reserved)}
<byte 4071>
utiny value
{}
<byte 4072>
{rsvd1[49] (06-FC Reserved)}
<byte 4072>
utiny value
{}
<byte 4073>
{rsvd1[48] (06-FC Reserved)}
<byte 4073>
utiny value
{}
<byte 4074>
{rsvd1[47] (06-FC Reserved)}
<byte 4074>
utiny value
{}
<byte 4075>
{rsvd1[46] (06-FC Reserved)}
<byte 4075>
utiny value
{}
<byte 4076>
{rsvd1[53] (06-FC Reserved)}
<byte 4076>
utiny value
{}
<byte 4077>
{rsvd1[52] (06-FC Reserved)}
<byte 4077>
utiny value
{}
<byte 4078>
{rsvd1[51] (06-FC Reserved)}
<byte 4078>
utiny value
{}
<byte 4079>
{rsvd1[50] (06-FC Reserved)}
<byte 4079>
utiny value
{}
<byte 4080>
{rsvd1[57] (06-FC Reserved)}
<byte 4080>
utiny value
{}
<byte 4081>
{rsvd1[56] (06-FC Reserved)}
<byte 4081>
utiny value
{}
<byte 4082>
{rsvd1[55] (06-FC Reserved)}
<byte 4082>
utiny value
{}
<byte 4083>
{rsvd1[54] (06-FC Reserved)}
<byte 4083>
utiny value
{}
<byte 4084>
{rsvd1[61] (06-FC Reserved)}
<byte 4084>
utiny value
{}
<byte 4085>
{rsvd1[60] (06-FC Reserved)}
<byte 4085>
utiny value
{}
<byte 4086>
{rsvd1[59] (06-FC Reserved)}
<byte 4086>
utiny value
{}
<byte 4087>
{rsvd1[58] (06-FC Reserved)}
<byte 4087>
utiny value
{}
<byte 4088>
{rsvd1[65] (06-FC Reserved)}
<byte 4088>
utiny value
{}
<byte 4089>
{rsvd1[64] (06-FC Reserved)}
<byte 4089>
utiny value
{}
<byte 4090>
{rsvd1[63] (06-FC Reserved)}
<byte 4090>
utiny value
{}
<byte 4091>
{rsvd1[62] (06-FC Reserved)}
<byte 4091>
utiny value
{}
<byte 4092>
{rsvd1[69] (06-FC Reserved)}
<byte 4092>
utiny value
{}
<byte 4093>
{rsvd1[68] (06-FC Reserved)}
<byte 4093>
utiny value
{}
<byte 4094>
{rsvd1[67] (06-FC Reserved)}
<byte 4094>
utiny value
{}
<byte 4095>
{rsvd1[66] (06-FC Reserved)}
<byte 4095>
utiny value
{}
<byte 4096>
{rsvd1[73] (06-FC Reserved)}
<byte 4096>
utiny value
{}
<byte 4097>
{rsvd1[72] (06-FC Reserved)}
<byte 4097>
utiny value
{}
<byte 4098>
{rsvd1[71] (06-FC Reserved)}
<byte 4098>
utiny value
{}
<byte 4099>
{rsvd1[70] (06-FC Reserved)}
<byte 4099>
utiny value
{}
<byte 4100>
{rsvd1[77] (06-FC Reserved)}
<byte 4100>
utiny value
{}
<byte 4101>
{rsvd1[76] (06-FC Reserved)}
<byte 4101>
utiny value
{}
<byte 4102>
{rsvd1[75] (06-FC Reserved)}
<byte 4102>
utiny value
{}
<byte 4103>
{rsvd1[74] (06-FC Reserved)}
<byte 4103>
utiny value
{}
<byte 4104>
{rsvd1[81] (06-FC Reserved)}
<byte 4104>
utiny value
{}
<byte 4105>
{rsvd1[80] (06-FC Reserved)}
<byte 4105>
utiny value
{}
<byte 4106>
{rsvd1[79] (06-FC Reserved)}
<byte 4106>
utiny value
{}
<byte 4107>
{rsvd1[78] (06-FC Reserved)}
<byte 4107>
utiny value
{}
<byte 4108>
{rsvd1[85] (06-FC Reserved)}
<byte 4108>
utiny value
{}
<byte 4109>
{rsvd1[84] (06-FC Reserved)}
<byte 4109>
utiny value
{}
<byte 4110>
{rsvd1[83] (06-FC Reserved)}
<byte 4110>
utiny value
{}
<byte 4111>
{rsvd1[82] (06-FC Reserved)}
<byte 4111>
utiny value
{}
<byte 4112>
{rsvd1[89] (06-FC Reserved)}
<byte 4112>
utiny value
{}
<byte 4113>
{rsvd1[88] (06-FC Reserved)}
<byte 4113>
utiny value
{}
<byte 4114>
{rsvd1[87] (06-FC Reserved)}
<byte 4114>
utiny value
{}
<byte 4115>
{rsvd1[86] (06-FC Reserved)}
<byte 4115>
utiny value
{}
<byte 4116>
{rsvd1[93] (06-FC Reserved)}
<byte 4116>
utiny value
{}
<byte 4117>
{rsvd1[92] (06-FC Reserved)}
<byte 4117>
utiny value
{}
<byte 4118>
{rsvd1[91] (06-FC Reserved)}
<byte 4118>
utiny value
{}
<byte 4119>
{rsvd1[90] (06-FC Reserved)}
<byte 4119>
utiny value
{}
<byte 4120>
{rsvd1[97] (06-FC Reserved)}
<byte 4120>
utiny value
{}
<byte 4121>
{rsvd1[96] (06-FC Reserved)}
<byte 4121>
utiny value
{}
<byte 4122>
{rsvd1[95] (06-FC Reserved)}
<byte 4122>
utiny value
{}
<byte 4123>
{rsvd1[94] (06-FC Reserved)}
<byte 4123>
utiny value
{}
<byte 4124>
{rsvd1[101] (06-FC Reserved)}
<byte 4124>
utiny value
{}
<byte 4125>
{rsvd1[100] (06-FC Reserved)}
<byte 4125>
utiny value
{}
<byte 4126>
{rsvd1[99] (06-FC Reserved)}
<byte 4126>
utiny value
{}
<byte 4127>
{rsvd1[98] (06-FC Reserved)}
<byte 4127>
utiny value
{}
<byte 4128>
{rsvd1[105] (06-FC Reserved)}
<byte 4128>
utiny value
{}
<byte 4129>
{rsvd1[104] (06-FC Reserved)}
<byte 4129>
utiny value
{}
<byte 4130>
{rsvd1[103] (06-FC Reserved)}
<byte 4130>
utiny value
{}
<byte 4131>
{rsvd1[102] (06-FC Reserved)}
<byte 4131>
utiny value
{}
<byte 4132>
{rsvd1[109] (06-FC Reserved)}
<byte 4132>
utiny value
{}
<byte 4133>
{rsvd1[108] (06-FC Reserved)}
<byte 4133>
utiny value
{}
<byte 4134>
{rsvd1[107] (06-FC Reserved)}
<byte 4134>
utiny value
{}
<byte 4135>
{rsvd1[106] (06-FC Reserved)}
<byte 4135>
utiny value
{}
<byte 4136>
{rsvd1[113] (06-FC Reserved)}
<byte 4136>
utiny value
{}
<byte 4137>
{rsvd1[112] (06-FC Reserved)}
<byte 4137>
utiny value
{}
<byte 4138>
{rsvd1[111] (06-FC Reserved)}
<byte 4138>
utiny value
{}
<byte 4139>
{rsvd1[110] (06-FC Reserved)}
<byte 4139>
utiny value
{}
<byte 4140>
{rsvd1[117] (06-FC Reserved)}
<byte 4140>
utiny value
{}
<byte 4141>
{rsvd1[116] (06-FC Reserved)}
<byte 4141>
utiny value
{}
<byte 4142>
{rsvd1[115] (06-FC Reserved)}
<byte 4142>
utiny value
{}
<byte 4143>
{rsvd1[114] (06-FC Reserved)}
<byte 4143>
utiny value
{}
<byte 4144>
{rsvd1[121] (06-FC Reserved)}
<byte 4144>
utiny value
{}
<byte 4145>
{rsvd1[120] (06-FC Reserved)}
<byte 4145>
utiny value
{}
<byte 4146>
{rsvd1[119] (06-FC Reserved)}
<byte 4146>
utiny value
{}
<byte 4147>
{rsvd1[118] (06-FC Reserved)}
<byte 4147>
utiny value
{}
<byte 4148>
{rsvd1[125] (06-FC Reserved)}
<byte 4148>
utiny value
{}
<byte 4149>
{rsvd1[124] (06-FC Reserved)}
<byte 4149>
utiny value
{}
<byte 4150>
{rsvd1[123] (06-FC Reserved)}
<byte 4150>
utiny value
{}
<byte 4151>
{rsvd1[122] (06-FC Reserved)}
<byte 4151>
utiny value
{}
<byte 4152>
{rsvd1[129] (06-FC Reserved)}
<byte 4152>
utiny value
{}
<byte 4153>
{rsvd1[128] (06-FC Reserved)}
<byte 4153>
utiny value
{}
<byte 4154>
{rsvd1[127] (06-FC Reserved)}
<byte 4154>
utiny value
{}
<byte 4155>
{rsvd1[126] (06-FC Reserved)}
<byte 4155>
utiny value
{}
<byte 4156>
{rsvd1[133] (06-FC Reserved)}
<byte 4156>
utiny value
{}
<byte 4157>
{rsvd1[132] (06-FC Reserved)}
<byte 4157>
utiny value
{}
<byte 4158>
{rsvd1[131] (06-FC Reserved)}
<byte 4158>
utiny value
{}
<byte 4159>
{rsvd1[130] (06-FC Reserved)}
<byte 4159>
utiny value
{}
<byte 4160>
{rsvd1[137] (06-FC Reserved)}
<byte 4160>
utiny value
{}
<byte 4161>
{rsvd1[136] (06-FC Reserved)}
<byte 4161>
utiny value
{}
<byte 4162>
{rsvd1[135] (06-FC Reserved)}
<byte 4162>
utiny value
{}
<byte 4163>
{rsvd1[134] (06-FC Reserved)}
<byte 4163>
utiny value
{}
<byte 4164>
{rsvd1[141] (06-FC Reserved)}
<byte 4164>
utiny value
{}
<byte 4165>
{rsvd1[140] (06-FC Reserved)}
<byte 4165>
utiny value
{}
<byte 4166>
{rsvd1[139] (06-FC Reserved)}
<byte 4166>
utiny value
{}
<byte 4167>
{rsvd1[138] (06-FC Reserved)}
<byte 4167>
utiny value
{}
<byte 4168>
{rsvd1[145] (06-FC Reserved)}
<byte 4168>
utiny value
{}
<byte 4169>
{rsvd1[144] (06-FC Reserved)}
<byte 4169>
utiny value
{}
<byte 4170>
{rsvd1[143] (06-FC Reserved)}
<byte 4170>
utiny value
{}
<byte 4171>
{rsvd1[142] (06-FC Reserved)}
<byte 4171>
utiny value
{}
<byte 4172>
{rsvd1[149] (06-FC Reserved)}
<byte 4172>
utiny value
{}
<byte 4173>
{rsvd1[148] (06-FC Reserved)}
<byte 4173>
utiny value
{}
<byte 4174>
{rsvd1[147] (06-FC Reserved)}
<byte 4174>
utiny value
{}
<byte 4175>
{rsvd1[146] (06-FC Reserved)}
<byte 4175>
utiny value
{}
<byte 4176>
{rsvd1[153] (06-FC Reserved)}
<byte 4176>
utiny value
{}
<byte 4177>
{rsvd1[152] (06-FC Reserved)}
<byte 4177>
utiny value
{}
<byte 4178>
{rsvd1[151] (06-FC Reserved)}
<byte 4178>
utiny value
{}
<byte 4179>
{rsvd1[150] (06-FC Reserved)}
<byte 4179>
utiny value
{}
<byte 4180>
{rsvd1[157] (06-FC Reserved)}
<byte 4180>
utiny value
{}
<byte 4181>
{rsvd1[156] (06-FC Reserved)}
<byte 4181>
utiny value
{}
<byte 4182>
{rsvd1[155] (06-FC Reserved)}
<byte 4182>
utiny value
{}
<byte 4183>
{rsvd1[154] (06-FC Reserved)}
<byte 4183>
utiny value
{}
<byte 4184>
{rsvd1[161] (06-FC Reserved)}
<byte 4184>
utiny value
{}
<byte 4185>
{rsvd1[160] (06-FC Reserved)}
<byte 4185>
utiny value
{}
<byte 4186>
{rsvd1[159] (06-FC Reserved)}
<byte 4186>
utiny value
{}
<byte 4187>
{rsvd1[158] (06-FC Reserved)}
<byte 4187>
utiny value
{}
<byte 4188>
{rsvd1[165] (06-FC Reserved)}
<byte 4188>
utiny value
{}
<byte 4189>
{rsvd1[164] (06-FC Reserved)}
<byte 4189>
utiny value
{}
<byte 4190>
{rsvd1[163] (06-FC Reserved)}
<byte 4190>
utiny value
{}
<byte 4191>
{rsvd1[162] (06-FC Reserved)}
<byte 4191>
utiny value
{}
<byte 4192>
{rsvd1[169] (06-FC Reserved)}
<byte 4192>
utiny value
{}
<byte 4193>
{rsvd1[168] (06-FC Reserved)}
<byte 4193>
utiny value
{}
<byte 4194>
{rsvd1[167] (06-FC Reserved)}
<byte 4194>
utiny value
{}
<byte 4195>
{rsvd1[166] (06-FC Reserved)}
<byte 4195>
utiny value
{}
<byte 4196>
{rsvd1[173] (06-FC Reserved)}
<byte 4196>
utiny value
{}
<byte 4197>
{rsvd1[172] (06-FC Reserved)}
<byte 4197>
utiny value
{}
<byte 4198>
{rsvd1[171] (06-FC Reserved)}
<byte 4198>
utiny value
{}
<byte 4199>
{rsvd1[170] (06-FC Reserved)}
<byte 4199>
utiny value
{}
<byte 4200>
{rsvd1[177] (06-FC Reserved)}
<byte 4200>
utiny value
{}
<byte 4201>
{rsvd1[176] (06-FC Reserved)}
<byte 4201>
utiny value
{}
<byte 4202>
{rsvd1[175] (06-FC Reserved)}
<byte 4202>
utiny value
{}
<byte 4203>
{rsvd1[174] (06-FC Reserved)}
<byte 4203>
utiny value
{}
<byte 4204>
{rsvd1[181] (06-FC Reserved)}
<byte 4204>
utiny value
{}
<byte 4205>
{rsvd1[180] (06-FC Reserved)}
<byte 4205>
utiny value
{}
<byte 4206>
{rsvd1[179] (06-FC Reserved)}
<byte 4206>
utiny value
{}
<byte 4207>
{rsvd1[178] (06-FC Reserved)}
<byte 4207>
utiny value
{}
<byte 4208>
{rsvd1[185] (06-FC Reserved)}
<byte 4208>
utiny value
{}
<byte 4209>
{rsvd1[184] (06-FC Reserved)}
<byte 4209>
utiny value
{}
<byte 4210>
{rsvd1[183] (06-FC Reserved)}
<byte 4210>
utiny value
{}
<byte 4211>
{rsvd1[182] (06-FC Reserved)}
<byte 4211>
utiny value
{}
<byte 4212>
{rsvd1[189] (06-FC Reserved)}
<byte 4212>
utiny value
{}
<byte 4213>
{rsvd1[188] (06-FC Reserved)}
<byte 4213>
utiny value
{}
<byte 4214>
{rsvd1[187] (06-FC Reserved)}
<byte 4214>
utiny value
{}
<byte 4215>
{rsvd1[186] (06-FC Reserved)}
<byte 4215>
utiny value
{}
<byte 4216>
{rsvd1[193] (06-FC Reserved)}
<byte 4216>
utiny value
{}
<byte 4217>
{rsvd1[192] (06-FC Reserved)}
<byte 4217>
utiny value
{}
<byte 4218>
{rsvd1[191] (06-FC Reserved)}
<byte 4218>
utiny value
{}
<byte 4219>
{rsvd1[190] (06-FC Reserved)}
<byte 4219>
utiny value
{}
<byte 4220>
{rsvd1[197] (06-FC Reserved)}
<byte 4220>
utiny value
{}
<byte 4221>
{rsvd1[196] (06-FC Reserved)}
<byte 4221>
utiny value
{}
<byte 4222>
{rsvd1[195] (06-FC Reserved)}
<byte 4222>
utiny value
{}
<byte 4223>
{rsvd1[194] (06-FC Reserved)}
<byte 4223>
utiny value
{}
<byte 4224>
{rsvd1[201] (06-FC Reserved)}
<byte 4224>
utiny value
{}
<byte 4225>
{rsvd1[200] (06-FC Reserved)}
<byte 4225>
utiny value
{}
<byte 4226>
{rsvd1[199] (06-FC Reserved)}
<byte 4226>
utiny value
{}
<byte 4227>
{rsvd1[198] (06-FC Reserved)}
<byte 4227>
utiny value
{}
<byte 4228>
{rsvd1[205] (06-FC Reserved)}
<byte 4228>
utiny value
{}
<byte 4229>
{rsvd1[204] (06-FC Reserved)}
<byte 4229>
utiny value
{}
<byte 4230>
{rsvd1[203] (06-FC Reserved)}
<byte 4230>
utiny value
{}
<byte 4231>
{rsvd1[202] (06-FC Reserved)}
<byte 4231>
utiny value
{}
<byte 4232>
{rsvd1[209] (06-FC Reserved)}
<byte 4232>
utiny value
{}
<byte 4233>
{rsvd1[208] (06-FC Reserved)}
<byte 4233>
utiny value
{}
<byte 4234>
{rsvd1[207] (06-FC Reserved)}
<byte 4234>
utiny value
{}
<byte 4235>
{rsvd1[206] (06-FC Reserved)}
<byte 4235>
utiny value
{}
<byte 4236>
{rsvd1[213] (06-FC Reserved)}
<byte 4236>
utiny value
{}
<byte 4237>
{rsvd1[212] (06-FC Reserved)}
<byte 4237>
utiny value
{}
<byte 4238>
{rsvd1[211] (06-FC Reserved)}
<byte 4238>
utiny value
{}
<byte 4239>
{rsvd1[210] (06-FC Reserved)}
<byte 4239>
utiny value
{}
<byte 4240>
{rsvd1[217] (06-FC Reserved)}
<byte 4240>
utiny value
{}
<byte 4241>
{rsvd1[216] (06-FC Reserved)}
<byte 4241>
utiny value
{}
<byte 4242>
{rsvd1[215] (06-FC Reserved)}
<byte 4242>
utiny value
{}
<byte 4243>
{rsvd1[214] (06-FC Reserved)}
<byte 4243>
utiny value
{}
<byte 4244>
{rsvd1[221] (06-FC Reserved)}
<byte 4244>
utiny value
{}
<byte 4245>
{rsvd1[220] (06-FC Reserved)}
<byte 4245>
utiny value
{}
<byte 4246>
{rsvd1[219] (06-FC Reserved)}
<byte 4246>
utiny value
{}
<byte 4247>
{rsvd1[218] (06-FC Reserved)}
<byte 4247>
utiny value
{}
<byte 4248>
{rsvd1[225] (06-FC Reserved)}
<byte 4248>
utiny value
{}
<byte 4249>
{rsvd1[224] (06-FC Reserved)}
<byte 4249>
utiny value
{}
<byte 4250>
{rsvd1[223] (06-FC Reserved)}
<byte 4250>
utiny value
{}
<byte 4251>
{rsvd1[222] (06-FC Reserved)}
<byte 4251>
utiny value
{}
<byte 4252>
{rsvd1[229] (06-FC Reserved)}
<byte 4252>
utiny value
{}
<byte 4253>
{rsvd1[228] (06-FC Reserved)}
<byte 4253>
utiny value
{}
<byte 4254>
{rsvd1[227] (06-FC Reserved)}
<byte 4254>
utiny value
{}
<byte 4255>
{rsvd1[226] (06-FC Reserved)}
<byte 4255>
utiny value
{}
<byte 4256>
{rsvd1[233] (06-FC Reserved)}
<byte 4256>
utiny value
{}
<byte 4257>
{rsvd1[232] (06-FC Reserved)}
<byte 4257>
utiny value
{}
<byte 4258>
{rsvd1[231] (06-FC Reserved)}
<byte 4258>
utiny value
{}
<byte 4259>
{rsvd1[230] (06-FC Reserved)}
<byte 4259>
utiny value
{}
<byte 4260>
{rsvd1[237] (06-FC Reserved)}
<byte 4260>
utiny value
{}
<byte 4261>
{rsvd1[236] (06-FC Reserved)}
<byte 4261>
utiny value
{}
<byte 4262>
{rsvd1[235] (06-FC Reserved)}
<byte 4262>
utiny value
{}
<byte 4263>
{rsvd1[234] (06-FC Reserved)}
<byte 4263>
utiny value
{}
<byte 4264>
{rsvd1[241] (06-FC Reserved)}
<byte 4264>
utiny value
{}
<byte 4265>
{rsvd1[240] (06-FC Reserved)}
<byte 4265>
utiny value
{}
<byte 4266>
{rsvd1[239] (06-FC Reserved)}
<byte 4266>
utiny value
{}
<byte 4267>
{rsvd1[238] (06-FC Reserved)}
<byte 4267>
utiny value
{}
<byte 4268>
{rsvd1[245] (06-FC Reserved)}
<byte 4268>
utiny value
{}
<byte 4269>
{rsvd1[244] (06-FC Reserved)}
<byte 4269>
utiny value
{}
<byte 4270>
{rsvd1[243] (06-FC Reserved)}
<byte 4270>
utiny value
{}
<byte 4271>
{rsvd1[242] (06-FC Reserved)}
<byte 4271>
utiny value
{}
<byte 4272>
{decoder_major_rev (FF Decoder Major Revision)}
<byte 4272>
utiny value
{}
<byte 4273>
{decoder_minor_rev (FE Decoder Minor Revision)}
<byte 4273>
utiny value
{}
<byte 4274>
{scratch (FD Scratch Register)}
<byte 4274>
utiny value
{}
<byte 4275>
{rsvd1[246] (06-FC Reserved)}
<byte 4275>
utiny value
{}
{}
<byte 4276>
{toyclock (DS1557 4MEG NV Y2KC Timekeeping RAM)}
<byte 4276>
union alarm_minutes Alarm Minutes Union
<byte 4276>
utiny value Alarm Minutes as byte
or alarm_minutes Alarm Minutes Union
<byte 4276>
{bits (Alarm Minutes by field)}
<byte 4276>
tbits:4 minutes
tbits:3 ten_minutes
tbits:1 am2
{}
endunion alarm_minutes Alarm Minutes Union
<byte 4277>
union alarm_seconds Alarm Seconds Union
<byte 4277>
utiny value Alarm Seconds as byte
or alarm_seconds Alarm Seconds Union
<byte 4277>
{bits (Alarm Seconds by field)}
<byte 4277>
tbits:4 seconds
tbits:3 ten_seconds
tbits:1 am1
{}
endunion alarm_seconds Alarm Seconds Union
<byte 4278>
utiny unused
<byte 4279>
union flag Alarm Enable/Status and Battery Status Flags Union
<byte 4279>
utiny value Alarm Enable/Status and Battery Status Flags as byte
or flag Alarm Enable/Status and Battery Status Flags Union
<byte 4279>
{bits (Alarm Enable/Status and Battery Status Flags by field)}
<byte 4279>
tbits:4 unused2
tbits:1 bat_low
tbits:1 unused1
tbits:1 alarm
tbits:1 alarm_enable
{}
endunion flag Alarm Enable/Status and Battery Status Flags Union
<byte 4280>
union watchdog Watchdog Timer Control Flags Union
<byte 4280>
utiny value Watchdog Timer Control Flags as byte
or watchdog Watchdog Timer Control Flags Union
<byte 4280>
{bits (Watchdog Timer Control Flags by field)}
<byte 4280>
tbits:7 multiplier
tbits:1 steering_bit
{}
endunion watchdog Watchdog Timer Control Flags Union
<byte 4281>
union interrupts Alarm Interrupt Enables Union
<byte 4281>
utiny value Alarm Interrupt Enables as byte
or interrupts Alarm Interrupt Enables Union
<byte 4281>
{bits (Alarm Interrupt Enables by field)}
<byte 4281>
tbits:5 unused2
tbits:1 alarm_enable_in_bat
tbits:1 unused1
tbits:1 alarm_enable
{}
endunion interrupts Alarm Interrupt Enables Union
<byte 4282>
union alarm_date Alarm Date Union
<byte 4282>
utiny value Alarm Date as byte
or alarm_date Alarm Date Union
<byte 4282>
{bits (Alarm Date by field)}
<byte 4282>
tbits:4 date
tbits:2 ten_date
tbits:1 unused
tbits:1 am4
{}
endunion alarm_date Alarm Date Union
<byte 4283>
union alarm_hours Alarm Hours Union
<byte 4283>
utiny value Alarm Hours as byte
or alarm_hours Alarm Hours Union
<byte 4283>
{alarm_hours (Alarm Hours by field)}
<byte 4283>
tbits:4 hours
tbits:2 ten_hours
tbits:1 unused
tbits:1 am3
{}
endunion alarm_hours Alarm Hours Union
<byte 4284>
union hour Hour Union
<byte 4284>
utiny value Hour as byte
or hour Hour Union
<byte 4284>
{bits (Hour by field)}
<byte 4284>
tbits:6 hour
tbits:2 unused
{}
endunion hour Hour Union
<byte 4285>
union minutes Minutes Union
<byte 4285>
utiny value Minutes as byte
or minutes Minutes Union
<byte 4285>
{bits (Minutes by field)}
<byte 4285>
tbits:7 minutes
tbits:1 unused
{}
endunion minutes Minutes Union
<byte 4286>
union seconds Seconds/Oscillator Control Union
<byte 4286>
utiny value Seconds/Oscillator Control as byte
or seconds Seconds/Oscillator Control Union
<byte 4286>
{bits (Seconds/Oscillator Control by field)}
<byte 4286>
tbits:7 seconds
tbits:1 osc
{}
endunion seconds Seconds/Oscillator Control Union
<byte 4287>
union control TOY Control Flags/Century Union
<byte 4287>
utiny value TOY Control Flags/Century as byte
or control TOY Control Flags/Century Union
<byte 4287>
{bits (TOY Control Flags/Century by field)}
<byte 4287>
tbits:6 century
tbits:1 read_bit
tbits:1 write_bit
{}
endunion control TOY Control Flags/Century Union
<byte 4288>
utiny year Year as byte
<byte 4289>
union month Month Union
<byte 4289>
utiny value Month as byte
or month Month Union
<byte 4289>
{bits (Month by field)}
<byte 4289>
tbits:5 month
tbits:3 unused
{}
endunion month Month Union
<byte 4290>
union date Date Union
<byte 4290>
utiny value Date as byte
or date Date Union
<byte 4290>
{bits (Date by field)}
<byte 4290>
tbits:6 date
tbits:2 unused
{}
endunion date Date Union
<byte 4291>
union day Day Union
<byte 4291>
utiny value Day/Frequency Test as byte
or day Day Union
<byte 4291>
{bits (Day/Frequency Test by field)}
<byte 4291>
tbits:3 day
tbits:3 unused2
tbits:1 freq_test
tbits:1 unused1
{}
endunion day Day Union
{}
<byte 4292>
{glue (Glue register save area)}
<byte 4292>
union csr Glue CSR Registers
<byte 4292>
ulong[256] csra Glue CSR Registers As Longwords
or csr Glue CSR Registers
<byte 4292>
{csrfield (Glue CSR Registers By Field)}
<byte 4292>
{rsvd[0] (03-0F Reserved)}
<byte 4292>
utiny value
{}
<byte 4293>
{self_reset (02 Self Reset (0xD1))}
<byte 4293>
utiny value
{}
<byte 4294>
union reset_in 01 Reset Inputs
<byte 4294>
{field (By field)}
<byte 4294>
tbits:1 button_self R/W Button or Self Reset
tbits:1 kill_other R/W Other, Kill Reset
tbits:1 rsvd1 R Reserved
tbits:1 pwr_up R/W Power Up Reset
tbits:1 swd R/W SW Watchdog Reset
tbits:3 rsvd R Reserved
{}
or reset_in 01 Reset Inputs
<byte 4294>
utiny value As utiny
endunion reset_in 01 Reset Inputs
<byte 4295>
union reset_dis 00 Reset Disables
<byte 4295>
{field (By field)}
<byte 4295>
tbits:1 button_self R/W Button or Self Reset
tbits:1 kill_other R/W Other, Kill Reset
tbits:1 rsvd1 R Reserved
tbits:1 pwr_up R/W Power Up Reset
tbits:1 swd R/W SW Watchdog Reset
tbits:3 rsvd R Reserved
{}
or reset_dis 00 Reset Disables
<byte 4295>
utiny value As utiny
endunion reset_dis 00 Reset Disables
<byte 4296>
{rsvd[4] (03-0F Reserved)}
<byte 4296>
utiny value
{}
<byte 4297>
{rsvd[3] (03-0F Reserved)}
<byte 4297>
utiny value
{}
<byte 4298>
{rsvd[2] (03-0F Reserved)}
<byte 4298>
utiny value
{}
<byte 4299>
{rsvd[1] (03-0F Reserved)}
<byte 4299>
utiny value
{}
<byte 4300>
{rsvd[8] (03-0F Reserved)}
<byte 4300>
utiny value
{}
<byte 4301>
{rsvd[7] (03-0F Reserved)}
<byte 4301>
utiny value
{}
<byte 4302>
{rsvd[6] (03-0F Reserved)}
<byte 4302>
utiny value
{}
<byte 4303>
{rsvd[5] (03-0F Reserved)}
<byte 4303>
utiny value
{}
<byte 4304>
{rsvd[12] (03-0F Reserved)}
<byte 4304>
utiny value
{}
<byte 4305>
{rsvd[11] (03-0F Reserved)}
<byte 4305>
utiny value
{}
<byte 4306>
{rsvd[10] (03-0F Reserved)}
<byte 4306>
utiny value
{}
<byte 4307>
{rsvd[9] (03-0F Reserved)}
<byte 4307>
utiny value
{}
<byte 4308>
{rsvd1[0] (13-21 Reserved)}
<byte 4308>
utiny value
{}
<byte 4309>
union req 12 Request
<byte 4309>
{field (By field)}
<byte 4309>
tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal
tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal
tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal
tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal
tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal
tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal
tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal
tbits:1 rsvd R Reserved
{}
or req 12 Request
<byte 4309>
utiny value As utiny
endunion req 12 Request
<byte 4310>
union gnt 11 Grant
<byte 4310>
{field (By field)}
<byte 4310>
tbits:1 devA R/W PCIX0, Device A Req/Gnt Signal
tbits:1 devB R/W PCIX0, Device B Req/Gnt Signal
tbits:1 sprite0 R/W PCIX0, Sprite Req/Gnt Signal
tbits:1 devE R/W PCIX0, Device E Req/Gnt Signal
tbits:1 devC R/W PCIX1, Device C Req/Gnt Signal
tbits:1 devD R/W PCIX1, Device D Req/Gnt Signal
tbits:1 sprite1 R/W PCIX1, Sprite Req/Gnt Signal
tbits:1 rsvd R Reserved
{}
or gnt 11 Grant
<byte 4310>
utiny value As utiny
endunion gnt 11 Grant
<byte 4311>
union arb 10 Arbitration Control & Status
<byte 4311>
{field (By field)}
<byte 4311>
tbits:2 ctrl0 R/W PCIX0 Arb Control
tbits:2 state0 R PCIX0 Arb State
tbits:2 ctrl1 R/W PCIX1 Arb Control
tbits:2 state1 R PCIX1 Arb State
{}
or arb 10 Arbitration Control & Status
<byte 4311>
utiny value As utiny
endunion arb 10 Arbitration Control & Status
<byte 4312>
{rsvd1[4] (13-21 Reserved)}
<byte 4312>
utiny value
{}
<byte 4313>
{rsvd1[3] (13-21 Reserved)}
<byte 4313>
utiny value
{}
<byte 4314>
{rsvd1[2] (13-21 Reserved)}
<byte 4314>
utiny value
{}
<byte 4315>
{rsvd1[1] (13-21 Reserved)}
<byte 4315>
utiny value
{}
<byte 4316>
{rsvd1[8] (13-21 Reserved)}
<byte 4316>
utiny value
{}
<byte 4317>
{rsvd1[7] (13-21 Reserved)}
<byte 4317>
utiny value
{}
<byte 4318>
{rsvd1[6] (13-21 Reserved)}
<byte 4318>
utiny value
{}
<byte 4319>
{rsvd1[5] (13-21 Reserved)}
<byte 4319>
utiny value
{}
<byte 4320>
{rsvd1[12] (13-21 Reserved)}
<byte 4320>
utiny value
{}
<byte 4321>
{rsvd1[11] (13-21 Reserved)}
<byte 4321>
utiny value
{}
<byte 4322>
{rsvd1[10] (13-21 Reserved)}
<byte 4322>
utiny value
{}
<byte 4323>
{rsvd1[9] (13-21 Reserved)}
<byte 4323>
utiny value
{}
<byte 4324>
{swd_tp (23 SW Watchdog Timer Trip Pt.)}
<byte 4324>
utiny value
{}
<byte 4325>
{swd_ct (22 SW Watchdog Current Time)}
<byte 4325>
utiny value
{}
<byte 4326>
{rsvd1[14] (13-21 Reserved)}
<byte 4326>
utiny value
{}
<byte 4327>
{rsvd1[13] (13-21 Reserved)}
<byte 4327>
utiny value
{}
<byte 4328>
{rsvd2[0] (27-3F Reserved)}
<byte 4328>
utiny value
{}
<byte 4329>
union timer_ctrl 26 Timer Control
<byte 4329>
{field (By field)}
<byte 4329>
tbits:1 mbd_ok R/W Driven Lo when Watchdog Expires
tbits:1 rsvd1 R Reserved
tbits:1 ena_swd R/W SW Watchdog Timer Enable
tbits:1 ena_ppc R/W PPC Bus Snoop Timer Enable
tbits:3 rsvd R Reserved
tbits:1 swd_rst R/W1R SW Watchdog Reset/Restart
{}
or timer_ctrl 26 Timer Control
<byte 4329>
utiny value As utiny
endunion timer_ctrl 26 Timer Control
<byte 4330>
{ppc_sv (25 PPC " " Timer Start Value)}
<byte 4330>
utiny value
{}
<byte 4331>
{ppc_ct (24 PPC Bus Snoop Current Value)}
<byte 4331>
utiny value
{}
<byte 4332>
{rsvd2[4] (27-3F Reserved)}
<byte 4332>
utiny value
{}
<byte 4333>
{rsvd2[3] (27-3F Reserved)}
<byte 4333>
utiny value
{}
<byte 4334>
{rsvd2[2] (27-3F Reserved)}
<byte 4334>
utiny value
{}
<byte 4335>
{rsvd2[1] (27-3F Reserved)}
<byte 4335>
utiny value
{}
<byte 4336>
{rsvd2[8] (27-3F Reserved)}
<byte 4336>
utiny value
{}
<byte 4337>
{rsvd2[7] (27-3F Reserved)}
<byte 4337>
utiny value
{}
<byte 4338>
{rsvd2[6] (27-3F Reserved)}
<byte 4338>
utiny value
{}
<byte 4339>
{rsvd2[5] (27-3F Reserved)}
<byte 4339>
utiny value
{}
<byte 4340>
{rsvd2[12] (27-3F Reserved)}
<byte 4340>
utiny value
{}
<byte 4341>
{rsvd2[11] (27-3F Reserved)}
<byte 4341>
utiny value
{}
<byte 4342>
{rsvd2[10] (27-3F Reserved)}
<byte 4342>
utiny value
{}
<byte 4343>
{rsvd2[9] (27-3F Reserved)}
<byte 4343>
utiny value
{}
<byte 4344>
{rsvd2[16] (27-3F Reserved)}
<byte 4344>
utiny value
{}
<byte 4345>
{rsvd2[15] (27-3F Reserved)}
<byte 4345>
utiny value
{}
<byte 4346>
{rsvd2[14] (27-3F Reserved)}
<byte 4346>
utiny value
{}
<byte 4347>
{rsvd2[13] (27-3F Reserved)}
<byte 4347>
utiny value
{}
<byte 4348>
{rsvd2[20] (27-3F Reserved)}
<byte 4348>
utiny value
{}
<byte 4349>
{rsvd2[19] (27-3F Reserved)}
<byte 4349>
utiny value
{}
<byte 4350>
{rsvd2[18] (27-3F Reserved)}
<byte 4350>
utiny value
{}
<byte 4351>
{rsvd2[17] (27-3F Reserved)}
<byte 4351>
utiny value
{}
<byte 4352>
{rsvd2[24] (27-3F Reserved)}
<byte 4352>
utiny value
{}
<byte 4353>
{rsvd2[23] (27-3F Reserved)}
<byte 4353>
utiny value
{}
<byte 4354>
{rsvd2[22] (27-3F Reserved)}
<byte 4354>
utiny value
{}
<byte 4355>
{rsvd2[21] (27-3F Reserved)}
<byte 4355>
utiny value
{}
<byte 4356>
{supply_a_off (43 Supply A Turn Off (0xA5))}
<byte 4356>
utiny value
{}
<byte 4357>
{rsvd3 (42 Reserved)}
<byte 4357>
utiny value
{}
<byte 4358>
{kill_other (41 Kill Other Controller (0x37))}
<byte 4358>
utiny value
{}
<byte 4359>
union dis_ctrl 40 Disable Control
<byte 4359>
{field (By field)}
<byte 4359>
tbits:1 ena_kill_other R/W Kill Other Controller - Enable
tbits:1 rsvd1 R Reserved
tbits:1 ena_ps_a_off R/W Power Supply A Off - Enable
tbits:1 ena_ps_b_off R/W Power Supply B Off - Enable
tbits:1 amb_ps_a_led R/W Amber Power Supply A Failure LED {E1}
tbits:1 amb_ps_b_led R/W Amber Power Supply B Failure LED {E2}
tbits:2 rsvd R Reserved
{}
or dis_ctrl 40 Disable Control
<byte 4359>
utiny value As utiny
endunion dis_ctrl 40 Disable Control
<byte 4360>
union iic_bus_ctrl 47 Atlantis IIC Bus Control
<byte 4360>
{field (By field Bus: A B C D)}
<byte 4360>
tbits:3 iic_sel R/W IIC Bus Select {AA9, AB9, W9, Y9}
tbits:5 rsvd R Reserved
{}
or iic_bus_ctrl 47 Atlantis IIC Bus Control
<byte 4360>
utiny value As utiny
endunion iic_bus_ctrl 47 Atlantis IIC Bus Control
<byte 4361>
{rsvdz[1] (45-46 Reserved)}
<byte 4361>
utiny value
{}
<byte 4362>
{rsvdz[0] (45-46 Reserved)}
<byte 4362>
utiny value
{}
<byte 4363>
{supply_b_off (44 Supply B Turn Off (0xB5))}
<byte 4363>
utiny value
{}
<byte 4364>
{rsvd4[3] (48-4F Reserved)}
<byte 4364>
utiny value
{}
<byte 4365>
{rsvd4[2] (48-4F Reserved)}
<byte 4365>
utiny value
{}
<byte 4366>
{rsvd4[1] (48-4F Reserved)}
<byte 4366>
utiny value
{}
<byte 4367>
{rsvd4[0] (48-4F Reserved)}
<byte 4367>
utiny value
{}
<byte 4368>
{rsvd4[7] (48-4F Reserved)}
<byte 4368>
utiny value
{}
<byte 4369>
{rsvd4[6] (48-4F Reserved)}
<byte 4369>
utiny value
{}
<byte 4370>
{rsvd4[5] (48-4F Reserved)}
<byte 4370>
utiny value
{}
<byte 4371>
{rsvd4[4] (48-4F Reserved)}
<byte 4371>
utiny value
{}
<byte 4372>
{rsvd5[2] (51-5F Reserved)}
<byte 4372>
utiny value
{}
<byte 4373>
{rsvd5[1] (51-5F Reserved)}
<byte 4373>
utiny value
{}
<byte 4374>
{rsvd5[0] (51-5F Reserved)}
<byte 4374>
utiny value
{}
<byte 4375>
union int_out 50 Interrupt Out
<byte 4375>
{field (By field)}
<byte 4375>
tbits:1 other_l R/W Int. to Other Ctrllr (Int=0) {V12}
tbits:1 rsvd1 R Reserved {U12}
tbits:1 smi_l R/W System Management Int. (Int=0) {B6}
tbits:1 mcp_l R/W Machine Check Interrupt (Int=0) {A6}
tbits:4 rsvd R Reserved
{}
or int_out 50 Interrupt Out
<byte 4375>
utiny value As utiny
endunion int_out 50 Interrupt Out
<byte 4376>
{rsvd5[6] (51-5F Reserved)}
<byte 4376>
utiny value
{}
<byte 4377>
{rsvd5[5] (51-5F Reserved)}
<byte 4377>
utiny value
{}
<byte 4378>
{rsvd5[4] (51-5F Reserved)}
<byte 4378>
utiny value
{}
<byte 4379>
{rsvd5[3] (51-5F Reserved)}
<byte 4379>
utiny value
{}
<byte 4380>
{rsvd5[10] (51-5F Reserved)}
<byte 4380>
utiny value
{}
<byte 4381>
{rsvd5[9] (51-5F Reserved)}
<byte 4381>
utiny value
{}
<byte 4382>
{rsvd5[8] (51-5F Reserved)}
<byte 4382>
utiny value
{}
<byte 4383>
{rsvd5[7] (51-5F Reserved)}
<byte 4383>
utiny value
{}
<byte 4384>
{rsvd5[14] (51-5F Reserved)}
<byte 4384>
utiny value
{}
<byte 4385>
{rsvd5[13] (51-5F Reserved)}
<byte 4385>
utiny value
{}
<byte 4386>
{rsvd5[12] (51-5F Reserved)}
<byte 4386>
utiny value
{}
<byte 4387>
{rsvd5[11] (51-5F Reserved)}
<byte 4387>
utiny value
{}
<byte 4388>
union int_smi_3 63 SMI Interrupt 31:24 (Int=1)
<byte 4388>
{field (By field)}
<byte 4388>
tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22}
tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21}
tbits:1 sdc SDC Int. (Int=0) {W20}
tbits:1 other Other Controller Int. (Int=0) {AA20}
tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17}
tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17}
tbits:1 dx2e_intb DX2E INTB (Int=0) {C18}
tbits:1 dx2e_inta DX2E INTA (Int=0) {D18}
{}
or int_smi_3 63 SMI Interrupt 31:24 (Int=1)
<byte 4388>
utiny value As utiny
endunion int_smi_3 63 SMI Interrupt 31:24 (Int=1)
<byte 4389>
union int_smi_2 62 SMI Interrupt 23:16 (Int=1)
<byte 4389>
{field (By field)}
<byte 4389>
tbits:1 can CAN Interrupt (Int=0) {T22}
tbits:1 uart UART Interrupt (Int=0) {T21}
tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22}
tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21}
tbits:1 lcd LCD Interrupt (Int=0) {V20}
tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19}
tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22}
tbits:1 rtc Real Time Clock (Int=0) {W21}
{}
or int_smi_2 62 SMI Interrupt 23:16 (Int=1)
<byte 4389>
utiny value As utiny
endunion int_smi_2 62 SMI Interrupt 23:16 (Int=1)
<byte 4390>
union int_smi_1 61 SMI Interrupt 15:08 (Int=1)
<byte 4390>
{field (By field)}
<byte 4390>
tbits:1 dx2d_intb DX2D INTB (Int=0) {P20}
tbits:1 dx2d_inta DX2D INTA (Int=0) {P19}
tbits:1 dx2c_intb DX2C INTB (Int=0) {R22}
tbits:1 dx2c_inta DX2C INTA (Int=0) {R21}
tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}
tbits:1 dx2b_inta DX2B INTA (Int=0) {R19}
tbits:1 dx2a_intb DX2A INTB (Int=0) {R18}
tbits:1 dx2a_inta DX2A INTA (Int=0) {P17}
{}
or int_smi_1 61 SMI Interrupt 15:08 (Int=1)
<byte 4390>
utiny value As utiny
endunion int_smi_1 61 SMI Interrupt 15:08 (Int=1)
<byte 4391>
union int_smi_0 60 SMI Interrupt 07:00 (Int=1)
<byte 4391>
{field (By field)}
<byte 4391>
tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22}
tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21}
tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20}
tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19}
tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18}
tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18}
tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22}
tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21}
{}
or int_smi_0 60 SMI Interrupt 07:00 (Int=1)
<byte 4391>
utiny value As utiny
endunion int_smi_0 60 SMI Interrupt 07:00 (Int=1)
<byte 4392>
union ena_smi_2 67 SMI Enables 23:16
<byte 4392>
{field (By field)}
<byte 4392>
tbits:1 can CAN Interrupt (Int=0) {T22}
tbits:1 uart UART Interrupt (Int=0) {T21}
tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22}
tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21}
tbits:1 lcd LCD Interrupt (Int=0) {V20}
tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19}
tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22}
tbits:1 rtc Real Time Clock (Int=0) {W21}
{}
or ena_smi_2 67 SMI Enables 23:16
<byte 4392>
utiny value As utiny
endunion ena_smi_2 67 SMI Enables 23:16
<byte 4393>
union ena_smi_1 66 SMI Enables 15:08
<byte 4393>
{field (By field)}
<byte 4393>
tbits:1 dx2d_intb DX2D INTB (Int=0) {P20}
tbits:1 dx2d_inta DX2D INTA (Int=0) {P19}
tbits:1 dx2c_intb DX2C INTB (Int=0) {R22}
tbits:1 dx2c_inta DX2C INTA (Int=0) {R21}
tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}
tbits:1 dx2b_inta DX2B INTA (Int=0) {R19}
tbits:1 dx2a_intb DX2A INTB (Int=0) {R18}
tbits:1 dx2a_inta DX2A INTA (Int=0) {P17}
{}
or ena_smi_1 66 SMI Enables 15:08
<byte 4393>
utiny value As utiny
endunion ena_smi_1 66 SMI Enables 15:08
<byte 4394>
union ena_smi_0 65 SMI Enables 07:00
<byte 4394>
{field (By field)}
<byte 4394>
tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22}
tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21}
tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20}
tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19}
tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18}
tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18}
tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22}
tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21}
{}
or ena_smi_0 65 SMI Enables 07:00
<byte 4394>
utiny value As utiny
endunion ena_smi_0 65 SMI Enables 07:00
<byte 4395>
union int_smi_4 64 SMI Interrupt 39:32 (Int=1)
<byte 4395>
{field (By field)}
<byte 4395>
tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19}
tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12}
tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3}
tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12}
tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4}
tbits:1 reset Reset
tbits:1 sdc_wdto SDC Watchdog Timeout
tbits:1 ppc_to PowerPC Bus Timeout
{}
or int_smi_4 64 SMI Interrupt 39:32 (Int=1)
<byte 4395>
utiny value As utiny
endunion int_smi_4 64 SMI Interrupt 39:32 (Int=1)
<byte 4396>
union int_mcp_1 6B MCP Interrupt 15:08 (Int=1)
<byte 4396>
{field (By field)}
<byte 4396>
tbits:1 dx2d_intb DX2D INTB (Int=0) {P20}
tbits:1 dx2d_inta DX2D INTA (Int=0) {P19}
tbits:1 dx2c_intb DX2C INTB (Int=0) {R22}
tbits:1 dx2c_inta DX2C INTA (Int=0) {R21}
tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}
tbits:1 dx2b_inta DX2B INTA (Int=0) {R19}
tbits:1 dx2a_intb DX2A INTB (Int=0) {R18}
tbits:1 dx2a_inta DX2A INTA (Int=0) {P17}
{}
or int_mcp_1 6B MCP Interrupt 15:08 (Int=1)
<byte 4396>
utiny value As utiny
endunion int_mcp_1 6B MCP Interrupt 15:08 (Int=1)
<byte 4397>
union int_mcp_0 6A MCP Interrupt 07:00 (Int=1)
<byte 4397>
{field (By field)}
<byte 4397>
tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22}
tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21}
tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20}
tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19}
tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18}
tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18}
tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22}
tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21}
{}
or int_mcp_0 6A MCP Interrupt 07:00 (Int=1)
<byte 4397>
utiny value As utiny
endunion int_mcp_0 6A MCP Interrupt 07:00 (Int=1)
<byte 4398>
union ena_smi_4 69 SMI Enables 39:32
<byte 4398>
{field (By field)}
<byte 4398>
tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19}
tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12}
tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3}
tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12}
tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4}
tbits:1 reset Reset
tbits:1 sdc_wdto SDC Watchdog Timeout
tbits:1 ppc_to PowerPC Bus Timeout
{}
or ena_smi_4 69 SMI Enables 39:32
<byte 4398>
utiny value As utiny
endunion ena_smi_4 69 SMI Enables 39:32
<byte 4399>
union ena_smi_3 68 SMI Enables 31:24
<byte 4399>
{field (By field)}
<byte 4399>
tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22}
tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21}
tbits:1 sdc SDC Int. (Int=0) {W20}
tbits:1 other Other Controller Int. (Int=0) {AA20}
tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17}
tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17}
tbits:1 dx2e_intb DX2E INTB (Int=0) {C18}
tbits:1 dx2e_inta DX2E INTA (Int=0) {D18}
{}
or ena_smi_3 68 SMI Enables 31:24
<byte 4399>
utiny value As utiny
endunion ena_smi_3 68 SMI Enables 31:24
<byte 4400>
union ena_mcp_0 6F MCP Enables 07:00
<byte 4400>
{field (By field)}
<byte 4400>
tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22}
tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21}
tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20}
tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19}
tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18}
tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18}
tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22}
tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21}
{}
or ena_mcp_0 6F MCP Enables 07:00
<byte 4400>
utiny value As utiny
endunion ena_mcp_0 6F MCP Enables 07:00
<byte 4401>
union int_mcp_4 6E MCP Interrupt 39:32 (Int=1)
<byte 4401>
{field (By field)}
<byte 4401>
tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19}
tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12}
tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3}
tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12}
tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4}
tbits:1 reset Reset
tbits:1 sdc_wdto SDC Watchdog Timeout
tbits:1 ppc_to PowerPC Bus Timeout
{}
or int_mcp_4 6E MCP Interrupt 39:32 (Int=1)
<byte 4401>
utiny value As utiny
endunion int_mcp_4 6E MCP Interrupt 39:32 (Int=1)
<byte 4402>
union int_mcp_3 6D MCP Interrupt 31:24 (Int=1)
<byte 4402>
{field (By field)}
<byte 4402>
tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22}
tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21}
tbits:1 sdc SDC Int. (Int=0) {W20}
tbits:1 other Other Controller Int. (Int=0) {AA20}
tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17}
tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17}
tbits:1 dx2e_intb DX2E INTB (Int=0) {C18}
tbits:1 dx2e_inta DX2E INTA (Int=0) {D18}
{}
or int_mcp_3 6D MCP Interrupt 31:24 (Int=1)
<byte 4402>
utiny value As utiny
endunion int_mcp_3 6D MCP Interrupt 31:24 (Int=1)
<byte 4403>
union int_mcp_2 6C MCP Interrupt 23:16 (Int=1)
<byte 4403>
{field (By field)}
<byte 4403>
tbits:1 can CAN Interrupt (Int=0) {T22}
tbits:1 uart UART Interrupt (Int=0) {T21}
tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22}
tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21}
tbits:1 lcd LCD Interrupt (Int=0) {V20}
tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19}
tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22}
tbits:1 rtc Real Time Clock (Int=0) {W21}
{}
or int_mcp_2 6C MCP Interrupt 23:16 (Int=1)
<byte 4403>
utiny value As utiny
endunion int_mcp_2 6C MCP Interrupt 23:16 (Int=1)
<byte 4404>
union ena_mcp_4 73 MCP Enables 39:32
<byte 4404>
{field (By field)}
<byte 4404>
tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19}
tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12}
tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3}
tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12}
tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4}
tbits:1 reset Reset
tbits:1 sdc_wdto SDC Watchdog Timeout
tbits:1 ppc_to PowerPC Bus Timeout
{}
or ena_mcp_4 73 MCP Enables 39:32
<byte 4404>
utiny value As utiny
endunion ena_mcp_4 73 MCP Enables 39:32
<byte 4405>
union ena_mcp_3 72 MCP Enables 31:24
<byte 4405>
{field (By field)}
<byte 4405>
tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22}
tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21}
tbits:1 sdc SDC Int. (Int=0) {W20}
tbits:1 other Other Controller Int. (Int=0) {AA20}
tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17}
tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17}
tbits:1 dx2e_intb DX2E INTB (Int=0) {C18}
tbits:1 dx2e_inta DX2E INTA (Int=0) {D18}
{}
or ena_mcp_3 72 MCP Enables 31:24
<byte 4405>
utiny value As utiny
endunion ena_mcp_3 72 MCP Enables 31:24
<byte 4406>
union ena_mcp_2 71 MCP Enables 23:16
<byte 4406>
{field (By field)}
<byte 4406>
tbits:1 can CAN Interrupt (Int=0) {T22}
tbits:1 uart UART Interrupt (Int=0) {T21}
tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22}
tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21}
tbits:1 lcd LCD Interrupt (Int=0) {V20}
tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19}
tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22}
tbits:1 rtc Real Time Clock (Int=0) {W21}
{}
or ena_mcp_2 71 MCP Enables 23:16
<byte 4406>
utiny value As utiny
endunion ena_mcp_2 71 MCP Enables 23:16
<byte 4407>
union ena_mcp_1 70 MCP Enables 15:08
<byte 4407>
{field (By field)}
<byte 4407>
tbits:1 dx2d_intb DX2D INTB (Int=0) {P20}
tbits:1 dx2d_inta DX2D INTA (Int=0) {P19}
tbits:1 dx2c_intb DX2C INTB (Int=0) {R22}
tbits:1 dx2c_inta DX2C INTA (Int=0) {R21}
tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}
tbits:1 dx2b_inta DX2B INTA (Int=0) {R19}
tbits:1 dx2a_intb DX2A INTB (Int=0) {R18}
tbits:1 dx2a_inta DX2A INTA (Int=0) {P17}
{}
or ena_mcp_1 70 MCP Enables 15:08
<byte 4407>
utiny value As utiny
endunion ena_mcp_1 70 MCP Enables 15:08
<byte 4408>
union int_in_3 77 Interrupt Inputs 31:24
<byte 4408>
{field (By field)}
<byte 4408>
tbits:1 dimm_dcok_3_l (NBBU) DIMM 3 DC NOT OK Int. (Int=0) {Y22}
tbits:1 dimm_dcok_012_l (BBU) DIMM 0-2 DC NOT OK Int. (Int=0) {Y21}
tbits:1 sdc SDC Int. (Int=0) {W20}
tbits:1 other Other Controller Int. (Int=0) {AA20}
tbits:1 dx2e_f1_dir_rst DX2E F1 DIR RST (Int=1) {N17}
tbits:1 dx2e_f0_dir_rst DX2E F0 DIR RST (Int=1) {M17}
tbits:1 dx2e_intb DX2E INTB (Int=0) {C18}
tbits:1 dx2e_inta DX2E INTA (Int=0) {D18}
{}
or int_in_3 77 Interrupt Inputs 31:24
<byte 4408>
utiny value As utiny
endunion int_in_3 77 Interrupt Inputs 31:24
<byte 4409>
union int_in_2 76 Interrupt Inputs 23:16
<byte 4409>
{field (By field)}
<byte 4409>
tbits:1 can CAN Interrupt (Int=0) {T22}
tbits:1 uart UART Interrupt (Int=0) {T21}
tbits:1 sprite1 Sprite Int. 1 (Int=0) {V22}
tbits:1 sprite0 Sprite Int. 0 (Int=0) {V21}
tbits:1 lcd LCD Interrupt (Int=0) {V20}
tbits:1 atlantis1 Atlantis CPU Int. 1 (Int=0) {V19}
tbits:1 atlantis0 Atlantis CPU Int. 0 (Int=0) {W22}
tbits:1 rtc Real Time Clock (Int=0) {W21}
{}
or int_in_2 76 Interrupt Inputs 23:16
<byte 4409>
utiny value As utiny
endunion int_in_2 76 Interrupt Inputs 23:16
<byte 4410>
union int_in_1 75 Interrupt Inputs 15:08
<byte 4410>
{field (By field)}
<byte 4410>
tbits:1 dx2d_intb DX2D INTB (Int=0) {P20}
tbits:1 dx2d_inta DX2D INTA (Int=0) {P19}
tbits:1 dx2c_intb DX2C INTB (Int=0) {R22}
tbits:1 dx2c_inta DX2C INTA (Int=0) {R21}
tbits:1 dx2b_intb DX2B INTB (Int=0) {R20}
tbits:1 dx2b_inta DX2B INTA (Int=0) {R19}
tbits:1 dx2a_intb DX2A INTB (Int=0) {R18}
tbits:1 dx2a_inta DX2A INTA (Int=0) {P17}
{}
or int_in_1 75 Interrupt Inputs 15:08
<byte 4410>
utiny value As utiny
endunion int_in_1 75 Interrupt Inputs 15:08
<byte 4411>
union int_in_0 74 Interrupt Inputs 07:00
<byte 4411>
{field (By field)}
<byte 4411>
tbits:1 dx2d_f1_dir_rst DX2D F1 DIR RST (Int=1) {N22}
tbits:1 dx2d_f0_dir_rst DX2D F0 DIR RST (Int=1) {N21}
tbits:1 dx2c_f1_dir_rst DX2C F1 DIR RST (Int=1) {N20}
tbits:1 dx2c_f0_dir_rst DX2C F0 DIR RST (Int=1) {N19}
tbits:1 dx2b_f1_dir_rst DX2B F1 DIR RST (Int=1) {N18}
tbits:1 dx2b_f0_dir_rst DX2B F0 DIR RST (Int=1) {P18}
tbits:1 dx2a_f1_dir_rst DX2A F1 DIR RST (Int=1) {P22}
tbits:1 dx2a_f0_dir_rst DX2A F0 DIR RST (Int=1) {P21}
{}
or int_in_0 74 Interrupt Inputs 07:00
<byte 4411>
utiny value As utiny
endunion int_in_0 74 Interrupt Inputs 07:00
<byte 4412>
union int_mcp_5 7B MCP Interrupt 43:40
<byte 4412>
{field (By field)}
<byte 4412>
tbits:1 atlantis_bus_req Atlantis Bus Request
tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4}
tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9}
tbits:5 rsvd Reserved
{}
or int_mcp_5 7B MCP Interrupt 43:40
<byte 4412>
utiny value As utiny
endunion int_mcp_5 7B MCP Interrupt 43:40
<byte 4413>
union int_in_5 7A Interrupt Inputs 43:40
<byte 4413>
{field (By field)}
<byte 4413>
tbits:1 atlantis_bus_req Atlantis Bus Request
tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4}
tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9}
tbits:5 rsvd Reserved
{}
or int_in_5 7A Interrupt Inputs 43:40
<byte 4413>
utiny value As utiny
endunion int_in_5 7A Interrupt Inputs 43:40
<byte 4414>
union int_smi_pulsed 79 SMI Latched Pulse Interrupts
<byte 4414>
{field (By field)}
<byte 4414>
tbits:2 rsvd2 Reserved
tbits:1 sdc_int SDC Latched Int. (Int=1)
tbits:1 rsvd1 Reserved
tbits:1 lcd_int LCD Latched Int. (Int=1)
tbits:3 rsvd Reserved
{}
or int_smi_pulsed 79 SMI Latched Pulse Interrupts
<byte 4414>
utiny value As utiny
endunion int_smi_pulsed 79 SMI Latched Pulse Interrupts
<byte 4415>
union int_in_4 78 Interrupt Inputs 39:32
<byte 4415>
{field (By field)}
<byte 4415>
tbits:1 atlantis_pcix0 Atlantis PCIX0 Int. (Int=0) {A19}
tbits:1 cache_vtt_fail Cache VTT Fail Int. (Int=0) {C12}
tbits:1 enet_dcard0 Ethernet Daughter Card Int.0 {H3}
tbits:1 ac_fail_ups1 AC fail UPS 1 (Int=0) {W12}
tbits:1 enet_dcard1 Ethernet Daughter Card Int.1 {H4}
tbits:1 reset Reset
tbits:1 sdc_wdto SDC Watchdog Timeout
tbits:1 ppc_to PowerPC Bus Timeout
{}
or int_in_4 78 Interrupt Inputs 39:32
<byte 4415>
utiny value As utiny
endunion int_in_4 78 Interrupt Inputs 39:32
<byte 4416>
{rsvda[2] (7D-7F Reserved)}
<byte 4416>
utiny value
{}
<byte 4417>
{rsvda[1] (7D-7F Reserved)}
<byte 4417>
utiny value
{}
<byte 4418>
{rsvda[0] (7D-7F Reserved)}
<byte 4418>
utiny value
{}
<byte 4419>
union ena_mcp_5 7C MCP Enables 43:40
<byte 4419>
{field (By field)}
<byte 4419>
tbits:1 atlantis_bus_req Atlantis Bus Request
tbits:1 ovr_tmp_ps_off Over Temp. Power Supply Shutdown {AB4}
tbits:1 ppc_addr_retry PowerPC 60x Bus Address Retry {B9}
tbits:5 rsvd Reserved
{}
or ena_mcp_5 7C MCP Enables 43:40
<byte 4419>
utiny value As utiny
endunion ena_mcp_5 7C MCP Enables 43:40
<byte 4420>
{int_sci_3 (83 State Change Interrupt 31:24)}
<byte 4420>
utiny value
{}
<byte 4421>
union int_sci_2 82 State Change Interrupt 23:16
<byte 4421>
{field (By field)}
<byte 4421>
tbits:1 sfp3_l SFP 3 Present Lo {R1}
tbits:1 sfp2_l SFP 2 Present Lo {R2}
tbits:1 sfp1_l SFP 1 Present Lo {R3}
tbits:1 sfp0_l SFP 0 Present Lo {R4}
tbits:1 agent_pres_l Agent Present Lo {T1}
tbits:1 ups1_pres_l UPS 1 Present Lo {T2}
tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3}
tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4}
{}
or int_sci_2 82 State Change Interrupt 23:16
<byte 4421>
utiny value As utiny
endunion int_sci_2 82 State Change Interrupt 23:16
<byte 4422>
union int_sci_1 81 State Change Interrupt 15:08
<byte 4422>
{field (By field)}
<byte 4422>
tbits:1 sfp9_l SFP 9 Present Lo {N5}
tbits:1 sfp8_l SFP 8 Present Lo {N6}
tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1}
tbits:1 lcd_l LCD Present Lo {P2}
tbits:1 sfp7_l SFP 7 Present Lo {P3}
tbits:1 sfp6_l SFP 6 Present Lo {P4}
tbits:1 sfp5_l SFP 5 Present Lo {P5}
tbits:1 sfp4_l SFP 4 Present Lo {P6}
{}
or int_sci_1 81 State Change Interrupt 15:08
<byte 4422>
utiny value As utiny
endunion int_sci_1 81 State Change Interrupt 15:08
<byte 4423>
union int_sci_0 80 State Change Interrupt 07:00
<byte 4423>
{field (By field)}
<byte 4423>
tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3}
tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4}
tbits:1 other_dcok_l Other Controller DC OK Lo {M5}
tbits:1 other_cable_l Other Controller cable present Lo {M6}
tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo
tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo
tbits:1 clf_pres_l Flash Card Present Lo {N3}
tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4}
{}
or int_sci_0 80 State Change Interrupt 07:00
<byte 4423>
utiny value As utiny
endunion int_sci_0 80 State Change Interrupt 07:00
<byte 4424>
union ena_sci_1 87 State Change Int Enable 15:08
<byte 4424>
{field (By field)}
<byte 4424>
tbits:1 sfp9_l SFP 9 Present Lo {N5}
tbits:1 sfp8_l SFP 8 Present Lo {N6}
tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1}
tbits:1 lcd_l LCD Present Lo {P2}
tbits:1 sfp7_l SFP 7 Present Lo {P3}
tbits:1 sfp6_l SFP 6 Present Lo {P4}
tbits:1 sfp5_l SFP 5 Present Lo {P5}
tbits:1 sfp4_l SFP 4 Present Lo {P6}
{}
or ena_sci_1 87 State Change Int Enable 15:08
<byte 4424>
utiny value As utiny
endunion ena_sci_1 87 State Change Int Enable 15:08
<byte 4425>
union ena_sci_0 86 State Change Int Enable 07:00
<byte 4425>
{field (By field)}
<byte 4425>
tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3}
tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4}
tbits:1 other_dcok_l Other Controller DC OK Lo {M5}
tbits:1 other_cable_l Other Controller cable present Lo {M6}
tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo
tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo
tbits:1 clf_pres_l Flash Card Present Lo {N3}
tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4}
{}
or ena_sci_0 86 State Change Int Enable 07:00
<byte 4425>
utiny value As utiny
endunion ena_sci_0 86 State Change Int Enable 07:00
<byte 4426>
{rsvdb (85 Reserved)}
<byte 4426>
utiny value
{}
<byte 4427>
union int_sci_4 84 State Change Interrupt 39:32
<byte 4427>
{field (By field)}
<byte 4427>
tbits:1 batt_det Battery Detect
tbits:1 blower_det Blower Detect
tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect
tbits:1 meltdown_temp_det Meltdown Temperature detect
tbits:4 rsvd Reserved
{}
or int_sci_4 84 State Change Interrupt 39:32
<byte 4427>
utiny value As utiny
endunion int_sci_4 84 State Change Interrupt 39:32
<byte 4428>
{rsvdc (8B Reserved)}
<byte 4428>
utiny value
{}
<byte 4429>
union ena_sci_4 8A State Change Int Enable 39:32
<byte 4429>
{field (By field)}
<byte 4429>
tbits:1 batt_det Battery Detect
tbits:1 blower_det Blower Detect
tbits:1 meltdown_temp_minus_4C_det Meltdown Temp minus 4 degrees C detect
tbits:1 meltdown_temp_det Meltdown Temperature detect
tbits:4 rsvd Reserved
{}
or ena_sci_4 8A State Change Int Enable 39:32
<byte 4429>
utiny value As utiny
endunion ena_sci_4 8A State Change Int Enable 39:32
<byte 4430>
{ena_sci_3 (89 State Change Int Enable 31:24)}
<byte 4430>
utiny value
{}
<byte 4431>
union ena_sci_2 88 State Change Int Enable 23:16
<byte 4431>
{field (By field)}
<byte 4431>
tbits:1 sfp3_l SFP 3 Present Lo {R1}
tbits:1 sfp2_l SFP 2 Present Lo {R2}
tbits:1 sfp1_l SFP 1 Present Lo {R3}
tbits:1 sfp0_l SFP 0 Present Lo {R4}
tbits:1 agent_pres_l Agent Present Lo {T1}
tbits:1 ups1_pres_l UPS 1 Present Lo {T2}
tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3}
tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4}
{}
or ena_sci_2 88 State Change Int Enable 23:16
<byte 4431>
utiny value As utiny
endunion ena_sci_2 88 State Change Int Enable 23:16
<byte 4432>
{sc_in_3 (8F State Change Inputs 31:24)}
<byte 4432>
utiny value
{}
<byte 4433>
union sc_in_2 8E State Change Inputs 23:16
<byte 4433>
{field (By field)}
<byte 4433>
tbits:1 sfp3_l SFP 3 Present Lo {R1}
tbits:1 sfp2_l SFP 2 Present Lo {R2}
tbits:1 sfp1_l SFP 1 Present Lo {R3}
tbits:1 sfp0_l SFP 0 Present Lo {R4}
tbits:1 agent_pres_l Agent Present Lo {T1}
tbits:1 ups1_pres_l UPS 1 Present Lo {T2}
tbits:1 ps_a_dcok_l Power Supply A DC OK Lo {U3}
tbits:1 ps_b_dcok_l Power Supply B DC OK Lo {U4}
{}
or sc_in_2 8E State Change Inputs 23:16
<byte 4433>
utiny value As utiny
endunion sc_in_2 8E State Change Inputs 23:16
<byte 4434>
union sc_in_1 8D State Change Inputs 15:08
<byte 4434>
{field (By field)}
<byte 4434>
tbits:1 sfp9_l SFP 9 Present Lo {N5}
tbits:1 sfp8_l SFP 8 Present Lo {N6}
tbits:1 sprite_hw_rdy_l Sprite HW ready Lo {P1}
tbits:1 lcd_l LCD Present Lo {P2}
tbits:1 sfp7_l SFP 7 Present Lo {P3}
tbits:1 sfp6_l SFP 6 Present Lo {P4}
tbits:1 sfp5_l SFP 5 Present Lo {P5}
tbits:1 sfp4_l SFP 4 Present Lo {P6}
{}
or sc_in_1 8D State Change Inputs 15:08
<byte 4434>
utiny value As utiny
endunion sc_in_1 8D State Change Inputs 15:08
<byte 4435>
union sc_in_0 8C State Change Inputs 07:00
<byte 4435>
{field (By field)}
<byte 4435>
tbits:1 ps_b_pres_l Power Supply B Present (Int=1) {M3}
tbits:1 ps_a_pres_l Power Supply A Present (Int=1) {M4}
tbits:1 other_dcok_l Other Controller DC OK Lo {M5}
tbits:1 other_cable_l Other Controller cable present Lo {M6}
tbits:1 bhm_pres_l Bulkhead Modules (Int=1) {N1} Present Lo
tbits:1 mpi_pres_l Mid Plane Interconnect (Int=1) {N2} Present Lo
tbits:1 clf_pres_l Flash Card Present Lo {N3}
tbits:1 other_ok_l Other Controller OK Lo (Int=1) {N4}
{}
or sc_in_0 8C State Change Inputs 07:00
<byte 4435>
utiny value As utiny
endunion sc_in_0 8C State Change Inputs 07:00
<byte 4436>
{rsvdd[0] (93-9F Reserved)}
<byte 4436>
utiny value
{}
<byte 4437>
{batt_good_tp (92 Battery Good Trip Point)}
<byte 4437>
utiny value
{}
<byte 4438>
{batt_lo_tp (91 Battery Low Trip Point)}
<byte 4438>
utiny value
{}
<byte 4439>
{melt_down (90 Meltdown Temp.)}
<byte 4439>
utiny value
{}
<byte 4440>
{rsvdd[4] (93-9F Reserved)}
<byte 4440>
utiny value
{}
<byte 4441>
{rsvdd[3] (93-9F Reserved)}
<byte 4441>
utiny value
{}
<byte 4442>
{rsvdd[2] (93-9F Reserved)}
<byte 4442>
utiny value
{}
<byte 4443>
{rsvdd[1] (93-9F Reserved)}
<byte 4443>
utiny value
{}
<byte 4444>
{rsvdd[8] (93-9F Reserved)}
<byte 4444>
utiny value
{}
<byte 4445>
{rsvdd[7] (93-9F Reserved)}
<byte 4445>
utiny value
{}
<byte 4446>
{rsvdd[6] (93-9F Reserved)}
<byte 4446>
utiny value
{}
<byte 4447>
{rsvdd[5] (93-9F Reserved)}
<byte 4447>
utiny value
{}
<byte 4448>
{rsvdd[12] (93-9F Reserved)}
<byte 4448>
utiny value
{}
<byte 4449>
{rsvdd[11] (93-9F Reserved)}
<byte 4449>
utiny value
{}
<byte 4450>
{rsvdd[10] (93-9F Reserved)}
<byte 4450>
utiny value
{}
<byte 4451>
{rsvdd[9] (93-9F Reserved)}
<byte 4451>
utiny value
{}
<byte 4452>
union reset_dev_0 A3 GPO D: Reset Devices Ctrl 0
<byte 4452>
{field (By field)}
<byte 4452>
tbits:1 dx2_a_l DX2 A Reset Lo {M21}
tbits:1 dx2_b_l DX2 B Reset Lo {M20}
tbits:1 dx2_c_l DX2 C Reset Lo {M19}
tbits:1 dx2_d_l DX2 D Reset Lo {M18}
tbits:1 sprite_l SPRITE Reset Lo {D1}
tbits:1 uart_l UART Reset Lo {W17}
tbits:1 enet1_l Ethernet 1 Reset Lo {Y17}
tbits:1 enet2_l Ethernet 2 Reset Lo {AA18}
{}
or reset_dev_0 A3 GPO D: Reset Devices Ctrl 0
<byte 4452>
utiny value As utiny
endunion reset_dev_0 A3 GPO D: Reset Devices Ctrl 0
<byte 4453>
union reprog_misc A2 GPO C: Reprog. & Misc. Ctrl
<byte 4453>
{field (By field)}
<byte 4453>
tbits:1 prog_sdc SDC reprogram mode (prog=1) {Y13}
tbits:1 prog_can CAN reprogram mode (prog=1) {W13}
tbits:1 prog_lcd LCD reprogram mode (prog=1) {V13}
tbits:1 rpgm_clk Shared PIC reprogram clock {U13}
tbits:1 rpgm_data Shared PIC reprogram data {U14}
tbits:1 dx2_e_l DX2 E Reset L {V14}
tbits:1 sdc_wdt SDC watchdog enable {Y5}
tbits:1 rsvd R Reserved {G2}
{}
or reprog_misc A2 GPO C: Reprog. & Misc. Ctrl
<byte 4453>
utiny value As utiny
endunion reprog_misc A2 GPO C: Reprog. & Misc. Ctrl
<byte 4454>
union sfp_laser A1 GPO B: SFP Laser Disable Ctrl
<byte 4454>
{field (By field)}
<byte 4454>
tbits:1 disable_0 SFP Laser 0 Disable (dis=1) {E18}
tbits:1 disable_1 SFP Laser 1 Disable (dis=1) {F18}
tbits:1 disable_2 SFP Laser 2 Disable (dis=1) {G22}
tbits:1 disable_3 SFP Laser 3 Disable (dis=1) {G21}
tbits:1 disable_4 SFP Laser 4 Disable (dis=1) {H22}
tbits:1 disable_5 SFP Laser 5 Disable (dis=1) {H21}
tbits:1 disable_6 SFP Laser 6 Disable (dis=1) {H20}
tbits:1 disable_7 SFP Laser 7 Disable (dis=1) {H19}
{}
or sfp_laser A1 GPO B: SFP Laser Disable Ctrl
<byte 4454>
utiny value As utiny
endunion sfp_laser A1 GPO B: SFP Laser Disable Ctrl
<byte 4455>
union pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals
<byte 4455>
{field (By field)}
<byte 4455>
tbits:1 bus0_stop_l Bus 0 STOP Lo {C22}
tbits:1 bus0_trdy_l Bus 0 TRDY Lo {C21}
tbits:1 bus0_devsel_l Bus 0 DEVSEL0 Lo {D22}
tbits:1 bus0_req64_l Bus 0 REQ64 Lo {D21}
tbits:2 rsvd1 Reserved
tbits:1 pcix1_cfg_en PCIX1 Configuration Enable {E20}
tbits:1 rsvd Reserved
{}
or pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals
<byte 4455>
utiny value As utiny
endunion pcix01 A0 GPO A: PCIX 0 & 1 Bus Signals
<byte 4456>
union gbic_act A7 GPI I: GBIC active
<byte 4456>
{field (By field)}
<byte 4456>
tbits:1 dx2a_f0 DX2A F0 ACTIVE {W1}
tbits:1 dx2b_f0 DX2B F0 ACTIVE {W2}
tbits:1 dx2c_f0 DX2C F0 ACTIVE {V3}
tbits:1 dx2d_f0 DX2D F0 ACTIVE {V4}
tbits:1 dx2e_f0 DX2E F0 ACTIVE {H2}
tbits:1 temp0_ovr_thresh Temp Sensor 0 Over Threshold {AB19}
tbits:1 temp1_ovr_thresh Temp Sensor 1 Over Threshold {AA17}
tbits:1 temp2_ovr_thresh Temp Sensor 2 Over Threshold {Y18}
{}
or gbic_act A7 GPI I: GBIC active
<byte 4456>
utiny value As utiny
endunion gbic_act A7 GPI I: GBIC active
<byte 4457>
union gbic_led A6 GPO G: GBIC LED Control
<byte 4457>
{field (By field)}
<byte 4457>
tbits:1 amb0_l R/W Amber 0 LED FLASH OFF Lo {E16}
tbits:1 amb1_l R/W Amber 1 LED FLASH OFF Lo {E17}
tbits:1 amb2_l R/W Amber 2 LED FLASH OFF Lo {A17}
tbits:1 amb3_l R/W Amber 3 LED FLASH OFF Lo {B17}
tbits:1 amb4_l R/W Amber 4 LED FLASH OFF Lo {C17}
tbits:1 amb5_l R/W Amber 5 LED FLASH OFF Lo {D17}
tbits:1 amb6_l R/W Amber 6 LED FLASH OFF Lo {A18}
tbits:1 amb7_l R/W Amber 7 LED FLASH OFF Lo {B18}
{}
or gbic_led A6 GPO G: GBIC LED Control
<byte 4457>
utiny value As utiny
endunion gbic_led A6 GPO G: GBIC LED Control
<byte 4458>
union gp_in A5 GPI F: Kills, msref_req, etc.
<byte 4458>
{field (By field)}
<byte 4458>
tbits:1 other_kill_2 Other Kill 2 {AB15}
tbits:1 other_kill_1 Other Kill 1 {AA15}
tbits:1 rsvd Reserved {AB17}
tbits:1 spr_debug2 Sprite Debug Bit2 {B8}
tbits:1 msref_req_l MSREF_REQ Sense Line (0=SelfRef){AB14}
tbits:1 lcd_ready LCD Ready {L22}
tbits:1 spr_debug3 Sprite Debug Bit3 {A8}
tbits:1 rpgm_data_in Shared PIC reprogram data in {W14}
{}
or gp_in A5 GPI F: Kills, msref_req, etc.
<byte 4458>
utiny value As utiny
endunion gp_in A5 GPI F: Kills, msref_req, etc.
<byte 4459>
union reset_dev_1 A4 GPO E: Reset Devices Ctrl 1
<byte 4459>
{field (By field)}
<byte 4459>
tbits:1 agent_l AGENT Reset Lo {AB5}
tbits:1 sdc_l SDC Reset Lo {AA5}
tbits:1 can_l CAN Reset Lo {Y6}
tbits:1 lcd_l LCD Reset Lo {W6}
tbits:1 toy_l TOY Reset Lo {V6}
tbits:1 rsvd1 Reserved {V7}
tbits:1 dpm_rdy PPC not accessing DPM {AB19}
tbits:1 sdc_int_l glue to sdc interrupt (Int=0) {AB18}
{}
or reset_dev_1 A4 GPO E: Reset Devices Ctrl 1
<byte 4459>
utiny value As utiny
endunion reset_dev_1 A4 GPO E: Reset Devices Ctrl 1
<byte 4460>
{rsvde[2] (A9-AE Reserved)}
<byte 4460>
utiny value
{}
<byte 4461>
{rsvde[1] (A9-AE Reserved)}
<byte 4461>
utiny value
{}
<byte 4462>
{rsvde[0] (A9-AE Reserved)}
<byte 4462>
utiny value
{}
<byte 4463>
union gbic_led8 A8 GPO H: GBIC LED Control
<byte 4463>
{field (By field)}
<byte 4463>
tbits:1 amb8_l R/W Amber 8 LED FLASH OFF Lo {Y2}
tbits:1 amb9_l R/W Amber 9 LED FLASH OFF Lo {Y1}
tbits:1 disable_8 SFP Laser 8 Disable (dis=1) {U5}
tbits:1 disable_9 SFP Laser 9 Disable (dis=1) {V5}
tbits:4 unused unused
{}
or gbic_led8 A8 GPO H: GBIC LED Control
<byte 4463>
utiny value As utiny
endunion gbic_led8 A8 GPO H: GBIC LED Control
<byte 4464>
union cache_ctrl AF Cache DIMM Control
<byte 4464>
{field (By field)}
<byte 4464>
tbits:1 msref_req_l R/W MSREF_REQ (0=Self-Refresh) {AB8}
tbits:1 dimm0_rst_l R/W DIMM 0 Reset Lo {D10}
tbits:1 dimm1_rst_l R/W DIMM 1 Reset Lo {C10}
tbits:1 dimm2_rst_l R/W DIMM 2 Reset Lo {B10}
tbits:1 dimm3_rst_l R/W DIMM 3 Reset Lo {A10}
tbits:1 bbu_dcok_clear R/W BBU DIMM DC OK LATCH CLEAR {AA8}
tbits:1 batt_on_l R/W Battery Turn ON Lo (to preset) {Y8}
tbits:1 batt_off_l R/W Battery Turn OFF Lo (to clear) {W8}
{}
or cache_ctrl AF Cache DIMM Control
<byte 4464>
utiny value As utiny
endunion cache_ctrl AF Cache DIMM Control
<byte 4465>
{rsvde[5] (A9-AE Reserved)}
<byte 4465>
utiny value
{}
<byte 4466>
{rsvde[4] (A9-AE Reserved)}
<byte 4466>
utiny value
{}
<byte 4467>
{rsvde[3] (A9-AE Reserved)}
<byte 4467>
utiny value
{}
<byte 4468>
{ppc_data[2] (B1-B4 PPC command data)}
<byte 4468>
utiny value
{}
<byte 4469>
{ppc_data[1] (B1-B4 PPC command data)}
<byte 4469>
utiny value
{}
<byte 4470>
{ppc_data[0] (B1-B4 PPC command data)}
<byte 4470>
utiny value
{}
<byte 4471>
{ppc_cmd (B0 PPC command to SDC)}
<byte 4471>
utiny value
{}
<byte 4472>
{sdc_toy[1] (B6-BC sdc toy data)}
<byte 4472>
utiny value
{}
<byte 4473>
{sdc_toy[0] (B6-BC sdc toy data)}
<byte 4473>
utiny value
{}
<byte 4474>
{rsvb5 (B5 Reserved)}
<byte 4474>
utiny value
{}
<byte 4475>
{ppc_data[3] (B1-B4 PPC command data)}
<byte 4475>
utiny value
{}
<byte 4476>
{sdc_toy[5] (B6-BC sdc toy data)}
<byte 4476>
utiny value
{}
<byte 4477>
{sdc_toy[4] (B6-BC sdc toy data)}
<byte 4477>
utiny value
{}
<byte 4478>
{sdc_toy[3] (B6-BC sdc toy data)}
<byte 4478>
utiny value
{}
<byte 4479>
{sdc_toy[2] (B6-BC sdc toy data)}
<byte 4479>
utiny value
{}
<byte 4480>
union blower_led BF Blower LED Override Control
<byte 4480>
{field (By field)}
<byte 4480>
tbits:1 grn_blwr_a R/W Green Blower A LED
tbits:1 amb_blwr_a R/W Amber Blower A LED
tbits:1 grn_blwr_b R/W Green Blower B LED
tbits:1 amb_blwr_b R/W Amber Blower B LED
tbits:4 rsvd R Reserved
{}
or blower_led BF Blower LED Override Control
<byte 4480>
utiny value As utiny
endunion blower_led BF Blower LED Override Control
<byte 4481>
union batt_led BE Battery LED Override Control
<byte 4481>
{field (By field)}
<byte 4481>
tbits:1 grn_brk0 R/W Green Brick 0 LED
tbits:1 amb_brk0 R/W Amber Brick 0 LED
tbits:1 grn_brk1 R/W Green Brick 1 LED
tbits:1 amb_brk1 R/W Amber Brick 1 LED
tbits:1 grn_brk2 R/W Green Brick 2 LED
tbits:1 amb_brk2 R/W Amber Brick 2 LED
tbits:1 grn_brk3 R/W Green Brick 3 LED
tbits:1 amb_brk3 R/W Amber Brick 3 LED
{}
or batt_led BE Battery LED Override Control
<byte 4481>
utiny value As utiny
endunion batt_led BE Battery LED Override Control
<byte 4482>
{rsvbd (BD Reserved)}
<byte 4482>
utiny value
{}
<byte 4483>
{sdc_toy[6] (B6-BC sdc toy data)}
<byte 4483>
utiny value
{}
<byte 4484>
{batt_mod_rev[3] (C0-C3 Battery Mod. Rev.)}
<byte 4484>
utiny value
{}
<byte 4485>
{batt_mod_rev[2] (C0-C3 Battery Mod. Rev.)}
<byte 4485>
utiny value
{}
<byte 4486>
{batt_mod_rev[1] (C0-C3 Battery Mod. Rev.)}
<byte 4486>
utiny value
{}
<byte 4487>
{batt_mod_rev[0] (C0-C3 Battery Mod. Rev.)}
<byte 4487>
utiny value
{}
<byte 4488>
{avg_temp (C7 Average Temperature)}
<byte 4488>
utiny value
{}
<byte 4489>
{temp_sensor[2] (C4-C6 Temp. Sensors 1, 2, & 3)}
<byte 4489>
utiny value
{}
<byte 4490>
{temp_sensor[1] (C4-C6 Temp. Sensors 1, 2, & 3)}
<byte 4490>
utiny value
{}
<byte 4491>
{temp_sensor[0] (C4-C6 Temp. Sensors 1, 2, & 3)}
<byte 4491>
utiny value
{}
<byte 4492>
{backup_time[1] (CA-CB backup time in x Watt-Sec)}
<byte 4492>
utiny value
{}
<byte 4493>
{backup_time[0] (CA-CB backup time in x Watt-Sec)}
<byte 4493>
utiny value
{}
<byte 4494>
{blower_rpm[1] (C8-C9 RPMs, Blowers 0 & 1)}
<byte 4494>
utiny value
{}
<byte 4495>
{blower_rpm[0] (C8-C9 RPMs, Blowers 0 & 1)}
<byte 4495>
utiny value
{}
<byte 4496>
{rsvcf (CF Spare Read Registers)}
<byte 4496>
utiny value
{}
<byte 4497>
{volts_12v (CE 12V Level)}
<byte 4497>
utiny value
{}
<byte 4498>
{sdc_major_rev (CD SDC Major Revision)}
<byte 4498>
utiny value
{}
<byte 4499>
{sdc_minor_rev (CC SDC Minor Revision)}
<byte 4499>
utiny value
{}
<byte 4500>
{brick_status[1] (D2-D5 brick interrupt status)}
<byte 4500>
utiny value
{}
<byte 4501>
{brick_status[0] (D2-D5 brick interrupt status)}
<byte 4501>
utiny value
{}
<byte 4502>
union sdc_int_cause1 D1 SDC interrupt cause1
<byte 4502>
{field (By field)}
<byte 4502>
tbits:1 rsvd R/WA0 Reserved
tbits:1 cmd_processed R/WA0 PPC command has been processed
tbits:2 rsvd1 R/WA0 Reserved
tbits:1 hut_changed R/WA0 Hold up time changed
tbits:2 rsvd2 R/WA0 Reserved
tbits:1 time_req R/WA0 SDC time request
{}
or sdc_int_cause1 D1 SDC interrupt cause1
<byte 4502>
utiny value As utiny
endunion sdc_int_cause1 D1 SDC interrupt cause1
<byte 4503>
union sdc_int_cause0 D0 SDC interrupt cause0
<byte 4503>
{field (By field)}
<byte 4503>
tbits:1 brick0 R/WA0 Brick 0
tbits:1 brick1 R/WA0 Brick 1
tbits:1 brick2 R/WA0 Brick 2
tbits:1 brick3 R/WA0 Brick 3
tbits:1 blower0 R/WA0 Blower 0
tbits:1 blower1 R/WA0 Blower 1
tbits:1 temperature R/WA0 Temperature
tbits:1 rsvd R/WA0 Reserved
{}
or sdc_int_cause0 D0 SDC interrupt cause0
<byte 4503>
utiny value As utiny
endunion sdc_int_cause0 D0 SDC interrupt cause0
<byte 4504>
{blower_status[1] (D6-D7 blower interrupt status)}
<byte 4504>
utiny value
{}
<byte 4505>
{blower_status[0] (D6-D7 blower interrupt status)}
<byte 4505>
utiny value
{}
<byte 4506>
{brick_status[3] (D2-D5 brick interrupt status)}
<byte 4506>
utiny value
{}
<byte 4507>
{brick_status[2] (D2-D5 brick interrupt status)}
<byte 4507>
utiny value
{}
<byte 4508>
{sdc_cmd_status (DB Battery Hold Up Time)}
<byte 4508>
utiny value
{}
<byte 4509>
union fru_detect DA fru detect bits
<byte 4509>
{field (By field)}
<byte 4509>
tbits:1 brick0_present R
tbits:1 brick1_present R
tbits:1 brick2_present R
tbits:1 brick3_present R
tbits:1 blower0_present R
tbits:1 blower1_present R
tbits:2 rsvd R
{}
or fru_detect DA fru detect bits
<byte 4509>
utiny value As utiny
endunion fru_detect DA fru detect bits
<byte 4510>
{sdc_status (D9 SDC codeload and brick test results)}
<byte 4510>
utiny value
{}
<byte 4511>
{tmp_status (D8 temperature interrupt status)}
<byte 4511>
utiny value
{}
<byte 4512>
{sdc_cmd_data[3] (DC-DF Reserved)}
<byte 4512>
utiny value
{}
<byte 4513>
{sdc_cmd_data[2] (DC-DF Reserved)}
<byte 4513>
utiny value
{}
<byte 4514>
{sdc_cmd_data[1] (DC-DF Reserved)}
<byte 4514>
utiny value
{}
<byte 4515>
{sdc_cmd_data[0] (DC-DF Reserved)}
<byte 4515>
utiny value
{}
<byte 4516>
{scratch[3] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4516>
utiny value
{}
<byte 4517>
{scratch[2] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4517>
utiny value
{}
<byte 4518>
{scratch[1] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4518>
utiny value
{}
<byte 4519>
{scratch[0] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4519>
utiny value
{}
<byte 4520>
{scratch[7] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4520>
utiny value
{}
<byte 4521>
{scratch[6] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4521>
utiny value
{}
<byte 4522>
{scratch[5] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4522>
utiny value
{}
<byte 4523>
{scratch[4] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4523>
utiny value
{}
<byte 4524>
{scratch[11] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4524>
utiny value
{}
<byte 4525>
{scratch[10] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4525>
utiny value
{}
<byte 4526>
{scratch[9] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4526>
utiny value
{}
<byte 4527>
{scratch[8] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4527>
utiny value
{}
<byte 4528>
{scratch[15] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4528>
utiny value
{}
<byte 4529>
{scratch[14] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4529>
utiny value
{}
<byte 4530>
{scratch[13] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4530>
utiny value
{}
<byte 4531>
{scratch[12] (E0-EF R/W Scratch Registers: Hardware team maintains right to reserve higher bytes if future Glue features need the space.)}
<byte 4531>
utiny value
{}
<byte 4532>
{rsvd12[3] (F0-FD Reserved)}
<byte 4532>
utiny value
{}
<byte 4533>
{rsvd12[2] (F0-FD Reserved)}
<byte 4533>
utiny value
{}
<byte 4534>
{rsvd12[1] (F0-FD Reserved)}
<byte 4534>
utiny value
{}
<byte 4535>
{rsvd12[0] (F0-FD Reserved)}
<byte 4535>
utiny value
{}
<byte 4536>
{rsvd12[7] (F0-FD Reserved)}
<byte 4536>
utiny value
{}
<byte 4537>
{rsvd12[6] (F0-FD Reserved)}
<byte 4537>
utiny value
{}
<byte 4538>
{rsvd12[5] (F0-FD Reserved)}
<byte 4538>
utiny value
{}
<byte 4539>
{rsvd12[4] (F0-FD Reserved)}
<byte 4539>
utiny value
{}
<byte 4540>
{rsvd12[11] (F0-FD Reserved)}
<byte 4540>
utiny value
{}
<byte 4541>
{rsvd12[10] (F0-FD Reserved)}
<byte 4541>
utiny value
{}
<byte 4542>
{rsvd12[9] (F0-FD Reserved)}
<byte 4542>
utiny value
{}
<byte 4543>
{rsvd12[8] (F0-FD Reserved)}
<byte 4543>
utiny value
{}
<byte 4544>
{glue_major_rev (FF Glue Major Revision)}
<byte 4544>
utiny value
{}
<byte 4545>
{glue_minor_rev (FE Glue Minor Revision)}
<byte 4545>
utiny value
{}
<byte 4546>
{rsvd12[13] (F0-FD Reserved)}
<byte 4546>
utiny value
{}
<byte 4547>
{rsvd12[12] (F0-FD Reserved)}
<byte 4547>
utiny value
{}
{}
<byte 4548>
do_not_display[768] union_pad Union Element Padding (DO NOT DISPLAY!)
endunion csr Glue CSR Registers
{}
<byte 5316>
{sprite (Sprite register save area)}
<byte 5316>
union csr Sprite CSR Registers
<byte 5316>
ulong[256] csra Sprite CSR Registers As Longwords
or csr Sprite CSR Registers
<byte 5316>
{csrfield (Sprite CSR Registers By Field)}
<byte 5316>
union pc_cba 000 ppc chip base address
<byte 5316>
{field (By field)}
<byte 5316>
lbits:4 rev R Revision of Sprite
lbits:5 rsvd R Reserved
lbits:23 reg_base_addr R/W Register Base Address
{}
or pc_cba 000 ppc chip base address
<byte 5316>
ulong value As longword
endunion pc_cba 000 ppc chip base address
<byte 5320>
union pc_m0_a 004 ppc to DDR memory window 0 description
<byte 5320>
{field (By field)}
<byte 5320>
lbits:12 ddr_addr R/W DDR base address, bits 35:xx
lbits:2 rsvd R Reserved
lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved
lbits:8 size R/W Window size, 16MB -> 2GB
lbits:8 base_addr R/W Sets bits 31:24 of base address
{}
or pc_m0_a 004 ppc to DDR memory window 0 description
<byte 5320>
ulong value As longword
endunion pc_m0_a 004 ppc to DDR memory window 0 description
<byte 5324>
union pc_m1_a 008 ppc to DDR memory window 1 description
<byte 5324>
{field (By field)}
<byte 5324>
lbits:12 ddr_addr R/W DDR base address, bits 35:xx
lbits:2 rsvd R Reserved
lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved
lbits:8 size R/W Window size, 16MB -> 2GB
lbits:8 base_addr R/W Sets bits 31:24 of base address
{}
or pc_m1_a 008 ppc to DDR memory window 1 description
<byte 5324>
ulong value As longword
endunion pc_m1_a 008 ppc to DDR memory window 1 description
<byte 5328>
union pc_m2_a 00c ppc to DDR memory window 2 description
<byte 5328>
{field (By field)}
<byte 5328>
lbits:12 ddr_addr R/W DDR base address, bits 35:xx
lbits:2 rsvd R Reserved
lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved
lbits:8 size R/W Window size, 16MB -> 2GB
lbits:8 base_addr R/W Sets bits 31:24 of base address
{}
or pc_m2_a 00c ppc to DDR memory window 2 description
<byte 5328>
ulong value As longword
endunion pc_m2_a 00c ppc to DDR memory window 2 description
<byte 5332>
union pc_m3_a 010 ppc to DDR memory window 3 description
<byte 5332>
{field (By field)}
<byte 5332>
lbits:12 ddr_addr R/W DDR base address, bits 35:xx
lbits:2 rsvd R Reserved
lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved
lbits:8 size R/W Window size, 16MB -> 2GB
lbits:8 base_addr R/W Sets bits 31:24 of base address
{}
or pc_m3_a 010 ppc to DDR memory window 3 description
<byte 5332>
ulong value As longword
endunion pc_m3_a 010 ppc to DDR memory window 3 description
<byte 5336>
union pc_p0_a 014 ppc to PCIX0 memory space window description
<byte 5336>
{field (By field)}
<byte 5336>
lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved
lbits:2 rsvd1 R Reserved
lbits:12 size R/W Window size, 1MB -> 2GB
lbits:4 rsvd R Reserved
lbits:12 base_addr R/W Sets bits 31:20 of base address
{}
or pc_p0_a 014 ppc to PCIX0 memory space window description
<byte 5336>
ulong value As longword
endunion pc_p0_a 014 ppc to PCIX0 memory space window description
<byte 5340>
{pc_p0_ua (018 ppc to PCIX0 upper address)}
<byte 5340>
ulong value
{}
<byte 5344>
union pc_p1_a 01c ppc to PCIX1 memory space window description
<byte 5344>
{field (By field)}
<byte 5344>
lbits:2 byte_swap R/W No swap, Quasar Emulation, or 32-bit Value Preserved
lbits:2 rsvd1 R Reserved
lbits:12 size R/W Window size, 1MB -> 2GB
lbits:4 rsvd R Reserved
lbits:12 base_addr R/W Sets bits 31:20 of base address
{}
or pc_p1_a 01c ppc to PCIX1 memory space window description
<byte 5344>
ulong value As longword
endunion pc_p1_a 01c ppc to PCIX1 memory space window description
<byte 5348>
{pc_p1_ua (020 ppc to PCIX1 upper address)}
<byte 5348>
ulong value
{}
<byte 5352>
union pc_io_a 024 ppc lower IO address description
<byte 5352>
{field (By field)}
<byte 5352>
lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1
lbits:1 rsvd R Reserved
lbits:30 base_addr R/W Sets bits 31:02 of base address
{}
or pc_io_a 024 ppc lower IO address description
<byte 5352>
ulong value As longword
endunion pc_io_a 024 ppc lower IO address description
<byte 5356>
union pc_dls 028 mirror data has left sprite counter
<byte 5356>
{field (By field)}
<byte 5356>
lbits:16 count R/WTI Count of writes to this reg.
lbits:16 rsvd R Reserved
{}
or pc_dls 028 mirror data has left sprite counter
<byte 5356>
ulong value As longword
endunion pc_dls 028 mirror data has left sprite counter
<byte 5360>
union pc_cfg_add 02c ppc configuration address phase description
<byte 5360>
{field (By field)}
<byte 5360>
lbits:1 pcix_bus R/W 0 = PCIX0, 1 = PCIX1
lbits:1 rsvd1 R Reserved
lbits:6 Register R/W Register Number
lbits:3 Function R/W Function Number
lbits:5 device R/W Device Number
lbits:8 bus R/W Bus Number
lbits:8 rsvd R Reserved
{}
or pc_cfg_add 02c ppc configuration address phase description
<byte 5360>
ulong value As longword
endunion pc_cfg_add 02c ppc configuration address phase description
<byte 5364>
union pc_wtt 030 ppc watchdog transfer timeout
<byte 5364>
{field (By field)}
<byte 5364>
lbits:19 wd_lo R Lower Bits of Count Value
lbits:8 wd_hi R/W Programmable Extra Count Value
lbits:4 rsvd R Reserved
lbits:1 wd_ena R/W Watchdog Enable
{}
or pc_wtt 030 ppc watchdog transfer timeout
<byte 5364>
ulong value As longword
endunion pc_wtt 030 ppc watchdog transfer timeout
<byte 5368>
union pc_tt 034 ppc transfer timeout
<byte 5368>
{field (By field)}
<byte 5368>
lbits:16 ttcounter R/W Transfer Timeout Counter
lbits:16 rsvd R Reserved
{}
or pc_tt 034 ppc transfer timeout
<byte 5368>
ulong value As longword
endunion pc_tt 034 ppc transfer timeout
<byte 5372>
union pc_csr 038 ppc control and status
<byte 5372>
{field (By field)}
<byte 5372>
lbits:1 esum_ddr_me R/CLL DDR Memory Error Summary
lbits:1 esum_mir_me R/CLL Mirror Memory Error Summary
lbits:1 esum_xor_dma R/CLL XOR-DMA Error Summary
lbits:1 esum_que R/CLL Queue Error Summary
lbits:1 esum_pcix1 R/CLL PCIX1 Error Summary
lbits:1 esum_pcix0 R/CLL PCIX0 Error Summary
lbits:1 err_pcixae R/W1C PCIX Access Error
lbits:1 err_qrdpe R/W1C Queue Read Data Parity Error
lbits:1 err_ppcttoe R/W1C PowerPC Transfer TimeOut Error
lbits:1 err_ppcae R/W1C PowerPC Alignment Error
lbits:1 err_ppcwdpe R/W1C PowerPC Write Data Parity Err
lbits:1 err_ppcape R/W1C PowerPC Address Parity Error
lbits:1 err_ppclee R/W1C PowerPC Last Entry Error
lbits:1 err_ppc2pcixtoe R/W1C PowerPC-PCIX Transfer Timeout
lbits:1 ena_pcixae R/W Enable PCIX Access Error
lbits:1 ena_qrdpe R/W Enable Queue Rd Data Parity Er
lbits:1 ena_ppcttoe R/W Enable PPC Transfer T.O. Error
lbits:1 ena_ppcae R/W Enable PPC Alignment Error
lbits:1 ena_ppcwdpe R/W Enable PPC Wrt Data Parity Err
lbits:1 ena_ppcape R/W Enable PPC Address Parity Err
lbits:1 ena_ppclee R/W Enable PPC Last Entry Error
lbits:1 ena_ppc2pcixtoe R/W Enable PPC-PCIX Transfer T.O.
lbits:1 ena_p_int1 R/W Ena PPC errs on INT1_L to Glue
lbits:1 ena_p_int0 R/W Ena PPC errs on INT0_L to Glue
lbits:1 sel_pcixae R/W Select P_INT(0/1)_L for pcixae
lbits:1 sel_qrddpe R/W Select P_INT(0/1)_L for qrddpe
lbits:1 sel_ppcttoe R/W Select P_INT(0/1)_L for ppcttoe
lbits:1 sel_ppcae R/W Select P_INT(0/1)_L for ppcae
lbits:1 sel_ppcwdpe R/W Select P_INT(0/1)_L for ppcwdpe
lbits:1 sel_ppcape R/W Select P_INT(0/1)_L for ppcape
lbits:1 sel_ppclee R/W Select P_INT(0/1)_L for ppclee
lbits:1 sel_ppc2pcixtoe R/W Sel P_INT(0/1)_L 4 ppc2pcixtoe
{}
or pc_csr 038 ppc control and status
<byte 5372>
ulong value As longword
endunion pc_csr 038 ppc control and status
<byte 5376>
union pc_err 03c ppc error status
<byte 5376>
{field (By field)}
<byte 5376>
lbits:1 hlt_mirror R/W Halt Mirror Block
lbits:1 hlt_pcix1 R/W Halt PCIX 1 Block
lbits:1 hlt_pcix0 R/W Halt PCIX 0 Block
lbits:1 hlt_queue R/W Halt Queue Block
lbits:1 hlt_ddrm R/W Halt DDR Memory Block
lbits:1 hlt_dma R/W Halt DMA Block
lbits:1 ena_tea R/W Enable Transfer Err Ack (TEA)
lbits:1 rsvd1 R Reserved
lbits:1 chk_even_ap R/W Set to Check Even Addr Parity
lbits:1 chk_even_wrp R/W Set to Check Even WR Parity
lbits:1 chk_even_rdp R/W Set to Check Even RD Parity
lbits:1 gen_even_wrp R/W Set to Generate Even WR Parity
lbits:1 gen_even_rdp R/W Set to Generate Even RD Parity
lbits:1 ppc_mode R/W PowerPC Mode (1=7450 / 0=other)
lbits:1 clr_hltd_mirror R/W Clear Mirror Halted Condition
lbits:1 clr_hltd_pcix1 R/W Clear PCIX 1 Halted Condition
lbits:1 clr_hltd_pcix0 R/W Clear PCIX 0 Halted Condition
lbits:1 clr_hltd_ddq R/W Clear dma,ddrm,queue Halt Cond.
lbits:8 rsvd R Reserved
lbits:1 hltd_mirror R Mirror Halted
lbits:1 hltd_pcix1 R PCIX 1 Halted
lbits:1 hltd_pcix0 R PCIX 0 Halted
lbits:1 hltd_queue R Queue Halted
lbits:1 hltd_ddrm R DDR Memory Halted
lbits:1 hltd_dma R DMA Halted
{}
or pc_err 03c ppc error status
<byte 5376>
ulong value As longword
endunion pc_err 03c ppc error status
<byte 5380>
{pc_io_data (040 ppc IO data (not configured; do not read))}
<byte 5380>
ulong value
{}
<byte 5384>
{pc_cfg_data (044 ppc configuration data)}
<byte 5384>
ulong value
{}
<byte 5388>
{pc_addr (048 ppc error address)}
<byte 5388>
ulong value
{}
<byte 5392>
{pc_rev (04c sprite3 hardware build revision)}
<byte 5392>
ulong value
{}
<byte 5396>
union pc_gen 050 sprite3 gpio control
<byte 5396>
{field (By field)}
<byte 5396>
lbits:1 gbic_amb0_l R/W GBIC Amber LED0 Lo
lbits:1 gbic_amb1_l R/W GBIC Amber LED1 Lo
lbits:1 gbic_amb2_l R/W GBIC Amber LED2 Lo
lbits:1 gbic_amb3_l R/W GBIC Amber LED3 Lo
lbits:1 gbic_amb4_l R/W GBIC Amber LED4 Lo
lbits:1 gbic_amb5_l R/W GBIC Amber LED5 Lo
lbits:1 gbic_amb6_l R/W GBIC Amber LED6 Lo
lbits:1 gbic_amb7_l R/W GBIC Amber LED7 Lo
lbits:1 gbic_amb8_l R/W GBIC Amber LED8 Lo
lbits:1 gbic_amb9_l R/W GBIC Amber LED9 Lo
lbits:1 sfp_dis_0 R/W SFP Laser 0 Disable (dis=1)
lbits:1 sfp_dis_1 R/W SFP Laser 1 Disable (dis=1)
lbits:1 sfp_dis_2 R/W SFP Laser 2 Disable (dis=1)
lbits:1 sfp_dis_3 R/W SFP Laser 3 Disable (dis=1)
lbits:1 sfp_dis_4 R/W SFP Laser 4 Disable (dis=1)
lbits:1 sfp_dis_5 R/W SFP Laser 5 Disable (dis=1)
lbits:1 sfp_dis_6 R/W SFP Laser 6 Disable (dis=1)
lbits:1 sfp_dis_7 R/W SFP Laser 7 Disable (dis=1)
lbits:1 sfp_dis_8 R/W SFP Laser 8 Disable (dis=1)
lbits:1 sfp_dis_9 R/W SFP Laser 9 Disable (dis=1)
lbits:6 rsvd1 R/W Reserved 3.3V LVTTL
lbits:6 rsvd R/W Reserved 2.5V CMOS
{}
or pc_gen 050 sprite3 gpio control
<byte 5396>
ulong value As longword
endunion pc_gen 050 sprite3 gpio control
<byte 5400>
union pc_pll 054 sprite3 pll config
<byte 5400>
{field (By field)}
<byte 5400>
lbits:2 pll_phase_m_cnt R/W PLL phase shift for m counter
lbits:2 pll_phase_c0 R/W PLL phase shift for clock C0
lbits:2 pll_phase_c1 R/W PLL phase shift for clock C1
lbits:2 pll_phase_c2 R/W PLL phase shift for clock C2
lbits:2 pll_phase_c3 R/W PLL phase shift for clock C3
lbits:2 pll_phase_c4 R/W PLL phase shift for clock C4
lbits:2 pll_phase_c5 R/W PLL phase shift for clock C5
lbits:1 rsvd1 R/W Reserved
lbits:1 e_scan_done_ck R/W Enable scan done check
lbits:7 pll_delay_parms R/W PLL delay parameters
lbits:8 rsvd R/W Reserved
lbits:1 pll_recon_w_e R/W PLL reconfig write enable
{}
or pc_pll 054 sprite3 pll config
<byte 5400>
ulong value As longword
endunion pc_pll 054 sprite3 pll config
<byte 5404>
{rsvd2[0] (058 - 05c unused)}
<byte 5404>
ulong value
{}
<byte 5408>
{rsvd2[1] (058 - 05c unused)}
<byte 5408>
ulong value
{}
<byte 5412>
union p0_mem_0 060 pcix0 to DDR window 0 description
<byte 5412>
{field (By field)}
<byte 5412>
lbits:12 size R/W Window size, 32MB -> 32GB
lbits:20 base_addr R/W Sets bits 45:25 of base address
{}
or p0_mem_0 060 pcix0 to DDR window 0 description
<byte 5412>
ulong value As longword
endunion p0_mem_0 060 pcix0 to DDR window 0 description
<byte 5416>
union p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits
<byte 5416>
{field (By field)}
<byte 5416>
lbits:12 rsvd R Reserved
lbits:20 trans_sel R/W Selects Translation bits 45:25
{}
or p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits
<byte 5416>
ulong value As longword
endunion p0_sel_tra_0 064 pcix0 to DDR window 0 select address translation bits
<byte 5420>
union p0_tra_0 068 pcix0 to DDR window 0 address translation value
<byte 5420>
{field (By field)}
<byte 5420>
lbits:12 rsvd R Reserved
lbits:20 trans_val R/W Translation Value, bits 45:25
{}
or p0_tra_0 068 pcix0 to DDR window 0 address translation value
<byte 5420>
ulong value As longword
endunion p0_tra_0 068 pcix0 to DDR window 0 address translation value
<byte 5424>
union p0_mem_1 06c pcix0 to DDR window 1 description
<byte 5424>
{field (By field)}
<byte 5424>
lbits:12 size R/W Window size, 32MB -> 32GB
lbits:20 base_addr R/W Sets bits 45:25 of base address
{}
or p0_mem_1 06c pcix0 to DDR window 1 description
<byte 5424>
ulong value As longword
endunion p0_mem_1 06c pcix0 to DDR window 1 description
<byte 5428>
union p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits
<byte 5428>
{field (By field)}
<byte 5428>
lbits:12 rsvd R Reserved
lbits:20 trans_sel R/W Selects Translation bits 45:25
{}
or p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits
<byte 5428>
ulong value As longword
endunion p0_sel_tra_1 070 pcix0 to DDR window 1 select address translation bits
<byte 5432>
union p0_tra_1 074 pcix0 to DDR window 1 address translation value
<byte 5432>
{field (By field)}
<byte 5432>
lbits:12 rsvd R Reserved
lbits:20 trans_val R/W Translation Value, bits 45:25
{}
or p0_tra_1 074 pcix0 to DDR window 1 address translation value
<byte 5432>
ulong value As longword
endunion p0_tra_1 074 pcix0 to DDR window 1 address translation value
<byte 5436>
union p0_csr 078 pcix0 control and status
<byte 5436>
{field (By field)}
<byte 5436>
lbits:1 err_mabort R/W1C Sprite performed a Master Abort
lbits:1 err_tabort R/W1C Sprite received a Target Abort
lbits:1 err_sa_serr R/W1C Sprite asserted SERR
lbits:1 err_sd_serr R/W1C Sprite detected SERR
lbits:1 err_perr R/W1C PERR asserted
lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors:
lbits:1 err_uesc R/W1C UnExpected SC
lbits:1 err_scemr R/W1C SC Error Message or SC Received
lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Errors:
lbits:1 err_trce R/W1C Target Retry-Count Exceeded
lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded:
lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err
lbits:1 err_tlmm R/W1C Transaction Length MisMatch
lbits:1 err_scce R/W1C Split-Completion Count Exceeded
lbits:1 rsvd R Reserved
lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination
lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort
lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort
lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr
lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr
lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr
lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit
lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc
lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr
lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce
lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce
lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm
lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe
lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm
lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce
lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm
lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd
{}
or p0_csr 078 pcix0 control and status
<byte 5436>
ulong value As longword
endunion p0_csr 078 pcix0 control and status
<byte 5440>
union p0_ecr 07c pcix0 error counters
<byte 5440>
{field (By field)}
<byte 5440>
lbits:12 sc_delay R/W Split-Completion Delay
lbits:10 i_retries R/W Initiator Retry Count
lbits:10 t_retries R/W Target Retry Count (N/A Mirror)
{}
or p0_ecr 07c pcix0 error counters
<byte 5440>
ulong value As longword
endunion p0_ecr 07c pcix0 error counters
<byte 5444>
union p0_edr 080 pcix0 error disables
<byte 5444>
{field (By field)}
<byte 5444>
lbits:1 dis_mabort R/W Sprite performed a Master Abort
lbits:1 dis_tabort R/W Sprite received a Target Abort
lbits:1 dis_sa_serr R/W Sprite asserted SERR
lbits:1 dis_sd_serr R/W Sprite detected SERR
lbits:1 dis_perr R/W PERR asserted
lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors:
lbits:1 dis_uesc R/W UnExpected SC
lbits:1 dis_scemr R/W SC Error Message or SC Received
lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Errors:
lbits:1 dis_trce R/W Target Retry-Count Exceeded
lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded:
lbits:1 dis_terpe R/W Transaction Entry RD Parity Err
lbits:1 dis_tlmm R/W Transaction Length MisMatch
lbits:1 dis_scce R/W Split-Completion Count Exceeded
lbits:1 rsvd1 R Reserved
lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination
lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response
lbits:13 rsvd R Reserved DISABLE interrupts from:
lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1_csr)
lbits:1 ena_perr_serr R/W Enable PERR and SERR
{}
or p0_edr 080 pcix0 error disables
<byte 5444>
ulong value As longword
endunion p0_edr 080 pcix0 error disables
<byte 5448>
union p0_pcix_atr 084 pcix0 attributes
<byte 5448>
{field (By field)}
<byte 5448>
lbits:8 rsvd1 R Reserved
lbits:3 function R/W Transaction Function Number
lbits:5 device R/W Transaction Device Number
lbits:8 bus R/W Transaction Bus Number
lbits:5 tag R/W Transaction Tag Number
lbits:3 rsvd R Reserved
{}
or p0_pcix_atr 084 pcix0 attributes
<byte 5448>
ulong value As longword
endunion p0_pcix_atr 084 pcix0 attributes
<byte 5452>
union p0_csr2 088 pcix0 control and status continued
<byte 5452>
{field (By field previous Split-Response)}
<byte 5452>
lbits:1 err_scwopsr R/W1C Split-Completion without a
lbits:14 rsvd1 R Reserved
lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr)
lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr
lbits:14 rsvd R Reserved
lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_csr)
{}
or p0_csr2 088 pcix0 control and status continued
<byte 5452>
ulong value As longword
endunion p0_csr2 088 pcix0 control and status continued
<byte 5456>
{rsvd3[0] (08c - 09c unused)}
<byte 5456>
ulong value
{}
<byte 5460>
{rsvd3[1] (08c - 09c unused)}
<byte 5460>
ulong value
{}
<byte 5464>
{rsvd3[2] (08c - 09c unused)}
<byte 5464>
ulong value
{}
<byte 5468>
{rsvd3[3] (08c - 09c unused)}
<byte 5468>
ulong value
{}
<byte 5472>
{rsvd3[4] (08c - 09c unused)}
<byte 5472>
ulong value
{}
<byte 5476>
union p1_mem_0 0a0 pcix1 to DDR window 0 description
<byte 5476>
{field (By field)}
<byte 5476>
lbits:12 size R/W Window size, 32MB -> 32GB
lbits:20 base_addr R/W Sets bits 45:25 of base address
{}
or p1_mem_0 0a0 pcix1 to DDR window 0 description
<byte 5476>
ulong value As longword
endunion p1_mem_0 0a0 pcix1 to DDR window 0 description
<byte 5480>
union p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits
<byte 5480>
{field (By field)}
<byte 5480>
lbits:12 rsvd R Reserved
lbits:20 trans_sel R/W Selects Translation bits 45:25
{}
or p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits
<byte 5480>
ulong value As longword
endunion p1_sel_tra_0 0a4 pcix1 to DDR window 0 select address translation bits
<byte 5484>
union p1_tra_0 0a8 pcix1 to DDR window 0 address translation value
<byte 5484>
{field (By field)}
<byte 5484>
lbits:12 rsvd R Reserved
lbits:20 trans_val R/W Translation Value, bits 45:25
{}
or p1_tra_0 0a8 pcix1 to DDR window 0 address translation value
<byte 5484>
ulong value As longword
endunion p1_tra_0 0a8 pcix1 to DDR window 0 address translation value
<byte 5488>
union p1_mem_1 0ac pcix1 to DDR window 1 description
<byte 5488>
{field (By field)}
<byte 5488>
lbits:12 size R/W Window size, 32MB -> 32GB
lbits:20 base_addr R/W Sets bits 45:25 of base address
{}
or p1_mem_1 0ac pcix1 to DDR window 1 description
<byte 5488>
ulong value As longword
endunion p1_mem_1 0ac pcix1 to DDR window 1 description
<byte 5492>
union p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits
<byte 5492>
{field (By field)}
<byte 5492>
lbits:12 rsvd R Reserved
lbits:20 trans_sel R/W Selects Translation bits 45:25
{}
or p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits
<byte 5492>
ulong value As longword
endunion p1_sel_tra_1 0b0 pcix1 to DDR window 1 select address translation bits
<byte 5496>
union p1_tra_1 0b4 pcix1 to DDR window 1 address translation value
<byte 5496>
{field (By field)}
<byte 5496>
lbits:12 rsvd R Reserved
lbits:20 trans_val R/W Translation Value, bits 45:25
{}
or p1_tra_1 0b4 pcix1 to DDR window 1 address translation value
<byte 5496>
ulong value As longword
endunion p1_tra_1 0b4 pcix1 to DDR window 1 address translation value
<byte 5500>
union p1_csr 0b8 pcix1 control and status
<byte 5500>
{field (By field)}
<byte 5500>
lbits:1 err_mabort R/W1C Sprite performed a Master Abort
lbits:1 err_tabort R/W1C Sprite received a Target Abort
lbits:1 err_sa_serr R/W1C Sprite asserted SERR
lbits:1 err_sd_serr R/W1C Sprite detected SERR
lbits:1 err_perr R/W1C PERR asserted
lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors:
lbits:1 err_uesc R/W1C UnExpected SC
lbits:1 err_scemr R/W1C SC Error Message or SC Received
lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Errors:
lbits:1 err_trce R/W1C Target Retry-Count Exceeded
lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded:
lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err
lbits:1 err_tlmm R/W1C Transaction Length MisMatch
lbits:1 err_scce R/W1C Split-Completion Count Exceeded
lbits:1 rsvd R Reserved
lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination
lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort
lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort
lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr
lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr
lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr
lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit
lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc
lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr
lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce
lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce
lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm
lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe
lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm
lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce
lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm
lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd
{}
or p1_csr 0b8 pcix1 control and status
<byte 5500>
ulong value As longword
endunion p1_csr 0b8 pcix1 control and status
<byte 5504>
union p1_ecr 0bc pcix1 error counters
<byte 5504>
{field (By field)}
<byte 5504>
lbits:12 sc_delay R/W Split-Completion Delay
lbits:10 i_retries R/W Initiator Retry Count
lbits:10 t_retries R/W Target Retry Count (N/A Mirror)
{}
or p1_ecr 0bc pcix1 error counters
<byte 5504>
ulong value As longword
endunion p1_ecr 0bc pcix1 error counters
<byte 5508>
union p1_edr 0c0 pcix1 error disables
<byte 5508>
{field (By field)}
<byte 5508>
lbits:1 dis_mabort R/W Sprite performed a Master Abort
lbits:1 dis_tabort R/W Sprite received a Target Abort
lbits:1 dis_sa_serr R/W Sprite asserted SERR
lbits:1 dis_sd_serr R/W Sprite detected SERR
lbits:1 dis_perr R/W PERR asserted
lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors:
lbits:1 dis_uesc R/W UnExpected SC
lbits:1 dis_scemr R/W SC Error Message or SC Received
lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Errors:
lbits:1 dis_trce R/W Target Retry-Count Exceeded
lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded:
lbits:1 dis_terpe R/W Transaction Entry RD Parity Err
lbits:1 dis_tlmm R/W Transaction Length MisMatch
lbits:1 dis_scce R/W Split-Completion Count Exceeded
lbits:1 rsvd1 R Reserved
lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination
lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response
lbits:13 rsvd R Reserved DISABLE interrupts from:
lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1_csr)
lbits:1 ena_perr_serr R/W Enable PERR and SERR
{}
or p1_edr 0c0 pcix1 error disables
<byte 5508>
ulong value As longword
endunion p1_edr 0c0 pcix1 error disables
<byte 5512>
union p1_pcix_atr 0c4 pcix1 attributes
<byte 5512>
{field (By field)}
<byte 5512>
lbits:8 rsvd1 R Reserved
lbits:3 function R/W Transaction Function Number
lbits:5 device R/W Transaction Device Number
lbits:8 bus R/W Transaction Bus Number
lbits:5 tag R/W Transaction Tag Number
lbits:3 rsvd R Reserved
{}
or p1_pcix_atr 0c4 pcix1 attributes
<byte 5512>
ulong value As longword
endunion p1_pcix_atr 0c4 pcix1 attributes
<byte 5516>
union p1_csr2 0c8 pcix1 control and status continued
<byte 5516>
{field (By field previous Split-Response)}
<byte 5516>
lbits:1 err_scwopsr R/W1C Split-Completion without a
lbits:14 rsvd1 R Reserved
lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr)
lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr
lbits:14 rsvd R Reserved
lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_csr)
{}
or p1_csr2 0c8 pcix1 control and status continued
<byte 5516>
ulong value As longword
endunion p1_csr2 0c8 pcix1 control and status continued
<byte 5520>
{rsvd4[0] (0cc - 0dc unused)}
<byte 5520>
ulong value
{}
<byte 5524>
{rsvd4[1] (0cc - 0dc unused)}
<byte 5524>
ulong value
{}
<byte 5528>
{rsvd4[2] (0cc - 0dc unused)}
<byte 5528>
ulong value
{}
<byte 5532>
{rsvd4[3] (0cc - 0dc unused)}
<byte 5532>
ulong value
{}
<byte 5536>
{rsvd4[4] (0cc - 0dc unused)}
<byte 5536>
ulong value
{}
<byte 5540>
union q_mir 0e0 mirror window description
<byte 5540>
{field (By field)}
<byte 5540>
lbits:12 size R/W Window size, 32MB -> 32GB
lbits:9 rsvd R Reserved
lbits:11 base_addr R/W Sets bits 35:25 of base address
{}
or q_mir 0e0 mirror window description
<byte 5540>
ulong value As longword
endunion q_mir 0e0 mirror window description
<byte 5544>
union q_wsb 0e4 write sensitive base
<byte 5544>
{field (By field)}
<byte 5544>
lbits:1 ena_perf_int R/W Enable Performance Interrupt
lbits:31 base_addr R/W Sets bits 35:5 of base address
{}
or q_wsb 0e4 write sensitive base
<byte 5544>
ulong value As longword
endunion q_wsb 0e4 write sensitive base
<byte 5548>
union q_pint 0e8 performance interrupt
<byte 5548>
{field (By field)}
<byte 5548>
lbits:1 wsa000 R/W1C Write Sensitive Area 0x000
lbits:1 wsa020 R/W1C Write Sensitive Area 0x020
lbits:1 wsa040 R/W1C Write Sensitive Area 0x040
lbits:1 wsa060 R/W1C Write Sensitive Area 0x060
lbits:1 wsa080 R/W1C Write Sensitive Area 0x080
lbits:1 wsa0A0 R/W1C Write Sensitive Area 0x0A0
lbits:1 wsa0C0 R/W1C Write Sensitive Area 0x0C0
lbits:1 wsa0E0 R/W1C Write Sensitive Area 0x0E0
lbits:1 wsa100 R/W1C Write Sensitive Area 0x100
lbits:1 wsa120 R/W1C Write Sensitive Area 0x120
lbits:1 wsa140 R/W1C Write Sensitive Area 0x140
lbits:1 wsa160 R/W1C Write Sensitive Area 0x160
lbits:1 wsa180 R/W1C Write Sensitive Area 0x180
lbits:1 wsa1A0 R/W1C Write Sensitive Area 0x1A0
lbits:1 wsa1C0 R/W1C Write Sensitive Area 0x1C0
lbits:1 wsa1E0 R/W1C Write Sensitive Area 0x1E0
lbits:1 wsa200 R/W1C Write Sensitive Area 0x200
lbits:1 wsa220 R/W1C Write Sensitive Area 0x220
lbits:1 wsa240 R/W1C Write Sensitive Area 0x240
lbits:1 wsa260 R/W1C Write Sensitive Area 0x260
lbits:1 wsa280 R/W1C Write Sensitive Area 0x280
lbits:1 wsa2A0 R/W1C Write Sensitive Area 0x2A0
lbits:1 wsa2C0 R/W1C Write Sensitive Area 0x2C0
lbits:1 wsa2E0 R/W1C Write Sensitive Area 0x2E0
lbits:1 wsa300 R/W1C Write Sensitive Area 0x300
lbits:1 wsa320 R/W1C Write Sensitive Area 0x320
lbits:1 wsa340 R/W1C Write Sensitive Area 0x340
lbits:1 wrt_mir_dls R/W1C Write to Mirror Data has Left Sprite register
lbits:1 dma_cmp_err R/W1C XOR-DMA Compare Error
lbits:1 dma_complete R/W1C XOR-DMA Operation Completed
lbits:1 int1 R/W1C INT_IN_1_L is asserted
lbits:1 int0 R/W1C INT_IN_0_L is asserted
{}
or q_pint 0e8 performance interrupt
<byte 5548>
ulong value As longword
endunion q_pint 0e8 performance interrupt
<byte 5552>
union q_csr 0ec queue control and status
<byte 5552>
{field (By field)}
<byte 5552>
lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK
lbits:1 err_qdid R/W1C Queue Detected an Invalid Destination
lbits:6 rsvd2 R Reserved
lbits:1 ena_mir_bad R/W Enable mir_bad to error & halt
lbits:1 ena_qdid R/W Enable qdid to error & halt
lbits:6 rsvd1 R Reserved
lbits:1 sel_mir_bad R/W Select P_INT(0/1)_L for mir_bad
lbits:1 sel_qdid R/W Select P_INT(0/1)_L for qdid
lbits:12 rsvd R Reserved
lbits:1 gp2ppc_rd R/W Give priority to PowerPC Read transactions
lbits:1 max_xfer_len R/W Max. Xfer Length 0=1K, 1=2K
{}
or q_csr 0ec queue control and status
<byte 5552>
ulong value As longword
endunion q_csr 0ec queue control and status
<byte 5556>
union q_egen 0f0 error generation
<byte 5556>
{field (By field)}
<byte 5556>
lbits:3 pdf R/W Port Detector Field
lbits:1 qrice R/W Queue Received an Invalid Command Entry
lbits:1 tmpdb R/W Transaction Missing Proper Destination Bit
lbits:1 twalanob R/W Transaction With a Low Actual Number of Bytes
lbits:1 peifte R/W Parity Error in First Transaction Entry
lbits:1 twnleb R/W Transaction With No Last-Entry Bit
lbits:1 twnfeb R/W Transaction With No First-Entry Bit
lbits:23 rsvd R Reserved
{}
or q_egen 0f0 error generation
<byte 5556>
ulong value As longword
endunion q_egen 0f0 error generation
<byte 5560>
union q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3
<byte 5560>
{field (By field)}
<byte 5560>
lbits:2 ctrl1 R/W PCIX0 Arb Control
lbits:2 state1 R PCIX0 Arb State
lbits:2 ctrl0 R/W PCIX1 Arb Control
lbits:2 state0 R PCIX1 Arb State
lbits:16 rsvd2 R Reserved
lbits:1 pcix1_init_stop_l R/W PCIX1 Initialization value for Stop_l
lbits:1 pcix1_init_trdy_l R/W PCIX1 Initialization value for Trdy_l
lbits:1 rsvd1 R Reserved
lbits:1 pcix1_init_req64_l R/W PCIX1 Initialization value for Req64_l
lbits:1 pcix0_init_stop_l R/W PCIX0 Initialization value for Stop_l
lbits:1 pcix0_init_trdy_l R/W PCIX0 Initialization value for Trdy_l
lbits:1 rsvd R Reserved
lbits:1 pcix0_init_req64_l R/W PCIX0 Initialization value for Req64_l
{}
or q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3
<byte 5560>
ulong value As longword
endunion q_pcix 0f4 pci-x arbitration and bootstrapping - new for sprite3
<byte 5564>
{rsvd5[0] (0f8 - 0fc unused)}
<byte 5564>
ulong value
{}
<byte 5568>
{rsvd5[1] (0f8 - 0fc unused)}
<byte 5568>
ulong value
{}
<byte 5572>
union mir_csr 100 mirror control and status
<byte 5572>
{field (By field)}
<byte 5572>
lbits:1 err_mabort R/W1C Sprite performed a Master Abort
lbits:1 err_tabort R/W1C Sprite received a Target Abort
lbits:1 err_sa_serr R/W1C Sprite asserted SERR
lbits:1 err_sd_serr R/W1C Sprite detected SERR
lbits:1 err_perr R/W1C PERR asserted
lbits:1 err_scit R/W1C SC Invalid Termination PCIX Errors:
lbits:1 err_uesc R/W1C UnExpected SC
lbits:1 err_scemr R/W1C SC Error Message or SC Received
lbits:1 err_irce R/W1C Initiator Retry-Count Exceeded Split-Completion (SC) Errors:
lbits:1 err_trce R/W1C Target Retry-Count Exceeded
lbits:1 err_bcmm R/W1C Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded:
lbits:1 err_terpe R/W1C Transaction Entry RD Parity Err
lbits:1 err_tlmm R/W1C Transaction Length MisMatch
lbits:1 err_scce R/W1C Split-Completion Count Exceeded
lbits:1 rsvd R Reserved
lbits:1 err_nbofisd R/W1C No Beginning-Of-Frame or Invalid Single Destination
lbits:1 sel_mabort R/W Select P_INT(0/1)_L for mabort
lbits:1 sel_tabort R/W Select P_INT(0/1)_L for tabort
lbits:1 sel_sa_serr R/W Select P_INT(0/1)_L for sa_serr
lbits:1 sel_sd_serr R/W Select P_INT(0/1)_L for sd_serr
lbits:1 sel_perr R/W Select P_INT(0/1)_L for perr
lbits:1 sel_scit R/W Select P_INT(0/1)_L for scit
lbits:1 sel_uesc R/W Select P_INT(0/1)_L for uesc
lbits:1 sel_scemr R/W Select P_INT(0/1)_L for scemr
lbits:1 sel_irce R/W Select P_INT(0/1)_L for irce
lbits:1 sel_trce R/W Select P_INT(0/1)_L for trce
lbits:1 sel_bcmm R/W Select P_INT(0/1)_L for bcmm
lbits:1 sel_terpe R/W Select P_INT(0/1)_L for terpe
lbits:1 sel_tlmm R/W Select P_INT(0/1)_L for tlmm
lbits:1 sel_scce R/W Select P_INT(0/1)_L for scce
lbits:1 sel_bt32bm R/W Select P_INT(0/1)_L for bt32bm
lbits:1 sel_nbofisd R/W Select P_INT(0/1)_L for nbofisd
{}
or mir_csr 100 mirror control and status
<byte 5572>
ulong value As longword
endunion mir_csr 100 mirror control and status
<byte 5576>
union mir_ecr 104 mirror error counters
<byte 5576>
{field (By field)}
<byte 5576>
lbits:12 sc_delay R/W Split-Completion Delay
lbits:10 i_retries R/W Initiator Retry Count
lbits:10 t_retries R/W Target Retry Count (N/A Mirror)
{}
or mir_ecr 104 mirror error counters
<byte 5576>
ulong value As longword
endunion mir_ecr 104 mirror error counters
<byte 5580>
union mir_edr 108 mirror error disables
<byte 5580>
{field (By field)}
<byte 5580>
lbits:1 dis_mabort R/W Sprite performed a Master Abort
lbits:1 dis_tabort R/W Sprite received a Target Abort
lbits:1 dis_sa_serr R/W Sprite asserted SERR
lbits:1 dis_sd_serr R/W Sprite detected SERR
lbits:1 dis_perr R/W PERR asserted
lbits:1 dis_scit R/W SC Invalid Termination PCIX Errors:
lbits:1 dis_uesc R/W UnExpected SC
lbits:1 dis_scemr R/W SC Error Message or SC Received
lbits:1 dis_irce R/W Initiator Retry-Count Exceeded Split-Completion (SC) Errors:
lbits:1 dis_trce R/W Target Retry-Count Exceeded
lbits:1 dis_bcmm R/W Bite-Count (BC) MisMatch (Transaction BC != BC in FIFO) Sprite Retry-Counts Exceeded:
lbits:1 dis_terpe R/W Transaction Entry RD Parity Err
lbits:1 dis_tlmm R/W Transaction Length MisMatch
lbits:1 dis_scce R/W Split-Completion Count Exceeded
lbits:1 rsvd1 R Reserved
lbits:1 dis_nbofisd R/W No Beginning-Of-Frame or Invalid Single Destination
lbits:1 dis_scwopsr R/W Split-Completion without a previous Split-Response
lbits:13 rsvd R Reserved DISABLE interrupts from:
lbits:1 ignore_mir_bad R/W Sprite ignores err_mir_bad bit (rsvd in p0_csr & p1_csr)
lbits:1 ena_perr_serr R/W Enable PERR and SERR
{}
or mir_edr 108 mirror error disables
<byte 5580>
ulong value As longword
endunion mir_edr 108 mirror error disables
<byte 5584>
union mir_pcix_atr 10c mirror pcix attributes
<byte 5584>
{field (By field)}
<byte 5584>
lbits:8 rsvd1 R Reserved
lbits:3 function R/W Transaction Function Number
lbits:5 device R/W Transaction Device Number
lbits:8 bus R/W Transaction Bus Number
lbits:5 tag R/W Transaction Tag Number
lbits:3 rsvd R Reserved
{}
or mir_pcix_atr 10c mirror pcix attributes
<byte 5584>
ulong value As longword
endunion mir_pcix_atr 10c mirror pcix attributes
<byte 5588>
union mir_dls 110 mirror data has left sprite counter
<byte 5588>
{field (By field)}
<byte 5588>
lbits:16 count R/WTI Count of writes to this reg.
lbits:16 rsvd R Reserved
{}
or mir_dls 110 mirror data has left sprite counter
<byte 5588>
ulong value As longword
endunion mir_dls 110 mirror data has left sprite counter
<byte 5592>
union mir_csr2 114 mirror control and status continued
<byte 5592>
{field (By field previous Split-Response)}
<byte 5592>
lbits:1 err_scwopsr R/W1C Split-Completion without a
lbits:14 rsvd1 R Reserved
lbits:1 err_mir_bad R/W1C Mirror Not Present or Not OK (rsvd in p0_csr & p1_csr)
lbits:1 sel_scwopsr R/W Select P_INT(0/1)_L for scnosr
lbits:14 rsvd R Reserved
lbits:1 sel_mir_bad R/W Sprite P_INT(0/1)_L for scnosr (rsvd in p0_csr & p1_csr)
{}
or mir_csr2 114 mirror control and status continued
<byte 5592>
ulong value As longword
endunion mir_csr2 114 mirror control and status continued
<byte 5596>
{rsvd6[0] (118 - 11c unused)}
<byte 5596>
ulong value
{}
<byte 5600>
{rsvd6[1] (118 - 11c unused)}
<byte 5600>
ulong value
{}
<byte 5604>
union x_cb 120 xor-dma command block base address
<byte 5604>
{field (By field)}
<byte 5604>
lbits:19 base_addr R/W Base Address of XOR-DMA SCDBs
lbits:13 rsvd R Reserved
{}
or x_cb 120 xor-dma command block base address
<byte 5604>
ulong value As longword
endunion x_cb 120 xor-dma command block base address
<byte 5608>
union x_pi 124 xor-dma producer index
<byte 5608>
{field (By field)}
<byte 5608>
lbits:11 index R/W SCDB index
lbits:21 rsvd R Reserved
{}
or x_pi 124 xor-dma producer index
<byte 5608>
ulong value As longword
endunion x_pi 124 xor-dma producer index
<byte 5612>
union x_ci 128 xor-dma consumer index
<byte 5612>
{field (By field)}
<byte 5612>
lbits:11 index R/W SCDB index
lbits:21 rsvd R Reserved
{}
or x_ci 128 xor-dma consumer index
<byte 5612>
ulong value As longword
endunion x_ci 128 xor-dma consumer index
<byte 5616>
union x_cc 12c xor-dma current command
<byte 5616>
{field (By field)}
<byte 5616>
lbits:4 rsvd R Reserved
lbits:20 qword_cnt R Transfer Size in Qwords
lbits:7 opcode R DMA Operation
lbits:1 I R Interrupt on command completion
{}
or x_cc 12c xor-dma current command
<byte 5616>
ulong value As longword
endunion x_cc 12c xor-dma current command
<byte 5620>
union x_usa 130 xor-dma upper source address
<byte 5620>
{field (By field)}
<byte 5620>
lbits:8 x_sa3 R Upper Source Address for x_sa3
lbits:8 x_sa2 R Upper Source Address for x_sa2
lbits:8 x_sa1 R Upper Source Address for x_sa1
lbits:8 x_sa0 R Upper Source Address for x_sa0
{}
or x_usa 130 xor-dma upper source address
<byte 5620>
ulong value As longword
endunion x_usa 130 xor-dma upper source address
<byte 5624>
union x_sa[0] 134 - 140 xor-dma source addresses 0-3
<byte 5624>
{field (By field)}
<byte 5624>
lbits:4 mrwc R Mirror R/W Control
lbits:28 addr R Source Address, (Lower)
{}
or x_sa[0] 134 - 140 xor-dma source addresses 0-3
<byte 5624>
ulong value As longword
endunion x_sa[0] 134 - 140 xor-dma source addresses 0-3
<byte 5628>
union x_sa[1] 134 - 140 xor-dma source addresses 0-3
<byte 5628>
{field (By field)}
<byte 5628>
lbits:4 mrwc R Mirror R/W Control
lbits:28 addr R Source Address, (Lower)
{}
or x_sa[1] 134 - 140 xor-dma source addresses 0-3
<byte 5628>
ulong value As longword
endunion x_sa[1] 134 - 140 xor-dma source addresses 0-3
<byte 5632>
union x_sa[2] 134 - 140 xor-dma source addresses 0-3
<byte 5632>
{field (By field)}
<byte 5632>
lbits:4 mrwc R Mirror R/W Control
lbits:28 addr R Source Address, (Lower)
{}
or x_sa[2] 134 - 140 xor-dma source addresses 0-3
<byte 5632>
ulong value As longword
endunion x_sa[2] 134 - 140 xor-dma source addresses 0-3
<byte 5636>
union x_sa[3] 134 - 140 xor-dma source addresses 0-3
<byte 5636>
{field (By field)}
<byte 5636>
lbits:4 mrwc R Mirror R/W Control
lbits:28 addr R Source Address, (Lower)
{}
or x_sa[3] 134 - 140 xor-dma source addresses 0-3
<byte 5636>
ulong value As longword
endunion x_sa[3] 134 - 140 xor-dma source addresses 0-3
<byte 5640>
union x_da 144 xor-dma destination address
<byte 5640>
{field (By field)}
<byte 5640>
lbits:4 mrwc R Mirror R/W Control
lbits:28 addr R Source Address, (Lower)
{}
or x_da 144 xor-dma destination address
<byte 5640>
ulong value As longword
endunion x_da 144 xor-dma destination address
<byte 5644>
union x_uda 148 xor-dma upper destination address
<byte 5644>
{field (By field)}
<byte 5644>
lbits:24 rsvd R Reserved
lbits:8 x_da R Upper Destination Addr for x_da
{}
or x_uda 148 xor-dma upper destination address
<byte 5644>
ulong value As longword
endunion x_uda 148 xor-dma upper destination address
<byte 5648>
{x_spare (14c xor-dma spare)}
<byte 5648>
ulong value
{}
<byte 5652>
{x_tmo (150 xor-dma transfer time out)}
<byte 5652>
ulong value
{}
<byte 5656>
union x_csr 154 xor-dma control and status
<byte 5656>
{field (By field ** in q_pint and W1C in q_pint))}
<byte 5656>
lbits:1 cmp_err R Compare Error -- (duplicated
lbits:1 err_count R/W1C Error, Count
lbits:1 err_invop R/W1C Error, Invalid Opcode
lbits:1 err_parity R/W1C Error, Parity
lbits:1 err_efe R/W1C Error, End Frame Error
lbits:1 err_sfe R/W1C Error, Start Frame Error
lbits:1 err_toe R/W1C Error, TimeOut Error
lbits:2 rsvd2 R Reserved
lbits:1 sel_count R/W Select P_INT(0/1)_L for count
lbits:1 sel_invop R/W Select P_INT(0/1)_L for invop
lbits:1 sel_parity R/W Select P_INT(0/1)_L for parity
lbits:1 sel_efe R/W Select P_INT(0/1)_L for efe
lbits:1 sel_sfe R/W Select P_INT(0/1)_L for sfe
lbits:1 sel_toe R/W Select P_INT(0/1)_L for toe
lbits:2 rsvd1 R Reserved
lbits:1 ena_count R/W Enable Count Errors
lbits:1 ena_invop R/W Enable Invalid Opcode Errors
lbits:1 ena_parity R/W Enable Parity Errors
lbits:1 ena_efe R/W Enable End Frame Errors
lbits:1 ena_sfe R/W Enable Start Frame Errors
lbits:9 rsvd R Reserved
lbits:1 ena_dma R/W Enables XOR-DMA operations
{}
or x_csr 154 xor-dma control and status
<byte 5656>
ulong value As longword
endunion x_csr 154 xor-dma control and status
<byte 5660>
{rsvd7[0] (158 - 15c unused)}
<byte 5660>
ulong value
{}
<byte 5664>
{rsvd7[1] (158 - 15c unused)}
<byte 5664>
ulong value
{}
<byte 5668>
union m_tr 160 memory timing
<byte 5668>
{field (By field)}
<byte 5668>
lbits:1 Twtr R/W Timing, WR to RD cmd delay
lbits:3 Trc R/W Timing, Activate to active cmd (same bnk) or Autoref to " "
lbits:2 Trcd R/W Timing, Activate to RD or WR
lbits:3 Tras R/W Timing, Activate to Precharge
lbits:2 Trp R/W Timing, Precharge to Activate
lbits:3 Trfc R/W Timing, Autoref cmd to Autoref or Activate cmd
lbits:1 sdram_avail R Memory Unavailable When Cleared
lbits:1 ecc_disable R/W Disable ECC Correction
lbits:1 self_ref R/W Refresh Mode: 1=DIMMs,0=Sprite
lbits:1 rsvd1 R/W Reserved (R/W from prev. use)
lbits:14 rsvd R Reserved
{}
or m_tr 160 memory timing
<byte 5668>
ulong value As longword
endunion m_tr 160 memory timing
<byte 5672>
union m_cfg 164 memory configuration
<byte 5672>
{field (By field)}
<byte 5672>
lbits:9 refrate R/W Refresh Rate Count
lbits:1 refcnten R/W Enable Refresh Rate Counter
lbits:1 init_rfsh R/W Issue Auto Refresh Commands
lbits:1 rsvd1 R/W Reserved (R/W from prev. use)
lbits:12 rfcntr R/W Refresh Cycles with init_rfsh
lbits:1 ss_dimms R/W Single Sided DIMMs Installed
lbits:1 scrub_en R/W Enable HW Scrubbing
lbits:6 rsvd R Reserved
{}
or m_cfg 164 memory configuration
<byte 5672>
ulong value As longword
endunion m_cfg 164 memory configuration
<byte 5676>
union m_mrs 168 mode register set
<byte 5676>
{field (By field)}
<byte 5676>
lbits:3 burst_length R Burst Length
lbits:1 burst_type R Burst Type
lbits:3 cas_latency R/W CAS Latency
lbits:5 op_mode R/W Operating Mode
lbits:20 rsvd R Reserved
{}
or m_mrs 168 mode register set
<byte 5676>
ulong value As longword
endunion m_mrs 168 mode register set
<byte 5680>
union m_emrs 16c extended mode register set
<byte 5680>
{field (By field)}
<byte 5680>
lbits:1 sdram_dll_dis R/W Disable DLL in DDR SDRAMs
lbits:1 ds R/W Drive Strength(1=Weak,0=Normal)
lbits:1 qfc R/W QFC FET Isolation Control
lbits:9 xemrs R/W Rsvd emrs JEDEC bits, set 0
lbits:20 rsvd R Reserved
{}
or m_emrs 16c extended mode register set
<byte 5680>
ulong value As longword
endunion m_emrs 16c extended mode register set
<byte 5684>
union m_siz 170 DDR SRAM Size
<byte 5684>
{field (By field)}
<byte 5684>
lbits:3 ddr_size R/W DDR Memory Size Code
lbits:2 installed_dimms R/W Number of DIMMs Installed
lbits:1 scrub_test R/W Test bit for HW Scrub Circuit
lbits:2 la_socket R/W Socket Number of L.A. (0->3)
lbits:1 lap R/W Logic Analyzer Probe Installed
lbits:23 rsvd R Reserved
{}
or m_siz 170 DDR SRAM Size
<byte 5684>
ulong value As longword
endunion m_siz 170 DDR SRAM Size
<byte 5688>
union m_ese 174 ECC error status even
<byte 5688>
{field (By field)}
<byte 5688>
lbits:1 ude R/WCA Test bit for HW Scrub Circuit
lbits:1 cde R/WCA Socket Number of L.A. (0->3)
lbits:22 rsvd R Reserved
lbits:8 syndrome R/WCA Syndrome when cde or ude == 1
{}
or m_ese 174 ECC error status even
<byte 5688>
ulong value As longword
endunion m_ese 174 ECC error status even
<byte 5692>
union m_eso 178 ECC error status odd
<byte 5692>
{field (By field)}
<byte 5692>
lbits:1 ude R/WCA Test bit for HW Scrub Circuit
lbits:1 cde R/WCA Socket Number of L.A. (0->3)
lbits:22 rsvd R Reserved
lbits:8 syndrome R/WCA Syndrome when cde or ude == 1
{}
or m_eso 178 ECC error status odd
<byte 5692>
ulong value As longword
endunion m_eso 178 ECC error status odd
<byte 5696>
union m_eae 17c ECC address error even
<byte 5696>
{field (By field)}
<byte 5696>
lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4
{}
or m_eae 17c ECC address error even
<byte 5696>
ulong value As longword
endunion m_eae 17c ECC address error even
<byte 5700>
union m_eao 180 ECC address error odd
<byte 5700>
{field (By field)}
<byte 5700>
lbits:32 ecc_aoe_35_4 R ECC Address of Error, bits 35:4
{}
or m_eao 180 ECC address error odd
<byte 5700>
ulong value As longword
endunion m_eao 180 ECC address error odd
<byte 5704>
union m_esc 184 ECC syndrome preset, correctable error counter
<byte 5704>
{field (By field)}
<byte 5704>
lbits:16 cec R/W Correctable Error Counter
lbits:8 odd_egs R/W Odd Error Generating Syndrome
lbits:8 even_egs R/W Even Error Generating Syndrome
{}
or m_esc 184 ECC syndrome preset, correctable error counter
<byte 5704>
ulong value As longword
endunion m_esc 184 ECC syndrome preset, correctable error counter
<byte 5708>
union m_es 188 DDR error status
<byte 5708>
{field (By field Halts chip - h)}
<byte 5708>
lbits:1 err_ncb R/W1C New Command Bad h
lbits:1 err_cdpe R/W1C Cmd/Data Parity Error h
lbits:1 err_ude R/CLL Uncorrectable Data Error h
lbits:1 err_bwde R/W1C Bad Write Data Error h
lbits:1 err_cde R/CLL Correctable Data Error
lbits:3 rsvd2 R Reserved
lbits:1 sel_ncb R/W Select P_INT(0/1)_L for ncb's
lbits:1 sel_cdpe R/W Select P_INT(0/1)_L for cdpe's
lbits:1 sel_ude R/W Select P_INT(0/1)_L for ude's
lbits:1 sel_bwde R/W Select P_INT(0/1)_L for bwde's
lbits:1 sel_cde R/W Select P_INT(0/1)_L for cde's
lbits:3 rsvd1 R Reserved
lbits:1 dis_ncb R/W Disable New Command Bad
lbits:1 dis_cdpe R/W Disable Cmd/Data Parity Error
lbits:1 dis_ude R/W Disable Uncorrectable Data Err
lbits:1 dis_bwde R/W Disable Bad Write Data Error
lbits:1 dis_cde R/W Disable Correctable Data Error
lbits:11 rsvd R Reserved
{}
or m_es 188 DDR error status
<byte 5708>
ulong value As longword
endunion m_es 188 DDR error status
<byte 5712>
union m_sta 18c scrub test address
<byte 5712>
{field (By field)}
<byte 5712>
lbits:32 start_addr_35_5 R/W Scrub Test Address, bits 35:5
{}
or m_sta 18c scrub test address
<byte 5712>
ulong value As longword
endunion m_sta 18c scrub test address
{}
<byte 5716>
do_not_display[624] union_pad Union Element Padding (DO NOT DISPLAY!)
endunion csr Sprite CSR Registers
{}
<byte 6340>
{quartcr[0] (SC28L194 Quad UART Control Registers a, b, c, d)}
<byte 6340>
union bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6340>
{field (By field)}
<byte 6340>
tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6340>
utiny value As byte
endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6341>
union iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6341>
{field (By field)}
<byte 6341>
tbits:2 io0_control Bits 1:0 I/O0 control
tbits:2 io1_control Bits 3:2 I/O1 control
tbits:2 io2_control Bits 5:4 I/O2 control
tbits:2 io3_control Bits 7:6 I/O3 control
{}
or iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6341>
utiny value As byte
endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6342>
union mr1 (Offset 0x01) R/W Mode Register 1
<byte 6342>
{field (By field)}
<byte 6342>
tbits:2 bits_per_character Bit 1:0 Bits per Character
tbits:1 parity_type Bit 2 Parity Type
tbits:2 parity_mode Bit 4:3 Parity Mode
tbits:1 error_mode Bit 5 Error Mode
tbits:1 isr_read_mode Bit 6 ISR Read Mode
tbits:1 rx_rts_control Bit 7 Receiver RTS Control
{}
or mr1 (Offset 0x01) R/W Mode Register 1
<byte 6342>
utiny value As byte
endunion mr1 (Offset 0x01) R/W Mode Register 1
<byte 6343>
union mr0 (Offset 0x00) R/W Mode Register 0
<byte 6343>
{field (By field)}
<byte 6343>
tbits:2 ar_control Bit 1:0 Address Recognition control
tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode
tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition
tbits:1 ar_transparency Bit 6 Address Recognition transparency
tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency
{}
or mr0 (Offset 0x00) R/W Mode Register 0
<byte 6343>
utiny value As byte
endunion mr0 (Offset 0x00) R/W Mode Register 0
<byte 6344>
union bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6344>
{field (By field)}
<byte 6344>
tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6344>
utiny value As byte
endunion bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6345>
union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6345>
{field (By field)}
<byte 6345>
tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6345>
utiny value As byte
endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6346>
{rsvd1 ((Offset 0x05) NA Reserved)}
<byte 6346>
utiny value
{}
<byte 6347>
union bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6347>
{field (By field)}
<byte 6347>
tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6347>
utiny value As byte
endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6348>
union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6348>
{field (By field)}
<byte 6348>
tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold
tbits:1 reserved Bit 7 Reserved. Set to 0
{}
or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6348>
utiny value As byte
endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6349>
union arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6349>
{field (By field)}
<byte 6349>
tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition
{}
or arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6349>
utiny value As byte
endunion arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6350>
union xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6350>
{field (By field)}
<byte 6350>
tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition
{}
or xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6350>
utiny value As byte
endunion xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6351>
union xoncr (Offset 0x08) R/W Xon Character Register
<byte 6351>
{field (By field)}
<byte 6351>
tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition
{}
or xoncr (Offset 0x08) R/W Xon Character Register
<byte 6351>
utiny value As byte
endunion xoncr (Offset 0x08) R/W Xon Character Register
<byte 6352>
union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6352>
union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6352>
{field (By field)}
<byte 6352>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6352>
utiny value As byte
endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6352>
union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6352>
{field (By field)}
<byte 6352>
tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector
{}
or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6352>
utiny value As byte
endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6352>
utiny value As byte
endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6353>
union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6353>
{field (By field)}
<byte 6353>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6353>
utiny value As byte
endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6354>
union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6354>
{testreg ((Offset 0x0D) R/W Test Register (UARTA only))}
<byte 6354>
utiny value
{}
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6354>
union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6354>
{field (By field)}
<byte 6354>
tbits:1 wdt_a Bit 0 WDT a
tbits:1 wdt_b Bit 1 WDT b
tbits:1 wdt_c Bit 2 WDT c
tbits:1 wdt_d Bit 3 WDT d
tbits:4 reserved Bits 7:4 Reserved
{}
or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6354>
utiny value As byte
endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6354>
utiny value As byte
endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6355>
union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6355>
{field (By field)}
<byte 6355>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6355>
utiny value As byte
endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
{}
<byte 6356>
{quartcr[1] (SC28L194 Quad UART Control Registers a, b, c, d)}
<byte 6356>
union bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6356>
{field (By field)}
<byte 6356>
tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6356>
utiny value As byte
endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6357>
union iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6357>
{field (By field)}
<byte 6357>
tbits:2 io0_control Bits 1:0 I/O0 control
tbits:2 io1_control Bits 3:2 I/O1 control
tbits:2 io2_control Bits 5:4 I/O2 control
tbits:2 io3_control Bits 7:6 I/O3 control
{}
or iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6357>
utiny value As byte
endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6358>
union mr1 (Offset 0x01) R/W Mode Register 1
<byte 6358>
{field (By field)}
<byte 6358>
tbits:2 bits_per_character Bit 1:0 Bits per Character
tbits:1 parity_type Bit 2 Parity Type
tbits:2 parity_mode Bit 4:3 Parity Mode
tbits:1 error_mode Bit 5 Error Mode
tbits:1 isr_read_mode Bit 6 ISR Read Mode
tbits:1 rx_rts_control Bit 7 Receiver RTS Control
{}
or mr1 (Offset 0x01) R/W Mode Register 1
<byte 6358>
utiny value As byte
endunion mr1 (Offset 0x01) R/W Mode Register 1
<byte 6359>
union mr0 (Offset 0x00) R/W Mode Register 0
<byte 6359>
{field (By field)}
<byte 6359>
tbits:2 ar_control Bit 1:0 Address Recognition control
tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode
tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition
tbits:1 ar_transparency Bit 6 Address Recognition transparency
tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency
{}
or mr0 (Offset 0x00) R/W Mode Register 0
<byte 6359>
utiny value As byte
endunion mr0 (Offset 0x00) R/W Mode Register 0
<byte 6360>
union bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6360>
{field (By field)}
<byte 6360>
tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6360>
utiny value As byte
endunion bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6361>
union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6361>
{field (By field)}
<byte 6361>
tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6361>
utiny value As byte
endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6362>
{rsvd1 ((Offset 0x05) NA Reserved)}
<byte 6362>
utiny value
{}
<byte 6363>
union bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6363>
{field (By field)}
<byte 6363>
tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6363>
utiny value As byte
endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6364>
union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6364>
{field (By field)}
<byte 6364>
tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold
tbits:1 reserved Bit 7 Reserved. Set to 0
{}
or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6364>
utiny value As byte
endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6365>
union arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6365>
{field (By field)}
<byte 6365>
tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition
{}
or arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6365>
utiny value As byte
endunion arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6366>
union xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6366>
{field (By field)}
<byte 6366>
tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition
{}
or xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6366>
utiny value As byte
endunion xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6367>
union xoncr (Offset 0x08) R/W Xon Character Register
<byte 6367>
{field (By field)}
<byte 6367>
tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition
{}
or xoncr (Offset 0x08) R/W Xon Character Register
<byte 6367>
utiny value As byte
endunion xoncr (Offset 0x08) R/W Xon Character Register
<byte 6368>
union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6368>
union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6368>
{field (By field)}
<byte 6368>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6368>
utiny value As byte
endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6368>
union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6368>
{field (By field)}
<byte 6368>
tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector
{}
or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6368>
utiny value As byte
endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6368>
utiny value As byte
endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6369>
union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6369>
{field (By field)}
<byte 6369>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6369>
utiny value As byte
endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6370>
union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6370>
{testreg ((Offset 0x0D) R/W Test Register (UARTA only))}
<byte 6370>
utiny value
{}
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6370>
union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6370>
{field (By field)}
<byte 6370>
tbits:1 wdt_a Bit 0 WDT a
tbits:1 wdt_b Bit 1 WDT b
tbits:1 wdt_c Bit 2 WDT c
tbits:1 wdt_d Bit 3 WDT d
tbits:4 reserved Bits 7:4 Reserved
{}
or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6370>
utiny value As byte
endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6370>
utiny value As byte
endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6371>
union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6371>
{field (By field)}
<byte 6371>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6371>
utiny value As byte
endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
{}
<byte 6372>
{quartcr[2] (SC28L194 Quad UART Control Registers a, b, c, d)}
<byte 6372>
union bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6372>
{field (By field)}
<byte 6372>
tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6372>
utiny value As byte
endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6373>
union iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6373>
{field (By field)}
<byte 6373>
tbits:2 io0_control Bits 1:0 I/O0 control
tbits:2 io1_control Bits 3:2 I/O1 control
tbits:2 io2_control Bits 5:4 I/O2 control
tbits:2 io3_control Bits 7:6 I/O3 control
{}
or iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6373>
utiny value As byte
endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6374>
union mr1 (Offset 0x01) R/W Mode Register 1
<byte 6374>
{field (By field)}
<byte 6374>
tbits:2 bits_per_character Bit 1:0 Bits per Character
tbits:1 parity_type Bit 2 Parity Type
tbits:2 parity_mode Bit 4:3 Parity Mode
tbits:1 error_mode Bit 5 Error Mode
tbits:1 isr_read_mode Bit 6 ISR Read Mode
tbits:1 rx_rts_control Bit 7 Receiver RTS Control
{}
or mr1 (Offset 0x01) R/W Mode Register 1
<byte 6374>
utiny value As byte
endunion mr1 (Offset 0x01) R/W Mode Register 1
<byte 6375>
union mr0 (Offset 0x00) R/W Mode Register 0
<byte 6375>
{field (By field)}
<byte 6375>
tbits:2 ar_control Bit 1:0 Address Recognition control
tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode
tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition
tbits:1 ar_transparency Bit 6 Address Recognition transparency
tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency
{}
or mr0 (Offset 0x00) R/W Mode Register 0
<byte 6375>
utiny value As byte
endunion mr0 (Offset 0x00) R/W Mode Register 0
<byte 6376>
union bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6376>
{field (By field)}
<byte 6376>
tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6376>
utiny value As byte
endunion bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6377>
union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6377>
{field (By field)}
<byte 6377>
tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6377>
utiny value As byte
endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6378>
{rsvd1 ((Offset 0x05) NA Reserved)}
<byte 6378>
utiny value
{}
<byte 6379>
union bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6379>
{field (By field)}
<byte 6379>
tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6379>
utiny value As byte
endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6380>
union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6380>
{field (By field)}
<byte 6380>
tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold
tbits:1 reserved Bit 7 Reserved. Set to 0
{}
or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6380>
utiny value As byte
endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6381>
union arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6381>
{field (By field)}
<byte 6381>
tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition
{}
or arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6381>
utiny value As byte
endunion arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6382>
union xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6382>
{field (By field)}
<byte 6382>
tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition
{}
or xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6382>
utiny value As byte
endunion xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6383>
union xoncr (Offset 0x08) R/W Xon Character Register
<byte 6383>
{field (By field)}
<byte 6383>
tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition
{}
or xoncr (Offset 0x08) R/W Xon Character Register
<byte 6383>
utiny value As byte
endunion xoncr (Offset 0x08) R/W Xon Character Register
<byte 6384>
union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6384>
union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6384>
{field (By field)}
<byte 6384>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6384>
utiny value As byte
endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6384>
union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6384>
{field (By field)}
<byte 6384>
tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector
{}
or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6384>
utiny value As byte
endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6384>
utiny value As byte
endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6385>
union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6385>
{field (By field)}
<byte 6385>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6385>
utiny value As byte
endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6386>
union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6386>
{testreg ((Offset 0x0D) R/W Test Register (UARTA only))}
<byte 6386>
utiny value
{}
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6386>
union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6386>
{field (By field)}
<byte 6386>
tbits:1 wdt_a Bit 0 WDT a
tbits:1 wdt_b Bit 1 WDT b
tbits:1 wdt_c Bit 2 WDT c
tbits:1 wdt_d Bit 3 WDT d
tbits:4 reserved Bits 7:4 Reserved
{}
or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6386>
utiny value As byte
endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6386>
utiny value As byte
endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6387>
union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6387>
{field (By field)}
<byte 6387>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6387>
utiny value As byte
endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
{}
<byte 6388>
{quartcr[3] (SC28L194 Quad UART Control Registers a, b, c, d)}
<byte 6388>
union bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6388>
{field (By field)}
<byte 6388>
tbits:3 msb_break_change_int_bid Bits 2:0 MSB of break change interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6388>
utiny value As byte
endunion bcrbrk (Offset 0x03) R/W Bid Control, Break Change
<byte 6389>
union iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6389>
{field (By field)}
<byte 6389>
tbits:2 io0_control Bits 1:0 I/O0 control
tbits:2 io1_control Bits 3:2 I/O1 control
tbits:2 io2_control Bits 5:4 I/O2 control
tbits:2 io3_control Bits 7:6 I/O3 control
{}
or iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6389>
utiny value As byte
endunion iopcr (Offset 0x02) R/W I/O Port Configuration Register
<byte 6390>
union mr1 (Offset 0x01) R/W Mode Register 1
<byte 6390>
{field (By field)}
<byte 6390>
tbits:2 bits_per_character Bit 1:0 Bits per Character
tbits:1 parity_type Bit 2 Parity Type
tbits:2 parity_mode Bit 4:3 Parity Mode
tbits:1 error_mode Bit 5 Error Mode
tbits:1 isr_read_mode Bit 6 ISR Read Mode
tbits:1 rx_rts_control Bit 7 Receiver RTS Control
{}
or mr1 (Offset 0x01) R/W Mode Register 1
<byte 6390>
utiny value As byte
endunion mr1 (Offset 0x01) R/W Mode Register 1
<byte 6391>
union mr0 (Offset 0x00) R/W Mode Register 0
<byte 6391>
{field (By field)}
<byte 6391>
tbits:2 ar_control Bit 1:0 Address Recognition control
tbits:2 inband_flow_control_mode Bit 3:2 In-band flow control mode
tbits:2 txint Bit 5:4 Transmitter initiation of interrupt bidding condition
tbits:1 ar_transparency Bit 6 Address Recognition transparency
tbits:1 xon_xoff_transparency Bit 7 Xon/Xoff transparency
{}
or mr0 (Offset 0x00) R/W Mode Register 0
<byte 6391>
utiny value As byte
endunion mr0 (Offset 0x00) R/W Mode Register 0
<byte 6392>
union bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6392>
{field (By field)}
<byte 6392>
tbits:3 msb_ar_event_int_bid Bits 2:0 MSB of an address recognition event interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6392>
utiny value As byte
endunion bcra (Offset 0x07) R/W Bid Control, Address recognition
<byte 6393>
union bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6393>
{field (By field)}
<byte 6393>
tbits:3 msb_xon_xoff_int_bid Bits 2:0 MSB of an Xon/Xoff interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6393>
utiny value As byte
endunion bcrx (Offset 0x06) R/W Bid Control, Xon/Xoff
<byte 6394>
{rsvd1 ((Offset 0x05) NA Reserved)}
<byte 6394>
utiny value
{}
<byte 6395>
union bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6395>
{field (By field)}
<byte 6395>
tbits:3 msb_cos_int_bid Bits 2:0 MSB of a COS interrupt bid
tbits:5 reserved Bits 7:3 Reserved
{}
or bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6395>
utiny value As byte
endunion bcrcos (Offset 0x04) R/W Bid Control, Change of State
<byte 6396>
union icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6396>
{field (By field)}
<byte 6396>
tbits:7 arbitration_threshold Bits 6:0 Upper seven bits of the Arbitration Threshold
tbits:1 reserved Bit 7 Reserved. Set to 0
{}
or icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6396>
utiny value As byte
endunion icr (Offset 0x0B) R/W Interrupt Control Register (UARTB only)
<byte 6397>
union arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6397>
{field (By field)}
<byte 6397>
tbits:8 multidrop_ac_recognition Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition
{}
or arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6397>
utiny value As byte
endunion arcr (Offset 0x0A) R/W Address Recognition Character
<byte 6398>
union xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6398>
{field (By field)}
<byte 6398>
tbits:8 xoff_character_recognition Bits 7:0 8 Bits of the Xoff Character Recognition
{}
or xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6398>
utiny value As byte
endunion xoffcr (Offset 0x09) R/W Xoff Character Register
<byte 6399>
union xoncr (Offset 0x08) R/W Xon Character Register
<byte 6399>
{field (By field)}
<byte 6399>
tbits:8 xon_character_recognition Bits 7:0 8 Bits of the Xon Character Recognition
{}
or xoncr (Offset 0x08) R/W Xon Character Register
<byte 6399>
utiny value As byte
endunion xoncr (Offset 0x08) R/W Xon Character Register
<byte 6400>
union c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6400>
union gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6400>
{field (By field)}
<byte 6400>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
<byte 6400>
utiny value As byte
endunion gccr (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6400>
union ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6400>
{field (By field)}
<byte 6400>
tbits:8 data_bits Bits 7:0 8 data bits of the Interrupt Vector
{}
or ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6400>
utiny value As byte
endunion ivr (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
or c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6400>
utiny value As byte
endunion c0f (Offset 0x0F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x0F) R/W Interrupt Vector Register (UARTB only)
<byte 6401>
union txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6401>
{field (By field)}
<byte 6401>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6401>
utiny value As byte
endunion txcsr (Offset 0x0E) R/W Transmitter Clock Select Register
<byte 6402>
union c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6402>
{testreg ((Offset 0x0D) R/W Test Register (UARTA only))}
<byte 6402>
utiny value
{}
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6402>
union wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6402>
{field (By field)}
<byte 6402>
tbits:1 wdt_a Bit 0 WDT a
tbits:1 wdt_b Bit 1 WDT b
tbits:1 wdt_c Bit 2 WDT c
tbits:1 wdt_d Bit 3 WDT d
tbits:4 reserved Bits 7:4 Reserved
{}
or wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6402>
utiny value As byte
endunion wdtrcr (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
or c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6402>
utiny value As byte
endunion c0d (Offset 0x0D) R/W Test Register (UARTA only) (Offset 0x0D) R/W Watch-dog Timer Run Control (UARTB only)
<byte 6403>
union rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6403>
{field (By field)}
<byte 6403>
tbits:5 tx_rx_clock_select_code Bits 4:0 Transmitter/Receiver Clock select code
tbits:3 reserved Bits 7:5 Reserved
{}
or rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
<byte 6403>
utiny value As byte
endunion rxcsr (Offset 0x0C) R/W Receiver Clock Select Register
{}
<byte 6404>
{quartdr[0] (SC28L194 Quad UART Data Registers a, b, c, d)}
<byte 6404>
union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6404>
union rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6404>
{field (By field)}
<byte 6404>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6404>
utiny value As byte
endunion rxfifo (Offset 0x83) R Receiver FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6404>
union txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6404>
{field (By field)}
<byte 6404>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6404>
utiny value As byte
endunion txfifo (Offset 0x83) W Transmitter FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6404>
utiny value As byte
endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6405>
union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6405>
union isr (Offset 0x82) R Interrupt Status Register
<byte 6405>
{field (By field)}
<byte 6405>
tbits:1 txrdy Bit 0 Transmitter has entered arbitration process
tbits:1 rxrdy Bit 1 Receiver has entered arbitration process
tbits:1 change_break_state Bit 2 Change of Break State
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event Bit 4 Xon/off event
tbits:1 ar_event Bit 5 Address recognition event
tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out
tbits:1 io_port_change_state Bit 7 I/O Port change of state
{}
or isr (Offset 0x82) R Interrupt Status Register
<byte 6405>
utiny value As byte
endunion isr (Offset 0x82) R Interrupt Status Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6405>
union imr (Offset 0x82) W Interrupt Mask Register
<byte 6405>
{field (By field)}
<byte 6405>
tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable
tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable
tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable
tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable
tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable
tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable
{}
or imr (Offset 0x82) W Interrupt Mask Register
<byte 6405>
utiny value As byte
endunion imr (Offset 0x82) W Interrupt Mask Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6405>
utiny value As byte
endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6406>
union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6406>
union sr (Offset 0x81) R Channel Status Register
<byte 6406>
{field (By field)}
<byte 6406>
tbits:1 rx_ready Bit 0 Receiver Ready
tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full
tbits:1 tx_ready Bit 2 Transmitter Ready
tbits:1 tx_empty Bit 3 Transmitter Empty
tbits:1 overrun_error Bit 4 Overrun Error
tbits:1 parity_error Bit 5 Parity Error
tbits:1 framing_error Bit 6 Framing Error
tbits:1 received_break Bit 7 Received Break
{}
or sr (Offset 0x81) R Channel Status Register
<byte 6406>
utiny value As byte
endunion sr (Offset 0x81) R Channel Status Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6406>
union cr (Offset 0x81) W Command Register
<byte 6406>
{field (By field)}
<byte 6406>
tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable
tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable
tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions
tbits:5 channel_command Bits 7:3 Channel Command
{}
or cr (Offset 0x81) W Command Register
<byte 6406>
utiny value As byte
endunion cr (Offset 0x81) W Command Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6406>
utiny value As byte
endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6407>
union mr2 (Offset 0x80) R/W Mode Register 2
<byte 6407>
{field (By field)}
<byte 6407>
tbits:2 stop_length Bit 1:0 Stop Length
tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition
tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter
tbits:1 tx_rts_control Bit 5 Transmitter RTS Control
tbits:2 channel_mode Bits 7:6 Channel Mode
{}
or mr2 (Offset 0x80) R/W Mode Register 2
<byte 6407>
utiny value As byte
endunion mr2 (Offset 0x80) R/W Mode Register 2
<byte 6408>
union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6408>
union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6408>
{field (By field)}
<byte 6408>
tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection
tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection
{}
or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6408>
utiny value As byte
endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6408>
union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6408>
{field (By field)}
<byte 6408>
tbits:1 gpor_0 Bit 0 GPOR(0)
tbits:1 gpor_1 Bit 1 GPOR(1)
tbits:1 gpor_2 Bit 2 GPOR(2)
tbits:1 gpor_3 Bit 3 GPOR(3)
tbits:4 reserved Bits 7:4 Reserved
{}
or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6408>
utiny value As byte
endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6408>
utiny value As byte
endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6409>
union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6409>
{field (By field)}
<byte 6409>
tbits:2 txd_character_status Bits 1:0 TxD character status
tbits:2 txd_flow_status Bits 3:2 TxD flow status
tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status
tbits:2 received_x_character_status Bits 7:6 Received X Character Status
{}
or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6409>
utiny value As byte
endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6410>
union iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6410>
{field (By field)}
<byte 6410>
tbits:1 io0_output Bit 0 I/O0 output
tbits:1 io1_output Bit 1 I/O1 output
tbits:1 io2_output Bit 2 I/O2 output
tbits:1 io3_output Bit 3 I/O3 output
tbits:1 io0_enable Bit 4 I/O0 enable
tbits:1 io1_enable Bit 5 I/O1 enable
tbits:1 io2_enable Bit 6 I/O2 enable
tbits:1 io3_enable Bit 7 I/O3 enable
{}
or iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6410>
utiny value As byte
endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6411>
union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6411>
union ipr (Offset 0x84) R Input Port Register
<byte 6411>
{field (By field)}
<byte 6411>
tbits:1 io0_state Bit 0 I/O0 state
tbits:1 io1_state Bit 1 I/O1 state
tbits:1 io2_state Bit 2 I/O2 state
tbits:1 io3_state Bit 3 I/O3 state
tbits:1 io0_change Bit 4 I/O0 change
tbits:1 io1_change Bit 5 I/O1 change
tbits:1 io2_change Bit 6 I/O2 change
tbits:1 io3_change Bit 7 I/O3 change
{}
or ipr (Offset 0x84) R Input Port Register
<byte 6411>
utiny value As byte
endunion ipr (Offset 0x84) R Input Port Register
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6411>
union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6411>
{field (By field)}
<byte 6411>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6411>
utiny value As byte
endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6411>
union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6411>
{field (By field)}
<byte 6411>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6411>
utiny value As byte
endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6411>
utiny value As byte
endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6412>
union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6412>
union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6412>
{field (By field)}
<byte 6412>
tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0)
tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1)
tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2)
tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3)
{}
or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6412>
utiny value As byte
endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6412>
union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6412>
{field (By field)}
<byte 6412>
tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0)
tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1)
tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2)
tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3)
{}
or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6412>
utiny value As byte
endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6412>
utiny value As byte
endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6413>
{rsvd3 ((Offset 0x8A) NA Reserved)}
<byte 6413>
utiny value
{}
<byte 6414>
{rsvd2 ((Offset 0x89) NA Reserved)}
<byte 6414>
utiny value
{}
<byte 6415>
{rsvd1 ((Offset 0x88) NA Reserved)}
<byte 6415>
utiny value
{}
<byte 6416>
union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6416>
union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6416>
{field (By field)}
<byte 6416>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6416>
utiny value As byte
endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6416>
union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6416>
{field (By field)}
<byte 6416>
tbits:3 other_types Bit 2:0 Other types
tbits:2 reserved Bit 4:3 Reserved
tbits:1 tx_interrupt Bit 5 Transmitter Interrupt
tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt
{}
or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6416>
utiny value As byte
endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6416>
utiny value As byte
endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6417>
union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6417>
union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6417>
{field (By field)}
<byte 6417>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6417>
utiny value As byte
endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6417>
union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6417>
{field (By field)}
<byte 6417>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6417>
utiny value As byte
endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6417>
utiny value As byte
endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6418>
union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6418>
union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6418>
{field (By field)}
<byte 6418>
tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code
tbits:4 reserved Bits 7:4 Reserved
{}
or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6418>
utiny value As byte
endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6418>
union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6418>
{field (By field)}
<byte 6418>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6418>
utiny value As byte
endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6418>
union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6418>
{field (By field)}
<byte 6418>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6418>
utiny value As byte
endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6418>
utiny value As byte
endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6419>
union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
union cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6419>
{field (By field)}
<byte 6419>
tbits:3 channel_number Bits 2:0 Channel number
tbits:3 current_byte_count_type Bits 5:3 Current byte count/type
tbits:2 type Bits 7:6 Type
{}
or cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6419>
utiny value As byte
endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6419>
{field (By field)}
<byte 6419>
tbits:3 channel_code Bits 2:0 Channel code
tbits:5 reserved Bits 7:3 Reserved
{}
or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6419>
utiny value As byte
endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
{ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))}
<byte 6419>
utiny value
{}
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
{field (By field)}
<byte 6419>
tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection
tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control
tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection
tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control
{}
or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
utiny value As byte
endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6419>
utiny value As byte
endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
{}
<byte 6420>
{quartdr[1] (SC28L194 Quad UART Data Registers a, b, c, d)}
<byte 6420>
union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6420>
union rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6420>
{field (By field)}
<byte 6420>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6420>
utiny value As byte
endunion rxfifo (Offset 0x83) R Receiver FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6420>
union txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6420>
{field (By field)}
<byte 6420>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6420>
utiny value As byte
endunion txfifo (Offset 0x83) W Transmitter FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6420>
utiny value As byte
endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6421>
union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6421>
union isr (Offset 0x82) R Interrupt Status Register
<byte 6421>
{field (By field)}
<byte 6421>
tbits:1 txrdy Bit 0 Transmitter has entered arbitration process
tbits:1 rxrdy Bit 1 Receiver has entered arbitration process
tbits:1 change_break_state Bit 2 Change of Break State
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event Bit 4 Xon/off event
tbits:1 ar_event Bit 5 Address recognition event
tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out
tbits:1 io_port_change_state Bit 7 I/O Port change of state
{}
or isr (Offset 0x82) R Interrupt Status Register
<byte 6421>
utiny value As byte
endunion isr (Offset 0x82) R Interrupt Status Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6421>
union imr (Offset 0x82) W Interrupt Mask Register
<byte 6421>
{field (By field)}
<byte 6421>
tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable
tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable
tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable
tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable
tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable
tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable
{}
or imr (Offset 0x82) W Interrupt Mask Register
<byte 6421>
utiny value As byte
endunion imr (Offset 0x82) W Interrupt Mask Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6421>
utiny value As byte
endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6422>
union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6422>
union sr (Offset 0x81) R Channel Status Register
<byte 6422>
{field (By field)}
<byte 6422>
tbits:1 rx_ready Bit 0 Receiver Ready
tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full
tbits:1 tx_ready Bit 2 Transmitter Ready
tbits:1 tx_empty Bit 3 Transmitter Empty
tbits:1 overrun_error Bit 4 Overrun Error
tbits:1 parity_error Bit 5 Parity Error
tbits:1 framing_error Bit 6 Framing Error
tbits:1 received_break Bit 7 Received Break
{}
or sr (Offset 0x81) R Channel Status Register
<byte 6422>
utiny value As byte
endunion sr (Offset 0x81) R Channel Status Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6422>
union cr (Offset 0x81) W Command Register
<byte 6422>
{field (By field)}
<byte 6422>
tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable
tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable
tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions
tbits:5 channel_command Bits 7:3 Channel Command
{}
or cr (Offset 0x81) W Command Register
<byte 6422>
utiny value As byte
endunion cr (Offset 0x81) W Command Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6422>
utiny value As byte
endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6423>
union mr2 (Offset 0x80) R/W Mode Register 2
<byte 6423>
{field (By field)}
<byte 6423>
tbits:2 stop_length Bit 1:0 Stop Length
tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition
tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter
tbits:1 tx_rts_control Bit 5 Transmitter RTS Control
tbits:2 channel_mode Bits 7:6 Channel Mode
{}
or mr2 (Offset 0x80) R/W Mode Register 2
<byte 6423>
utiny value As byte
endunion mr2 (Offset 0x80) R/W Mode Register 2
<byte 6424>
union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6424>
union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6424>
{field (By field)}
<byte 6424>
tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection
tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection
{}
or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6424>
utiny value As byte
endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6424>
union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6424>
{field (By field)}
<byte 6424>
tbits:1 gpor_0 Bit 0 GPOR(0)
tbits:1 gpor_1 Bit 1 GPOR(1)
tbits:1 gpor_2 Bit 2 GPOR(2)
tbits:1 gpor_3 Bit 3 GPOR(3)
tbits:4 reserved Bits 7:4 Reserved
{}
or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6424>
utiny value As byte
endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6424>
utiny value As byte
endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6425>
union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6425>
{field (By field)}
<byte 6425>
tbits:2 txd_character_status Bits 1:0 TxD character status
tbits:2 txd_flow_status Bits 3:2 TxD flow status
tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status
tbits:2 received_x_character_status Bits 7:6 Received X Character Status
{}
or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6425>
utiny value As byte
endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6426>
union iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6426>
{field (By field)}
<byte 6426>
tbits:1 io0_output Bit 0 I/O0 output
tbits:1 io1_output Bit 1 I/O1 output
tbits:1 io2_output Bit 2 I/O2 output
tbits:1 io3_output Bit 3 I/O3 output
tbits:1 io0_enable Bit 4 I/O0 enable
tbits:1 io1_enable Bit 5 I/O1 enable
tbits:1 io2_enable Bit 6 I/O2 enable
tbits:1 io3_enable Bit 7 I/O3 enable
{}
or iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6426>
utiny value As byte
endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6427>
union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6427>
union ipr (Offset 0x84) R Input Port Register
<byte 6427>
{field (By field)}
<byte 6427>
tbits:1 io0_state Bit 0 I/O0 state
tbits:1 io1_state Bit 1 I/O1 state
tbits:1 io2_state Bit 2 I/O2 state
tbits:1 io3_state Bit 3 I/O3 state
tbits:1 io0_change Bit 4 I/O0 change
tbits:1 io1_change Bit 5 I/O1 change
tbits:1 io2_change Bit 6 I/O2 change
tbits:1 io3_change Bit 7 I/O3 change
{}
or ipr (Offset 0x84) R Input Port Register
<byte 6427>
utiny value As byte
endunion ipr (Offset 0x84) R Input Port Register
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6427>
union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6427>
{field (By field)}
<byte 6427>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6427>
utiny value As byte
endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6427>
union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6427>
{field (By field)}
<byte 6427>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6427>
utiny value As byte
endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6427>
utiny value As byte
endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6428>
union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6428>
union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6428>
{field (By field)}
<byte 6428>
tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0)
tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1)
tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2)
tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3)
{}
or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6428>
utiny value As byte
endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6428>
union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6428>
{field (By field)}
<byte 6428>
tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0)
tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1)
tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2)
tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3)
{}
or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6428>
utiny value As byte
endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6428>
utiny value As byte
endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6429>
{rsvd3 ((Offset 0x8A) NA Reserved)}
<byte 6429>
utiny value
{}
<byte 6430>
{rsvd2 ((Offset 0x89) NA Reserved)}
<byte 6430>
utiny value
{}
<byte 6431>
{rsvd1 ((Offset 0x88) NA Reserved)}
<byte 6431>
utiny value
{}
<byte 6432>
union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6432>
union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6432>
{field (By field)}
<byte 6432>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6432>
utiny value As byte
endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6432>
union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6432>
{field (By field)}
<byte 6432>
tbits:3 other_types Bit 2:0 Other types
tbits:2 reserved Bit 4:3 Reserved
tbits:1 tx_interrupt Bit 5 Transmitter Interrupt
tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt
{}
or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6432>
utiny value As byte
endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6432>
utiny value As byte
endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6433>
union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6433>
union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6433>
{field (By field)}
<byte 6433>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6433>
utiny value As byte
endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6433>
union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6433>
{field (By field)}
<byte 6433>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6433>
utiny value As byte
endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6433>
utiny value As byte
endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6434>
union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6434>
union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6434>
{field (By field)}
<byte 6434>
tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code
tbits:4 reserved Bits 7:4 Reserved
{}
or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6434>
utiny value As byte
endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6434>
union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6434>
{field (By field)}
<byte 6434>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6434>
utiny value As byte
endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6434>
union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6434>
{field (By field)}
<byte 6434>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6434>
utiny value As byte
endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6434>
utiny value As byte
endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6435>
union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
union cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6435>
{field (By field)}
<byte 6435>
tbits:3 channel_number Bits 2:0 Channel number
tbits:3 current_byte_count_type Bits 5:3 Current byte count/type
tbits:2 type Bits 7:6 Type
{}
or cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6435>
utiny value As byte
endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6435>
{field (By field)}
<byte 6435>
tbits:3 channel_code Bits 2:0 Channel code
tbits:5 reserved Bits 7:3 Reserved
{}
or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6435>
utiny value As byte
endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
{ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))}
<byte 6435>
utiny value
{}
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
{field (By field)}
<byte 6435>
tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection
tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control
tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection
tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control
{}
or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
utiny value As byte
endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6435>
utiny value As byte
endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
{}
<byte 6436>
{quartdr[2] (SC28L194 Quad UART Data Registers a, b, c, d)}
<byte 6436>
union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6436>
union rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6436>
{field (By field)}
<byte 6436>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6436>
utiny value As byte
endunion rxfifo (Offset 0x83) R Receiver FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6436>
union txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6436>
{field (By field)}
<byte 6436>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6436>
utiny value As byte
endunion txfifo (Offset 0x83) W Transmitter FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6436>
utiny value As byte
endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6437>
union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6437>
union isr (Offset 0x82) R Interrupt Status Register
<byte 6437>
{field (By field)}
<byte 6437>
tbits:1 txrdy Bit 0 Transmitter has entered arbitration process
tbits:1 rxrdy Bit 1 Receiver has entered arbitration process
tbits:1 change_break_state Bit 2 Change of Break State
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event Bit 4 Xon/off event
tbits:1 ar_event Bit 5 Address recognition event
tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out
tbits:1 io_port_change_state Bit 7 I/O Port change of state
{}
or isr (Offset 0x82) R Interrupt Status Register
<byte 6437>
utiny value As byte
endunion isr (Offset 0x82) R Interrupt Status Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6437>
union imr (Offset 0x82) W Interrupt Mask Register
<byte 6437>
{field (By field)}
<byte 6437>
tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable
tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable
tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable
tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable
tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable
tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable
{}
or imr (Offset 0x82) W Interrupt Mask Register
<byte 6437>
utiny value As byte
endunion imr (Offset 0x82) W Interrupt Mask Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6437>
utiny value As byte
endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6438>
union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6438>
union sr (Offset 0x81) R Channel Status Register
<byte 6438>
{field (By field)}
<byte 6438>
tbits:1 rx_ready Bit 0 Receiver Ready
tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full
tbits:1 tx_ready Bit 2 Transmitter Ready
tbits:1 tx_empty Bit 3 Transmitter Empty
tbits:1 overrun_error Bit 4 Overrun Error
tbits:1 parity_error Bit 5 Parity Error
tbits:1 framing_error Bit 6 Framing Error
tbits:1 received_break Bit 7 Received Break
{}
or sr (Offset 0x81) R Channel Status Register
<byte 6438>
utiny value As byte
endunion sr (Offset 0x81) R Channel Status Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6438>
union cr (Offset 0x81) W Command Register
<byte 6438>
{field (By field)}
<byte 6438>
tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable
tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable
tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions
tbits:5 channel_command Bits 7:3 Channel Command
{}
or cr (Offset 0x81) W Command Register
<byte 6438>
utiny value As byte
endunion cr (Offset 0x81) W Command Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6438>
utiny value As byte
endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6439>
union mr2 (Offset 0x80) R/W Mode Register 2
<byte 6439>
{field (By field)}
<byte 6439>
tbits:2 stop_length Bit 1:0 Stop Length
tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition
tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter
tbits:1 tx_rts_control Bit 5 Transmitter RTS Control
tbits:2 channel_mode Bits 7:6 Channel Mode
{}
or mr2 (Offset 0x80) R/W Mode Register 2
<byte 6439>
utiny value As byte
endunion mr2 (Offset 0x80) R/W Mode Register 2
<byte 6440>
union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6440>
union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6440>
{field (By field)}
<byte 6440>
tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection
tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection
{}
or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6440>
utiny value As byte
endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6440>
union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6440>
{field (By field)}
<byte 6440>
tbits:1 gpor_0 Bit 0 GPOR(0)
tbits:1 gpor_1 Bit 1 GPOR(1)
tbits:1 gpor_2 Bit 2 GPOR(2)
tbits:1 gpor_3 Bit 3 GPOR(3)
tbits:4 reserved Bits 7:4 Reserved
{}
or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6440>
utiny value As byte
endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6440>
utiny value As byte
endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6441>
union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6441>
{field (By field)}
<byte 6441>
tbits:2 txd_character_status Bits 1:0 TxD character status
tbits:2 txd_flow_status Bits 3:2 TxD flow status
tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status
tbits:2 received_x_character_status Bits 7:6 Received X Character Status
{}
or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6441>
utiny value As byte
endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6442>
union iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6442>
{field (By field)}
<byte 6442>
tbits:1 io0_output Bit 0 I/O0 output
tbits:1 io1_output Bit 1 I/O1 output
tbits:1 io2_output Bit 2 I/O2 output
tbits:1 io3_output Bit 3 I/O3 output
tbits:1 io0_enable Bit 4 I/O0 enable
tbits:1 io1_enable Bit 5 I/O1 enable
tbits:1 io2_enable Bit 6 I/O2 enable
tbits:1 io3_enable Bit 7 I/O3 enable
{}
or iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6442>
utiny value As byte
endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6443>
union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6443>
union ipr (Offset 0x84) R Input Port Register
<byte 6443>
{field (By field)}
<byte 6443>
tbits:1 io0_state Bit 0 I/O0 state
tbits:1 io1_state Bit 1 I/O1 state
tbits:1 io2_state Bit 2 I/O2 state
tbits:1 io3_state Bit 3 I/O3 state
tbits:1 io0_change Bit 4 I/O0 change
tbits:1 io1_change Bit 5 I/O1 change
tbits:1 io2_change Bit 6 I/O2 change
tbits:1 io3_change Bit 7 I/O3 change
{}
or ipr (Offset 0x84) R Input Port Register
<byte 6443>
utiny value As byte
endunion ipr (Offset 0x84) R Input Port Register
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6443>
union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6443>
{field (By field)}
<byte 6443>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6443>
utiny value As byte
endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6443>
union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6443>
{field (By field)}
<byte 6443>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6443>
utiny value As byte
endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6443>
utiny value As byte
endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6444>
union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6444>
union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6444>
{field (By field)}
<byte 6444>
tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0)
tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1)
tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2)
tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3)
{}
or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6444>
utiny value As byte
endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6444>
union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6444>
{field (By field)}
<byte 6444>
tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0)
tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1)
tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2)
tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3)
{}
or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6444>
utiny value As byte
endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6444>
utiny value As byte
endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6445>
{rsvd3 ((Offset 0x8A) NA Reserved)}
<byte 6445>
utiny value
{}
<byte 6446>
{rsvd2 ((Offset 0x89) NA Reserved)}
<byte 6446>
utiny value
{}
<byte 6447>
{rsvd1 ((Offset 0x88) NA Reserved)}
<byte 6447>
utiny value
{}
<byte 6448>
union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6448>
union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6448>
{field (By field)}
<byte 6448>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6448>
utiny value As byte
endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6448>
union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6448>
{field (By field)}
<byte 6448>
tbits:3 other_types Bit 2:0 Other types
tbits:2 reserved Bit 4:3 Reserved
tbits:1 tx_interrupt Bit 5 Transmitter Interrupt
tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt
{}
or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6448>
utiny value As byte
endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6448>
utiny value As byte
endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6449>
union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6449>
union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6449>
{field (By field)}
<byte 6449>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6449>
utiny value As byte
endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6449>
union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6449>
{field (By field)}
<byte 6449>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6449>
utiny value As byte
endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6449>
utiny value As byte
endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6450>
union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6450>
union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6450>
{field (By field)}
<byte 6450>
tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code
tbits:4 reserved Bits 7:4 Reserved
{}
or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6450>
utiny value As byte
endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6450>
union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6450>
{field (By field)}
<byte 6450>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6450>
utiny value As byte
endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6450>
union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6450>
{field (By field)}
<byte 6450>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6450>
utiny value As byte
endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6450>
utiny value As byte
endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6451>
union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
union cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6451>
{field (By field)}
<byte 6451>
tbits:3 channel_number Bits 2:0 Channel number
tbits:3 current_byte_count_type Bits 5:3 Current byte count/type
tbits:2 type Bits 7:6 Type
{}
or cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6451>
utiny value As byte
endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6451>
{field (By field)}
<byte 6451>
tbits:3 channel_code Bits 2:0 Channel code
tbits:5 reserved Bits 7:3 Reserved
{}
or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6451>
utiny value As byte
endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
{ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))}
<byte 6451>
utiny value
{}
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
{field (By field)}
<byte 6451>
tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection
tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control
tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection
tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control
{}
or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
utiny value As byte
endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6451>
utiny value As byte
endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
{}
<byte 6452>
{quartdr[3] (SC28L194 Quad UART Data Registers a, b, c, d)}
<byte 6452>
union d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6452>
union rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6452>
{field (By field)}
<byte 6452>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or rxfifo (Offset 0x83) R Receiver FIFO Register
<byte 6452>
utiny value As byte
endunion rxfifo (Offset 0x83) R Receiver FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6452>
union txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6452>
{field (By field)}
<byte 6452>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or txfifo (Offset 0x83) W Transmitter FIFO Register
<byte 6452>
utiny value As byte
endunion txfifo (Offset 0x83) W Transmitter FIFO Register
or d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6452>
utiny value As byte
endunion d83 (Offset 0x83) R Receiver FIFO Register (Offset 0x83) W Transmitter FIFO Register
<byte 6453>
union d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6453>
union isr (Offset 0x82) R Interrupt Status Register
<byte 6453>
{field (By field)}
<byte 6453>
tbits:1 txrdy Bit 0 Transmitter has entered arbitration process
tbits:1 rxrdy Bit 1 Receiver has entered arbitration process
tbits:1 change_break_state Bit 2 Change of Break State
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event Bit 4 Xon/off event
tbits:1 ar_event Bit 5 Address recognition event
tbits:1 rx_watch_dog_time_out Bit 6 Receiver Watch-dog Time-out
tbits:1 io_port_change_state Bit 7 I/O Port change of state
{}
or isr (Offset 0x82) R Interrupt Status Register
<byte 6453>
utiny value As byte
endunion isr (Offset 0x82) R Interrupt Status Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6453>
union imr (Offset 0x82) W Interrupt Mask Register
<byte 6453>
{field (By field)}
<byte 6453>
tbits:1 txrdy_int_enable Bit 0 TxRDY interrupt enable
tbits:1 rxrdy_int_enable Bit 1 RxRDY interrupt enable
tbits:1 change_break_state_int_enable Bit 2 Change of Break State interrupt enable
tbits:1 reserved Bit 3 Reserved
tbits:1 xon_off_event_int_enable Bit 4 Xon/off event interrupt enable
tbits:1 ar_event_int_enable Bit 5 Address recognition event interrupt enable
tbits:1 rx_watch_dog_time_out_int_enable Bit 6 Receiver Watch-dog Time-out interrupt enable
tbits:1 io_port_change_state_int_enable Bit 7 I/O Port change of state interrupted enable
{}
or imr (Offset 0x82) W Interrupt Mask Register
<byte 6453>
utiny value As byte
endunion imr (Offset 0x82) W Interrupt Mask Register
or d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6453>
utiny value As byte
endunion d82 (Offset 0x82) R Interrupt Status Register (Offset 0x82) W Interrupt Mask Register
<byte 6454>
union d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6454>
union sr (Offset 0x81) R Channel Status Register
<byte 6454>
{field (By field)}
<byte 6454>
tbits:1 rx_ready Bit 0 Receiver Ready
tbits:1 rx_fifo_full Bit 1 Receiver FIFO Full
tbits:1 tx_ready Bit 2 Transmitter Ready
tbits:1 tx_empty Bit 3 Transmitter Empty
tbits:1 overrun_error Bit 4 Overrun Error
tbits:1 parity_error Bit 5 Parity Error
tbits:1 framing_error Bit 6 Framing Error
tbits:1 received_break Bit 7 Received Break
{}
or sr (Offset 0x81) R Channel Status Register
<byte 6454>
utiny value As byte
endunion sr (Offset 0x81) R Channel Status Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6454>
union cr (Offset 0x81) W Command Register
<byte 6454>
{field (By field)}
<byte 6454>
tbits:1 rx_enable_disable Bit 0 Receiver Enable/Disable
tbits:1 tx_enable_disable Bit 1 Transmitter Enable/Disable
tbits:1 lock_txd_rxfifo_enables Bit 2 Hold present condition of Transmitter & Receiver enables/Change Transmitter & Receiver enable conditions
tbits:5 channel_command Bits 7:3 Channel Command
{}
or cr (Offset 0x81) W Command Register
<byte 6454>
utiny value As byte
endunion cr (Offset 0x81) W Command Register
or d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6454>
utiny value As byte
endunion d81 (Offset 0x81) R Channel Status Register (Offset 0x81) W Command Register
<byte 6455>
union mr2 (Offset 0x80) R/W Mode Register 2
<byte 6455>
{field (By field)}
<byte 6455>
tbits:2 stop_length Bit 1:0 Stop Length
tbits:2 txint Bit 3:2 Receiver initiation of interrupt bidding condition
tbits:1 ctsn_enable_tx Bit 4 CTSN Enable Transmitter
tbits:1 tx_rts_control Bit 5 Transmitter RTS Control
tbits:2 channel_mode Bits 7:6 Channel Mode
{}
or mr2 (Offset 0x80) R/W Mode Register 2
<byte 6455>
utiny value As byte
endunion mr2 (Offset 0x80) R/W Mode Register 2
<byte 6456>
union d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6456>
union gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6456>
{field (By field)}
<byte 6456>
tbits:4 ggpo_0_selection Bits 3:0 Global General Purpose Output 0 Selection
tbits:4 ggpo_1_selection Bits 7:4 Global General Purpose Output 1 Selection
{}
or gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
<byte 6456>
utiny value As byte
endunion gposr (Offset 0x87) R/W General Purpose Output Select Register (UARTA only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6456>
union gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6456>
{field (By field)}
<byte 6456>
tbits:1 gpor_0 Bit 0 GPOR(0)
tbits:1 gpor_1 Bit 1 GPOR(1)
tbits:1 gpor_2 Bit 2 GPOR(2)
tbits:1 gpor_3 Bit 3 GPOR(3)
tbits:4 reserved Bits 7:4 Reserved
{}
or gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6456>
utiny value As byte
endunion gpor (Offset 0x87) R/W General Purpose Output Register (UARTB only)
or d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6456>
utiny value As byte
endunion d87 (Offset 0x87) R/W General Purpose Output Select Register (UARTA only) (Offset 0x87) R/W General Purpose Output Register (UARTB only)
<byte 6457>
union xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6457>
{field (By field)}
<byte 6457>
tbits:2 txd_character_status Bits 1:0 TxD character status
tbits:2 txd_flow_status Bits 3:2 TxD flow status
tbits:2 auto_x_character_xmission_status Bits 5:4 Automatic Character transmission status
tbits:2 received_x_character_status Bits 7:6 Received X Character Status
{}
or xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6457>
utiny value As byte
endunion xisr (Offset 0x86) R Xon/Xoff Interrupt Status Register
<byte 6458>
union iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6458>
{field (By field)}
<byte 6458>
tbits:1 io0_output Bit 0 I/O0 output
tbits:1 io1_output Bit 1 I/O1 output
tbits:1 io2_output Bit 2 I/O2 output
tbits:1 io3_output Bit 3 I/O3 output
tbits:1 io0_enable Bit 4 I/O0 enable
tbits:1 io1_enable Bit 5 I/O1 enable
tbits:1 io2_enable Bit 6 I/O2 enable
tbits:1 io3_enable Bit 7 I/O3 enable
{}
or iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6458>
utiny value As byte
endunion iopior (Offset 0x85) R/W I/O Port Interrupt and Output
<byte 6459>
union d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6459>
union ipr (Offset 0x84) R Input Port Register
<byte 6459>
{field (By field)}
<byte 6459>
tbits:1 io0_state Bit 0 I/O0 state
tbits:1 io1_state Bit 1 I/O1 state
tbits:1 io2_state Bit 2 I/O2 state
tbits:1 io3_state Bit 3 I/O3 state
tbits:1 io0_change Bit 4 I/O0 change
tbits:1 io1_change Bit 5 I/O1 change
tbits:1 io2_change Bit 6 I/O2 change
tbits:1 io3_change Bit 7 I/O3 change
{}
or ipr (Offset 0x84) R Input Port Register
<byte 6459>
utiny value As byte
endunion ipr (Offset 0x84) R Input Port Register
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6459>
union brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6459>
{field (By field)}
<byte 6459>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
<byte 6459>
utiny value As byte
endunion brgtrua (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6459>
union brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6459>
{field (By field)}
<byte 6459>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6459>
utiny value As byte
endunion brgtrla (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
or d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6459>
utiny value As byte
endunion d84 (Offset 0x84) R Input Port Register (Offset 0x84) W Baud Rate Generator Timer Register Upper a (UARTA only) (Offset 0x84) W Baud Rate Generator Timer Register Lower a (UARTB only)
<byte 6460>
union d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6460>
union gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6460>
{field (By field)}
<byte 6460>
tbits:2 clock_selection_gpor_0 Bits 1:0 Clock Selection GPOR(0)
tbits:2 clock_selection_gpor_1 Bits 3:2 Clock Selection GPOR(1)
tbits:2 clock_selection_gpor_2 Bits 5:4 Clock Selection GPOR(2)
tbits:2 clock_selection_gpor_3 Bits 7:6 Clock Selection GPOR(3)
{}
or gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
<byte 6460>
utiny value As byte
endunion gpoc (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6460>
union gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6460>
{field (By field)}
<byte 6460>
tbits:2 data_selection_gpor_0 Bits 1:0 Data Selection GPOR(0)
tbits:2 data_selection_gpor_1 Bits 3:2 Data Selection GPOR(1)
tbits:2 data_selection_gpor_2 Bits 5:4 Data Selection GPOR(2)
tbits:2 data_selection_gpor_3 Bits 7:6 Data Selection GPOR(3)
{}
or gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6460>
utiny value As byte
endunion gpod (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
or d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6460>
utiny value As byte
endunion d8B (Offset 0x8B) R/W General Purpose Output Clock Register (UARTA only) (Offset 0x8B) R/W General Purpose Output Data Register (UARTB only)
<byte 6461>
{rsvd3 ((Offset 0x8A) NA Reserved)}
<byte 6461>
utiny value
{}
<byte 6462>
{rsvd2 ((Offset 0x89) NA Reserved)}
<byte 6462>
utiny value
{}
<byte 6463>
{rsvd1 ((Offset 0x88) NA Reserved)}
<byte 6463>
utiny value
{}
<byte 6464>
union d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6464>
union gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6464>
{field (By field)}
<byte 6464>
tbits:1 power_down_mode Bit 0 Power Down Mode
tbits:2 int_vector_control Bit 2:1 Interrupt Vector Control
tbits:3 reserved_5_3 Bit 5:3 Reserved
tbits:1 sync_bus_cycles Bit 6 Sync bus cycles
tbits:1 reserved_7 Bit 7 Reserved
{}
or gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
<byte 6464>
utiny value As byte
endunion gccr (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6464>
union gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6464>
{field (By field)}
<byte 6464>
tbits:3 other_types Bit 2:0 Other types
tbits:2 reserved Bit 4:3 Reserved
tbits:1 tx_interrupt Bit 5 Transmitter Interrupt
tbits:2 rx_interrupt Bit 7:6 Receiver Interrupt
{}
or gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6464>
utiny value As byte
endunion gitr (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
or d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6464>
utiny value As byte
endunion d8F (Offset 0x8F) R/W Global Chip Configuration Register (UARTA only) (Offset 0x8F) R Global Interrupt Type Register (UARTB only)
<byte 6465>
union d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6465>
union grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6465>
{field (By field)}
<byte 6465>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
<byte 6465>
utiny value As byte
endunion grxfifo (Offset 0x8E) R Global Receive FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6465>
union gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6465>
{field (By field)}
<byte 6465>
tbits:8 data_bits Bits [7:0] 8 data bits MSBs =0 for 7,6,5 bit data
{}
or gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6465>
utiny value As byte
endunion gtxfifo (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
or d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6465>
utiny value As byte
endunion d8E (Offset 0x8E) R Global Receive FIFO Register (UARTA only) (Offset 0x8E) W Global Transmit FIFO Register (UARTA only)
<byte 6466>
union d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6466>
union gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6466>
{field (By field)}
<byte 6466>
tbits:4 channel_byte_count_code Bits 3:0 Channel byte count code
tbits:4 reserved Bits 7:4 Reserved
{}
or gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
<byte 6466>
utiny value As byte
endunion gibcr (Offset 0x8D) R Global Interrupt Byte Count (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6466>
union brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6466>
{field (By field)}
<byte 6466>
tbits:8 msb_brg_timer_divisor Bits 7:0 8 MSB of the Baud Rate Generator Timer divisor
{}
or brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
<byte 6466>
utiny value As byte
endunion brgtrub (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6466>
union brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6466>
{field (By field)}
<byte 6466>
tbits:8 lsb_brg_timer_divisor Bits 7:0 8 LSB of the Baud Rate Generator Timer divisor
{}
or brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6466>
utiny value As byte
endunion brgtrlb (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
or d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6466>
utiny value As byte
endunion d8D (Offset 0x8D) R Global Interrupt Byte Count (UARTB only) (Offset 0x8D) W Baud Rate Generator Timer Register Upper b (UARTA only) (Offset 0x8D) W Baud Rate Generator Timer Register Lower b (UARTB only)
<byte 6467>
union d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
union cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6467>
{field (By field)}
<byte 6467>
tbits:3 channel_number Bits 2:0 Channel number
tbits:3 current_byte_count_type Bits 5:3 Current byte count/type
tbits:2 type Bits 7:6 Type
{}
or cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
<byte 6467>
utiny value As byte
endunion cir (Offset 0x8C) R Current Interrupt Register (UARTA only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
union gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6467>
{field (By field)}
<byte 6467>
tbits:3 channel_code Bits 2:0 Channel code
tbits:5 reserved Bits 7:3 Reserved
{}
or gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
<byte 6467>
utiny value As byte
endunion gicr (Offset 0x8C) R Global Interrupt Channel Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
{ucir ((Offset 0x8C) W Update Current Interrupt Register (UARTA only))}
<byte 6467>
utiny value
{}
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
union brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
{field (By field)}
<byte 6467>
tbits:3 brgtcr_a_clock_selection Bit 2:0 BRGTCR a, Clock selection
tbits:1 brgtcr_a_register_control Bit 3 BRGTCR a, Register control
tbits:3 brgtcr_b_clock_selection Bit 6:4 BRGTCR b, Clock selection
tbits:1 brgtcr_b_register_control Bit 7 BRGTCR b, Register control
{}
or brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
utiny value As byte
endunion brgtcr (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
or d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
<byte 6467>
utiny value As byte
endunion d8C (Offset 0x8C) R Current Interrupt Register (UARTA only) (Offset 0x8C) R Global Interrupt Channel Register (UARTB only) (Offset 0x8C) W Update Current Interrupt Register (UARTA only) (Offset 0x8C) W Baud Rate Generator Timer Control Register (UARTB only)
{}
<byte 6468>
{tachyon (Tachyon DX2+ register save area)}
<byte 6468>
union portcorr[0] Port Correlation
<byte 6468>
ulong portcorra Port Correlation As Longword
or portcorr[0] Port Correlation
<byte 6468>
{portcorr (Port Correlation By Field)}
<byte 6468>
utiny real_port Real hardware port number
<byte 6469>
utiny port_type Port type
<byte 6470>
ushort reserved Reserved
{}
endunion portcorr[0] Port Correlation
<byte 6472>
union portcorr[1] Port Correlation
<byte 6472>
ulong portcorra Port Correlation As Longword
or portcorr[1] Port Correlation
<byte 6472>
{portcorr (Port Correlation By Field)}
<byte 6472>
utiny real_port Real hardware port number
<byte 6473>
utiny port_type Port type
<byte 6474>
ushort reserved Reserved
{}
endunion portcorr[1] Port Correlation
<byte 6476>
union portcorr[2] Port Correlation
<byte 6476>
ulong portcorra Port Correlation As Longword
or portcorr[2] Port Correlation
<byte 6476>
{portcorr (Port Correlation By Field)}
<byte 6476>
utiny real_port Real hardware port number
<byte 6477>
utiny port_type Port type
<byte 6478>
ushort reserved Reserved
{}
endunion portcorr[2] Port Correlation
<byte 6480>
union portcorr[3] Port Correlation
<byte 6480>
ulong portcorra Port Correlation As Longword
or portcorr[3] Port Correlation
<byte 6480>
{portcorr (Port Correlation By Field)}
<byte 6480>
utiny real_port Real hardware port number
<byte 6481>
utiny port_type Port type
<byte 6482>
ushort reserved Reserved
{}
endunion portcorr[3] Port Correlation
<byte 6484>
union portcorr[4] Port Correlation
<byte 6484>
ulong portcorra Port Correlation As Longword
or portcorr[4] Port Correlation
<byte 6484>
{portcorr (Port Correlation By Field)}
<byte 6484>
utiny real_port Real hardware port number
<byte 6485>
utiny port_type Port type
<byte 6486>
ushort reserved Reserved
{}
endunion portcorr[4] Port Correlation
<byte 6488>
union portcorr[5] Port Correlation
<byte 6488>
ulong portcorra Port Correlation As Longword
or portcorr[5] Port Correlation
<byte 6488>
{portcorr (Port Correlation By Field)}
<byte 6488>
utiny real_port Real hardware port number
<byte 6489>
utiny port_type Port type
<byte 6490>
ushort reserved Reserved
{}
endunion portcorr[5] Port Correlation
<byte 6492>
union portcorr[6] Port Correlation
<byte 6492>
ulong portcorra Port Correlation As Longword
or portcorr[6] Port Correlation
<byte 6492>
{portcorr (Port Correlation By Field)}
<byte 6492>
utiny real_port Real hardware port number
<byte 6493>
utiny port_type Port type
<byte 6494>
ushort reserved Reserved
{}
endunion portcorr[6] Port Correlation
<byte 6496>
union portcorr[7] Port Correlation
<byte 6496>
ulong portcorra Port Correlation As Longword
or portcorr[7] Port Correlation
<byte 6496>
{portcorr (Port Correlation By Field)}
<byte 6496>
utiny real_port Real hardware port number
<byte 6497>
utiny port_type Port type
<byte 6498>
ushort reserved Reserved
{}
endunion portcorr[7] Port Correlation
<byte 6500>
union portcorr[8] Port Correlation
<byte 6500>
ulong portcorra Port Correlation As Longword
or portcorr[8] Port Correlation
<byte 6500>
{portcorr (Port Correlation By Field)}
<byte 6500>
utiny real_port Real hardware port number
<byte 6501>
utiny port_type Port type
<byte 6502>
ushort reserved Reserved
{}
endunion portcorr[8] Port Correlation
<byte 6504>
union portcorr[9] Port Correlation
<byte 6504>
ulong portcorra Port Correlation As Longword
or portcorr[9] Port Correlation
<byte 6504>
{portcorr (Port Correlation By Field)}
<byte 6504>
utiny real_port Real hardware port number
<byte 6505>
utiny port_type Port type
<byte 6506>
ushort reserved Reserved
{}
endunion portcorr[9] Port Correlation
<byte 6508>
union csr[0] Tachyon DX2+ CSR Registers
<byte 6508>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[0] Tachyon DX2+ CSR Registers
<byte 6508>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 6508>
union erq_base (Offset 000) ERQ Base (write only)
<byte 6508>
{field (By field)}
<byte 6508>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 6508>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 6512>
union erq_len (Offset 004) ERQ Length (write only)
<byte 6512>
{field (By field)}
<byte 6512>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 6512>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 6516>
union erq_prod (Offset 008) ERQ Producer Index
<byte 6516>
{field (By field)}
<byte 6516>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 6516>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 6520>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 6520>
{field (By field)}
<byte 6520>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 6520>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 6524>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 6524>
{field (By field)}
<byte 6524>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 6524>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 6528>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 6528>
ulong value
{}
<byte 6532>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 6532>
ulong value
{}
<byte 6536>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 6536>
ulong value
{}
<byte 6540>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 6540>
ulong value
{}
<byte 6544>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 6544>
ulong value
{}
<byte 6548>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 6548>
ulong value
{}
<byte 6552>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 6552>
ulong value
{}
<byte 6556>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 6556>
ulong value
{}
<byte 6560>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 6560>
ulong value
{}
<byte 6564>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 6564>
ulong value
{}
<byte 6568>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 6568>
ulong value
{}
<byte 6572>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 6572>
ulong value
{}
<byte 6576>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 6576>
ulong value
{}
<byte 6580>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 6580>
ulong value
{}
<byte 6584>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 6584>
ulong value
{}
<byte 6588>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 6588>
{field (By field)}
<byte 6588>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 6588>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 6592>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 6592>
{field (By field)}
<byte 6592>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 6592>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 6596>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 6596>
{field (By field)}
<byte 6596>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 6596>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 6600>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 6600>
ulong value
{}
<byte 6604>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 6604>
ulong value
{}
<byte 6608>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 6608>
ulong value
{}
<byte 6612>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 6612>
ulong value
{}
<byte 6616>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 6616>
ulong value
{}
<byte 6620>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 6620>
ulong value
{}
<byte 6624>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 6624>
ulong value
{}
<byte 6628>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 6628>
ulong value
{}
<byte 6632>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 6632>
{field (By field)}
<byte 6632>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 6632>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 6636>
union imq_base (Offset 080) IMQ Base (write only)
<byte 6636>
{field (By field)}
<byte 6636>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 6636>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 6640>
union imq_len (Offset 084) IMQ Length (write only)
<byte 6640>
{field (By field)}
<byte 6640>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 6640>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 6644>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 6644>
{field (By field)}
<byte 6644>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 6644>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 6648>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 6648>
{field (By field)}
<byte 6648>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 6648>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 6652>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 6652>
ulong value
{}
<byte 6656>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 6656>
ulong value
{}
<byte 6660>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 6660>
ulong value
{}
<byte 6664>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 6664>
ulong value
{}
<byte 6668>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 6668>
ulong value
{}
<byte 6672>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 6672>
ulong value
{}
<byte 6676>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 6676>
ulong value
{}
<byte 6680>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 6680>
ulong value
{}
<byte 6684>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 6684>
ulong value
{}
<byte 6688>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 6688>
ulong value
{}
<byte 6692>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 6692>
ulong value
{}
<byte 6696>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 6696>
ulong value
{}
<byte 6700>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 6700>
ulong value
{}
<byte 6704>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 6704>
ulong value
{}
<byte 6708>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 6708>
ulong value
{}
<byte 6712>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 6712>
ulong value
{}
<byte 6716>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 6716>
ulong value
{}
<byte 6720>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 6720>
ulong value
{}
<byte 6724>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 6724>
ulong value
{}
<byte 6728>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 6728>
ulong value
{}
<byte 6732>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 6732>
ulong value
{}
<byte 6736>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 6736>
ulong value
{}
<byte 6740>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 6740>
ulong value
{}
<byte 6744>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 6744>
ulong value
{}
<byte 6748>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 6748>
ulong value
{}
<byte 6752>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 6752>
ulong value
{}
<byte 6756>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 6756>
ulong value
{}
<byte 6760>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 6760>
ulong value
{}
<byte 6764>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 6764>
{field (By field)}
<byte 6764>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 6764>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 6768>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 6768>
{field (By field)}
<byte 6768>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 6768>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 6772>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 6772>
ulong value
{}
<byte 6776>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 6776>
ulong value
{}
<byte 6780>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 6780>
{field (No description available)}
<byte 6780>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 6780>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 6784>
union sfp_data (Offset 114) SFP data
<byte 6784>
{field (By field)}
<byte 6784>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 6784>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 6788>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 6788>
{field (By field)}
<byte 6788>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 6788>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 6792>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 6792>
{field (By field)}
<byte 6792>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 6792>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 6796>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 6796>
ulong value
{}
<byte 6800>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 6800>
ulong value
{}
<byte 6804>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 6804>
ulong value
{}
<byte 6808>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 6808>
ulong value
{}
<byte 6812>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 6812>
ulong value
{}
<byte 6816>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 6816>
ulong value
{}
<byte 6820>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 6820>
ulong value
{}
<byte 6824>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 6824>
ulong value
{}
<byte 6828>
union sest_base (Offset 140) SEST Base (write only)
<byte 6828>
{field (By field)}
<byte 6828>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 6828>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 6832>
union sest_len (Offset 144) SEST Length (write only)
<byte 6832>
{field (By field)}
<byte 6832>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 6832>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 6836>
{rsvd4 ((Offset 148) Reserved)}
<byte 6836>
ulong value
{}
<byte 6840>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 6840>
{field (By field)}
<byte 6840>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 6840>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 6844>
union prog_addr (Offset 150) Programmable Address register
<byte 6844>
{field (By field)}
<byte 6844>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 6844>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 6848>
union prog_data (Offset 154) programmable data register
<byte 6848>
{field (By field)}
<byte 6848>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 6848>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 6852>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 6852>
ulong value
{}
<byte 6856>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 6856>
ulong value
{}
<byte 6860>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 6860>
{field (By field)}
<byte 6860>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 6860>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 6864>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 6864>
{field (By field)}
<byte 6864>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 6864>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 6868>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 6868>
{field (By field)}
<byte 6868>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 6868>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 6872>
union my_id (Offset 16C) My ID
<byte 6872>
{field (By field)}
<byte 6872>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 6872>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 6876>
union gpio (Offset 170) General Purpose I/O
<byte 6876>
{field (By field)}
<byte 6876>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 6876>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 6880>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 6880>
ulong value
{}
<byte 6884>
union edc_config (Offset 178) EDC Configuration Register
<byte 6884>
{field (By field)}
<byte 6884>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 6884>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 6888>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 6888>
{field (By field)}
<byte 6888>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 6888>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 6892>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 6892>
{field (By field)}
<byte 6892>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 6892>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 6896>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 6896>
{field (By field)}
<byte 6896>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 6896>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 6900>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 6900>
{field (By field)}
<byte 6900>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 6900>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 6904>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 6904>
{field (By field)}
<byte 6904>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 6904>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 6908>
{rsvd7 ((Offset 190) Reserved)}
<byte 6908>
ulong value
{}
<byte 6912>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 6912>
{field (By field)}
<byte 6912>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 6912>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 6916>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 6916>
{field (By field)}
<byte 6916>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 6916>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 6920>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 6920>
{field (By field)}
<byte 6920>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 6920>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 6924>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 6924>
{field (By field)}
<byte 6924>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 6924>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 6928>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 6928>
{field (By field)}
<byte 6928>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 6928>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 6932>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 6932>
{field (By field)}
<byte 6932>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 6932>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 6936>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 6936>
{field (By field)}
<byte 6936>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 6936>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 6940>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 6940>
{field (By field)}
<byte 6940>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 6940>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 6944>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 6944>
{field (By field)}
<byte 6944>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 6944>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 6948>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 6948>
{field (By field)}
<byte 6948>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 6948>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 6952>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 6952>
{field (By field)}
<byte 6952>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 6952>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 6956>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 6956>
{field (By field)}
<byte 6956>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 6956>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 6960>
union fm_control (Offset 1C4) Frame Manager Control
<byte 6960>
{field (By field)}
<byte 6960>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 6960>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 6964>
union fm_status (Offset 1C8) Frame Manager Status
<byte 6964>
{field (By field)}
<byte 6964>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 6964>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 6968>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 6968>
{field (By field)}
<byte 6968>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 6968>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 6972>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 6972>
{field (By field)}
<byte 6972>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 6972>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 6976>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 6976>
{field (By field)}
<byte 6976>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 6976>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 6980>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 6980>
{field (By field)}
<byte 6980>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 6980>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 6984>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 6984>
{field (By field)}
<byte 6984>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 6984>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 6988>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 6988>
{field (By field)}
<byte 6988>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 6988>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 6992>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 6992>
{field (By field)}
<byte 6992>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 6992>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 6996>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 6996>
{field (By field)}
<byte 6996>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 6996>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 7000>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 7000>
{field (By field)}
<byte 7000>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 7000>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 7004>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 7004>
{field (By field)}
<byte 7004>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 7004>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 7008>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 7008>
{field (By field)}
<byte 7008>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 7008>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 7012>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 7012>
{field (By field)}
<byte 7012>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 7012>
utiny value
{}
<byte 7013>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 7013>
utiny value
{}
<byte 7014>
union romctr (Offset 1FA) PCI ROM Control
<byte 7014>
{field (By field)}
<byte 7014>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 7014>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 7015>
union mctr (Offset 1FB) PCI Master Control
<byte 7015>
{field (By field)}
<byte 7015>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 7015>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 7012>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 7016>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 7016>
{field (By field)}
<byte 7016>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 7016>
{field (By field)}
<byte 7016>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 7016>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 7017>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 7017>
{field (By field)}
<byte 7017>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 7017>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 7018>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 7018>
{field (By field)}
<byte 7018>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 7018>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 7019>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 7019>
{field (By field)}
<byte 7019>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 7019>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 7016>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[0] Tachyon DX2+ CSR Registers
<byte 7020>
union csr[1] Tachyon DX2+ CSR Registers
<byte 7020>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[1] Tachyon DX2+ CSR Registers
<byte 7020>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 7020>
union erq_base (Offset 000) ERQ Base (write only)
<byte 7020>
{field (By field)}
<byte 7020>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 7020>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 7024>
union erq_len (Offset 004) ERQ Length (write only)
<byte 7024>
{field (By field)}
<byte 7024>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 7024>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 7028>
union erq_prod (Offset 008) ERQ Producer Index
<byte 7028>
{field (By field)}
<byte 7028>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 7028>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 7032>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 7032>
{field (By field)}
<byte 7032>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 7032>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 7036>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 7036>
{field (By field)}
<byte 7036>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 7036>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 7040>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 7040>
ulong value
{}
<byte 7044>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 7044>
ulong value
{}
<byte 7048>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 7048>
ulong value
{}
<byte 7052>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 7052>
ulong value
{}
<byte 7056>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 7056>
ulong value
{}
<byte 7060>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 7060>
ulong value
{}
<byte 7064>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 7064>
ulong value
{}
<byte 7068>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 7068>
ulong value
{}
<byte 7072>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 7072>
ulong value
{}
<byte 7076>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 7076>
ulong value
{}
<byte 7080>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 7080>
ulong value
{}
<byte 7084>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 7084>
ulong value
{}
<byte 7088>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 7088>
ulong value
{}
<byte 7092>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 7092>
ulong value
{}
<byte 7096>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 7096>
ulong value
{}
<byte 7100>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 7100>
{field (By field)}
<byte 7100>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 7100>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 7104>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 7104>
{field (By field)}
<byte 7104>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 7104>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 7108>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 7108>
{field (By field)}
<byte 7108>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 7108>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 7112>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 7112>
ulong value
{}
<byte 7116>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 7116>
ulong value
{}
<byte 7120>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 7120>
ulong value
{}
<byte 7124>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 7124>
ulong value
{}
<byte 7128>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 7128>
ulong value
{}
<byte 7132>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 7132>
ulong value
{}
<byte 7136>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 7136>
ulong value
{}
<byte 7140>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 7140>
ulong value
{}
<byte 7144>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 7144>
{field (By field)}
<byte 7144>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 7144>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 7148>
union imq_base (Offset 080) IMQ Base (write only)
<byte 7148>
{field (By field)}
<byte 7148>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 7148>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 7152>
union imq_len (Offset 084) IMQ Length (write only)
<byte 7152>
{field (By field)}
<byte 7152>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 7152>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 7156>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 7156>
{field (By field)}
<byte 7156>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 7156>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 7160>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 7160>
{field (By field)}
<byte 7160>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 7160>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 7164>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 7164>
ulong value
{}
<byte 7168>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 7168>
ulong value
{}
<byte 7172>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 7172>
ulong value
{}
<byte 7176>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 7176>
ulong value
{}
<byte 7180>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 7180>
ulong value
{}
<byte 7184>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 7184>
ulong value
{}
<byte 7188>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 7188>
ulong value
{}
<byte 7192>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 7192>
ulong value
{}
<byte 7196>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 7196>
ulong value
{}
<byte 7200>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 7200>
ulong value
{}
<byte 7204>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 7204>
ulong value
{}
<byte 7208>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 7208>
ulong value
{}
<byte 7212>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 7212>
ulong value
{}
<byte 7216>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 7216>
ulong value
{}
<byte 7220>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 7220>
ulong value
{}
<byte 7224>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 7224>
ulong value
{}
<byte 7228>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 7228>
ulong value
{}
<byte 7232>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 7232>
ulong value
{}
<byte 7236>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 7236>
ulong value
{}
<byte 7240>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 7240>
ulong value
{}
<byte 7244>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 7244>
ulong value
{}
<byte 7248>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 7248>
ulong value
{}
<byte 7252>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 7252>
ulong value
{}
<byte 7256>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 7256>
ulong value
{}
<byte 7260>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 7260>
ulong value
{}
<byte 7264>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 7264>
ulong value
{}
<byte 7268>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 7268>
ulong value
{}
<byte 7272>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 7272>
ulong value
{}
<byte 7276>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 7276>
{field (By field)}
<byte 7276>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 7276>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 7280>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 7280>
{field (By field)}
<byte 7280>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 7280>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 7284>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 7284>
ulong value
{}
<byte 7288>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 7288>
ulong value
{}
<byte 7292>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 7292>
{field (No description available)}
<byte 7292>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 7292>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 7296>
union sfp_data (Offset 114) SFP data
<byte 7296>
{field (By field)}
<byte 7296>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 7296>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 7300>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 7300>
{field (By field)}
<byte 7300>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 7300>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 7304>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 7304>
{field (By field)}
<byte 7304>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 7304>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 7308>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 7308>
ulong value
{}
<byte 7312>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 7312>
ulong value
{}
<byte 7316>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 7316>
ulong value
{}
<byte 7320>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 7320>
ulong value
{}
<byte 7324>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 7324>
ulong value
{}
<byte 7328>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 7328>
ulong value
{}
<byte 7332>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 7332>
ulong value
{}
<byte 7336>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 7336>
ulong value
{}
<byte 7340>
union sest_base (Offset 140) SEST Base (write only)
<byte 7340>
{field (By field)}
<byte 7340>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 7340>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 7344>
union sest_len (Offset 144) SEST Length (write only)
<byte 7344>
{field (By field)}
<byte 7344>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 7344>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 7348>
{rsvd4 ((Offset 148) Reserved)}
<byte 7348>
ulong value
{}
<byte 7352>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 7352>
{field (By field)}
<byte 7352>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 7352>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 7356>
union prog_addr (Offset 150) Programmable Address register
<byte 7356>
{field (By field)}
<byte 7356>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 7356>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 7360>
union prog_data (Offset 154) programmable data register
<byte 7360>
{field (By field)}
<byte 7360>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 7360>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 7364>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 7364>
ulong value
{}
<byte 7368>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 7368>
ulong value
{}
<byte 7372>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 7372>
{field (By field)}
<byte 7372>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 7372>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 7376>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 7376>
{field (By field)}
<byte 7376>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 7376>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 7380>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 7380>
{field (By field)}
<byte 7380>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 7380>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 7384>
union my_id (Offset 16C) My ID
<byte 7384>
{field (By field)}
<byte 7384>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 7384>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 7388>
union gpio (Offset 170) General Purpose I/O
<byte 7388>
{field (By field)}
<byte 7388>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 7388>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 7392>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 7392>
ulong value
{}
<byte 7396>
union edc_config (Offset 178) EDC Configuration Register
<byte 7396>
{field (By field)}
<byte 7396>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 7396>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 7400>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 7400>
{field (By field)}
<byte 7400>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 7400>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 7404>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 7404>
{field (By field)}
<byte 7404>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 7404>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 7408>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 7408>
{field (By field)}
<byte 7408>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 7408>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 7412>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 7412>
{field (By field)}
<byte 7412>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 7412>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 7416>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 7416>
{field (By field)}
<byte 7416>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 7416>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 7420>
{rsvd7 ((Offset 190) Reserved)}
<byte 7420>
ulong value
{}
<byte 7424>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 7424>
{field (By field)}
<byte 7424>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 7424>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 7428>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 7428>
{field (By field)}
<byte 7428>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 7428>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 7432>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 7432>
{field (By field)}
<byte 7432>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 7432>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 7436>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 7436>
{field (By field)}
<byte 7436>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 7436>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 7440>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 7440>
{field (By field)}
<byte 7440>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 7440>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 7444>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 7444>
{field (By field)}
<byte 7444>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 7444>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 7448>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 7448>
{field (By field)}
<byte 7448>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 7448>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 7452>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 7452>
{field (By field)}
<byte 7452>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 7452>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 7456>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 7456>
{field (By field)}
<byte 7456>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 7456>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 7460>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 7460>
{field (By field)}
<byte 7460>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 7460>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 7464>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 7464>
{field (By field)}
<byte 7464>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 7464>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 7468>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 7468>
{field (By field)}
<byte 7468>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 7468>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 7472>
union fm_control (Offset 1C4) Frame Manager Control
<byte 7472>
{field (By field)}
<byte 7472>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 7472>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 7476>
union fm_status (Offset 1C8) Frame Manager Status
<byte 7476>
{field (By field)}
<byte 7476>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 7476>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 7480>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 7480>
{field (By field)}
<byte 7480>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 7480>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 7484>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 7484>
{field (By field)}
<byte 7484>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 7484>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 7488>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 7488>
{field (By field)}
<byte 7488>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 7488>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 7492>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 7492>
{field (By field)}
<byte 7492>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 7492>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 7496>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 7496>
{field (By field)}
<byte 7496>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 7496>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 7500>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 7500>
{field (By field)}
<byte 7500>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 7500>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 7504>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 7504>
{field (By field)}
<byte 7504>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 7504>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 7508>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 7508>
{field (By field)}
<byte 7508>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 7508>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 7512>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 7512>
{field (By field)}
<byte 7512>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 7512>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 7516>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 7516>
{field (By field)}
<byte 7516>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 7516>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 7520>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 7520>
{field (By field)}
<byte 7520>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 7520>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 7524>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 7524>
{field (By field)}
<byte 7524>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 7524>
utiny value
{}
<byte 7525>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 7525>
utiny value
{}
<byte 7526>
union romctr (Offset 1FA) PCI ROM Control
<byte 7526>
{field (By field)}
<byte 7526>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 7526>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 7527>
union mctr (Offset 1FB) PCI Master Control
<byte 7527>
{field (By field)}
<byte 7527>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 7527>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 7524>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 7528>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 7528>
{field (By field)}
<byte 7528>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 7528>
{field (By field)}
<byte 7528>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 7528>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 7529>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 7529>
{field (By field)}
<byte 7529>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 7529>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 7530>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 7530>
{field (By field)}
<byte 7530>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 7530>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 7531>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 7531>
{field (By field)}
<byte 7531>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 7531>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 7528>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[1] Tachyon DX2+ CSR Registers
<byte 7532>
union csr[2] Tachyon DX2+ CSR Registers
<byte 7532>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[2] Tachyon DX2+ CSR Registers
<byte 7532>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 7532>
union erq_base (Offset 000) ERQ Base (write only)
<byte 7532>
{field (By field)}
<byte 7532>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 7532>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 7536>
union erq_len (Offset 004) ERQ Length (write only)
<byte 7536>
{field (By field)}
<byte 7536>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 7536>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 7540>
union erq_prod (Offset 008) ERQ Producer Index
<byte 7540>
{field (By field)}
<byte 7540>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 7540>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 7544>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 7544>
{field (By field)}
<byte 7544>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 7544>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 7548>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 7548>
{field (By field)}
<byte 7548>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 7548>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 7552>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 7552>
ulong value
{}
<byte 7556>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 7556>
ulong value
{}
<byte 7560>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 7560>
ulong value
{}
<byte 7564>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 7564>
ulong value
{}
<byte 7568>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 7568>
ulong value
{}
<byte 7572>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 7572>
ulong value
{}
<byte 7576>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 7576>
ulong value
{}
<byte 7580>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 7580>
ulong value
{}
<byte 7584>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 7584>
ulong value
{}
<byte 7588>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 7588>
ulong value
{}
<byte 7592>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 7592>
ulong value
{}
<byte 7596>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 7596>
ulong value
{}
<byte 7600>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 7600>
ulong value
{}
<byte 7604>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 7604>
ulong value
{}
<byte 7608>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 7608>
ulong value
{}
<byte 7612>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 7612>
{field (By field)}
<byte 7612>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 7612>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 7616>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 7616>
{field (By field)}
<byte 7616>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 7616>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 7620>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 7620>
{field (By field)}
<byte 7620>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 7620>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 7624>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 7624>
ulong value
{}
<byte 7628>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 7628>
ulong value
{}
<byte 7632>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 7632>
ulong value
{}
<byte 7636>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 7636>
ulong value
{}
<byte 7640>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 7640>
ulong value
{}
<byte 7644>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 7644>
ulong value
{}
<byte 7648>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 7648>
ulong value
{}
<byte 7652>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 7652>
ulong value
{}
<byte 7656>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 7656>
{field (By field)}
<byte 7656>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 7656>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 7660>
union imq_base (Offset 080) IMQ Base (write only)
<byte 7660>
{field (By field)}
<byte 7660>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 7660>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 7664>
union imq_len (Offset 084) IMQ Length (write only)
<byte 7664>
{field (By field)}
<byte 7664>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 7664>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 7668>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 7668>
{field (By field)}
<byte 7668>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 7668>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 7672>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 7672>
{field (By field)}
<byte 7672>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 7672>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 7676>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 7676>
ulong value
{}
<byte 7680>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 7680>
ulong value
{}
<byte 7684>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 7684>
ulong value
{}
<byte 7688>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 7688>
ulong value
{}
<byte 7692>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 7692>
ulong value
{}
<byte 7696>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 7696>
ulong value
{}
<byte 7700>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 7700>
ulong value
{}
<byte 7704>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 7704>
ulong value
{}
<byte 7708>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 7708>
ulong value
{}
<byte 7712>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 7712>
ulong value
{}
<byte 7716>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 7716>
ulong value
{}
<byte 7720>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 7720>
ulong value
{}
<byte 7724>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 7724>
ulong value
{}
<byte 7728>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 7728>
ulong value
{}
<byte 7732>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 7732>
ulong value
{}
<byte 7736>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 7736>
ulong value
{}
<byte 7740>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 7740>
ulong value
{}
<byte 7744>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 7744>
ulong value
{}
<byte 7748>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 7748>
ulong value
{}
<byte 7752>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 7752>
ulong value
{}
<byte 7756>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 7756>
ulong value
{}
<byte 7760>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 7760>
ulong value
{}
<byte 7764>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 7764>
ulong value
{}
<byte 7768>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 7768>
ulong value
{}
<byte 7772>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 7772>
ulong value
{}
<byte 7776>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 7776>
ulong value
{}
<byte 7780>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 7780>
ulong value
{}
<byte 7784>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 7784>
ulong value
{}
<byte 7788>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 7788>
{field (By field)}
<byte 7788>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 7788>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 7792>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 7792>
{field (By field)}
<byte 7792>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 7792>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 7796>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 7796>
ulong value
{}
<byte 7800>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 7800>
ulong value
{}
<byte 7804>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 7804>
{field (No description available)}
<byte 7804>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 7804>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 7808>
union sfp_data (Offset 114) SFP data
<byte 7808>
{field (By field)}
<byte 7808>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 7808>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 7812>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 7812>
{field (By field)}
<byte 7812>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 7812>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 7816>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 7816>
{field (By field)}
<byte 7816>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 7816>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 7820>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 7820>
ulong value
{}
<byte 7824>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 7824>
ulong value
{}
<byte 7828>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 7828>
ulong value
{}
<byte 7832>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 7832>
ulong value
{}
<byte 7836>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 7836>
ulong value
{}
<byte 7840>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 7840>
ulong value
{}
<byte 7844>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 7844>
ulong value
{}
<byte 7848>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 7848>
ulong value
{}
<byte 7852>
union sest_base (Offset 140) SEST Base (write only)
<byte 7852>
{field (By field)}
<byte 7852>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 7852>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 7856>
union sest_len (Offset 144) SEST Length (write only)
<byte 7856>
{field (By field)}
<byte 7856>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 7856>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 7860>
{rsvd4 ((Offset 148) Reserved)}
<byte 7860>
ulong value
{}
<byte 7864>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 7864>
{field (By field)}
<byte 7864>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 7864>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 7868>
union prog_addr (Offset 150) Programmable Address register
<byte 7868>
{field (By field)}
<byte 7868>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 7868>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 7872>
union prog_data (Offset 154) programmable data register
<byte 7872>
{field (By field)}
<byte 7872>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 7872>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 7876>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 7876>
ulong value
{}
<byte 7880>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 7880>
ulong value
{}
<byte 7884>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 7884>
{field (By field)}
<byte 7884>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 7884>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 7888>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 7888>
{field (By field)}
<byte 7888>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 7888>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 7892>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 7892>
{field (By field)}
<byte 7892>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 7892>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 7896>
union my_id (Offset 16C) My ID
<byte 7896>
{field (By field)}
<byte 7896>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 7896>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 7900>
union gpio (Offset 170) General Purpose I/O
<byte 7900>
{field (By field)}
<byte 7900>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 7900>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 7904>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 7904>
ulong value
{}
<byte 7908>
union edc_config (Offset 178) EDC Configuration Register
<byte 7908>
{field (By field)}
<byte 7908>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 7908>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 7912>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 7912>
{field (By field)}
<byte 7912>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 7912>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 7916>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 7916>
{field (By field)}
<byte 7916>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 7916>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 7920>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 7920>
{field (By field)}
<byte 7920>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 7920>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 7924>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 7924>
{field (By field)}
<byte 7924>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 7924>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 7928>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 7928>
{field (By field)}
<byte 7928>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 7928>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 7932>
{rsvd7 ((Offset 190) Reserved)}
<byte 7932>
ulong value
{}
<byte 7936>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 7936>
{field (By field)}
<byte 7936>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 7936>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 7940>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 7940>
{field (By field)}
<byte 7940>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 7940>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 7944>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 7944>
{field (By field)}
<byte 7944>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 7944>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 7948>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 7948>
{field (By field)}
<byte 7948>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 7948>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 7952>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 7952>
{field (By field)}
<byte 7952>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 7952>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 7956>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 7956>
{field (By field)}
<byte 7956>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 7956>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 7960>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 7960>
{field (By field)}
<byte 7960>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 7960>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 7964>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 7964>
{field (By field)}
<byte 7964>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 7964>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 7968>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 7968>
{field (By field)}
<byte 7968>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 7968>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 7972>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 7972>
{field (By field)}
<byte 7972>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 7972>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 7976>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 7976>
{field (By field)}
<byte 7976>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 7976>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 7980>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 7980>
{field (By field)}
<byte 7980>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 7980>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 7984>
union fm_control (Offset 1C4) Frame Manager Control
<byte 7984>
{field (By field)}
<byte 7984>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 7984>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 7988>
union fm_status (Offset 1C8) Frame Manager Status
<byte 7988>
{field (By field)}
<byte 7988>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 7988>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 7992>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 7992>
{field (By field)}
<byte 7992>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 7992>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 7996>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 7996>
{field (By field)}
<byte 7996>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 7996>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 8000>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 8000>
{field (By field)}
<byte 8000>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 8000>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 8004>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 8004>
{field (By field)}
<byte 8004>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 8004>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 8008>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 8008>
{field (By field)}
<byte 8008>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 8008>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 8012>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 8012>
{field (By field)}
<byte 8012>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 8012>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 8016>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 8016>
{field (By field)}
<byte 8016>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 8016>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 8020>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 8020>
{field (By field)}
<byte 8020>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 8020>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 8024>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 8024>
{field (By field)}
<byte 8024>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 8024>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 8028>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 8028>
{field (By field)}
<byte 8028>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 8028>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 8032>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 8032>
{field (By field)}
<byte 8032>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 8032>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 8036>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 8036>
{field (By field)}
<byte 8036>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 8036>
utiny value
{}
<byte 8037>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 8037>
utiny value
{}
<byte 8038>
union romctr (Offset 1FA) PCI ROM Control
<byte 8038>
{field (By field)}
<byte 8038>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 8038>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 8039>
union mctr (Offset 1FB) PCI Master Control
<byte 8039>
{field (By field)}
<byte 8039>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 8039>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 8036>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 8040>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 8040>
{field (By field)}
<byte 8040>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 8040>
{field (By field)}
<byte 8040>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 8040>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 8041>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 8041>
{field (By field)}
<byte 8041>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 8041>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 8042>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 8042>
{field (By field)}
<byte 8042>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 8042>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 8043>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 8043>
{field (By field)}
<byte 8043>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 8043>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 8040>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[2] Tachyon DX2+ CSR Registers
<byte 8044>
union csr[3] Tachyon DX2+ CSR Registers
<byte 8044>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[3] Tachyon DX2+ CSR Registers
<byte 8044>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 8044>
union erq_base (Offset 000) ERQ Base (write only)
<byte 8044>
{field (By field)}
<byte 8044>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 8044>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 8048>
union erq_len (Offset 004) ERQ Length (write only)
<byte 8048>
{field (By field)}
<byte 8048>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 8048>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 8052>
union erq_prod (Offset 008) ERQ Producer Index
<byte 8052>
{field (By field)}
<byte 8052>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 8052>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 8056>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 8056>
{field (By field)}
<byte 8056>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 8056>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 8060>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 8060>
{field (By field)}
<byte 8060>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 8060>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 8064>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 8064>
ulong value
{}
<byte 8068>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 8068>
ulong value
{}
<byte 8072>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 8072>
ulong value
{}
<byte 8076>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 8076>
ulong value
{}
<byte 8080>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 8080>
ulong value
{}
<byte 8084>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 8084>
ulong value
{}
<byte 8088>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 8088>
ulong value
{}
<byte 8092>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 8092>
ulong value
{}
<byte 8096>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 8096>
ulong value
{}
<byte 8100>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 8100>
ulong value
{}
<byte 8104>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 8104>
ulong value
{}
<byte 8108>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 8108>
ulong value
{}
<byte 8112>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 8112>
ulong value
{}
<byte 8116>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 8116>
ulong value
{}
<byte 8120>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 8120>
ulong value
{}
<byte 8124>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 8124>
{field (By field)}
<byte 8124>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 8124>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 8128>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 8128>
{field (By field)}
<byte 8128>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 8128>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 8132>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 8132>
{field (By field)}
<byte 8132>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 8132>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 8136>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 8136>
ulong value
{}
<byte 8140>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 8140>
ulong value
{}
<byte 8144>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 8144>
ulong value
{}
<byte 8148>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 8148>
ulong value
{}
<byte 8152>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 8152>
ulong value
{}
<byte 8156>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 8156>
ulong value
{}
<byte 8160>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 8160>
ulong value
{}
<byte 8164>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 8164>
ulong value
{}
<byte 8168>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 8168>
{field (By field)}
<byte 8168>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 8168>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 8172>
union imq_base (Offset 080) IMQ Base (write only)
<byte 8172>
{field (By field)}
<byte 8172>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 8172>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 8176>
union imq_len (Offset 084) IMQ Length (write only)
<byte 8176>
{field (By field)}
<byte 8176>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 8176>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 8180>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 8180>
{field (By field)}
<byte 8180>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 8180>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 8184>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 8184>
{field (By field)}
<byte 8184>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 8184>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 8188>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 8188>
ulong value
{}
<byte 8192>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 8192>
ulong value
{}
<byte 8196>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 8196>
ulong value
{}
<byte 8200>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 8200>
ulong value
{}
<byte 8204>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 8204>
ulong value
{}
<byte 8208>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 8208>
ulong value
{}
<byte 8212>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 8212>
ulong value
{}
<byte 8216>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 8216>
ulong value
{}
<byte 8220>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 8220>
ulong value
{}
<byte 8224>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 8224>
ulong value
{}
<byte 8228>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 8228>
ulong value
{}
<byte 8232>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 8232>
ulong value
{}
<byte 8236>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 8236>
ulong value
{}
<byte 8240>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 8240>
ulong value
{}
<byte 8244>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 8244>
ulong value
{}
<byte 8248>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 8248>
ulong value
{}
<byte 8252>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 8252>
ulong value
{}
<byte 8256>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 8256>
ulong value
{}
<byte 8260>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 8260>
ulong value
{}
<byte 8264>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 8264>
ulong value
{}
<byte 8268>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 8268>
ulong value
{}
<byte 8272>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 8272>
ulong value
{}
<byte 8276>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 8276>
ulong value
{}
<byte 8280>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 8280>
ulong value
{}
<byte 8284>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 8284>
ulong value
{}
<byte 8288>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 8288>
ulong value
{}
<byte 8292>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 8292>
ulong value
{}
<byte 8296>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 8296>
ulong value
{}
<byte 8300>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 8300>
{field (By field)}
<byte 8300>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 8300>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 8304>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 8304>
{field (By field)}
<byte 8304>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 8304>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 8308>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 8308>
ulong value
{}
<byte 8312>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 8312>
ulong value
{}
<byte 8316>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 8316>
{field (No description available)}
<byte 8316>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 8316>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 8320>
union sfp_data (Offset 114) SFP data
<byte 8320>
{field (By field)}
<byte 8320>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 8320>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 8324>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 8324>
{field (By field)}
<byte 8324>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 8324>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 8328>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 8328>
{field (By field)}
<byte 8328>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 8328>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 8332>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 8332>
ulong value
{}
<byte 8336>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 8336>
ulong value
{}
<byte 8340>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 8340>
ulong value
{}
<byte 8344>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 8344>
ulong value
{}
<byte 8348>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 8348>
ulong value
{}
<byte 8352>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 8352>
ulong value
{}
<byte 8356>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 8356>
ulong value
{}
<byte 8360>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 8360>
ulong value
{}
<byte 8364>
union sest_base (Offset 140) SEST Base (write only)
<byte 8364>
{field (By field)}
<byte 8364>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 8364>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 8368>
union sest_len (Offset 144) SEST Length (write only)
<byte 8368>
{field (By field)}
<byte 8368>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 8368>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 8372>
{rsvd4 ((Offset 148) Reserved)}
<byte 8372>
ulong value
{}
<byte 8376>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 8376>
{field (By field)}
<byte 8376>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 8376>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 8380>
union prog_addr (Offset 150) Programmable Address register
<byte 8380>
{field (By field)}
<byte 8380>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 8380>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 8384>
union prog_data (Offset 154) programmable data register
<byte 8384>
{field (By field)}
<byte 8384>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 8384>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 8388>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 8388>
ulong value
{}
<byte 8392>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 8392>
ulong value
{}
<byte 8396>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 8396>
{field (By field)}
<byte 8396>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 8396>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 8400>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 8400>
{field (By field)}
<byte 8400>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 8400>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 8404>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 8404>
{field (By field)}
<byte 8404>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 8404>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 8408>
union my_id (Offset 16C) My ID
<byte 8408>
{field (By field)}
<byte 8408>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 8408>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 8412>
union gpio (Offset 170) General Purpose I/O
<byte 8412>
{field (By field)}
<byte 8412>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 8412>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 8416>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 8416>
ulong value
{}
<byte 8420>
union edc_config (Offset 178) EDC Configuration Register
<byte 8420>
{field (By field)}
<byte 8420>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 8420>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 8424>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 8424>
{field (By field)}
<byte 8424>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 8424>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 8428>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 8428>
{field (By field)}
<byte 8428>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 8428>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 8432>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 8432>
{field (By field)}
<byte 8432>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 8432>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 8436>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 8436>
{field (By field)}
<byte 8436>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 8436>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 8440>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 8440>
{field (By field)}
<byte 8440>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 8440>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 8444>
{rsvd7 ((Offset 190) Reserved)}
<byte 8444>
ulong value
{}
<byte 8448>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 8448>
{field (By field)}
<byte 8448>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 8448>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 8452>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 8452>
{field (By field)}
<byte 8452>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 8452>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 8456>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 8456>
{field (By field)}
<byte 8456>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 8456>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 8460>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 8460>
{field (By field)}
<byte 8460>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 8460>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 8464>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 8464>
{field (By field)}
<byte 8464>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 8464>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 8468>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 8468>
{field (By field)}
<byte 8468>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 8468>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 8472>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 8472>
{field (By field)}
<byte 8472>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 8472>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 8476>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 8476>
{field (By field)}
<byte 8476>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 8476>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 8480>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 8480>
{field (By field)}
<byte 8480>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 8480>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 8484>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 8484>
{field (By field)}
<byte 8484>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 8484>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 8488>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 8488>
{field (By field)}
<byte 8488>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 8488>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 8492>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 8492>
{field (By field)}
<byte 8492>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 8492>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 8496>
union fm_control (Offset 1C4) Frame Manager Control
<byte 8496>
{field (By field)}
<byte 8496>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 8496>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 8500>
union fm_status (Offset 1C8) Frame Manager Status
<byte 8500>
{field (By field)}
<byte 8500>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 8500>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 8504>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 8504>
{field (By field)}
<byte 8504>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 8504>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 8508>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 8508>
{field (By field)}
<byte 8508>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 8508>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 8512>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 8512>
{field (By field)}
<byte 8512>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 8512>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 8516>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 8516>
{field (By field)}
<byte 8516>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 8516>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 8520>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 8520>
{field (By field)}
<byte 8520>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 8520>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 8524>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 8524>
{field (By field)}
<byte 8524>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 8524>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 8528>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 8528>
{field (By field)}
<byte 8528>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 8528>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 8532>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 8532>
{field (By field)}
<byte 8532>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 8532>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 8536>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 8536>
{field (By field)}
<byte 8536>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 8536>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 8540>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 8540>
{field (By field)}
<byte 8540>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 8540>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 8544>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 8544>
{field (By field)}
<byte 8544>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 8544>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 8548>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 8548>
{field (By field)}
<byte 8548>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 8548>
utiny value
{}
<byte 8549>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 8549>
utiny value
{}
<byte 8550>
union romctr (Offset 1FA) PCI ROM Control
<byte 8550>
{field (By field)}
<byte 8550>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 8550>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 8551>
union mctr (Offset 1FB) PCI Master Control
<byte 8551>
{field (By field)}
<byte 8551>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 8551>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 8548>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 8552>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 8552>
{field (By field)}
<byte 8552>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 8552>
{field (By field)}
<byte 8552>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 8552>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 8553>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 8553>
{field (By field)}
<byte 8553>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 8553>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 8554>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 8554>
{field (By field)}
<byte 8554>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 8554>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 8555>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 8555>
{field (By field)}
<byte 8555>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 8555>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 8552>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[3] Tachyon DX2+ CSR Registers
<byte 8556>
union csr[4] Tachyon DX2+ CSR Registers
<byte 8556>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[4] Tachyon DX2+ CSR Registers
<byte 8556>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 8556>
union erq_base (Offset 000) ERQ Base (write only)
<byte 8556>
{field (By field)}
<byte 8556>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 8556>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 8560>
union erq_len (Offset 004) ERQ Length (write only)
<byte 8560>
{field (By field)}
<byte 8560>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 8560>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 8564>
union erq_prod (Offset 008) ERQ Producer Index
<byte 8564>
{field (By field)}
<byte 8564>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 8564>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 8568>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 8568>
{field (By field)}
<byte 8568>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 8568>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 8572>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 8572>
{field (By field)}
<byte 8572>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 8572>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 8576>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 8576>
ulong value
{}
<byte 8580>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 8580>
ulong value
{}
<byte 8584>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 8584>
ulong value
{}
<byte 8588>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 8588>
ulong value
{}
<byte 8592>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 8592>
ulong value
{}
<byte 8596>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 8596>
ulong value
{}
<byte 8600>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 8600>
ulong value
{}
<byte 8604>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 8604>
ulong value
{}
<byte 8608>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 8608>
ulong value
{}
<byte 8612>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 8612>
ulong value
{}
<byte 8616>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 8616>
ulong value
{}
<byte 8620>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 8620>
ulong value
{}
<byte 8624>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 8624>
ulong value
{}
<byte 8628>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 8628>
ulong value
{}
<byte 8632>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 8632>
ulong value
{}
<byte 8636>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 8636>
{field (By field)}
<byte 8636>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 8636>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 8640>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 8640>
{field (By field)}
<byte 8640>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 8640>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 8644>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 8644>
{field (By field)}
<byte 8644>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 8644>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 8648>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 8648>
ulong value
{}
<byte 8652>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 8652>
ulong value
{}
<byte 8656>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 8656>
ulong value
{}
<byte 8660>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 8660>
ulong value
{}
<byte 8664>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 8664>
ulong value
{}
<byte 8668>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 8668>
ulong value
{}
<byte 8672>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 8672>
ulong value
{}
<byte 8676>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 8676>
ulong value
{}
<byte 8680>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 8680>
{field (By field)}
<byte 8680>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 8680>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 8684>
union imq_base (Offset 080) IMQ Base (write only)
<byte 8684>
{field (By field)}
<byte 8684>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 8684>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 8688>
union imq_len (Offset 084) IMQ Length (write only)
<byte 8688>
{field (By field)}
<byte 8688>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 8688>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 8692>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 8692>
{field (By field)}
<byte 8692>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 8692>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 8696>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 8696>
{field (By field)}
<byte 8696>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 8696>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 8700>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 8700>
ulong value
{}
<byte 8704>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 8704>
ulong value
{}
<byte 8708>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 8708>
ulong value
{}
<byte 8712>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 8712>
ulong value
{}
<byte 8716>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 8716>
ulong value
{}
<byte 8720>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 8720>
ulong value
{}
<byte 8724>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 8724>
ulong value
{}
<byte 8728>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 8728>
ulong value
{}
<byte 8732>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 8732>
ulong value
{}
<byte 8736>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 8736>
ulong value
{}
<byte 8740>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 8740>
ulong value
{}
<byte 8744>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 8744>
ulong value
{}
<byte 8748>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 8748>
ulong value
{}
<byte 8752>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 8752>
ulong value
{}
<byte 8756>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 8756>
ulong value
{}
<byte 8760>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 8760>
ulong value
{}
<byte 8764>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 8764>
ulong value
{}
<byte 8768>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 8768>
ulong value
{}
<byte 8772>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 8772>
ulong value
{}
<byte 8776>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 8776>
ulong value
{}
<byte 8780>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 8780>
ulong value
{}
<byte 8784>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 8784>
ulong value
{}
<byte 8788>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 8788>
ulong value
{}
<byte 8792>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 8792>
ulong value
{}
<byte 8796>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 8796>
ulong value
{}
<byte 8800>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 8800>
ulong value
{}
<byte 8804>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 8804>
ulong value
{}
<byte 8808>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 8808>
ulong value
{}
<byte 8812>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 8812>
{field (By field)}
<byte 8812>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 8812>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 8816>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 8816>
{field (By field)}
<byte 8816>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 8816>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 8820>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 8820>
ulong value
{}
<byte 8824>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 8824>
ulong value
{}
<byte 8828>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 8828>
{field (No description available)}
<byte 8828>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 8828>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 8832>
union sfp_data (Offset 114) SFP data
<byte 8832>
{field (By field)}
<byte 8832>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 8832>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 8836>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 8836>
{field (By field)}
<byte 8836>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 8836>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 8840>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 8840>
{field (By field)}
<byte 8840>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 8840>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 8844>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 8844>
ulong value
{}
<byte 8848>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 8848>
ulong value
{}
<byte 8852>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 8852>
ulong value
{}
<byte 8856>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 8856>
ulong value
{}
<byte 8860>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 8860>
ulong value
{}
<byte 8864>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 8864>
ulong value
{}
<byte 8868>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 8868>
ulong value
{}
<byte 8872>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 8872>
ulong value
{}
<byte 8876>
union sest_base (Offset 140) SEST Base (write only)
<byte 8876>
{field (By field)}
<byte 8876>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 8876>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 8880>
union sest_len (Offset 144) SEST Length (write only)
<byte 8880>
{field (By field)}
<byte 8880>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 8880>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 8884>
{rsvd4 ((Offset 148) Reserved)}
<byte 8884>
ulong value
{}
<byte 8888>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 8888>
{field (By field)}
<byte 8888>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 8888>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 8892>
union prog_addr (Offset 150) Programmable Address register
<byte 8892>
{field (By field)}
<byte 8892>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 8892>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 8896>
union prog_data (Offset 154) programmable data register
<byte 8896>
{field (By field)}
<byte 8896>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 8896>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 8900>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 8900>
ulong value
{}
<byte 8904>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 8904>
ulong value
{}
<byte 8908>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 8908>
{field (By field)}
<byte 8908>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 8908>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 8912>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 8912>
{field (By field)}
<byte 8912>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 8912>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 8916>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 8916>
{field (By field)}
<byte 8916>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 8916>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 8920>
union my_id (Offset 16C) My ID
<byte 8920>
{field (By field)}
<byte 8920>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 8920>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 8924>
union gpio (Offset 170) General Purpose I/O
<byte 8924>
{field (By field)}
<byte 8924>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 8924>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 8928>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 8928>
ulong value
{}
<byte 8932>
union edc_config (Offset 178) EDC Configuration Register
<byte 8932>
{field (By field)}
<byte 8932>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 8932>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 8936>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 8936>
{field (By field)}
<byte 8936>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 8936>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 8940>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 8940>
{field (By field)}
<byte 8940>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 8940>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 8944>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 8944>
{field (By field)}
<byte 8944>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 8944>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 8948>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 8948>
{field (By field)}
<byte 8948>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 8948>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 8952>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 8952>
{field (By field)}
<byte 8952>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 8952>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 8956>
{rsvd7 ((Offset 190) Reserved)}
<byte 8956>
ulong value
{}
<byte 8960>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 8960>
{field (By field)}
<byte 8960>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 8960>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 8964>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 8964>
{field (By field)}
<byte 8964>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 8964>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 8968>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 8968>
{field (By field)}
<byte 8968>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 8968>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 8972>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 8972>
{field (By field)}
<byte 8972>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 8972>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 8976>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 8976>
{field (By field)}
<byte 8976>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 8976>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 8980>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 8980>
{field (By field)}
<byte 8980>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 8980>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 8984>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 8984>
{field (By field)}
<byte 8984>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 8984>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 8988>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 8988>
{field (By field)}
<byte 8988>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 8988>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 8992>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 8992>
{field (By field)}
<byte 8992>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 8992>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 8996>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 8996>
{field (By field)}
<byte 8996>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 8996>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 9000>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 9000>
{field (By field)}
<byte 9000>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 9000>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 9004>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 9004>
{field (By field)}
<byte 9004>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 9004>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 9008>
union fm_control (Offset 1C4) Frame Manager Control
<byte 9008>
{field (By field)}
<byte 9008>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 9008>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 9012>
union fm_status (Offset 1C8) Frame Manager Status
<byte 9012>
{field (By field)}
<byte 9012>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 9012>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 9016>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 9016>
{field (By field)}
<byte 9016>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 9016>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 9020>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 9020>
{field (By field)}
<byte 9020>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 9020>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 9024>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 9024>
{field (By field)}
<byte 9024>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 9024>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 9028>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 9028>
{field (By field)}
<byte 9028>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 9028>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 9032>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 9032>
{field (By field)}
<byte 9032>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 9032>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 9036>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 9036>
{field (By field)}
<byte 9036>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 9036>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 9040>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 9040>
{field (By field)}
<byte 9040>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 9040>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 9044>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 9044>
{field (By field)}
<byte 9044>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 9044>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 9048>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 9048>
{field (By field)}
<byte 9048>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 9048>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 9052>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 9052>
{field (By field)}
<byte 9052>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 9052>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 9056>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 9056>
{field (By field)}
<byte 9056>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 9056>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 9060>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 9060>
{field (By field)}
<byte 9060>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 9060>
utiny value
{}
<byte 9061>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 9061>
utiny value
{}
<byte 9062>
union romctr (Offset 1FA) PCI ROM Control
<byte 9062>
{field (By field)}
<byte 9062>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 9062>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 9063>
union mctr (Offset 1FB) PCI Master Control
<byte 9063>
{field (By field)}
<byte 9063>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 9063>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 9060>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 9064>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 9064>
{field (By field)}
<byte 9064>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 9064>
{field (By field)}
<byte 9064>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 9064>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 9065>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 9065>
{field (By field)}
<byte 9065>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 9065>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 9066>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 9066>
{field (By field)}
<byte 9066>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 9066>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 9067>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 9067>
{field (By field)}
<byte 9067>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 9067>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 9064>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[4] Tachyon DX2+ CSR Registers
<byte 9068>
union csr[5] Tachyon DX2+ CSR Registers
<byte 9068>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[5] Tachyon DX2+ CSR Registers
<byte 9068>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 9068>
union erq_base (Offset 000) ERQ Base (write only)
<byte 9068>
{field (By field)}
<byte 9068>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 9068>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 9072>
union erq_len (Offset 004) ERQ Length (write only)
<byte 9072>
{field (By field)}
<byte 9072>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 9072>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 9076>
union erq_prod (Offset 008) ERQ Producer Index
<byte 9076>
{field (By field)}
<byte 9076>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 9076>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 9080>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 9080>
{field (By field)}
<byte 9080>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 9080>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 9084>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 9084>
{field (By field)}
<byte 9084>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 9084>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 9088>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 9088>
ulong value
{}
<byte 9092>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 9092>
ulong value
{}
<byte 9096>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 9096>
ulong value
{}
<byte 9100>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 9100>
ulong value
{}
<byte 9104>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 9104>
ulong value
{}
<byte 9108>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 9108>
ulong value
{}
<byte 9112>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 9112>
ulong value
{}
<byte 9116>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 9116>
ulong value
{}
<byte 9120>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 9120>
ulong value
{}
<byte 9124>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 9124>
ulong value
{}
<byte 9128>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 9128>
ulong value
{}
<byte 9132>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 9132>
ulong value
{}
<byte 9136>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 9136>
ulong value
{}
<byte 9140>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 9140>
ulong value
{}
<byte 9144>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 9144>
ulong value
{}
<byte 9148>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 9148>
{field (By field)}
<byte 9148>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 9148>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 9152>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 9152>
{field (By field)}
<byte 9152>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 9152>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 9156>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 9156>
{field (By field)}
<byte 9156>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 9156>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 9160>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 9160>
ulong value
{}
<byte 9164>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 9164>
ulong value
{}
<byte 9168>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 9168>
ulong value
{}
<byte 9172>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 9172>
ulong value
{}
<byte 9176>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 9176>
ulong value
{}
<byte 9180>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 9180>
ulong value
{}
<byte 9184>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 9184>
ulong value
{}
<byte 9188>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 9188>
ulong value
{}
<byte 9192>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 9192>
{field (By field)}
<byte 9192>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 9192>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 9196>
union imq_base (Offset 080) IMQ Base (write only)
<byte 9196>
{field (By field)}
<byte 9196>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 9196>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 9200>
union imq_len (Offset 084) IMQ Length (write only)
<byte 9200>
{field (By field)}
<byte 9200>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 9200>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 9204>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 9204>
{field (By field)}
<byte 9204>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 9204>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 9208>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 9208>
{field (By field)}
<byte 9208>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 9208>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 9212>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 9212>
ulong value
{}
<byte 9216>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 9216>
ulong value
{}
<byte 9220>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 9220>
ulong value
{}
<byte 9224>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 9224>
ulong value
{}
<byte 9228>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 9228>
ulong value
{}
<byte 9232>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 9232>
ulong value
{}
<byte 9236>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 9236>
ulong value
{}
<byte 9240>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 9240>
ulong value
{}
<byte 9244>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 9244>
ulong value
{}
<byte 9248>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 9248>
ulong value
{}
<byte 9252>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 9252>
ulong value
{}
<byte 9256>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 9256>
ulong value
{}
<byte 9260>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 9260>
ulong value
{}
<byte 9264>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 9264>
ulong value
{}
<byte 9268>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 9268>
ulong value
{}
<byte 9272>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 9272>
ulong value
{}
<byte 9276>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 9276>
ulong value
{}
<byte 9280>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 9280>
ulong value
{}
<byte 9284>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 9284>
ulong value
{}
<byte 9288>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 9288>
ulong value
{}
<byte 9292>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 9292>
ulong value
{}
<byte 9296>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 9296>
ulong value
{}
<byte 9300>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 9300>
ulong value
{}
<byte 9304>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 9304>
ulong value
{}
<byte 9308>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 9308>
ulong value
{}
<byte 9312>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 9312>
ulong value
{}
<byte 9316>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 9316>
ulong value
{}
<byte 9320>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 9320>
ulong value
{}
<byte 9324>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 9324>
{field (By field)}
<byte 9324>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 9324>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 9328>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 9328>
{field (By field)}
<byte 9328>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 9328>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 9332>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 9332>
ulong value
{}
<byte 9336>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 9336>
ulong value
{}
<byte 9340>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 9340>
{field (No description available)}
<byte 9340>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 9340>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 9344>
union sfp_data (Offset 114) SFP data
<byte 9344>
{field (By field)}
<byte 9344>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 9344>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 9348>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 9348>
{field (By field)}
<byte 9348>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 9348>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 9352>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 9352>
{field (By field)}
<byte 9352>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 9352>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 9356>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 9356>
ulong value
{}
<byte 9360>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 9360>
ulong value
{}
<byte 9364>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 9364>
ulong value
{}
<byte 9368>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 9368>
ulong value
{}
<byte 9372>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 9372>
ulong value
{}
<byte 9376>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 9376>
ulong value
{}
<byte 9380>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 9380>
ulong value
{}
<byte 9384>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 9384>
ulong value
{}
<byte 9388>
union sest_base (Offset 140) SEST Base (write only)
<byte 9388>
{field (By field)}
<byte 9388>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 9388>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 9392>
union sest_len (Offset 144) SEST Length (write only)
<byte 9392>
{field (By field)}
<byte 9392>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 9392>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 9396>
{rsvd4 ((Offset 148) Reserved)}
<byte 9396>
ulong value
{}
<byte 9400>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 9400>
{field (By field)}
<byte 9400>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 9400>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 9404>
union prog_addr (Offset 150) Programmable Address register
<byte 9404>
{field (By field)}
<byte 9404>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 9404>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 9408>
union prog_data (Offset 154) programmable data register
<byte 9408>
{field (By field)}
<byte 9408>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 9408>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 9412>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 9412>
ulong value
{}
<byte 9416>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 9416>
ulong value
{}
<byte 9420>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 9420>
{field (By field)}
<byte 9420>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 9420>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 9424>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 9424>
{field (By field)}
<byte 9424>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 9424>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 9428>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 9428>
{field (By field)}
<byte 9428>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 9428>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 9432>
union my_id (Offset 16C) My ID
<byte 9432>
{field (By field)}
<byte 9432>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 9432>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 9436>
union gpio (Offset 170) General Purpose I/O
<byte 9436>
{field (By field)}
<byte 9436>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 9436>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 9440>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 9440>
ulong value
{}
<byte 9444>
union edc_config (Offset 178) EDC Configuration Register
<byte 9444>
{field (By field)}
<byte 9444>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 9444>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 9448>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 9448>
{field (By field)}
<byte 9448>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 9448>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 9452>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 9452>
{field (By field)}
<byte 9452>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 9452>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 9456>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 9456>
{field (By field)}
<byte 9456>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 9456>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 9460>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 9460>
{field (By field)}
<byte 9460>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 9460>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 9464>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 9464>
{field (By field)}
<byte 9464>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 9464>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 9468>
{rsvd7 ((Offset 190) Reserved)}
<byte 9468>
ulong value
{}
<byte 9472>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 9472>
{field (By field)}
<byte 9472>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 9472>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 9476>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 9476>
{field (By field)}
<byte 9476>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 9476>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 9480>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 9480>
{field (By field)}
<byte 9480>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 9480>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 9484>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 9484>
{field (By field)}
<byte 9484>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 9484>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 9488>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 9488>
{field (By field)}
<byte 9488>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 9488>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 9492>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 9492>
{field (By field)}
<byte 9492>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 9492>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 9496>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 9496>
{field (By field)}
<byte 9496>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 9496>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 9500>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 9500>
{field (By field)}
<byte 9500>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 9500>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 9504>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 9504>
{field (By field)}
<byte 9504>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 9504>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 9508>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 9508>
{field (By field)}
<byte 9508>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 9508>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 9512>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 9512>
{field (By field)}
<byte 9512>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 9512>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 9516>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 9516>
{field (By field)}
<byte 9516>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 9516>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 9520>
union fm_control (Offset 1C4) Frame Manager Control
<byte 9520>
{field (By field)}
<byte 9520>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 9520>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 9524>
union fm_status (Offset 1C8) Frame Manager Status
<byte 9524>
{field (By field)}
<byte 9524>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 9524>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 9528>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 9528>
{field (By field)}
<byte 9528>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 9528>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 9532>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 9532>
{field (By field)}
<byte 9532>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 9532>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 9536>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 9536>
{field (By field)}
<byte 9536>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 9536>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 9540>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 9540>
{field (By field)}
<byte 9540>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 9540>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 9544>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 9544>
{field (By field)}
<byte 9544>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 9544>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 9548>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 9548>
{field (By field)}
<byte 9548>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 9548>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 9552>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 9552>
{field (By field)}
<byte 9552>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 9552>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 9556>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 9556>
{field (By field)}
<byte 9556>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 9556>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 9560>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 9560>
{field (By field)}
<byte 9560>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 9560>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 9564>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 9564>
{field (By field)}
<byte 9564>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 9564>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 9568>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 9568>
{field (By field)}
<byte 9568>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 9568>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 9572>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 9572>
{field (By field)}
<byte 9572>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 9572>
utiny value
{}
<byte 9573>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 9573>
utiny value
{}
<byte 9574>
union romctr (Offset 1FA) PCI ROM Control
<byte 9574>
{field (By field)}
<byte 9574>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 9574>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 9575>
union mctr (Offset 1FB) PCI Master Control
<byte 9575>
{field (By field)}
<byte 9575>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 9575>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 9572>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 9576>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 9576>
{field (By field)}
<byte 9576>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 9576>
{field (By field)}
<byte 9576>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 9576>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 9577>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 9577>
{field (By field)}
<byte 9577>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 9577>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 9578>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 9578>
{field (By field)}
<byte 9578>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 9578>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 9579>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 9579>
{field (By field)}
<byte 9579>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 9579>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 9576>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[5] Tachyon DX2+ CSR Registers
<byte 9580>
union csr[6] Tachyon DX2+ CSR Registers
<byte 9580>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[6] Tachyon DX2+ CSR Registers
<byte 9580>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 9580>
union erq_base (Offset 000) ERQ Base (write only)
<byte 9580>
{field (By field)}
<byte 9580>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 9580>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 9584>
union erq_len (Offset 004) ERQ Length (write only)
<byte 9584>
{field (By field)}
<byte 9584>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 9584>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 9588>
union erq_prod (Offset 008) ERQ Producer Index
<byte 9588>
{field (By field)}
<byte 9588>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 9588>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 9592>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 9592>
{field (By field)}
<byte 9592>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 9592>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 9596>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 9596>
{field (By field)}
<byte 9596>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 9596>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 9600>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 9600>
ulong value
{}
<byte 9604>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 9604>
ulong value
{}
<byte 9608>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 9608>
ulong value
{}
<byte 9612>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 9612>
ulong value
{}
<byte 9616>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 9616>
ulong value
{}
<byte 9620>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 9620>
ulong value
{}
<byte 9624>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 9624>
ulong value
{}
<byte 9628>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 9628>
ulong value
{}
<byte 9632>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 9632>
ulong value
{}
<byte 9636>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 9636>
ulong value
{}
<byte 9640>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 9640>
ulong value
{}
<byte 9644>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 9644>
ulong value
{}
<byte 9648>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 9648>
ulong value
{}
<byte 9652>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 9652>
ulong value
{}
<byte 9656>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 9656>
ulong value
{}
<byte 9660>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 9660>
{field (By field)}
<byte 9660>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 9660>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 9664>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 9664>
{field (By field)}
<byte 9664>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 9664>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 9668>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 9668>
{field (By field)}
<byte 9668>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 9668>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 9672>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 9672>
ulong value
{}
<byte 9676>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 9676>
ulong value
{}
<byte 9680>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 9680>
ulong value
{}
<byte 9684>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 9684>
ulong value
{}
<byte 9688>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 9688>
ulong value
{}
<byte 9692>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 9692>
ulong value
{}
<byte 9696>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 9696>
ulong value
{}
<byte 9700>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 9700>
ulong value
{}
<byte 9704>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 9704>
{field (By field)}
<byte 9704>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 9704>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 9708>
union imq_base (Offset 080) IMQ Base (write only)
<byte 9708>
{field (By field)}
<byte 9708>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 9708>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 9712>
union imq_len (Offset 084) IMQ Length (write only)
<byte 9712>
{field (By field)}
<byte 9712>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 9712>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 9716>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 9716>
{field (By field)}
<byte 9716>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 9716>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 9720>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 9720>
{field (By field)}
<byte 9720>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 9720>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 9724>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 9724>
ulong value
{}
<byte 9728>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 9728>
ulong value
{}
<byte 9732>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 9732>
ulong value
{}
<byte 9736>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 9736>
ulong value
{}
<byte 9740>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 9740>
ulong value
{}
<byte 9744>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 9744>
ulong value
{}
<byte 9748>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 9748>
ulong value
{}
<byte 9752>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 9752>
ulong value
{}
<byte 9756>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 9756>
ulong value
{}
<byte 9760>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 9760>
ulong value
{}
<byte 9764>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 9764>
ulong value
{}
<byte 9768>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 9768>
ulong value
{}
<byte 9772>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 9772>
ulong value
{}
<byte 9776>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 9776>
ulong value
{}
<byte 9780>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 9780>
ulong value
{}
<byte 9784>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 9784>
ulong value
{}
<byte 9788>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 9788>
ulong value
{}
<byte 9792>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 9792>
ulong value
{}
<byte 9796>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 9796>
ulong value
{}
<byte 9800>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 9800>
ulong value
{}
<byte 9804>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 9804>
ulong value
{}
<byte 9808>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 9808>
ulong value
{}
<byte 9812>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 9812>
ulong value
{}
<byte 9816>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 9816>
ulong value
{}
<byte 9820>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 9820>
ulong value
{}
<byte 9824>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 9824>
ulong value
{}
<byte 9828>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 9828>
ulong value
{}
<byte 9832>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 9832>
ulong value
{}
<byte 9836>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 9836>
{field (By field)}
<byte 9836>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 9836>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 9840>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 9840>
{field (By field)}
<byte 9840>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 9840>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 9844>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 9844>
ulong value
{}
<byte 9848>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 9848>
ulong value
{}
<byte 9852>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 9852>
{field (No description available)}
<byte 9852>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 9852>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 9856>
union sfp_data (Offset 114) SFP data
<byte 9856>
{field (By field)}
<byte 9856>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 9856>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 9860>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 9860>
{field (By field)}
<byte 9860>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 9860>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 9864>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 9864>
{field (By field)}
<byte 9864>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 9864>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 9868>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 9868>
ulong value
{}
<byte 9872>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 9872>
ulong value
{}
<byte 9876>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 9876>
ulong value
{}
<byte 9880>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 9880>
ulong value
{}
<byte 9884>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 9884>
ulong value
{}
<byte 9888>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 9888>
ulong value
{}
<byte 9892>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 9892>
ulong value
{}
<byte 9896>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 9896>
ulong value
{}
<byte 9900>
union sest_base (Offset 140) SEST Base (write only)
<byte 9900>
{field (By field)}
<byte 9900>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 9900>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 9904>
union sest_len (Offset 144) SEST Length (write only)
<byte 9904>
{field (By field)}
<byte 9904>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 9904>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 9908>
{rsvd4 ((Offset 148) Reserved)}
<byte 9908>
ulong value
{}
<byte 9912>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 9912>
{field (By field)}
<byte 9912>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 9912>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 9916>
union prog_addr (Offset 150) Programmable Address register
<byte 9916>
{field (By field)}
<byte 9916>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 9916>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 9920>
union prog_data (Offset 154) programmable data register
<byte 9920>
{field (By field)}
<byte 9920>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 9920>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 9924>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 9924>
ulong value
{}
<byte 9928>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 9928>
ulong value
{}
<byte 9932>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 9932>
{field (By field)}
<byte 9932>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 9932>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 9936>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 9936>
{field (By field)}
<byte 9936>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 9936>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 9940>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 9940>
{field (By field)}
<byte 9940>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 9940>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 9944>
union my_id (Offset 16C) My ID
<byte 9944>
{field (By field)}
<byte 9944>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 9944>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 9948>
union gpio (Offset 170) General Purpose I/O
<byte 9948>
{field (By field)}
<byte 9948>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 9948>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 9952>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 9952>
ulong value
{}
<byte 9956>
union edc_config (Offset 178) EDC Configuration Register
<byte 9956>
{field (By field)}
<byte 9956>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 9956>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 9960>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 9960>
{field (By field)}
<byte 9960>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 9960>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 9964>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 9964>
{field (By field)}
<byte 9964>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 9964>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 9968>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 9968>
{field (By field)}
<byte 9968>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 9968>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 9972>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 9972>
{field (By field)}
<byte 9972>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 9972>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 9976>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 9976>
{field (By field)}
<byte 9976>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 9976>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 9980>
{rsvd7 ((Offset 190) Reserved)}
<byte 9980>
ulong value
{}
<byte 9984>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 9984>
{field (By field)}
<byte 9984>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 9984>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 9988>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 9988>
{field (By field)}
<byte 9988>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 9988>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 9992>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 9992>
{field (By field)}
<byte 9992>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 9992>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 9996>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 9996>
{field (By field)}
<byte 9996>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 9996>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 10000>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 10000>
{field (By field)}
<byte 10000>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 10000>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 10004>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 10004>
{field (By field)}
<byte 10004>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 10004>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 10008>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 10008>
{field (By field)}
<byte 10008>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 10008>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 10012>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 10012>
{field (By field)}
<byte 10012>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 10012>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 10016>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 10016>
{field (By field)}
<byte 10016>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 10016>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 10020>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 10020>
{field (By field)}
<byte 10020>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 10020>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 10024>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 10024>
{field (By field)}
<byte 10024>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 10024>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 10028>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 10028>
{field (By field)}
<byte 10028>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 10028>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 10032>
union fm_control (Offset 1C4) Frame Manager Control
<byte 10032>
{field (By field)}
<byte 10032>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 10032>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 10036>
union fm_status (Offset 1C8) Frame Manager Status
<byte 10036>
{field (By field)}
<byte 10036>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 10036>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 10040>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 10040>
{field (By field)}
<byte 10040>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 10040>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 10044>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 10044>
{field (By field)}
<byte 10044>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 10044>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 10048>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 10048>
{field (By field)}
<byte 10048>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 10048>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 10052>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 10052>
{field (By field)}
<byte 10052>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 10052>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 10056>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 10056>
{field (By field)}
<byte 10056>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 10056>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 10060>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 10060>
{field (By field)}
<byte 10060>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 10060>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 10064>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 10064>
{field (By field)}
<byte 10064>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 10064>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 10068>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 10068>
{field (By field)}
<byte 10068>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 10068>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 10072>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 10072>
{field (By field)}
<byte 10072>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 10072>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 10076>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 10076>
{field (By field)}
<byte 10076>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 10076>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 10080>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 10080>
{field (By field)}
<byte 10080>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 10080>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 10084>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 10084>
{field (By field)}
<byte 10084>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 10084>
utiny value
{}
<byte 10085>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 10085>
utiny value
{}
<byte 10086>
union romctr (Offset 1FA) PCI ROM Control
<byte 10086>
{field (By field)}
<byte 10086>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 10086>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 10087>
union mctr (Offset 1FB) PCI Master Control
<byte 10087>
{field (By field)}
<byte 10087>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 10087>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 10084>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 10088>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 10088>
{field (By field)}
<byte 10088>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 10088>
{field (By field)}
<byte 10088>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 10088>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 10089>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 10089>
{field (By field)}
<byte 10089>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 10089>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 10090>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 10090>
{field (By field)}
<byte 10090>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 10090>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 10091>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 10091>
{field (By field)}
<byte 10091>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 10091>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 10088>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[6] Tachyon DX2+ CSR Registers
<byte 10092>
union csr[7] Tachyon DX2+ CSR Registers
<byte 10092>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[7] Tachyon DX2+ CSR Registers
<byte 10092>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 10092>
union erq_base (Offset 000) ERQ Base (write only)
<byte 10092>
{field (By field)}
<byte 10092>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 10092>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 10096>
union erq_len (Offset 004) ERQ Length (write only)
<byte 10096>
{field (By field)}
<byte 10096>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 10096>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 10100>
union erq_prod (Offset 008) ERQ Producer Index
<byte 10100>
{field (By field)}
<byte 10100>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 10100>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 10104>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 10104>
{field (By field)}
<byte 10104>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 10104>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 10108>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 10108>
{field (By field)}
<byte 10108>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 10108>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 10112>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 10112>
ulong value
{}
<byte 10116>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 10116>
ulong value
{}
<byte 10120>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 10120>
ulong value
{}
<byte 10124>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 10124>
ulong value
{}
<byte 10128>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 10128>
ulong value
{}
<byte 10132>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 10132>
ulong value
{}
<byte 10136>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 10136>
ulong value
{}
<byte 10140>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 10140>
ulong value
{}
<byte 10144>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 10144>
ulong value
{}
<byte 10148>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 10148>
ulong value
{}
<byte 10152>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 10152>
ulong value
{}
<byte 10156>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 10156>
ulong value
{}
<byte 10160>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 10160>
ulong value
{}
<byte 10164>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 10164>
ulong value
{}
<byte 10168>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 10168>
ulong value
{}
<byte 10172>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 10172>
{field (By field)}
<byte 10172>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 10172>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 10176>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 10176>
{field (By field)}
<byte 10176>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 10176>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 10180>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 10180>
{field (By field)}
<byte 10180>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 10180>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 10184>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 10184>
ulong value
{}
<byte 10188>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 10188>
ulong value
{}
<byte 10192>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 10192>
ulong value
{}
<byte 10196>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 10196>
ulong value
{}
<byte 10200>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 10200>
ulong value
{}
<byte 10204>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 10204>
ulong value
{}
<byte 10208>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 10208>
ulong value
{}
<byte 10212>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 10212>
ulong value
{}
<byte 10216>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 10216>
{field (By field)}
<byte 10216>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 10216>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 10220>
union imq_base (Offset 080) IMQ Base (write only)
<byte 10220>
{field (By field)}
<byte 10220>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 10220>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 10224>
union imq_len (Offset 084) IMQ Length (write only)
<byte 10224>
{field (By field)}
<byte 10224>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 10224>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 10228>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 10228>
{field (By field)}
<byte 10228>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 10228>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 10232>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 10232>
{field (By field)}
<byte 10232>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 10232>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 10236>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 10236>
ulong value
{}
<byte 10240>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 10240>
ulong value
{}
<byte 10244>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 10244>
ulong value
{}
<byte 10248>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 10248>
ulong value
{}
<byte 10252>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 10252>
ulong value
{}
<byte 10256>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 10256>
ulong value
{}
<byte 10260>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 10260>
ulong value
{}
<byte 10264>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 10264>
ulong value
{}
<byte 10268>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 10268>
ulong value
{}
<byte 10272>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 10272>
ulong value
{}
<byte 10276>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 10276>
ulong value
{}
<byte 10280>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 10280>
ulong value
{}
<byte 10284>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 10284>
ulong value
{}
<byte 10288>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 10288>
ulong value
{}
<byte 10292>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 10292>
ulong value
{}
<byte 10296>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 10296>
ulong value
{}
<byte 10300>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 10300>
ulong value
{}
<byte 10304>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 10304>
ulong value
{}
<byte 10308>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 10308>
ulong value
{}
<byte 10312>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 10312>
ulong value
{}
<byte 10316>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 10316>
ulong value
{}
<byte 10320>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 10320>
ulong value
{}
<byte 10324>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 10324>
ulong value
{}
<byte 10328>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 10328>
ulong value
{}
<byte 10332>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 10332>
ulong value
{}
<byte 10336>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 10336>
ulong value
{}
<byte 10340>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 10340>
ulong value
{}
<byte 10344>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 10344>
ulong value
{}
<byte 10348>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 10348>
{field (By field)}
<byte 10348>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 10348>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 10352>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 10352>
{field (By field)}
<byte 10352>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 10352>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 10356>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 10356>
ulong value
{}
<byte 10360>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 10360>
ulong value
{}
<byte 10364>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 10364>
{field (No description available)}
<byte 10364>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 10364>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 10368>
union sfp_data (Offset 114) SFP data
<byte 10368>
{field (By field)}
<byte 10368>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 10368>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 10372>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 10372>
{field (By field)}
<byte 10372>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 10372>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 10376>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 10376>
{field (By field)}
<byte 10376>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 10376>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 10380>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 10380>
ulong value
{}
<byte 10384>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 10384>
ulong value
{}
<byte 10388>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 10388>
ulong value
{}
<byte 10392>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 10392>
ulong value
{}
<byte 10396>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 10396>
ulong value
{}
<byte 10400>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 10400>
ulong value
{}
<byte 10404>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 10404>
ulong value
{}
<byte 10408>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 10408>
ulong value
{}
<byte 10412>
union sest_base (Offset 140) SEST Base (write only)
<byte 10412>
{field (By field)}
<byte 10412>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 10412>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 10416>
union sest_len (Offset 144) SEST Length (write only)
<byte 10416>
{field (By field)}
<byte 10416>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 10416>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 10420>
{rsvd4 ((Offset 148) Reserved)}
<byte 10420>
ulong value
{}
<byte 10424>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 10424>
{field (By field)}
<byte 10424>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 10424>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 10428>
union prog_addr (Offset 150) Programmable Address register
<byte 10428>
{field (By field)}
<byte 10428>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 10428>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 10432>
union prog_data (Offset 154) programmable data register
<byte 10432>
{field (By field)}
<byte 10432>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 10432>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 10436>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 10436>
ulong value
{}
<byte 10440>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 10440>
ulong value
{}
<byte 10444>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 10444>
{field (By field)}
<byte 10444>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 10444>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 10448>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 10448>
{field (By field)}
<byte 10448>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 10448>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 10452>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 10452>
{field (By field)}
<byte 10452>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 10452>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 10456>
union my_id (Offset 16C) My ID
<byte 10456>
{field (By field)}
<byte 10456>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 10456>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 10460>
union gpio (Offset 170) General Purpose I/O
<byte 10460>
{field (By field)}
<byte 10460>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 10460>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 10464>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 10464>
ulong value
{}
<byte 10468>
union edc_config (Offset 178) EDC Configuration Register
<byte 10468>
{field (By field)}
<byte 10468>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 10468>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 10472>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 10472>
{field (By field)}
<byte 10472>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 10472>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 10476>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 10476>
{field (By field)}
<byte 10476>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 10476>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 10480>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 10480>
{field (By field)}
<byte 10480>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 10480>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 10484>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 10484>
{field (By field)}
<byte 10484>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 10484>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 10488>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 10488>
{field (By field)}
<byte 10488>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 10488>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 10492>
{rsvd7 ((Offset 190) Reserved)}
<byte 10492>
ulong value
{}
<byte 10496>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 10496>
{field (By field)}
<byte 10496>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 10496>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 10500>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 10500>
{field (By field)}
<byte 10500>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 10500>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 10504>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 10504>
{field (By field)}
<byte 10504>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 10504>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 10508>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 10508>
{field (By field)}
<byte 10508>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 10508>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 10512>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 10512>
{field (By field)}
<byte 10512>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 10512>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 10516>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 10516>
{field (By field)}
<byte 10516>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 10516>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 10520>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 10520>
{field (By field)}
<byte 10520>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 10520>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 10524>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 10524>
{field (By field)}
<byte 10524>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 10524>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 10528>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 10528>
{field (By field)}
<byte 10528>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 10528>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 10532>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 10532>
{field (By field)}
<byte 10532>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 10532>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 10536>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 10536>
{field (By field)}
<byte 10536>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 10536>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 10540>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 10540>
{field (By field)}
<byte 10540>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 10540>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 10544>
union fm_control (Offset 1C4) Frame Manager Control
<byte 10544>
{field (By field)}
<byte 10544>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 10544>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 10548>
union fm_status (Offset 1C8) Frame Manager Status
<byte 10548>
{field (By field)}
<byte 10548>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 10548>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 10552>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 10552>
{field (By field)}
<byte 10552>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 10552>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 10556>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 10556>
{field (By field)}
<byte 10556>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 10556>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 10560>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 10560>
{field (By field)}
<byte 10560>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 10560>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 10564>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 10564>
{field (By field)}
<byte 10564>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 10564>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 10568>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 10568>
{field (By field)}
<byte 10568>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 10568>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 10572>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 10572>
{field (By field)}
<byte 10572>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 10572>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 10576>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 10576>
{field (By field)}
<byte 10576>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 10576>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 10580>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 10580>
{field (By field)}
<byte 10580>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 10580>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 10584>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 10584>
{field (By field)}
<byte 10584>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 10584>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 10588>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 10588>
{field (By field)}
<byte 10588>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 10588>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 10592>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 10592>
{field (By field)}
<byte 10592>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 10592>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 10596>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 10596>
{field (By field)}
<byte 10596>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 10596>
utiny value
{}
<byte 10597>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 10597>
utiny value
{}
<byte 10598>
union romctr (Offset 1FA) PCI ROM Control
<byte 10598>
{field (By field)}
<byte 10598>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 10598>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 10599>
union mctr (Offset 1FB) PCI Master Control
<byte 10599>
{field (By field)}
<byte 10599>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 10599>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 10596>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 10600>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 10600>
{field (By field)}
<byte 10600>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 10600>
{field (By field)}
<byte 10600>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 10600>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 10601>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 10601>
{field (By field)}
<byte 10601>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 10601>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 10602>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 10602>
{field (By field)}
<byte 10602>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 10602>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 10603>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 10603>
{field (By field)}
<byte 10603>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 10603>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 10600>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[7] Tachyon DX2+ CSR Registers
<byte 10604>
union csr[8] Tachyon DX2+ CSR Registers
<byte 10604>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[8] Tachyon DX2+ CSR Registers
<byte 10604>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 10604>
union erq_base (Offset 000) ERQ Base (write only)
<byte 10604>
{field (By field)}
<byte 10604>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 10604>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 10608>
union erq_len (Offset 004) ERQ Length (write only)
<byte 10608>
{field (By field)}
<byte 10608>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 10608>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 10612>
union erq_prod (Offset 008) ERQ Producer Index
<byte 10612>
{field (By field)}
<byte 10612>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 10612>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 10616>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 10616>
{field (By field)}
<byte 10616>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 10616>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 10620>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 10620>
{field (By field)}
<byte 10620>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 10620>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 10624>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 10624>
ulong value
{}
<byte 10628>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 10628>
ulong value
{}
<byte 10632>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 10632>
ulong value
{}
<byte 10636>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 10636>
ulong value
{}
<byte 10640>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 10640>
ulong value
{}
<byte 10644>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 10644>
ulong value
{}
<byte 10648>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 10648>
ulong value
{}
<byte 10652>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 10652>
ulong value
{}
<byte 10656>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 10656>
ulong value
{}
<byte 10660>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 10660>
ulong value
{}
<byte 10664>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 10664>
ulong value
{}
<byte 10668>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 10668>
ulong value
{}
<byte 10672>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 10672>
ulong value
{}
<byte 10676>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 10676>
ulong value
{}
<byte 10680>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 10680>
ulong value
{}
<byte 10684>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 10684>
{field (By field)}
<byte 10684>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 10684>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 10688>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 10688>
{field (By field)}
<byte 10688>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 10688>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 10692>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 10692>
{field (By field)}
<byte 10692>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 10692>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 10696>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 10696>
ulong value
{}
<byte 10700>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 10700>
ulong value
{}
<byte 10704>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 10704>
ulong value
{}
<byte 10708>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 10708>
ulong value
{}
<byte 10712>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 10712>
ulong value
{}
<byte 10716>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 10716>
ulong value
{}
<byte 10720>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 10720>
ulong value
{}
<byte 10724>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 10724>
ulong value
{}
<byte 10728>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 10728>
{field (By field)}
<byte 10728>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 10728>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 10732>
union imq_base (Offset 080) IMQ Base (write only)
<byte 10732>
{field (By field)}
<byte 10732>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 10732>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 10736>
union imq_len (Offset 084) IMQ Length (write only)
<byte 10736>
{field (By field)}
<byte 10736>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 10736>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 10740>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 10740>
{field (By field)}
<byte 10740>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 10740>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 10744>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 10744>
{field (By field)}
<byte 10744>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 10744>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 10748>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 10748>
ulong value
{}
<byte 10752>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 10752>
ulong value
{}
<byte 10756>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 10756>
ulong value
{}
<byte 10760>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 10760>
ulong value
{}
<byte 10764>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 10764>
ulong value
{}
<byte 10768>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 10768>
ulong value
{}
<byte 10772>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 10772>
ulong value
{}
<byte 10776>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 10776>
ulong value
{}
<byte 10780>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 10780>
ulong value
{}
<byte 10784>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 10784>
ulong value
{}
<byte 10788>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 10788>
ulong value
{}
<byte 10792>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 10792>
ulong value
{}
<byte 10796>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 10796>
ulong value
{}
<byte 10800>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 10800>
ulong value
{}
<byte 10804>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 10804>
ulong value
{}
<byte 10808>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 10808>
ulong value
{}
<byte 10812>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 10812>
ulong value
{}
<byte 10816>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 10816>
ulong value
{}
<byte 10820>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 10820>
ulong value
{}
<byte 10824>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 10824>
ulong value
{}
<byte 10828>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 10828>
ulong value
{}
<byte 10832>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 10832>
ulong value
{}
<byte 10836>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 10836>
ulong value
{}
<byte 10840>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 10840>
ulong value
{}
<byte 10844>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 10844>
ulong value
{}
<byte 10848>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 10848>
ulong value
{}
<byte 10852>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 10852>
ulong value
{}
<byte 10856>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 10856>
ulong value
{}
<byte 10860>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 10860>
{field (By field)}
<byte 10860>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 10860>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 10864>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 10864>
{field (By field)}
<byte 10864>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 10864>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 10868>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 10868>
ulong value
{}
<byte 10872>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 10872>
ulong value
{}
<byte 10876>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 10876>
{field (No description available)}
<byte 10876>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 10876>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 10880>
union sfp_data (Offset 114) SFP data
<byte 10880>
{field (By field)}
<byte 10880>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 10880>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 10884>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 10884>
{field (By field)}
<byte 10884>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 10884>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 10888>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 10888>
{field (By field)}
<byte 10888>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 10888>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 10892>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 10892>
ulong value
{}
<byte 10896>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 10896>
ulong value
{}
<byte 10900>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 10900>
ulong value
{}
<byte 10904>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 10904>
ulong value
{}
<byte 10908>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 10908>
ulong value
{}
<byte 10912>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 10912>
ulong value
{}
<byte 10916>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 10916>
ulong value
{}
<byte 10920>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 10920>
ulong value
{}
<byte 10924>
union sest_base (Offset 140) SEST Base (write only)
<byte 10924>
{field (By field)}
<byte 10924>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 10924>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 10928>
union sest_len (Offset 144) SEST Length (write only)
<byte 10928>
{field (By field)}
<byte 10928>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 10928>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 10932>
{rsvd4 ((Offset 148) Reserved)}
<byte 10932>
ulong value
{}
<byte 10936>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 10936>
{field (By field)}
<byte 10936>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 10936>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 10940>
union prog_addr (Offset 150) Programmable Address register
<byte 10940>
{field (By field)}
<byte 10940>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 10940>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 10944>
union prog_data (Offset 154) programmable data register
<byte 10944>
{field (By field)}
<byte 10944>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 10944>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 10948>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 10948>
ulong value
{}
<byte 10952>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 10952>
ulong value
{}
<byte 10956>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 10956>
{field (By field)}
<byte 10956>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 10956>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 10960>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 10960>
{field (By field)}
<byte 10960>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 10960>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 10964>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 10964>
{field (By field)}
<byte 10964>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 10964>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 10968>
union my_id (Offset 16C) My ID
<byte 10968>
{field (By field)}
<byte 10968>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 10968>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 10972>
union gpio (Offset 170) General Purpose I/O
<byte 10972>
{field (By field)}
<byte 10972>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 10972>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 10976>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 10976>
ulong value
{}
<byte 10980>
union edc_config (Offset 178) EDC Configuration Register
<byte 10980>
{field (By field)}
<byte 10980>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 10980>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 10984>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 10984>
{field (By field)}
<byte 10984>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 10984>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 10988>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 10988>
{field (By field)}
<byte 10988>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 10988>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 10992>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 10992>
{field (By field)}
<byte 10992>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 10992>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 10996>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 10996>
{field (By field)}
<byte 10996>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 10996>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 11000>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 11000>
{field (By field)}
<byte 11000>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 11000>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 11004>
{rsvd7 ((Offset 190) Reserved)}
<byte 11004>
ulong value
{}
<byte 11008>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 11008>
{field (By field)}
<byte 11008>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 11008>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 11012>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 11012>
{field (By field)}
<byte 11012>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 11012>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 11016>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 11016>
{field (By field)}
<byte 11016>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 11016>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 11020>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 11020>
{field (By field)}
<byte 11020>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 11020>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 11024>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 11024>
{field (By field)}
<byte 11024>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 11024>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 11028>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 11028>
{field (By field)}
<byte 11028>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 11028>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 11032>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 11032>
{field (By field)}
<byte 11032>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 11032>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 11036>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 11036>
{field (By field)}
<byte 11036>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 11036>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 11040>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 11040>
{field (By field)}
<byte 11040>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 11040>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 11044>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 11044>
{field (By field)}
<byte 11044>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 11044>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 11048>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 11048>
{field (By field)}
<byte 11048>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 11048>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 11052>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 11052>
{field (By field)}
<byte 11052>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 11052>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 11056>
union fm_control (Offset 1C4) Frame Manager Control
<byte 11056>
{field (By field)}
<byte 11056>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 11056>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 11060>
union fm_status (Offset 1C8) Frame Manager Status
<byte 11060>
{field (By field)}
<byte 11060>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 11060>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 11064>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 11064>
{field (By field)}
<byte 11064>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 11064>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 11068>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 11068>
{field (By field)}
<byte 11068>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 11068>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 11072>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 11072>
{field (By field)}
<byte 11072>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 11072>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 11076>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 11076>
{field (By field)}
<byte 11076>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 11076>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 11080>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 11080>
{field (By field)}
<byte 11080>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 11080>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 11084>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 11084>
{field (By field)}
<byte 11084>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 11084>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 11088>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 11088>
{field (By field)}
<byte 11088>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 11088>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 11092>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 11092>
{field (By field)}
<byte 11092>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 11092>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 11096>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 11096>
{field (By field)}
<byte 11096>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 11096>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 11100>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 11100>
{field (By field)}
<byte 11100>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 11100>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 11104>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 11104>
{field (By field)}
<byte 11104>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 11104>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 11108>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 11108>
{field (By field)}
<byte 11108>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 11108>
utiny value
{}
<byte 11109>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 11109>
utiny value
{}
<byte 11110>
union romctr (Offset 1FA) PCI ROM Control
<byte 11110>
{field (By field)}
<byte 11110>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 11110>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 11111>
union mctr (Offset 1FB) PCI Master Control
<byte 11111>
{field (By field)}
<byte 11111>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 11111>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 11108>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 11112>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 11112>
{field (By field)}
<byte 11112>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 11112>
{field (By field)}
<byte 11112>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 11112>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 11113>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 11113>
{field (By field)}
<byte 11113>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 11113>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 11114>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 11114>
{field (By field)}
<byte 11114>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 11114>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 11115>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 11115>
{field (By field)}
<byte 11115>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 11115>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 11112>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[8] Tachyon DX2+ CSR Registers
<byte 11116>
union csr[9] Tachyon DX2+ CSR Registers
<byte 11116>
ulong[128] csra Tachyon DX2+ CSR Registers As Longwords
or csr[9] Tachyon DX2+ CSR Registers
<byte 11116>
{csr (Tachyon DX2+ CSR Registers By Field)}
<byte 11116>
union erq_base (Offset 000) ERQ Base (write only)
<byte 11116>
{field (By field)}
<byte 11116>
lbits:32 address ERQ Base Address
{}
or erq_base (Offset 000) ERQ Base (write only)
<byte 11116>
ulong value As longword
endunion erq_base (Offset 000) ERQ Base (write only)
<byte 11120>
union erq_len (Offset 004) ERQ Length (write only)
<byte 11120>
{field (By field)}
<byte 11120>
lbits:12 length ERQ Length
lbits:20 reserved Reserved
{}
or erq_len (Offset 004) ERQ Length (write only)
<byte 11120>
ulong value As longword
endunion erq_len (Offset 004) ERQ Length (write only)
<byte 11124>
union erq_prod (Offset 008) ERQ Producer Index
<byte 11124>
{field (By field)}
<byte 11124>
lbits:12 index ERQ Producer Index
lbits:20 reserved Reserved
{}
or erq_prod (Offset 008) ERQ Producer Index
<byte 11124>
ulong value As longword
endunion erq_prod (Offset 008) ERQ Producer Index
<byte 11128>
union erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 11128>
{field (By field)}
<byte 11128>
lbits:32 address ERQ Consumer Index Address
{}
or erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 11128>
ulong value As longword
endunion erq_cons_adr (Offset 00C) ERQ Consumer Index Address (write only)
<byte 11132>
union erq_cons (Offset 010) ERQ Consumer Index
<byte 11132>
{field (By field)}
<byte 11132>
lbits:12 index ERQ Consumer Index
lbits:20 reserved Reserved
{}
or erq_cons (Offset 010) ERQ Consumer Index
<byte 11132>
ulong value As longword
endunion erq_cons (Offset 010) ERQ Consumer Index
<byte 11136>
{rsvd1[0] ((Offset 014-04F) Reserved)}
<byte 11136>
ulong value
{}
<byte 11140>
{rsvd1[1] ((Offset 014-04F) Reserved)}
<byte 11140>
ulong value
{}
<byte 11144>
{rsvd1[2] ((Offset 014-04F) Reserved)}
<byte 11144>
ulong value
{}
<byte 11148>
{rsvd1[3] ((Offset 014-04F) Reserved)}
<byte 11148>
ulong value
{}
<byte 11152>
{rsvd1[4] ((Offset 014-04F) Reserved)}
<byte 11152>
ulong value
{}
<byte 11156>
{rsvd1[5] ((Offset 014-04F) Reserved)}
<byte 11156>
ulong value
{}
<byte 11160>
{rsvd1[6] ((Offset 014-04F) Reserved)}
<byte 11160>
ulong value
{}
<byte 11164>
{rsvd1[7] ((Offset 014-04F) Reserved)}
<byte 11164>
ulong value
{}
<byte 11168>
{rsvd1[8] ((Offset 014-04F) Reserved)}
<byte 11168>
ulong value
{}
<byte 11172>
{rsvd1[9] ((Offset 014-04F) Reserved)}
<byte 11172>
ulong value
{}
<byte 11176>
{rsvd1[10] ((Offset 014-04F) Reserved)}
<byte 11176>
ulong value
{}
<byte 11180>
{rsvd1[11] ((Offset 014-04F) Reserved)}
<byte 11180>
ulong value
{}
<byte 11184>
{rsvd1[12] ((Offset 014-04F) Reserved)}
<byte 11184>
ulong value
{}
<byte 11188>
{rsvd1[13] ((Offset 014-04F) Reserved)}
<byte 11188>
ulong value
{}
<byte 11192>
{rsvd1[14] ((Offset 014-04F) Reserved)}
<byte 11192>
ulong value
{}
<byte 11196>
union sfq_base (Offset 050) SFQ Base (write only)
<byte 11196>
{field (By field)}
<byte 11196>
lbits:32 address SFQ Base Address
{}
or sfq_base (Offset 050) SFQ Base (write only)
<byte 11196>
ulong value As longword
endunion sfq_base (Offset 050) SFQ Base (write only)
<byte 11200>
union sfq_len (Offset 054) SFQ Length (write only)
<byte 11200>
{field (By field)}
<byte 11200>
lbits:12 length SFQ Length
lbits:20 reserved Reserved
{}
or sfq_len (Offset 054) SFQ Length (write only)
<byte 11200>
ulong value As longword
endunion sfq_len (Offset 054) SFQ Length (write only)
<byte 11204>
union sfq_cons (Offset 058) SFQ Consumer Index
<byte 11204>
{field (By field)}
<byte 11204>
lbits:12 index SFQ Consumer Index
lbits:20 reserved Reserved
{}
or sfq_cons (Offset 058) SFQ Consumer Index
<byte 11204>
ulong value As longword
endunion sfq_cons (Offset 058) SFQ Consumer Index
<byte 11208>
{rsvd2[0] ((Offset 05C-07B) Reserved)}
<byte 11208>
ulong value
{}
<byte 11212>
{rsvd2[1] ((Offset 05C-07B) Reserved)}
<byte 11212>
ulong value
{}
<byte 11216>
{rsvd2[2] ((Offset 05C-07B) Reserved)}
<byte 11216>
ulong value
{}
<byte 11220>
{rsvd2[3] ((Offset 05C-07B) Reserved)}
<byte 11220>
ulong value
{}
<byte 11224>
{rsvd2[4] ((Offset 05C-07B) Reserved)}
<byte 11224>
ulong value
{}
<byte 11228>
{rsvd2[5] ((Offset 05C-07B) Reserved)}
<byte 11228>
ulong value
{}
<byte 11232>
{rsvd2[6] ((Offset 05C-07B) Reserved)}
<byte 11232>
ulong value
{}
<byte 11236>
{rsvd2[7] ((Offset 05C-07B) Reserved)}
<byte 11236>
ulong value
{}
<byte 11240>
union int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 11240>
{field (By field)}
<byte 11240>
lbits:4 timer Interrupt Timer Value
lbits:3 reserved Reserved
lbits:1 ihf Interrupt when IMQ Half Full
lbits:24 reserved1 Reserved
{}
or int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 11240>
ulong value As longword
endunion int_delay_timer (Offset 07C) Interrupt Delay Timer (write only)
<byte 11244>
union imq_base (Offset 080) IMQ Base (write only)
<byte 11244>
{field (By field)}
<byte 11244>
lbits:32 address IMQ Base Address
{}
or imq_base (Offset 080) IMQ Base (write only)
<byte 11244>
ulong value As longword
endunion imq_base (Offset 080) IMQ Base (write only)
<byte 11248>
union imq_len (Offset 084) IMQ Length (write only)
<byte 11248>
{field (By field)}
<byte 11248>
lbits:12 length IMQ Length
lbits:20 reserved Reserved
{}
or imq_len (Offset 084) IMQ Length (write only)
<byte 11248>
ulong value As longword
endunion imq_len (Offset 084) IMQ Length (write only)
<byte 11252>
union imq_cons (Offset 088) IMQ Consumer Index
<byte 11252>
{field (By field)}
<byte 11252>
lbits:12 index IMQ Consumer Index
lbits:20 reserved Reserved
{}
or imq_cons (Offset 088) IMQ Consumer Index
<byte 11252>
ulong value As longword
endunion imq_cons (Offset 088) IMQ Consumer Index
<byte 11256>
union imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 11256>
{field (By field)}
<byte 11256>
lbits:32 address IMQ Producer Index Address
{}
or imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 11256>
ulong value As longword
endunion imq_prod_adr (Offset 08C) IMQ Producer Index Address (write only)
<byte 11260>
{rsvd3[0] ((Offset 090-0FC) Reserved)}
<byte 11260>
ulong value
{}
<byte 11264>
{rsvd3[1] ((Offset 090-0FC) Reserved)}
<byte 11264>
ulong value
{}
<byte 11268>
{rsvd3[2] ((Offset 090-0FC) Reserved)}
<byte 11268>
ulong value
{}
<byte 11272>
{rsvd3[3] ((Offset 090-0FC) Reserved)}
<byte 11272>
ulong value
{}
<byte 11276>
{rsvd3[4] ((Offset 090-0FC) Reserved)}
<byte 11276>
ulong value
{}
<byte 11280>
{rsvd3[5] ((Offset 090-0FC) Reserved)}
<byte 11280>
ulong value
{}
<byte 11284>
{rsvd3[6] ((Offset 090-0FC) Reserved)}
<byte 11284>
ulong value
{}
<byte 11288>
{rsvd3[7] ((Offset 090-0FC) Reserved)}
<byte 11288>
ulong value
{}
<byte 11292>
{rsvd3[8] ((Offset 090-0FC) Reserved)}
<byte 11292>
ulong value
{}
<byte 11296>
{rsvd3[9] ((Offset 090-0FC) Reserved)}
<byte 11296>
ulong value
{}
<byte 11300>
{rsvd3[10] ((Offset 090-0FC) Reserved)}
<byte 11300>
ulong value
{}
<byte 11304>
{rsvd3[11] ((Offset 090-0FC) Reserved)}
<byte 11304>
ulong value
{}
<byte 11308>
{rsvd3[12] ((Offset 090-0FC) Reserved)}
<byte 11308>
ulong value
{}
<byte 11312>
{rsvd3[13] ((Offset 090-0FC) Reserved)}
<byte 11312>
ulong value
{}
<byte 11316>
{rsvd3[14] ((Offset 090-0FC) Reserved)}
<byte 11316>
ulong value
{}
<byte 11320>
{rsvd3[15] ((Offset 090-0FC) Reserved)}
<byte 11320>
ulong value
{}
<byte 11324>
{rsvd3[16] ((Offset 090-0FC) Reserved)}
<byte 11324>
ulong value
{}
<byte 11328>
{rsvd3[17] ((Offset 090-0FC) Reserved)}
<byte 11328>
ulong value
{}
<byte 11332>
{rsvd3[18] ((Offset 090-0FC) Reserved)}
<byte 11332>
ulong value
{}
<byte 11336>
{rsvd3[19] ((Offset 090-0FC) Reserved)}
<byte 11336>
ulong value
{}
<byte 11340>
{rsvd3[20] ((Offset 090-0FC) Reserved)}
<byte 11340>
ulong value
{}
<byte 11344>
{rsvd3[21] ((Offset 090-0FC) Reserved)}
<byte 11344>
ulong value
{}
<byte 11348>
{rsvd3[22] ((Offset 090-0FC) Reserved)}
<byte 11348>
ulong value
{}
<byte 11352>
{rsvd3[23] ((Offset 090-0FC) Reserved)}
<byte 11352>
ulong value
{}
<byte 11356>
{rsvd3[24] ((Offset 090-0FC) Reserved)}
<byte 11356>
ulong value
{}
<byte 11360>
{rsvd3[25] ((Offset 090-0FC) Reserved)}
<byte 11360>
ulong value
{}
<byte 11364>
{rsvd3[26] ((Offset 090-0FC) Reserved)}
<byte 11364>
ulong value
{}
<byte 11368>
{rsvd3[27] ((Offset 090-0FC) Reserved)}
<byte 11368>
ulong value
{}
<byte 11372>
union fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 11372>
{field (By field)}
<byte 11372>
lbits:6 bec Termination Receive
lbits:3 reserved4 Reserved
lbits:1 xrb Wrapback
lbits:2 reserved Reserved
lbits:3 xem Output pre-emphasis
lbits:4 reserved1 Reserved
lbits:1 mustbe1 Must be 1
lbits:1 stb Start BERT
lbits:1 enb Enable BERT
lbits:2 sdm Signal differential mode
lbits:2 rxs Receiver Speed
lbits:2 txs Transmitter Speed
lbits:1 reserved3 Reserved
lbits:1 xlr Force iTR to lock reference clock
lbits:1 reserved0 Reserved
lbits:1 xcv Type of Transceiver
{}
or fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 11372>
ulong value As longword
endunion fm_config3 (Offset 100) Frame Manager Configuration 3
<byte 11376>
union fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 11376>
{field (By field)}
<byte 11376>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 11376>
ulong value As longword
endunion fm_statuss (Offset 104) Frame Manager Status Shadow (read only)
<byte 11380>
{rsvd3a[0] ((Offset 108-10f) Reserved)}
<byte 11380>
ulong value
{}
<byte 11384>
{rsvd3a[1] ((Offset 108-10f) Reserved)}
<byte 11384>
ulong value
{}
<byte 11388>
union sfp_cmd_status (Offset 110) SFP command and status
<byte 11388>
{field (No description available)}
<byte 11388>
lbits:1 gna Generate NACK
lbits:1 rts Reset Slave
lbits:1 wrc Write command
lbits:1 rdc Read command
lbits:1 gst Generate Stop
lbits:1 sta Generate Start
lbits:2 reserved1 Reserved
lbits:1 rna Received NACK
lbits:1 sby SFP Busy
lbits:1 tip Transfer in progress
lbits:9 reserved Reserved
lbits:12 lp Clock Divisor
{}
or sfp_cmd_status (Offset 110) SFP command and status
<byte 11388>
ulong value
endunion sfp_cmd_status (Offset 110) SFP command and status
<byte 11392>
union sfp_data (Offset 114) SFP data
<byte 11392>
{field (By field)}
<byte 11392>
lbits:8 sfpd SFPD Transmit
lbits:24 reserved Reserved
{}
or sfp_data (Offset 114) SFP data
<byte 11392>
ulong value As longword
endunion sfp_data (Offset 114) SFP data
<byte 11396>
union fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 11396>
{field (By field)}
<byte 11396>
lbits:1 tbe Transmit Link BIST error
lbits:1 tlr Transmit Link BIST reset
lbits:1 tle Transmit Link BIST enable
lbits:1 rbe Receive Link BIST error
lbits:1 rll Receive Link BIST loop-back
lbits:1 rlr Receive Link BIST reset
lbits:1 rle Receive Link BIST enable
lbits:7 reserved3 Reserved
lbits:1 ipl ITR PPL Lock
lbits:1 reserved2 Reserved
lbits:1 dtf Disable transceiver LOS filter
lbits:1 dtl Disable transceiver LOS
lbits:1 dsr Disable iTR RXLOS
lbits:1 ttd Transceiver Tx Disable
lbits:2 reserved1 Reserved
lbits:1 rfl Receive ast Lock Disable
lbits:9 reserved Reserved
{}
or fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 11396>
ulong value As longword
endunion fm_config4 (Offset 118) Frame Manager Configuration 4
<byte 11400>
union fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 11400>
{field (By field)}
<byte 11400>
lbits:32 reserved Reserved
{}
or fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 11400>
ulong value As longword
endunion fm_config5 (Offset 11C) Frame Manager Configuration 5
<byte 11404>
{rsvd3b[0] ((Offset 120-13F) Reserved)}
<byte 11404>
ulong value
{}
<byte 11408>
{rsvd3b[1] ((Offset 120-13F) Reserved)}
<byte 11408>
ulong value
{}
<byte 11412>
{rsvd3b[2] ((Offset 120-13F) Reserved)}
<byte 11412>
ulong value
{}
<byte 11416>
{rsvd3b[3] ((Offset 120-13F) Reserved)}
<byte 11416>
ulong value
{}
<byte 11420>
{rsvd3b[4] ((Offset 120-13F) Reserved)}
<byte 11420>
ulong value
{}
<byte 11424>
{rsvd3b[5] ((Offset 120-13F) Reserved)}
<byte 11424>
ulong value
{}
<byte 11428>
{rsvd3b[6] ((Offset 120-13F) Reserved)}
<byte 11428>
ulong value
{}
<byte 11432>
{rsvd3b[7] ((Offset 120-13F) Reserved)}
<byte 11432>
ulong value
{}
<byte 11436>
union sest_base (Offset 140) SEST Base (write only)
<byte 11436>
{field (By field)}
<byte 11436>
lbits:32 address SEST Base Address
{}
or sest_base (Offset 140) SEST Base (write only)
<byte 11436>
ulong value As longword
endunion sest_base (Offset 140) SEST Base (write only)
<byte 11440>
union sest_len (Offset 144) SEST Length (write only)
<byte 11440>
{field (By field)}
<byte 11440>
lbits:16 length SEST Length
lbits:16 reserved Reserved
{}
or sest_len (Offset 144) SEST Length (write only)
<byte 11440>
ulong value As longword
endunion sest_len (Offset 144) SEST Length (write only)
<byte 11444>
{rsvd4 ((Offset 148) Reserved)}
<byte 11444>
ulong value
{}
<byte 11448>
union scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 11448>
{field (By field)}
<byte 11448>
lbits:16 tail Tail
lbits:16 head Head
{}
or scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 11448>
ulong value As longword
endunion scsi_link_lst (Offset 14C) SCSI Linked List Head and Tail
<byte 11452>
union prog_addr (Offset 150) Programmable Address register
<byte 11452>
{field (By field)}
<byte 11452>
lbits:20 ra ROM/RAM address
lbits:11 reserved Reserved
lbits:1 inc Increment
{}
or prog_addr (Offset 150) Programmable Address register
<byte 11452>
ulong value As longword
endunion prog_addr (Offset 150) Programmable Address register
<byte 11456>
union prog_data (Offset 154) programmable data register
<byte 11456>
{field (By field)}
<byte 11456>
lbits:32 pdr Programmable data
{}
or prog_data (Offset 154) programmable data register
<byte 11456>
ulong value As longword
endunion prog_data (Offset 154) programmable data register
<byte 11460>
{rsvd5[0] ((Offset 158-15F) Reserved)}
<byte 11460>
ulong value
{}
<byte 11464>
{rsvd5[1] ((Offset 158-15F) Reserved)}
<byte 11464>
ulong value
{}
<byte 11468>
union int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 11468>
{field (By field)}
<byte 11468>
lbits:32 address Interrupt Message Address
{}
or int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 11468>
ulong value As longword
endunion int_mess_adr (Offset 160) Interrupt Message Address (write only)
<byte 11472>
union int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 11472>
{field (By field)}
<byte 11472>
lbits:32 value Interrupt Message Value
{}
or int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 11472>
ulong value As longword
endunion int_mess_value (Offset 164) Interrupt Message Value (write only)
<byte 11476>
union sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 11476>
{field (By field)}
<byte 11476>
lbits:8 length SGL Page Length
lbits:24 reserved Reserved
{}
or sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 11476>
ulong value As longword
endunion sgl_page_len (Offset 168) Scatter/Gather List Page Length (write only)
<byte 11480>
union my_id (Offset 16C) My ID
<byte 11480>
{field (By field)}
<byte 11480>
lbits:24 id My ID
lbits:8 reserved Reserved
{}
or my_id (Offset 16C) My ID
<byte 11480>
ulong value As longword
endunion my_id (Offset 16C) My ID
<byte 11484>
union gpio (Offset 170) General Purpose I/O
<byte 11484>
{field (By field)}
<byte 11484>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:1 gc5 General Purpose Control 5
lbits:1 gc6 General Purpose Control 6
lbits:1 gc7 General Purpose Control 7
lbits:8 reserved Reserved
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose I/O 4
lbits:1 gp5 General Purpose I/O 5
lbits:1 gp6 General Purpose I/O 6
lbits:1 gp7 General Purpose I/O 7
lbits:8 reserved1 Reserved
{}
or gpio (Offset 170) General Purpose I/O
<byte 11484>
ulong value As longword
endunion gpio (Offset 170) General Purpose I/O
<byte 11488>
{rsvd6a ((Offset 174-177) Reserved)}
<byte 11488>
ulong value
{}
<byte 11492>
union edc_config (Offset 178) EDC Configuration Register
<byte 11492>
{field (By field)}
<byte 11492>
lbits:16 io_seed Starting Seed
lbits:16 reserved Reserved
{}
or edc_config (Offset 178) EDC Configuration Register
<byte 11492>
ulong value As longword
endunion edc_config (Offset 178) EDC Configuration Register
<byte 11496>
union dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 11496>
{field (By field)}
<byte 11496>
lbits:9 pfs2 Programmable Frame size field 2
lbits:9 pfs3 Programmable Frame size field 3
lbits:9 pfs4 Programmable Frame size field 4
lbits:5 reserved Reserved
{}
or dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 11496>
ulong value As longword
endunion dx4_config3 (Offset 17C) DX4 Configuration Register 3
<byte 11500>
union tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 11500>
{field (By field)}
<byte 11500>
lbits:9 pfs Programmable Frame Size
lbits:15 reserved Reserved
lbits:8 esi_range Exchange_ID Signaled Interrupt Range
{}
or tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 11500>
ulong value As longword
endunion tach_config2 (Offset 180) Tachyon DX2+ Configuration 2
<byte 11504>
union tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 11504>
{field (By field)}
<byte 11504>
lbits:1 fad FCP Assist Disable
lbits:1 ino In Order
lbits:1 dof Discard OOO FCP Frames
lbits:1 fua FCP Unassisted ACK Enable
lbits:1 ime Interrupt Message Enable
lbits:1 fab Fabric
lbits:1 sic S_ID Copy Enable
lbits:1 eqs Equal Service
lbits:2 reserved Reserved
lbits:1 aks Automatic ACK
lbits:1 ddf Disable Delayed Freeze
lbits:1 ebe Enable Big Endian Mode
lbits:11 reserved1 Reserved
lbits:1 fc2 FCP Class 2 Reassembly Enable
lbits:1 reserved2 Reserved
lbits:1 sdf Save Discarded Frames
lbits:1 rde Response Detect Enable
lbits:1 dam Default ACK Model
lbits:2 reserved3 Reserved
lbits:1 m66 66 MHz Enabled
{}
or tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 11504>
ulong value As longword
endunion tach_config (Offset 184) Tachyon DX2+ Configuration 1
<byte 11508>
union tach_control (Offset 188) Tachyon DX2+ Control
<byte 11508>
{field (By field)}
<byte 11508>
lbits:1 gc0 General Purpose Control 0
lbits:1 gc1 General Purpose Control 1
lbits:1 gc2 General Purpose Control 2
lbits:1 gc3 General Purpose Control 3
lbits:1 gc4 General Purpose Control 4
lbits:3 reserved Reserved
lbits:1 feq Freeze ERQ
lbits:1 ffa Freeze FCP Assists
lbits:2 reserved1 Reserved
lbits:1 fis Freeze Inbound FCP Assists When Frame Placed in SFQ
lbits:1 fib Freeze Inbound FCP Assists
lbits:2 reserved2 Reserved
lbits:1 req Resume ERQ
lbits:1 rif Resume Inbound FCP Assists
lbits:1 rof Resume Outbound FCP Assists
lbits:12 reserved3 Reserved
lbits:1 crs Core Reset
{}
or tach_control (Offset 188) Tachyon DX2+ Control
<byte 11508>
ulong value As longword
endunion tach_control (Offset 188) Tachyon DX2+ Control
<byte 11512>
union tach_status (Offset 18C) Tachyon DX2+ Status
<byte 11512>
{field (By field)}
<byte 11512>
lbits:1 gp0 General Purpose I/O 0
lbits:1 gp1 General Purpose I/O 1
lbits:1 gp2 General Purpose I/O 2
lbits:1 gp3 General Purpose I/O 3
lbits:1 gp4 General Purpose Input 4
lbits:5 reserved Reserved
lbits:1 ipe Inbound Parity Error
lbits:1 ope Outbound Parity Error
lbits:4 reserved1 Reserved
lbits:1 eqf ERQ Frozen
lbits:1 iff Inbound FCP Assists Frozen
lbits:1 off Outbound FCP Assists Frozen
lbits:4 reserved2 Reserved
lbits:1 ifce Inbound FIFO CRC Error
lbits:1 ofce Outbound FIFO CRC Error
lbits:1 m66 66 Mhz Enabled
lbits:1 ile Inbound Link Control FIFO Empty
lbits:1 ole Outbound Link Control List Empty
lbits:1 ife Inbound FIFO Empty
lbits:1 ofe Outbound FIFO Empty
lbits:1 imf IMQ Full
lbits:1 ssf SFQ Full
{}
or tach_status (Offset 18C) Tachyon DX2+ Status
<byte 11512>
ulong value As longword
endunion tach_status (Offset 18C) Tachyon DX2+ Status
<byte 11516>
{rsvd7 ((Offset 190) Reserved)}
<byte 11516>
ulong value
{}
<byte 11520>
union hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 11520>
{field (By field)}
<byte 11520>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 11520>
ulong value As longword
endunion hi_pri_send1 (Offset 194) High Priority Send 1 (write only)
<byte 11524>
union hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 11524>
{field (By field)}
<byte 11524>
lbits:12 length Frame Length
lbits:7 reserved Reserved
lbits:12 upper_addr Frame Upper Address
lbits:1 reserved1 Reserved
{}
or hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 11524>
ulong value As longword
endunion hi_pri_send2 (Offset 198) High Priority Send 2 (write only)
<byte 11528>
union inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 11528>
{field (By field)}
<byte 11528>
lbits:24 reserved Reserved
lbits:8 sest_lru_count SEST LRU Count
{}
or inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 11528>
ulong value As longword
endunion inbound_rstat1 (Offset 19C) Inbound Resource Status 1
<byte 11532>
union inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 11532>
{field (By field)}
<byte 11532>
lbits:8 discd_frames Discarded Frame Count
lbits:24 reserved Reserved
{}
or inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 11532>
ulong value As longword
endunion inbound_rstat2 (Offset 1A0) Inbound Resource Status 2
<byte 11536>
union ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 11536>
{field (By field)}
<byte 11536>
lbits:28 threshold EE_Credit Zero Timer Threshold
lbits:4 reserved Reserved
{}
or ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 11536>
ulong value As longword
endunion ee_cr_z_tmr_thr (Offset 1A4) EE_Credit Zero Timer Threshold (write only)
<byte 11540>
union up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 11540>
{field (By field)}
<byte 11540>
lbits:12 reserved Reserved
lbits:1 upper_addr1 Upper Data Address--44 bit data space
lbits:19 upper_addr Upper Data Address
{}
or up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 11540>
ulong value As longword
endunion up_data_addr (Offset 1A8) Upper Data Address (write only)
<byte 11544>
union up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 11544>
{field (By field)}
<byte 11544>
lbits:32 upper_addr Upper Control Address
{}
or up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 11544>
ulong value As longword
endunion up_ctrl_addr (Offset 1AC) Upper Control Address (write only)
<byte 11548>
union dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 11548>
{field (By field)}
<byte 11548>
lbits:1 ef AL_PA 0xEF DHD Login Information
lbits:1 e8 AL_PA 0xE8 DHD Login Information
lbits:1 e4 AL_PA 0xE4 DHD Login Information
lbits:1 e2 AL_PA 0xE2 DHD Login Information
lbits:1 e1 AL_PA 0xE1 DHD Login Information
lbits:1 e0 AL_PA 0xE0 DHD Login Information
lbits:1 dc AL_PA 0xDC DHD Login Information
lbits:1 da AL_PA 0xDA DHD Login Information
lbits:1 d9 AL_PA 0xD9 DHD Login Information
lbits:1 d6 AL_PA 0xD6 DHD Login Information
lbits:1 d5 AL_PA 0xD5 DHD Login Information
lbits:1 d4 AL_PA 0xD4 DHD Login Information
lbits:1 d3 AL_PA 0xD3 DHD Login Information
lbits:1 d2 AL_PA 0xD2 DHD Login Information
lbits:1 d1 AL_PA 0xD1 DHD Login Information
lbits:1 ce AL_PA 0xCE DHD Login Information
lbits:1 cd AL_PA 0xCD DHD Login Information
lbits:1 cc AL_PA 0xCC DHD Login Information
lbits:1 cb AL_PA 0xCB DHD Login Information
lbits:1 ca AL_PA 0xCA DHD Login Information
lbits:1 c9 AL_PA 0xC9 DHD Login Information
lbits:1 c7 AL_PA 0xC7 DHD Login Information
lbits:1 c6 AL_PA 0xC6 DHD Login Information
lbits:1 c5 AL_PA 0xC5 DHD Login Information
lbits:1 c3 AL_PA 0xC3 DHD Login Information
lbits:1 bc AL_PA 0xBC DHD Login Information
lbits:1 ba AL_PA 0xBA DHD Login Information
lbits:1 b9 AL_PA 0xB9 DHD Login Information
lbits:1 b6 AL_PA 0xB6 DHD Login Information
lbits:1 b5 AL_PA 0xB5 DHD Login Information
lbits:1 b4 AL_PA 0xB4 DHD Login Information
lbits:1 b3 AL_PA 0xB3 DHD Login Information
{}
or dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 11548>
ulong value As longword
endunion dyn_half_dup3 (Offset 1B0) Dynamic Half Duplex 3
<byte 11552>
union dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 11552>
{field (By field)}
<byte 11552>
lbits:1 alpab2 AL_PA 0xB2 DHD Login Information
lbits:1 alpab1 AL_PA 0xB1 DHD Login Information
lbits:1 alpaae AL_PA 0xAE DHD Login Information
lbits:1 alpaad AL_PA 0xAD DHD Login Information
lbits:1 alpaac AL_PA 0xAC DHD Login Information
lbits:1 alpaab AL_PA 0xAB DHD Login Information
lbits:1 alpaaa AL_PA 0xAA DHD Login Information
lbits:1 alpaa9 AL_PA 0xA9 DHD Login Information
lbits:1 alpaa7 AL_PA 0xA7 DHD Login Information
lbits:1 alpaa6 AL_PA 0xA6 DHD Login Information
lbits:1 alpaa5 AL_PA 0xA5 DHD Login Information
lbits:1 alpaa3 AL_PA 0xA3 DHD Login Information
lbits:1 alpa9f AL_PA 0x9F DHD Login Information
lbits:1 alpa9e AL_PA 0x9E DHD Login Information
lbits:1 alpa9d AL_PA 0x9D DHD Login Information
lbits:1 alpa9b AL_PA 0x9B DHD Login Information
lbits:1 alpa98 AL_PA 0x98 DHD Login Information
lbits:1 alpa97 AL_PA 0x97 DHD Login Information
lbits:1 alpa90 AL_PA 0x90 DHD Login Information
lbits:1 alpa8f AL_PA 0x8F DHD Login Information
lbits:1 alpa88 AL_PA 0x88 DHD Login Information
lbits:1 alpa84 AL_PA 0x84 DHD Login Information
lbits:1 alpa82 AL_PA 0x82 DHD Login Information
lbits:1 alpa81 AL_PA 0x81 DHD Login Information
lbits:1 alpa80 AL_PA 0x80 DHD Login Information
lbits:1 alpa7c AL_PA 0x7C DHD Login Information
lbits:1 alpa7a AL_PA 0x7A DHD Login Information
lbits:1 alpa79 AL_PA 0x79 DHD Login Information
lbits:1 alpa76 AL_PA 0x76 DHD Login Information
lbits:1 alpa75 AL_PA 0x75 DHD Login Information
lbits:1 alpa74 AL_PA 0x74 DHD Login Information
lbits:1 alpa73 AL_PA 0x73 DHD Login Information
{}
or dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 11552>
ulong value As longword
endunion dyn_half_dup2 (Offset 1B4) Dynamic Half Duplex 2
<byte 11556>
union dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 11556>
{field (By field)}
<byte 11556>
lbits:1 alpa72 AL_PA 0x72 DHD Login Information
lbits:1 alpa71 AL_PA 0x71 DHD Login Information
lbits:1 alpa6e AL_PA 0x6E DHD Login Information
lbits:1 alpa6d AL_PA 0x6D DHD Login Information
lbits:1 alpa6c AL_PA 0x6C DHD Login Information
lbits:1 alpa6b AL_PA 0x6B DHD Login Information
lbits:1 alpa6a AL_PA 0x6A DHD Login Information
lbits:1 alpa69 AL_PA 0x69 DHD Login Information
lbits:1 alpa67 AL_PA 0x67 DHD Login Information
lbits:1 alpa66 AL_PA 0x66 DHD Login Information
lbits:1 alpa65 AL_PA 0x65 DHD Login Information
lbits:1 alpa63 AL_PA 0x63 DHD Login Information
lbits:1 alpa5c AL_PA 0x5C DHD Login Information
lbits:1 alpa5a AL_PA 0x5A DHD Login Information
lbits:1 alpa59 AL_PA 0x59 DHD Login Information
lbits:1 alpa56 AL_PA 0x56 DHD Login Information
lbits:1 alpa55 AL_PA 0x55 DHD Login Information
lbits:1 alpa54 AL_PA 0x54 DHD Login Information
lbits:1 alpa53 AL_PA 0x53 DHD Login Information
lbits:1 alpa52 AL_PA 0x52 DHD Login Information
lbits:1 alpa51 AL_PA 0x51 DHD Login Information
lbits:1 alpa4e AL_PA 0x4E DHD Login Information
lbits:1 alpa4d AL_PA 0x4D DHD Login Information
lbits:1 alpa4c AL_PA 0x4C DHD Login Information
lbits:1 alpa4b AL_PA 0x4B DHD Login Information
lbits:1 alpa4a AL_PA 0x4A DHD Login Information
lbits:1 alpa49 AL_PA 0x49 DHD Login Information
lbits:1 alpa47 AL_PA 0x47 DHD Login Information
lbits:1 alpa46 AL_PA 0x46 DHD Login Information
lbits:1 alpa45 AL_PA 0x45 DHD Login Information
lbits:1 alpa43 AL_PA 0x43 DHD Login Information
lbits:1 alpa3c AL_PA 0x3C DHD Login Information
{}
or dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 11556>
ulong value As longword
endunion dyn_half_dup1 (Offset 1B8) Dynamic Half Duplex 1
<byte 11560>
union dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 11560>
{field (By field)}
<byte 11560>
lbits:1 alpa3a AL_PA 0x3A DHD Login Information
lbits:1 alpa39 AL_PA 0x39 DHD Login Information
lbits:1 alpa36 AL_PA 0x36 DHD Login Information
lbits:1 alpa35 AL_PA 0x35 DHD Login Information
lbits:1 alpa34 AL_PA 0x34 DHD Login Information
lbits:1 alpa33 AL_PA 0x33 DHD Login Information
lbits:1 alpa32 AL_PA 0x32 DHD Login Information
lbits:1 alpa31 AL_PA 0x31 DHD Login Information
lbits:1 alpa2e AL_PA 0x2E DHD Login Information
lbits:1 alpa2d AL_PA 0x2D DHD Login Information
lbits:1 alpa2c AL_PA 0x2C DHD Login Information
lbits:1 alpa2b AL_PA 0x2B DHD Login Information
lbits:1 alpa2a AL_PA 0x2A DHD Login Information
lbits:1 alpa29 AL_PA 0x29 DHD Login Information
lbits:1 alpa27 AL_PA 0x27 DHD Login Information
lbits:1 alpa26 AL_PA 0x26 DHD Login Information
lbits:1 alpa25 AL_PA 0x25 DHD Login Information
lbits:1 alpa23 AL_PA 0x23 DHD Login Information
lbits:1 alpa1f AL_PA 0x1F DHD Login Information
lbits:1 alpa1e AL_PA 0x1E DHD Login Information
lbits:1 alpa1d AL_PA 0x1D DHD Login Information
lbits:1 alpa1b AL_PA 0x1B DHD Login Information
lbits:1 alpa18 AL_PA 0x18 DHD Login Information
lbits:1 alpa17 AL_PA 0x17 DHD Login Information
lbits:1 alpa10 AL_PA 0x10 DHD Login Information
lbits:1 alpa0f AL_PA 0x0F DHD Login Information
lbits:1 alpa08 AL_PA 0x08 DHD Login Information
lbits:1 alpa04 AL_PA 0x04 DHD Login Information
lbits:1 alpa02 AL_PA 0x02 DHD Login Information
lbits:1 alpa01 AL_PA 0x01 DHD Login Information
lbits:1 alpa00 AL_PA 0x00 DHD Login Information
lbits:1 reserved Reserved
{}
or dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 11560>
ulong value As longword
endunion dyn_half_dup0 (Offset 1BC) Dynamic Half Duplex 0
<byte 11564>
union fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 11564>
{field (By field)}
<byte 11564>
lbits:1 bli Bypass Loop Initialization
lbits:1 reserved Reserved
lbits:1 enp Enable N_Port Mode
lbits:1 lr Login Required
lbits:1 inif Initialize as Fabric
lbits:1 rf Respond to Fabric Address
lbits:1 blm Bypass Loop Map
lbits:1 sa Acquire Soft Address
lbits:1 ha Acquire Hard Address
lbits:1 aq Acquire Previously Acquired Address
lbits:1 fa Acquire Fabric Aquired Address
lbits:1 td Timer Disable
lbits:1 sap Skip Arbitration Phase
lbits:1 elb External Loopback/Pad Loopback
lbits:1 ilb Internal loopback
lbits:1 npi Initialize as N_Port
lbits:8 bb_credit BB_Credit
lbits:8 al_pa Desired AL_PA
{}
or fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 11564>
ulong value As longword
endunion fm_config1 (Offset 1C0) Frame Manager Configuration 1
<byte 11568>
union fm_control (Offset 1C4) Frame Manager Control
<byte 11568>
{field (By field)}
<byte 11568>
lbits:3 cmd State Machine Command
lbits:1 cl Close Loop Request
lbits:1 reserved Reserved
lbits:1 sp Send Prim_Reg
lbits:1 sq Primitive Sequence
lbits:25 reserved1 Reserved
{}
or fm_control (Offset 1C4) Frame Manager Control
<byte 11568>
ulong value As longword
endunion fm_control (Offset 1C4) Frame Manager Control
<byte 11572>
union fm_status (Offset 1C8) Frame Manager Status
<byte 11572>
{field (By field)}
<byte 11572>
lbits:4 psm Port State Machine
lbits:4 lsm Loop State Machine
lbits:1 ldn Link Down
lbits:1 lup Link Up
lbits:1 es Elastic Store Error
lbits:1 ce Credit Error
lbits:1 lf Link Failure
lbits:1 lg Login Required
lbits:1 ptx Primitive Transmitted
lbits:1 prx Primitive Received
lbits:1 ba Bad AL_PA
lbits:1 lpf LIPf
lbits:1 sto State Time-out
lbits:1 ols OLS/NOS Received
lbits:1 lpb Loop Port Bypass (LPB) Primitive Sequence Received
lbits:1 lpe Loop Port Enable (LPE) Primitive Sequence Received
lbits:1 drs Directed LIP Sequence Received
lbits:1 reserved Reserved
lbits:1 ls Loss of Signal
lbits:1 os Out of Synchronization
lbits:1 flt Link Fault
lbits:1 reserved1 Reserved
lbits:1 byp Node Bypassed
lbits:1 np Non-Participating
lbits:1 tp Transmit Parity Error
lbits:1 lp Loop
{}
or fm_status (Offset 1C8) Frame Manager Status
<byte 11572>
ulong value As longword
endunion fm_status (Offset 1C8) Frame Manager Status
<byte 11576>
union fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 11576>
{field (By field)}
<byte 11576>
lbits:16 ed_tov Error Detect Time-Out
lbits:9 rt_tov Receiver Transmitter Time-Out
lbits:7 reserved Reserved
{}
or fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 11576>
ulong value As longword
endunion fm_to_values1 (Offset 1CC) Frame Manager Time-Out Values 1
<byte 11580>
union fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 11580>
{field (By field)}
<byte 11580>
lbits:8 link_fail Link Fail Count
lbits:8 loss_of_sync Loss of Synchronization Count
lbits:8 bad_rx_char Bad Received Character Count
lbits:8 loss_of_signal Loss of Signal Count
{}
or fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 11580>
ulong value As longword
endunion fm_link_stat1 (Offset 1D0) Frame Manager Link Status 1
<byte 11584>
union fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 11584>
{field (By field)}
<byte 11584>
lbits:8 proto_er Protocol Error Count
lbits:8 bad_crc Bad CRC Count
lbits:8 dis_frm Discarded Frames
lbits:8 rx_eofa Received EOFa
{}
or fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 11584>
ulong value As longword
endunion fm_link_stat2 (Offset 1D4) Frame Manager Link Status 2
<byte 11588>
union fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 11588>
{field (By field)}
<byte 11588>
lbits:9 al_time Arbitrated Loop Time-Out
lbits:7 reserved Reserved
lbits:16 lp_tov Loop Time-Out
{}
or fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 11588>
ulong value As longword
endunion fm_to_values2 (Offset 1D8) Frame Manager Time-Out Values 2
<byte 11592>
union fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 11592>
{field (By field)}
<byte 11592>
lbits:24 bb0_timer BB_Credit Timer
lbits:8 reserved Reserved
{}
or fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 11592>
ulong value As longword
endunion fm_bb0_timer (Offset 1DC) Frame Manager BB_Credit Zero Timer
<byte 11596>
union fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 11596>
{field (By field)}
<byte 11596>
lbits:32 wwn World Wide Name
{}
or fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 11596>
ulong value As longword
endunion fm_wwn_hi (Offset 1E0) Frame Manager World Wide Name High
<byte 11600>
union fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 11600>
{field (By field)}
<byte 11600>
lbits:32 wwn World Wide Name
{}
or fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 11600>
ulong value As longword
endunion fm_wwn_lo (Offset 1E4) Frame Manager World Wide Name Low
<byte 11604>
union fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 11604>
{field (By field)}
<byte 11604>
lbits:8 lipf_alpa AL_PA of Most Recent LIPf Received
lbits:8 bad_alpa AL_PA of Most Recent OPN Sent and Returned Without Being Accepted
lbits:8 acq_alpa AL_PA Acquired During Loop Initialization
lbits:8 reserved Reserved
{}
or fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 11604>
ulong value As longword
endunion fm_rcvd_al_pa (Offset 1E8) Frame Manager Received AL_PA
<byte 11608>
union fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 11608>
{field (By field)}
<byte 11608>
lbits:24 prim_value Primitive to be Sent
lbits:8 reserved Reserved
{}
or fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 11608>
ulong value As longword
endunion fm_primitive (Offset 1EC) Frame Manager Primitive
<byte 11612>
union fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 11612>
{field (By field)}
<byte 11612>
lbits:8 exp_frm Expired Frames
lbits:24 reserved Reserved
{}
or fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 11612>
ulong value As longword
endunion fm_link_stat3 (Offset 1F0) Frame Manager Link Status 3
<byte 11616>
union fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 11616>
{field (By field)}
<byte 11616>
lbits:1 dac Disable Auto Close
lbits:2 nbc Non-zero Login BB_Credit
lbits:1 eei Enable ERR_INIT
lbits:1 icb Ignore Close Bit
lbits:2 atv Arbitration Threshold Value
lbits:1 gde Garbage Deletion Enable
lbits:8 laa Lowest Allowable AL_PA
lbits:5 reserved Reserved
lbits:1 dao Disable 2xAL_TIME Timeout on Open
lbits:3 reserved1 Reserved
lbits:1 prm Promiscuous Mode
lbits:1 wpe Wait For Port Enable
lbits:1 fmh Force Monitor State With Hard Address
lbits:1 fmn Force Monitor Non-participating State
lbits:1 dlm Disable Loop Master
lbits:1 dsa Disable Soft Address Selection
lbits:1 ilp Ignore LPB/LPE Primitive Sequences
{}
or fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 11616>
ulong value As longword
endunion fm_config2 (Offset 1F4) Frame Manager Configuration 2
<byte 11620>
union pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 11620>
{field (By field)}
<byte 11620>
{pci_rsvd1F8 ((Offset 1F8) Reserved)}
<byte 11620>
utiny value
{}
<byte 11621>
{pci_rsvd1F9 ((Offset 1F9) Reserved)}
<byte 11621>
utiny value
{}
<byte 11622>
union romctr (Offset 1FA) PCI ROM Control
<byte 11622>
{field (By field)}
<byte 11622>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or romctr (Offset 1FA) PCI ROM Control
<byte 11622>
utiny value As byte
endunion romctr (Offset 1FA) PCI ROM Control
<byte 11623>
union mctr (Offset 1FB) PCI Master Control
<byte 11623>
{field (By field)}
<byte 11623>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or mctr (Offset 1FB) PCI Master Control
<byte 11623>
utiny value As byte
endunion mctr (Offset 1FB) PCI Master Control
{}
or pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 11620>
ulong value As longword
endunion pci_reg_1F8 (Offset 1F8) PCI MCTR/ROMCTR/RESERVED
<byte 11624>
union pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 11624>
{field (By field)}
<byte 11624>
union softrst (Offset 1FC) PCI Interface Reset Control
<byte 11624>
{field (By field)}
<byte 11624>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or softrst (Offset 1FC) PCI Interface Reset Control
<byte 11624>
utiny value As byte
endunion softrst (Offset 1FC) PCI Interface Reset Control
<byte 11625>
union intpend (Offset 1FD) PCI Interrupt Pending
<byte 11625>
{field (By field)}
<byte 11625>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intpend (Offset 1FD) PCI Interrupt Pending
<byte 11625>
utiny value As byte
endunion intpend (Offset 1FD) PCI Interrupt Pending
<byte 11626>
union inten (Offset 1FE) PCI Interrupt Enable
<byte 11626>
{field (By field)}
<byte 11626>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or inten (Offset 1FE) PCI Interrupt Enable
<byte 11626>
utiny value As byte
endunion inten (Offset 1FE) PCI Interrupt Enable
<byte 11627>
union intstat (Offset 1FF) PCI Interrupt Status
<byte 11627>
{field (By field)}
<byte 11627>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or intstat (Offset 1FF) PCI Interrupt Status
<byte 11627>
utiny value As byte
endunion intstat (Offset 1FF) PCI Interrupt Status
{}
or pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
<byte 11624>
ulong value As longword
endunion pci_reg_1FC (Offset 1FC) INTSTAT/INTEN/INTPEND/SOFTRST
{}
endunion csr[9] Tachyon DX2+ CSR Registers
<byte 11628>
union ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11628>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11628>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11628>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11628>
{field (By field)}
<byte 11628>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11628>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11632>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11632>
{field (By field)}
<byte 11632>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11632>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11636>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11636>
{field (By field)}
<byte 11636>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11636>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[0] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11640>
union ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11640>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11640>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11640>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11640>
{field (By field)}
<byte 11640>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11640>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11644>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11644>
{field (By field)}
<byte 11644>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11644>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11648>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11648>
{field (By field)}
<byte 11648>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11648>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[1] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11652>
union ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11652>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11652>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11652>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11652>
{field (By field)}
<byte 11652>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11652>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11656>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11656>
{field (By field)}
<byte 11656>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11656>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11660>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11660>
{field (By field)}
<byte 11660>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11660>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[2] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11664>
union ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11664>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11664>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11664>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11664>
{field (By field)}
<byte 11664>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11664>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11668>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11668>
{field (By field)}
<byte 11668>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11668>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11672>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11672>
{field (By field)}
<byte 11672>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11672>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[3] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11676>
union ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11676>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11676>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11676>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11676>
{field (By field)}
<byte 11676>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11676>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11680>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11680>
{field (By field)}
<byte 11680>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11680>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11684>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11684>
{field (By field)}
<byte 11684>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11684>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[4] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11688>
union ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11688>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11688>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11688>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11688>
{field (By field)}
<byte 11688>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11688>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11692>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11692>
{field (By field)}
<byte 11692>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11692>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11696>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11696>
{field (By field)}
<byte 11696>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11696>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[5] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11700>
union ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11700>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11700>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11700>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11700>
{field (By field)}
<byte 11700>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11700>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11704>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11704>
{field (By field)}
<byte 11704>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11704>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11708>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11708>
{field (By field)}
<byte 11708>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11708>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[6] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11712>
union ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11712>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11712>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11712>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11712>
{field (By field)}
<byte 11712>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11712>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11716>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11716>
{field (By field)}
<byte 11716>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11716>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11720>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11720>
{field (By field)}
<byte 11720>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11720>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[7] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11724>
union ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11724>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11724>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11724>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11724>
{field (By field)}
<byte 11724>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11724>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11728>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11728>
{field (By field)}
<byte 11728>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11728>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11732>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11732>
{field (By field)}
<byte 11732>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11732>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[8] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11736>
union ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11736>
ulong[3] ncfgloa Tachyon DX2+ PCI Non-Configuration Registers -- Low As Longwords
or ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11736>
{ncfglo (Tachyon DX2+ PCI Non-Configuration Registers -- Low By Field)}
<byte 11736>
union ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11736>
{field (By field)}
<byte 11736>
lbits:3 mrbl Maximum Read Burst Length
lbits:3 mwbl Maximum Write Burst Length
lbits:26 rsvd1 Reserved
{}
or ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11736>
ulong value As longword
endunion ncfglo_fcr (Offset 0x200) Function Control Register
<byte 11740>
union ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11740>
{field (By field)}
<byte 11740>
lbits:2 sro Split Reads Outstanding
lbits:1 ssdr Servicing Split or Delayed Read
lbits:1 mie Message Interrupt Error
lbits:1 dte Discard Timer Expired
lbits:1 rbce Read Byte Count Excessive
lbits:1 sbce Split Completion Byte Count Excessive
lbits:1 madr59 MADDR5/MADDR9 status on reset deassertion for function_0/function_1
lbits:1 ape Attribute Parity Error
lbits:1 peod Parity Error on Outgoing Data
lbits:1 peid Parity Error on Incoming Data
lbits:1 pesc Parity Error on Split Completion
lbits:1 rfe Read fifo Empty
lbits:1 rff Read fifo Full
lbits:1 wfe Write fifo Empty
lbits:1 wff Write fifo Full
lbits:1 wfpe Write fifo Parity Error
lbits:1 rfpe Read fifo Parity Error
lbits:1 npt No Pending Transaction
lbits:1 pes Parity Error on Split Related Transaction
lbits:1 llos Live Loss of Signal
lbits:1 ftl Function Fatal
lbits:10 reserved Reserved
{}
or ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11740>
ulong value As longword
endunion ncfglo_fsr (Offset 0x204) Function Status Register
<byte 11744>
union ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11744>
{field (By field)}
<byte 11744>
lbits:12 rbc Remaining Byte Count
lbits:7 rla Remaining Lower Address
lbits:1 reserved Reserved
lbits:8 mi Message Index
lbits:4 mc Message Class
{}
or ncfglo_escr (Offset 0x208) Error Split Completion Register
<byte 11744>
ulong value As longword
endunion ncfglo_escr (Offset 0x208) Error Split Completion Register
{}
endunion ncfglo[9] Tachyon DX2+ PCI Non-Configuration Registers Low
<byte 11748>
union pcicfg[0] Tachyon DX2+ PCI Configuration Registers
<byte 11748>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[0] Tachyon DX2+ PCI Configuration Registers
<byte 11748>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 11748>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11748>
{field (By field)}
<byte 11748>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11748>
{field (By field)}
<byte 11748>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11748>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11750>
union pci_device_id (Offset 02) PCI Device ID
<byte 11750>
{field (By field)}
<byte 11750>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 11750>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11748>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11752>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 11752>
{field (By field)}
<byte 11752>
union pci_cmd (Offset 04) PCI Command
<byte 11752>
{field (By field)}
<byte 11752>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 11752>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 11754>
union pci_status (Offset 06) PCI Status
<byte 11754>
{field (By field)}
<byte 11754>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 11754>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 11752>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 11756>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 11756>
{field (By field)}
<byte 11756>
union pci_revid (Offset 08) PCI Revision
<byte 11756>
{field (By field)}
<byte 11756>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 11756>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 11757>
union pci_class (Offset 09) PCI Class
<byte 11757>
{field (By field)}
<byte 11757>
tbits:8 baseclcode Base Class Code
<byte 11758>
tbits:8 subclcode Subclass Code
<byte 11759>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 11757>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 11756>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 11760>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 11760>
{field (By field)}
<byte 11760>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 11760>
{field (By field)}
<byte 11760>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 11760>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 11761>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 11761>
{field (By field)}
<byte 11761>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 11761>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 11762>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 11762>
{field (By field)}
<byte 11762>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 11762>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 11763>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 11763>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 11760>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 11764>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 11764>
ulong value
{}
<byte 11768>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 11768>
ulong value
{}
<byte 11772>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 11772>
{field (By field)}
<byte 11772>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 11772>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 11776>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 11776>
{field (By field)}
<byte 11776>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 11776>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 11780>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 11780>
{field (By field)}
<byte 11780>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 11780>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 11784>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 11784>
{field (By field)}
<byte 11784>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 11784>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 11788>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 11788>
ulong value
{}
<byte 11792>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 11792>
{field (By field)}
<byte 11792>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 11792>
{field (By field)}
<byte 11792>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 11792>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 11794>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 11794>
{field (By field)}
<byte 11794>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 11794>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 11792>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 11796>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 11796>
{field (By field)}
<byte 11796>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 11796>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 11800>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 11800>
{field (By field)}
<byte 11800>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 11800>
{field (By field)}
<byte 11800>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 11800>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 11801>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 11801>
utiny value
{}
<byte 11802>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 11802>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 11800>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 11804>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 11804>
ulong value
{}
<byte 11808>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 11808>
{field (By field)}
<byte 11808>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 11808>
{field (By field)}
<byte 11808>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 11808>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 11809>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 11809>
{field (By field)}
<byte 11809>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 11809>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 11810>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 11810>
{field (By field)}
<byte 11810>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 11810>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 11811>
{reserved ((Offset 3F) Reserved)}
<byte 11811>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 11808>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 11812>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 11812>
{field (By field)}
<byte 11812>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 11812>
utiny value
{}
<byte 11813>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 11813>
utiny value
{}
<byte 11814>
union pci_romctr (Offset 42) PCI ROM Control
<byte 11814>
{field (By field)}
<byte 11814>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 11814>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 11815>
union pci_mctr (Offset 43) PCI Master Control
<byte 11815>
{field (By field)}
<byte 11815>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 11815>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 11812>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 11816>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 11816>
{field (By field)}
<byte 11816>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 11816>
{field (By field)}
<byte 11816>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 11816>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 11817>
union pci_intpend (Offset 45) PCI Interrupt
<byte 11817>
{field (By field)}
<byte 11817>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 11817>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 11818>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 11818>
{field (By field)}
<byte 11818>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 11818>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 11819>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 11819>
{field (By field)}
<byte 11819>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 11819>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 11816>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 11820>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 11820>
ulong value
{}
<byte 11824>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 11824>
ulong value
{}
<byte 11828>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 11828>
{field (By field)}
<byte 11828>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 11828>
{field (By field)}
<byte 11828>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 11828>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 11829>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 11829>
{field (By field)}
<byte 11829>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 11829>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 11830>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 11830>
{field (By field)}
<byte 11830>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 11830>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 11828>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 11832>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 11832>
{field (By field)}
<byte 11832>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 11832>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 11836>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 11836>
{field (By field)}
<byte 11836>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 11836>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 11840>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 11840>
{field (By field)}
<byte 11840>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 11840>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 11844>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 11844>
ulong value
{}
<byte 11848>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 11848>
{field (By field)}
<byte 11848>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 11848>
{field (By field)}
<byte 11848>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 11848>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 11849>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 11849>
{field (By field)}
<byte 11849>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 11849>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 11850>
union pci_mc (Offset 66) PCI Message Control Register
<byte 11850>
{field (By field)}
<byte 11850>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 11850>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 11848>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 11852>
union pci_ma (Offset 68) PCI Message Address
<byte 11852>
{field (By field)}
<byte 11852>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 11852>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 11856>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 11856>
{field (By field)}
<byte 11856>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 11856>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 11860>
union pci_md (Offset 70) PCI Message Data
<byte 11860>
{field (By field)}
<byte 11860>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 11860>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 11864>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 11864>
{field (By field)}
<byte 11864>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 11864>
{field (By field)}
<byte 11864>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 11864>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 11865>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 11865>
{field (By field)}
<byte 11865>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 11865>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 11866>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 11866>
{field (By field)}
<byte 11866>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 11866>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 11864>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 11868>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 11868>
{field (By field)}
<byte 11868>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 11868>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[0] Tachyon DX2+ PCI Configuration Registers
<byte 11872>
union pcicfg[1] Tachyon DX2+ PCI Configuration Registers
<byte 11872>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[1] Tachyon DX2+ PCI Configuration Registers
<byte 11872>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 11872>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11872>
{field (By field)}
<byte 11872>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11872>
{field (By field)}
<byte 11872>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11872>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11874>
union pci_device_id (Offset 02) PCI Device ID
<byte 11874>
{field (By field)}
<byte 11874>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 11874>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11872>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11876>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 11876>
{field (By field)}
<byte 11876>
union pci_cmd (Offset 04) PCI Command
<byte 11876>
{field (By field)}
<byte 11876>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 11876>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 11878>
union pci_status (Offset 06) PCI Status
<byte 11878>
{field (By field)}
<byte 11878>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 11878>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 11876>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 11880>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 11880>
{field (By field)}
<byte 11880>
union pci_revid (Offset 08) PCI Revision
<byte 11880>
{field (By field)}
<byte 11880>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 11880>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 11881>
union pci_class (Offset 09) PCI Class
<byte 11881>
{field (By field)}
<byte 11881>
tbits:8 baseclcode Base Class Code
<byte 11882>
tbits:8 subclcode Subclass Code
<byte 11883>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 11881>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 11880>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 11884>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 11884>
{field (By field)}
<byte 11884>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 11884>
{field (By field)}
<byte 11884>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 11884>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 11885>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 11885>
{field (By field)}
<byte 11885>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 11885>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 11886>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 11886>
{field (By field)}
<byte 11886>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 11886>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 11887>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 11887>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 11884>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 11888>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 11888>
ulong value
{}
<byte 11892>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 11892>
ulong value
{}
<byte 11896>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 11896>
{field (By field)}
<byte 11896>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 11896>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 11900>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 11900>
{field (By field)}
<byte 11900>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 11900>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 11904>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 11904>
{field (By field)}
<byte 11904>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 11904>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 11908>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 11908>
{field (By field)}
<byte 11908>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 11908>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 11912>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 11912>
ulong value
{}
<byte 11916>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 11916>
{field (By field)}
<byte 11916>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 11916>
{field (By field)}
<byte 11916>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 11916>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 11918>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 11918>
{field (By field)}
<byte 11918>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 11918>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 11916>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 11920>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 11920>
{field (By field)}
<byte 11920>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 11920>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 11924>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 11924>
{field (By field)}
<byte 11924>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 11924>
{field (By field)}
<byte 11924>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 11924>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 11925>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 11925>
utiny value
{}
<byte 11926>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 11926>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 11924>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 11928>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 11928>
ulong value
{}
<byte 11932>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 11932>
{field (By field)}
<byte 11932>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 11932>
{field (By field)}
<byte 11932>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 11932>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 11933>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 11933>
{field (By field)}
<byte 11933>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 11933>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 11934>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 11934>
{field (By field)}
<byte 11934>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 11934>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 11935>
{reserved ((Offset 3F) Reserved)}
<byte 11935>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 11932>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 11936>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 11936>
{field (By field)}
<byte 11936>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 11936>
utiny value
{}
<byte 11937>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 11937>
utiny value
{}
<byte 11938>
union pci_romctr (Offset 42) PCI ROM Control
<byte 11938>
{field (By field)}
<byte 11938>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 11938>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 11939>
union pci_mctr (Offset 43) PCI Master Control
<byte 11939>
{field (By field)}
<byte 11939>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 11939>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 11936>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 11940>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 11940>
{field (By field)}
<byte 11940>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 11940>
{field (By field)}
<byte 11940>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 11940>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 11941>
union pci_intpend (Offset 45) PCI Interrupt
<byte 11941>
{field (By field)}
<byte 11941>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 11941>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 11942>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 11942>
{field (By field)}
<byte 11942>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 11942>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 11943>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 11943>
{field (By field)}
<byte 11943>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 11943>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 11940>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 11944>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 11944>
ulong value
{}
<byte 11948>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 11948>
ulong value
{}
<byte 11952>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 11952>
{field (By field)}
<byte 11952>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 11952>
{field (By field)}
<byte 11952>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 11952>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 11953>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 11953>
{field (By field)}
<byte 11953>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 11953>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 11954>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 11954>
{field (By field)}
<byte 11954>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 11954>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 11952>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 11956>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 11956>
{field (By field)}
<byte 11956>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 11956>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 11960>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 11960>
{field (By field)}
<byte 11960>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 11960>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 11964>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 11964>
{field (By field)}
<byte 11964>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 11964>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 11968>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 11968>
ulong value
{}
<byte 11972>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 11972>
{field (By field)}
<byte 11972>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 11972>
{field (By field)}
<byte 11972>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 11972>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 11973>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 11973>
{field (By field)}
<byte 11973>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 11973>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 11974>
union pci_mc (Offset 66) PCI Message Control Register
<byte 11974>
{field (By field)}
<byte 11974>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 11974>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 11972>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 11976>
union pci_ma (Offset 68) PCI Message Address
<byte 11976>
{field (By field)}
<byte 11976>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 11976>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 11980>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 11980>
{field (By field)}
<byte 11980>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 11980>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 11984>
union pci_md (Offset 70) PCI Message Data
<byte 11984>
{field (By field)}
<byte 11984>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 11984>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 11988>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 11988>
{field (By field)}
<byte 11988>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 11988>
{field (By field)}
<byte 11988>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 11988>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 11989>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 11989>
{field (By field)}
<byte 11989>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 11989>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 11990>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 11990>
{field (By field)}
<byte 11990>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 11990>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 11988>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 11992>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 11992>
{field (By field)}
<byte 11992>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 11992>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[1] Tachyon DX2+ PCI Configuration Registers
<byte 11996>
union pcicfg[2] Tachyon DX2+ PCI Configuration Registers
<byte 11996>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[2] Tachyon DX2+ PCI Configuration Registers
<byte 11996>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 11996>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11996>
{field (By field)}
<byte 11996>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11996>
{field (By field)}
<byte 11996>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11996>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 11998>
union pci_device_id (Offset 02) PCI Device ID
<byte 11998>
{field (By field)}
<byte 11998>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 11998>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 11996>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12000>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12000>
{field (By field)}
<byte 12000>
union pci_cmd (Offset 04) PCI Command
<byte 12000>
{field (By field)}
<byte 12000>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12000>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12002>
union pci_status (Offset 06) PCI Status
<byte 12002>
{field (By field)}
<byte 12002>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12002>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12000>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12004>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12004>
{field (By field)}
<byte 12004>
union pci_revid (Offset 08) PCI Revision
<byte 12004>
{field (By field)}
<byte 12004>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12004>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12005>
union pci_class (Offset 09) PCI Class
<byte 12005>
{field (By field)}
<byte 12005>
tbits:8 baseclcode Base Class Code
<byte 12006>
tbits:8 subclcode Subclass Code
<byte 12007>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12005>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12004>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12008>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12008>
{field (By field)}
<byte 12008>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12008>
{field (By field)}
<byte 12008>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12008>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12009>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12009>
{field (By field)}
<byte 12009>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12009>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12010>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12010>
{field (By field)}
<byte 12010>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12010>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12011>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12011>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12008>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12012>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12012>
ulong value
{}
<byte 12016>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12016>
ulong value
{}
<byte 12020>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12020>
{field (By field)}
<byte 12020>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12020>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12024>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12024>
{field (By field)}
<byte 12024>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12024>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12028>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12028>
{field (By field)}
<byte 12028>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12028>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12032>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12032>
{field (By field)}
<byte 12032>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12032>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12036>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12036>
ulong value
{}
<byte 12040>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12040>
{field (By field)}
<byte 12040>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12040>
{field (By field)}
<byte 12040>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12040>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12042>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12042>
{field (By field)}
<byte 12042>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12042>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12040>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12044>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12044>
{field (By field)}
<byte 12044>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12044>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12048>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12048>
{field (By field)}
<byte 12048>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12048>
{field (By field)}
<byte 12048>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12048>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12049>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12049>
utiny value
{}
<byte 12050>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12050>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12048>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12052>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12052>
ulong value
{}
<byte 12056>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12056>
{field (By field)}
<byte 12056>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12056>
{field (By field)}
<byte 12056>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12056>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12057>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12057>
{field (By field)}
<byte 12057>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12057>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12058>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12058>
{field (By field)}
<byte 12058>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12058>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12059>
{reserved ((Offset 3F) Reserved)}
<byte 12059>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12056>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12060>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12060>
{field (By field)}
<byte 12060>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12060>
utiny value
{}
<byte 12061>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12061>
utiny value
{}
<byte 12062>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12062>
{field (By field)}
<byte 12062>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12062>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12063>
union pci_mctr (Offset 43) PCI Master Control
<byte 12063>
{field (By field)}
<byte 12063>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12063>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12060>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12064>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12064>
{field (By field)}
<byte 12064>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12064>
{field (By field)}
<byte 12064>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12064>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12065>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12065>
{field (By field)}
<byte 12065>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12065>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12066>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12066>
{field (By field)}
<byte 12066>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12066>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12067>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12067>
{field (By field)}
<byte 12067>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12067>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12064>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12068>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12068>
ulong value
{}
<byte 12072>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12072>
ulong value
{}
<byte 12076>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12076>
{field (By field)}
<byte 12076>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12076>
{field (By field)}
<byte 12076>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12076>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12077>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12077>
{field (By field)}
<byte 12077>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12077>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12078>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12078>
{field (By field)}
<byte 12078>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12078>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12076>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12080>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12080>
{field (By field)}
<byte 12080>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12080>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12084>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12084>
{field (By field)}
<byte 12084>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12084>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12088>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12088>
{field (By field)}
<byte 12088>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12088>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12092>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12092>
ulong value
{}
<byte 12096>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12096>
{field (By field)}
<byte 12096>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12096>
{field (By field)}
<byte 12096>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12096>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12097>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12097>
{field (By field)}
<byte 12097>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12097>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12098>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12098>
{field (By field)}
<byte 12098>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12098>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12096>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12100>
union pci_ma (Offset 68) PCI Message Address
<byte 12100>
{field (By field)}
<byte 12100>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12100>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12104>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12104>
{field (By field)}
<byte 12104>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12104>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12108>
union pci_md (Offset 70) PCI Message Data
<byte 12108>
{field (By field)}
<byte 12108>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12108>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12112>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12112>
{field (By field)}
<byte 12112>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12112>
{field (By field)}
<byte 12112>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12112>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12113>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12113>
{field (By field)}
<byte 12113>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12113>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12114>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12114>
{field (By field)}
<byte 12114>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12114>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12112>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12116>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12116>
{field (By field)}
<byte 12116>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12116>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[2] Tachyon DX2+ PCI Configuration Registers
<byte 12120>
union pcicfg[3] Tachyon DX2+ PCI Configuration Registers
<byte 12120>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[3] Tachyon DX2+ PCI Configuration Registers
<byte 12120>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12120>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12120>
{field (By field)}
<byte 12120>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12120>
{field (By field)}
<byte 12120>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12120>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12122>
union pci_device_id (Offset 02) PCI Device ID
<byte 12122>
{field (By field)}
<byte 12122>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12122>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12120>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12124>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12124>
{field (By field)}
<byte 12124>
union pci_cmd (Offset 04) PCI Command
<byte 12124>
{field (By field)}
<byte 12124>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12124>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12126>
union pci_status (Offset 06) PCI Status
<byte 12126>
{field (By field)}
<byte 12126>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12126>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12124>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12128>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12128>
{field (By field)}
<byte 12128>
union pci_revid (Offset 08) PCI Revision
<byte 12128>
{field (By field)}
<byte 12128>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12128>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12129>
union pci_class (Offset 09) PCI Class
<byte 12129>
{field (By field)}
<byte 12129>
tbits:8 baseclcode Base Class Code
<byte 12130>
tbits:8 subclcode Subclass Code
<byte 12131>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12129>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12128>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12132>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12132>
{field (By field)}
<byte 12132>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12132>
{field (By field)}
<byte 12132>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12132>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12133>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12133>
{field (By field)}
<byte 12133>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12133>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12134>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12134>
{field (By field)}
<byte 12134>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12134>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12135>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12135>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12132>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12136>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12136>
ulong value
{}
<byte 12140>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12140>
ulong value
{}
<byte 12144>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12144>
{field (By field)}
<byte 12144>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12144>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12148>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12148>
{field (By field)}
<byte 12148>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12148>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12152>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12152>
{field (By field)}
<byte 12152>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12152>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12156>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12156>
{field (By field)}
<byte 12156>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12156>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12160>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12160>
ulong value
{}
<byte 12164>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12164>
{field (By field)}
<byte 12164>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12164>
{field (By field)}
<byte 12164>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12164>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12166>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12166>
{field (By field)}
<byte 12166>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12166>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12164>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12168>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12168>
{field (By field)}
<byte 12168>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12168>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12172>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12172>
{field (By field)}
<byte 12172>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12172>
{field (By field)}
<byte 12172>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12172>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12173>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12173>
utiny value
{}
<byte 12174>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12174>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12172>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12176>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12176>
ulong value
{}
<byte 12180>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12180>
{field (By field)}
<byte 12180>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12180>
{field (By field)}
<byte 12180>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12180>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12181>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12181>
{field (By field)}
<byte 12181>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12181>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12182>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12182>
{field (By field)}
<byte 12182>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12182>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12183>
{reserved ((Offset 3F) Reserved)}
<byte 12183>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12180>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12184>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12184>
{field (By field)}
<byte 12184>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12184>
utiny value
{}
<byte 12185>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12185>
utiny value
{}
<byte 12186>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12186>
{field (By field)}
<byte 12186>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12186>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12187>
union pci_mctr (Offset 43) PCI Master Control
<byte 12187>
{field (By field)}
<byte 12187>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12187>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12184>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12188>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12188>
{field (By field)}
<byte 12188>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12188>
{field (By field)}
<byte 12188>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12188>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12189>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12189>
{field (By field)}
<byte 12189>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12189>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12190>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12190>
{field (By field)}
<byte 12190>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12190>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12191>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12191>
{field (By field)}
<byte 12191>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12191>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12188>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12192>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12192>
ulong value
{}
<byte 12196>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12196>
ulong value
{}
<byte 12200>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12200>
{field (By field)}
<byte 12200>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12200>
{field (By field)}
<byte 12200>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12200>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12201>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12201>
{field (By field)}
<byte 12201>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12201>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12202>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12202>
{field (By field)}
<byte 12202>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12202>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12200>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12204>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12204>
{field (By field)}
<byte 12204>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12204>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12208>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12208>
{field (By field)}
<byte 12208>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12208>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12212>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12212>
{field (By field)}
<byte 12212>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12212>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12216>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12216>
ulong value
{}
<byte 12220>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12220>
{field (By field)}
<byte 12220>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12220>
{field (By field)}
<byte 12220>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12220>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12221>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12221>
{field (By field)}
<byte 12221>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12221>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12222>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12222>
{field (By field)}
<byte 12222>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12222>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12220>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12224>
union pci_ma (Offset 68) PCI Message Address
<byte 12224>
{field (By field)}
<byte 12224>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12224>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12228>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12228>
{field (By field)}
<byte 12228>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12228>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12232>
union pci_md (Offset 70) PCI Message Data
<byte 12232>
{field (By field)}
<byte 12232>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12232>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12236>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12236>
{field (By field)}
<byte 12236>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12236>
{field (By field)}
<byte 12236>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12236>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12237>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12237>
{field (By field)}
<byte 12237>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12237>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12238>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12238>
{field (By field)}
<byte 12238>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12238>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12236>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12240>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12240>
{field (By field)}
<byte 12240>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12240>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[3] Tachyon DX2+ PCI Configuration Registers
<byte 12244>
union pcicfg[4] Tachyon DX2+ PCI Configuration Registers
<byte 12244>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[4] Tachyon DX2+ PCI Configuration Registers
<byte 12244>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12244>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12244>
{field (By field)}
<byte 12244>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12244>
{field (By field)}
<byte 12244>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12244>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12246>
union pci_device_id (Offset 02) PCI Device ID
<byte 12246>
{field (By field)}
<byte 12246>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12246>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12244>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12248>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12248>
{field (By field)}
<byte 12248>
union pci_cmd (Offset 04) PCI Command
<byte 12248>
{field (By field)}
<byte 12248>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12248>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12250>
union pci_status (Offset 06) PCI Status
<byte 12250>
{field (By field)}
<byte 12250>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12250>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12248>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12252>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12252>
{field (By field)}
<byte 12252>
union pci_revid (Offset 08) PCI Revision
<byte 12252>
{field (By field)}
<byte 12252>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12252>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12253>
union pci_class (Offset 09) PCI Class
<byte 12253>
{field (By field)}
<byte 12253>
tbits:8 baseclcode Base Class Code
<byte 12254>
tbits:8 subclcode Subclass Code
<byte 12255>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12253>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12252>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12256>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12256>
{field (By field)}
<byte 12256>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12256>
{field (By field)}
<byte 12256>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12256>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12257>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12257>
{field (By field)}
<byte 12257>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12257>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12258>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12258>
{field (By field)}
<byte 12258>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12258>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12259>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12259>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12256>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12260>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12260>
ulong value
{}
<byte 12264>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12264>
ulong value
{}
<byte 12268>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12268>
{field (By field)}
<byte 12268>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12268>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12272>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12272>
{field (By field)}
<byte 12272>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12272>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12276>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12276>
{field (By field)}
<byte 12276>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12276>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12280>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12280>
{field (By field)}
<byte 12280>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12280>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12284>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12284>
ulong value
{}
<byte 12288>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12288>
{field (By field)}
<byte 12288>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12288>
{field (By field)}
<byte 12288>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12288>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12290>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12290>
{field (By field)}
<byte 12290>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12290>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12288>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12292>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12292>
{field (By field)}
<byte 12292>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12292>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12296>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12296>
{field (By field)}
<byte 12296>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12296>
{field (By field)}
<byte 12296>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12296>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12297>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12297>
utiny value
{}
<byte 12298>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12298>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12296>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12300>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12300>
ulong value
{}
<byte 12304>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12304>
{field (By field)}
<byte 12304>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12304>
{field (By field)}
<byte 12304>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12304>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12305>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12305>
{field (By field)}
<byte 12305>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12305>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12306>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12306>
{field (By field)}
<byte 12306>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12306>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12307>
{reserved ((Offset 3F) Reserved)}
<byte 12307>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12304>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12308>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12308>
{field (By field)}
<byte 12308>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12308>
utiny value
{}
<byte 12309>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12309>
utiny value
{}
<byte 12310>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12310>
{field (By field)}
<byte 12310>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12310>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12311>
union pci_mctr (Offset 43) PCI Master Control
<byte 12311>
{field (By field)}
<byte 12311>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12311>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12308>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12312>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12312>
{field (By field)}
<byte 12312>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12312>
{field (By field)}
<byte 12312>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12312>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12313>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12313>
{field (By field)}
<byte 12313>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12313>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12314>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12314>
{field (By field)}
<byte 12314>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12314>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12315>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12315>
{field (By field)}
<byte 12315>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12315>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12312>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12316>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12316>
ulong value
{}
<byte 12320>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12320>
ulong value
{}
<byte 12324>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12324>
{field (By field)}
<byte 12324>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12324>
{field (By field)}
<byte 12324>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12324>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12325>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12325>
{field (By field)}
<byte 12325>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12325>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12326>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12326>
{field (By field)}
<byte 12326>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12326>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12324>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12328>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12328>
{field (By field)}
<byte 12328>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12328>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12332>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12332>
{field (By field)}
<byte 12332>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12332>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12336>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12336>
{field (By field)}
<byte 12336>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12336>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12340>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12340>
ulong value
{}
<byte 12344>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12344>
{field (By field)}
<byte 12344>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12344>
{field (By field)}
<byte 12344>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12344>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12345>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12345>
{field (By field)}
<byte 12345>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12345>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12346>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12346>
{field (By field)}
<byte 12346>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12346>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12344>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12348>
union pci_ma (Offset 68) PCI Message Address
<byte 12348>
{field (By field)}
<byte 12348>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12348>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12352>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12352>
{field (By field)}
<byte 12352>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12352>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12356>
union pci_md (Offset 70) PCI Message Data
<byte 12356>
{field (By field)}
<byte 12356>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12356>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12360>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12360>
{field (By field)}
<byte 12360>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12360>
{field (By field)}
<byte 12360>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12360>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12361>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12361>
{field (By field)}
<byte 12361>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12361>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12362>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12362>
{field (By field)}
<byte 12362>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12362>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12360>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12364>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12364>
{field (By field)}
<byte 12364>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12364>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[4] Tachyon DX2+ PCI Configuration Registers
<byte 12368>
union pcicfg[5] Tachyon DX2+ PCI Configuration Registers
<byte 12368>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[5] Tachyon DX2+ PCI Configuration Registers
<byte 12368>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12368>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12368>
{field (By field)}
<byte 12368>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12368>
{field (By field)}
<byte 12368>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12368>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12370>
union pci_device_id (Offset 02) PCI Device ID
<byte 12370>
{field (By field)}
<byte 12370>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12370>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12368>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12372>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12372>
{field (By field)}
<byte 12372>
union pci_cmd (Offset 04) PCI Command
<byte 12372>
{field (By field)}
<byte 12372>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12372>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12374>
union pci_status (Offset 06) PCI Status
<byte 12374>
{field (By field)}
<byte 12374>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12374>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12372>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12376>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12376>
{field (By field)}
<byte 12376>
union pci_revid (Offset 08) PCI Revision
<byte 12376>
{field (By field)}
<byte 12376>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12376>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12377>
union pci_class (Offset 09) PCI Class
<byte 12377>
{field (By field)}
<byte 12377>
tbits:8 baseclcode Base Class Code
<byte 12378>
tbits:8 subclcode Subclass Code
<byte 12379>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12377>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12376>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12380>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12380>
{field (By field)}
<byte 12380>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12380>
{field (By field)}
<byte 12380>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12380>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12381>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12381>
{field (By field)}
<byte 12381>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12381>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12382>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12382>
{field (By field)}
<byte 12382>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12382>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12383>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12383>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12380>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12384>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12384>
ulong value
{}
<byte 12388>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12388>
ulong value
{}
<byte 12392>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12392>
{field (By field)}
<byte 12392>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12392>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12396>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12396>
{field (By field)}
<byte 12396>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12396>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12400>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12400>
{field (By field)}
<byte 12400>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12400>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12404>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12404>
{field (By field)}
<byte 12404>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12404>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12408>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12408>
ulong value
{}
<byte 12412>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12412>
{field (By field)}
<byte 12412>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12412>
{field (By field)}
<byte 12412>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12412>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12414>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12414>
{field (By field)}
<byte 12414>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12414>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12412>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12416>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12416>
{field (By field)}
<byte 12416>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12416>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12420>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12420>
{field (By field)}
<byte 12420>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12420>
{field (By field)}
<byte 12420>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12420>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12421>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12421>
utiny value
{}
<byte 12422>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12422>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12420>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12424>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12424>
ulong value
{}
<byte 12428>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12428>
{field (By field)}
<byte 12428>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12428>
{field (By field)}
<byte 12428>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12428>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12429>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12429>
{field (By field)}
<byte 12429>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12429>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12430>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12430>
{field (By field)}
<byte 12430>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12430>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12431>
{reserved ((Offset 3F) Reserved)}
<byte 12431>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12428>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12432>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12432>
{field (By field)}
<byte 12432>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12432>
utiny value
{}
<byte 12433>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12433>
utiny value
{}
<byte 12434>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12434>
{field (By field)}
<byte 12434>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12434>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12435>
union pci_mctr (Offset 43) PCI Master Control
<byte 12435>
{field (By field)}
<byte 12435>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12435>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12432>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12436>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12436>
{field (By field)}
<byte 12436>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12436>
{field (By field)}
<byte 12436>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12436>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12437>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12437>
{field (By field)}
<byte 12437>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12437>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12438>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12438>
{field (By field)}
<byte 12438>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12438>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12439>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12439>
{field (By field)}
<byte 12439>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12439>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12436>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12440>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12440>
ulong value
{}
<byte 12444>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12444>
ulong value
{}
<byte 12448>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12448>
{field (By field)}
<byte 12448>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12448>
{field (By field)}
<byte 12448>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12448>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12449>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12449>
{field (By field)}
<byte 12449>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12449>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12450>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12450>
{field (By field)}
<byte 12450>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12450>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12448>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12452>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12452>
{field (By field)}
<byte 12452>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12452>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12456>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12456>
{field (By field)}
<byte 12456>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12456>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12460>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12460>
{field (By field)}
<byte 12460>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12460>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12464>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12464>
ulong value
{}
<byte 12468>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12468>
{field (By field)}
<byte 12468>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12468>
{field (By field)}
<byte 12468>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12468>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12469>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12469>
{field (By field)}
<byte 12469>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12469>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12470>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12470>
{field (By field)}
<byte 12470>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12470>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12468>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12472>
union pci_ma (Offset 68) PCI Message Address
<byte 12472>
{field (By field)}
<byte 12472>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12472>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12476>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12476>
{field (By field)}
<byte 12476>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12476>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12480>
union pci_md (Offset 70) PCI Message Data
<byte 12480>
{field (By field)}
<byte 12480>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12480>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12484>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12484>
{field (By field)}
<byte 12484>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12484>
{field (By field)}
<byte 12484>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12484>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12485>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12485>
{field (By field)}
<byte 12485>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12485>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12486>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12486>
{field (By field)}
<byte 12486>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12486>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12484>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12488>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12488>
{field (By field)}
<byte 12488>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12488>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[5] Tachyon DX2+ PCI Configuration Registers
<byte 12492>
union pcicfg[6] Tachyon DX2+ PCI Configuration Registers
<byte 12492>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[6] Tachyon DX2+ PCI Configuration Registers
<byte 12492>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12492>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12492>
{field (By field)}
<byte 12492>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12492>
{field (By field)}
<byte 12492>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12492>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12494>
union pci_device_id (Offset 02) PCI Device ID
<byte 12494>
{field (By field)}
<byte 12494>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12494>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12492>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12496>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12496>
{field (By field)}
<byte 12496>
union pci_cmd (Offset 04) PCI Command
<byte 12496>
{field (By field)}
<byte 12496>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12496>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12498>
union pci_status (Offset 06) PCI Status
<byte 12498>
{field (By field)}
<byte 12498>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12498>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12496>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12500>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12500>
{field (By field)}
<byte 12500>
union pci_revid (Offset 08) PCI Revision
<byte 12500>
{field (By field)}
<byte 12500>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12500>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12501>
union pci_class (Offset 09) PCI Class
<byte 12501>
{field (By field)}
<byte 12501>
tbits:8 baseclcode Base Class Code
<byte 12502>
tbits:8 subclcode Subclass Code
<byte 12503>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12501>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12500>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12504>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12504>
{field (By field)}
<byte 12504>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12504>
{field (By field)}
<byte 12504>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12504>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12505>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12505>
{field (By field)}
<byte 12505>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12505>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12506>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12506>
{field (By field)}
<byte 12506>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12506>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12507>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12507>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12504>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12508>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12508>
ulong value
{}
<byte 12512>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12512>
ulong value
{}
<byte 12516>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12516>
{field (By field)}
<byte 12516>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12516>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12520>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12520>
{field (By field)}
<byte 12520>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12520>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12524>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12524>
{field (By field)}
<byte 12524>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12524>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12528>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12528>
{field (By field)}
<byte 12528>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12528>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12532>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12532>
ulong value
{}
<byte 12536>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12536>
{field (By field)}
<byte 12536>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12536>
{field (By field)}
<byte 12536>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12536>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12538>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12538>
{field (By field)}
<byte 12538>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12538>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12536>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12540>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12540>
{field (By field)}
<byte 12540>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12540>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12544>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12544>
{field (By field)}
<byte 12544>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12544>
{field (By field)}
<byte 12544>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12544>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12545>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12545>
utiny value
{}
<byte 12546>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12546>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12544>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12548>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12548>
ulong value
{}
<byte 12552>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12552>
{field (By field)}
<byte 12552>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12552>
{field (By field)}
<byte 12552>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12552>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12553>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12553>
{field (By field)}
<byte 12553>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12553>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12554>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12554>
{field (By field)}
<byte 12554>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12554>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12555>
{reserved ((Offset 3F) Reserved)}
<byte 12555>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12552>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12556>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12556>
{field (By field)}
<byte 12556>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12556>
utiny value
{}
<byte 12557>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12557>
utiny value
{}
<byte 12558>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12558>
{field (By field)}
<byte 12558>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12558>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12559>
union pci_mctr (Offset 43) PCI Master Control
<byte 12559>
{field (By field)}
<byte 12559>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12559>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12556>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12560>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12560>
{field (By field)}
<byte 12560>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12560>
{field (By field)}
<byte 12560>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12560>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12561>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12561>
{field (By field)}
<byte 12561>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12561>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12562>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12562>
{field (By field)}
<byte 12562>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12562>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12563>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12563>
{field (By field)}
<byte 12563>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12563>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12560>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12564>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12564>
ulong value
{}
<byte 12568>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12568>
ulong value
{}
<byte 12572>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12572>
{field (By field)}
<byte 12572>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12572>
{field (By field)}
<byte 12572>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12572>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12573>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12573>
{field (By field)}
<byte 12573>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12573>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12574>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12574>
{field (By field)}
<byte 12574>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12574>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12572>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12576>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12576>
{field (By field)}
<byte 12576>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12576>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12580>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12580>
{field (By field)}
<byte 12580>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12580>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12584>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12584>
{field (By field)}
<byte 12584>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12584>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12588>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12588>
ulong value
{}
<byte 12592>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12592>
{field (By field)}
<byte 12592>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12592>
{field (By field)}
<byte 12592>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12592>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12593>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12593>
{field (By field)}
<byte 12593>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12593>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12594>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12594>
{field (By field)}
<byte 12594>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12594>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12592>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12596>
union pci_ma (Offset 68) PCI Message Address
<byte 12596>
{field (By field)}
<byte 12596>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12596>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12600>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12600>
{field (By field)}
<byte 12600>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12600>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12604>
union pci_md (Offset 70) PCI Message Data
<byte 12604>
{field (By field)}
<byte 12604>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12604>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12608>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12608>
{field (By field)}
<byte 12608>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12608>
{field (By field)}
<byte 12608>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12608>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12609>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12609>
{field (By field)}
<byte 12609>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12609>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12610>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12610>
{field (By field)}
<byte 12610>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12610>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12608>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12612>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12612>
{field (By field)}
<byte 12612>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12612>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[6] Tachyon DX2+ PCI Configuration Registers
<byte 12616>
union pcicfg[7] Tachyon DX2+ PCI Configuration Registers
<byte 12616>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[7] Tachyon DX2+ PCI Configuration Registers
<byte 12616>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12616>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12616>
{field (By field)}
<byte 12616>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12616>
{field (By field)}
<byte 12616>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12616>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12618>
union pci_device_id (Offset 02) PCI Device ID
<byte 12618>
{field (By field)}
<byte 12618>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12618>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12616>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12620>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12620>
{field (By field)}
<byte 12620>
union pci_cmd (Offset 04) PCI Command
<byte 12620>
{field (By field)}
<byte 12620>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12620>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12622>
union pci_status (Offset 06) PCI Status
<byte 12622>
{field (By field)}
<byte 12622>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12622>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12620>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12624>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12624>
{field (By field)}
<byte 12624>
union pci_revid (Offset 08) PCI Revision
<byte 12624>
{field (By field)}
<byte 12624>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12624>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12625>
union pci_class (Offset 09) PCI Class
<byte 12625>
{field (By field)}
<byte 12625>
tbits:8 baseclcode Base Class Code
<byte 12626>
tbits:8 subclcode Subclass Code
<byte 12627>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12625>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12624>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12628>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12628>
{field (By field)}
<byte 12628>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12628>
{field (By field)}
<byte 12628>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12628>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12629>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12629>
{field (By field)}
<byte 12629>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12629>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12630>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12630>
{field (By field)}
<byte 12630>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12630>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12631>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12631>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12628>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12632>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12632>
ulong value
{}
<byte 12636>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12636>
ulong value
{}
<byte 12640>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12640>
{field (By field)}
<byte 12640>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12640>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12644>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12644>
{field (By field)}
<byte 12644>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12644>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12648>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12648>
{field (By field)}
<byte 12648>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12648>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12652>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12652>
{field (By field)}
<byte 12652>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12652>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12656>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12656>
ulong value
{}
<byte 12660>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12660>
{field (By field)}
<byte 12660>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12660>
{field (By field)}
<byte 12660>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12660>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12662>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12662>
{field (By field)}
<byte 12662>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12662>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12660>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12664>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12664>
{field (By field)}
<byte 12664>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12664>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12668>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12668>
{field (By field)}
<byte 12668>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12668>
{field (By field)}
<byte 12668>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12668>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12669>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12669>
utiny value
{}
<byte 12670>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12670>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12668>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12672>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12672>
ulong value
{}
<byte 12676>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12676>
{field (By field)}
<byte 12676>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12676>
{field (By field)}
<byte 12676>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12676>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12677>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12677>
{field (By field)}
<byte 12677>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12677>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12678>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12678>
{field (By field)}
<byte 12678>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12678>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12679>
{reserved ((Offset 3F) Reserved)}
<byte 12679>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12676>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12680>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12680>
{field (By field)}
<byte 12680>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12680>
utiny value
{}
<byte 12681>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12681>
utiny value
{}
<byte 12682>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12682>
{field (By field)}
<byte 12682>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12682>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12683>
union pci_mctr (Offset 43) PCI Master Control
<byte 12683>
{field (By field)}
<byte 12683>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12683>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12680>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12684>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12684>
{field (By field)}
<byte 12684>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12684>
{field (By field)}
<byte 12684>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12684>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12685>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12685>
{field (By field)}
<byte 12685>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12685>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12686>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12686>
{field (By field)}
<byte 12686>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12686>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12687>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12687>
{field (By field)}
<byte 12687>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12687>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12684>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12688>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12688>
ulong value
{}
<byte 12692>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12692>
ulong value
{}
<byte 12696>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12696>
{field (By field)}
<byte 12696>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12696>
{field (By field)}
<byte 12696>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12696>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12697>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12697>
{field (By field)}
<byte 12697>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12697>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12698>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12698>
{field (By field)}
<byte 12698>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12698>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12696>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12700>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12700>
{field (By field)}
<byte 12700>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12700>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12704>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12704>
{field (By field)}
<byte 12704>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12704>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12708>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12708>
{field (By field)}
<byte 12708>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12708>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12712>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12712>
ulong value
{}
<byte 12716>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12716>
{field (By field)}
<byte 12716>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12716>
{field (By field)}
<byte 12716>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12716>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12717>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12717>
{field (By field)}
<byte 12717>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12717>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12718>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12718>
{field (By field)}
<byte 12718>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12718>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12716>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12720>
union pci_ma (Offset 68) PCI Message Address
<byte 12720>
{field (By field)}
<byte 12720>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12720>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12724>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12724>
{field (By field)}
<byte 12724>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12724>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12728>
union pci_md (Offset 70) PCI Message Data
<byte 12728>
{field (By field)}
<byte 12728>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12728>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12732>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12732>
{field (By field)}
<byte 12732>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12732>
{field (By field)}
<byte 12732>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12732>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12733>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12733>
{field (By field)}
<byte 12733>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12733>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12734>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12734>
{field (By field)}
<byte 12734>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12734>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12732>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12736>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12736>
{field (By field)}
<byte 12736>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12736>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[7] Tachyon DX2+ PCI Configuration Registers
<byte 12740>
union pcicfg[8] Tachyon DX2+ PCI Configuration Registers
<byte 12740>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[8] Tachyon DX2+ PCI Configuration Registers
<byte 12740>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12740>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12740>
{field (By field)}
<byte 12740>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12740>
{field (By field)}
<byte 12740>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12740>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12742>
union pci_device_id (Offset 02) PCI Device ID
<byte 12742>
{field (By field)}
<byte 12742>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12742>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12740>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12744>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12744>
{field (By field)}
<byte 12744>
union pci_cmd (Offset 04) PCI Command
<byte 12744>
{field (By field)}
<byte 12744>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12744>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12746>
union pci_status (Offset 06) PCI Status
<byte 12746>
{field (By field)}
<byte 12746>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12746>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12744>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12748>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12748>
{field (By field)}
<byte 12748>
union pci_revid (Offset 08) PCI Revision
<byte 12748>
{field (By field)}
<byte 12748>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12748>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12749>
union pci_class (Offset 09) PCI Class
<byte 12749>
{field (By field)}
<byte 12749>
tbits:8 baseclcode Base Class Code
<byte 12750>
tbits:8 subclcode Subclass Code
<byte 12751>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12749>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12748>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12752>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12752>
{field (By field)}
<byte 12752>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12752>
{field (By field)}
<byte 12752>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12752>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12753>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12753>
{field (By field)}
<byte 12753>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12753>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12754>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12754>
{field (By field)}
<byte 12754>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12754>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12755>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12755>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12752>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12756>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12756>
ulong value
{}
<byte 12760>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12760>
ulong value
{}
<byte 12764>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12764>
{field (By field)}
<byte 12764>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12764>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12768>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12768>
{field (By field)}
<byte 12768>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12768>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12772>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12772>
{field (By field)}
<byte 12772>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12772>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12776>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12776>
{field (By field)}
<byte 12776>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12776>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12780>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12780>
ulong value
{}
<byte 12784>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12784>
{field (By field)}
<byte 12784>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12784>
{field (By field)}
<byte 12784>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12784>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12786>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12786>
{field (By field)}
<byte 12786>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12786>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12784>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12788>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12788>
{field (By field)}
<byte 12788>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12788>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12792>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12792>
{field (By field)}
<byte 12792>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12792>
{field (By field)}
<byte 12792>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12792>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12793>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12793>
utiny value
{}
<byte 12794>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12794>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12792>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12796>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12796>
ulong value
{}
<byte 12800>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12800>
{field (By field)}
<byte 12800>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12800>
{field (By field)}
<byte 12800>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12800>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12801>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12801>
{field (By field)}
<byte 12801>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12801>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12802>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12802>
{field (By field)}
<byte 12802>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12802>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12803>
{reserved ((Offset 3F) Reserved)}
<byte 12803>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12800>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12804>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12804>
{field (By field)}
<byte 12804>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12804>
utiny value
{}
<byte 12805>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12805>
utiny value
{}
<byte 12806>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12806>
{field (By field)}
<byte 12806>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12806>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12807>
union pci_mctr (Offset 43) PCI Master Control
<byte 12807>
{field (By field)}
<byte 12807>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12807>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12804>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12808>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12808>
{field (By field)}
<byte 12808>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12808>
{field (By field)}
<byte 12808>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12808>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12809>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12809>
{field (By field)}
<byte 12809>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12809>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12810>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12810>
{field (By field)}
<byte 12810>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12810>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12811>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12811>
{field (By field)}
<byte 12811>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12811>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12808>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12812>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12812>
ulong value
{}
<byte 12816>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12816>
ulong value
{}
<byte 12820>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12820>
{field (By field)}
<byte 12820>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12820>
{field (By field)}
<byte 12820>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12820>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12821>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12821>
{field (By field)}
<byte 12821>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12821>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12822>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12822>
{field (By field)}
<byte 12822>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12822>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12820>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12824>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12824>
{field (By field)}
<byte 12824>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12824>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12828>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12828>
{field (By field)}
<byte 12828>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12828>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12832>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12832>
{field (By field)}
<byte 12832>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12832>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12836>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12836>
ulong value
{}
<byte 12840>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12840>
{field (By field)}
<byte 12840>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12840>
{field (By field)}
<byte 12840>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12840>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12841>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12841>
{field (By field)}
<byte 12841>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12841>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12842>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12842>
{field (By field)}
<byte 12842>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12842>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12840>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12844>
union pci_ma (Offset 68) PCI Message Address
<byte 12844>
{field (By field)}
<byte 12844>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12844>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12848>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12848>
{field (By field)}
<byte 12848>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12848>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12852>
union pci_md (Offset 70) PCI Message Data
<byte 12852>
{field (By field)}
<byte 12852>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12852>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12856>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12856>
{field (By field)}
<byte 12856>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12856>
{field (By field)}
<byte 12856>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12856>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12857>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12857>
{field (By field)}
<byte 12857>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12857>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12858>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12858>
{field (By field)}
<byte 12858>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12858>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12856>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12860>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12860>
{field (By field)}
<byte 12860>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12860>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[8] Tachyon DX2+ PCI Configuration Registers
<byte 12864>
union pcicfg[9] Tachyon DX2+ PCI Configuration Registers
<byte 12864>
ulong[31] pcicfga Tachyon DX2+ PCI Configuration Registers As Longwords
or pcicfg[9] Tachyon DX2+ PCI Configuration Registers
<byte 12864>
{pcicfg (Tachyon DX2+ PCI Configuration Registers By Field)}
<byte 12864>
union pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12864>
{field (By field)}
<byte 12864>
union pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12864>
{field (By field)}
<byte 12864>
bits:16 id ID
{}
or pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12864>
ushort value As word
endunion pci_vendor_id (Offset 00) PCI Vendor ID
<byte 12866>
union pci_device_id (Offset 02) PCI Device ID
<byte 12866>
{field (By field)}
<byte 12866>
bits:16 id ID
{}
or pci_device_id (Offset 02) PCI Device ID
<byte 12866>
ushort value As word
endunion pci_device_id (Offset 02) PCI Device ID
{}
or pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12864>
ulong value As longword
endunion pcicfg_reg_00 (Offset 00) PCI VENDID/DEVID
<byte 12868>
union pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12868>
{field (By field)}
<byte 12868>
union pci_cmd (Offset 04) PCI Command
<byte 12868>
{field (By field)}
<byte 12868>
bits:1 io_access I/O Access Control
bits:1 mem_access Memory Access Control
bits:1 pcim_en PCI Master Enable
bits:1 scycle_en Special Cycle Enable (read only, always returns 0)
bits:1 memwinv Memory Write & Invalidate
bits:1 paltsnp_en Palette Snooping Enable (read only, always returns 0)
bits:1 perrrsp Parity Error Response
bits:1 waitcycctrl Wait Cycle Control
bits:1 serrx_en SERR# Enable
bits:1 fbbw_en Fast Back-to-Back Write enable (read only, always returns 0)
bits:6 rsvd Reserved
{}
or pci_cmd (Offset 04) PCI Command
<byte 12868>
ushort value As word
endunion pci_cmd (Offset 04) PCI Command
<byte 12870>
union pci_status (Offset 06) PCI Status
<byte 12870>
{field (By field)}
<byte 12870>
bits:4 rsvd Reserved
bits:1 cpl New Capabilities
bits:1 cap66mhz 66MHz Capable
bits:1 udfsup UDF Supported (read only, always returns 0)
bits:1 capfbbw Fast Back-to-Back Capable (read only, always returns 0)
bits:1 dperr Data Parity Error Detected
bits:2 devsel_time PCI_DEVSEL# response timing (read only, always returns 1)
bits:1 sgnltabrt Signaled Target Abort
bits:1 rcvdtabrt Received Target Abort
bits:1 rcvdmabrt Received Master Abort
bits:1 sgnlsyserr Signaled System Error
bits:1 perr Detected Parity Error
{}
or pci_status (Offset 06) PCI Status
<byte 12870>
ushort value As word
endunion pci_status (Offset 06) PCI Status
{}
or pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12868>
ulong value As longword
endunion pcicfg_reg_04 (Offset 04) PCI CMD/STATUS
<byte 12872>
union pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12872>
{field (By field)}
<byte 12872>
union pci_revid (Offset 08) PCI Revision
<byte 12872>
{field (By field)}
<byte 12872>
tbits:2 minor Minor
tbits:3 major Major
tbits:3 res Reserved
{}
or pci_revid (Offset 08) PCI Revision
<byte 12872>
utiny value As byte
endunion pci_revid (Offset 08) PCI Revision
<byte 12873>
union pci_class (Offset 09) PCI Class
<byte 12873>
{field (By field)}
<byte 12873>
tbits:8 baseclcode Base Class Code
<byte 12874>
tbits:8 subclcode Subclass Code
<byte 12875>
tbits:8 reglevpi Register Level Programming Interface
{}
or pci_class (Offset 09) PCI Class
<byte 12873>
utiny[3] value As byte array
endunion pci_class (Offset 09) PCI Class
{}
or pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12872>
ulong value As longword
endunion pcicfg_reg_08 (Offset 08) PCI REVID/CLASS
<byte 12876>
union pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12876>
{field (By field)}
<byte 12876>
union pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12876>
{field (By field)}
<byte 12876>
tbits:8 size PCI cache line size
{}
or pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12876>
utiny value As byte
endunion pci_clsize (Offset 0C) PCI Cache Line Size
<byte 12877>
union pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12877>
{field (By field)}
<byte 12877>
tbits:8 tmr PCI latency timer
{}
or pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12877>
utiny value As byte
endunion pci_lattmr (Offset 0D) PCI Latency Timer
<byte 12878>
union pci_hdrtype (Offset 0E) PCI Header Type
<byte 12878>
{field (By field)}
<byte 12878>
tbits:8 type PCI header type (read only)
{}
or pci_hdrtype (Offset 0E) PCI Header Type
<byte 12878>
utiny value As byte
endunion pci_hdrtype (Offset 0E) PCI Header Type
<byte 12879>
{pci_rsvd0f ((Offset 0F) Reserved (BIST))}
<byte 12879>
utiny value
{}
{}
or pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12876>
ulong value As longword
endunion pcicfg_reg_0C (Offset 0C) PCI CLSIZE/LATTMR/ HDRTYPE/RESDBIST
<byte 12880>
{pci_rsvd10_13 ((Offset 10) Reserved (RSVBAR))}
<byte 12880>
ulong value
{}
<byte 12884>
{pci_rsvd14_17 ((Offset 14) Reserved (RSVBAR))}
<byte 12884>
ulong value
{}
<byte 12888>
union pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12888>
{field (By field)}
<byte 12888>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12888>
ulong value As longword
endunion pci_iobasel (Offset 18) PCI Lower I/O Base Address
<byte 12892>
union pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12892>
{field (By field)}
<byte 12892>
lbits:1 memspace I/O Space Indicator
lbits:7 alwayszero Always read as zero
lbits:24 baseaddr Base Address
{}
or pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12892>
ulong value As longword
endunion pci_iobaseu (Offset 1C) PCI Upper I/O Base Address
<byte 12896>
union pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12896>
{field (By field)}
<byte 12896>
lbits:1 memspace Memory Space Indicator
lbits:2 loctype Location Type
lbits:1 prefetch Prefetchable
lbits:9 alwayszero Always read as zero
lbits:19 baseaddr Lower Base Address
{}
or pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12896>
ulong value As longword (Bits 31:0)
endunion pci_membasel (Offset 20) PCI Lower Memory Address Base
<byte 12900>
union pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12900>
{field (By field)}
<byte 12900>
lbits:32 baseaddr Upper Base Address
{}
or pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12900>
ulong value As longword (Bits 63:32)
endunion pci_membaseu (Offset 24) PCI Upper Memory Address Base
<byte 12904>
{pci_rsrvd28_2b ((Offset 28) Reserved)}
<byte 12904>
ulong value
{}
<byte 12908>
union pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12908>
{field (By field)}
<byte 12908>
union pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12908>
{field (By field)}
<byte 12908>
bits:16 id ID
{}
or pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12908>
ushort value As word
endunion pci_ssvdor_id (Offset 2C) PCI Subsystem Vendor ID
<byte 12910>
union pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12910>
{field (By field)}
<byte 12910>
bits:16 id ID
{}
or pci_subsys_id (Offset 2E) PCI Subsystem ID
<byte 12910>
ushort value As word
endunion pci_subsys_id (Offset 2E) PCI Subsystem ID
{}
or pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12908>
ulong value As longword
endunion pcicfg_reg_2C (Offset 2C) PCI SSVDOR/SUBSYSID
<byte 12912>
union pci_rombase (Offset 30) PCI ROM Base Address
<byte 12912>
{field (By field)}
<byte 12912>
lbits:1 decode_en Decode enable
lbits:16 rsvd Reserved - always zero
lbits:15 address Address Decoding
{}
or pci_rombase (Offset 30) PCI ROM Base Address
<byte 12912>
ulong value As longword
endunion pci_rombase (Offset 30) PCI ROM Base Address
<byte 12916>
union pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12916>
{field (By field)}
<byte 12916>
union pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12916>
{field (By field)}
<byte 12916>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12916>
utiny value As byte
endunion pci_cap_ptr (Offset 34) PCI Capabilities Pointer
<byte 12917>
{pci_rsvd35 ((Offset 35) Reserved)}
<byte 12917>
utiny value
{}
<byte 12918>
{pci_rsvd36_37 ((Offset 36) Reserved)}
<byte 12918>
ushort value
{}
{}
or pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12916>
ulong value As longword
endunion pcicfg_reg_34 (Offset 34) PCI CAPPTR/ RESERVED
<byte 12920>
{pci_rsvd38_3b ((Offset 38) Reserved)}
<byte 12920>
ulong value
{}
<byte 12924>
union pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12924>
{field (By field)}
<byte 12924>
union pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12924>
{field (By field)}
<byte 12924>
tbits:8 line PCI Interrupt Line
{}
or pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12924>
utiny value As byte
endunion pci_int_line (Offset 3C) PCI Interrupt Line
<byte 12925>
union pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12925>
{field (By field)}
<byte 12925>
tbits:8 pin PCI Interrupt Pin (read only)
{}
or pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12925>
utiny value As byte
endunion pci_int_pin (Offset 3D) PCI Interrupt Pin
<byte 12926>
union pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12926>
{field (By field)}
<byte 12926>
tbits:8 grant PCI Minimum Grant (read only)
{}
or pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12926>
utiny value As byte
endunion pci_min_gnt (Offset 3E) PCI Minimum Grant
<byte 12927>
{reserved ((Offset 3F) Reserved)}
<byte 12927>
utiny value
{}
{}
or pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12924>
ulong value As longword
endunion pcicfg_reg_3C (Offset 3C) PCI INTLINE/ INTPIN/MINGNT/RESERVED
<byte 12928>
union pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12928>
{field (By field)}
<byte 12928>
{pci_rsvd40 ((Offset 40) Reserved)}
<byte 12928>
utiny value
{}
<byte 12929>
{pci_rsvd41 ((Offset 41) Reserved)}
<byte 12929>
utiny value
{}
<byte 12930>
union pci_romctr (Offset 42) PCI ROM Control
<byte 12930>
{field (By field)}
<byte 12930>
tbits:1 vpp_en ROM VPP Enable
tbits:1 fla Flash Installed (read only)
tbits:1 rom ROM Installed (read only)
tbits:5 reserved Reserved
{}
or pci_romctr (Offset 42) PCI ROM Control
<byte 12930>
utiny value As byte
endunion pci_romctr (Offset 42) PCI ROM Control
<byte 12931>
union pci_mctr (Offset 43) PCI Master Control
<byte 12931>
{field (By field)}
<byte 12931>
tbits:2 reserved1 Reserved
tbits:1 p64 PCI Present and Active
tbits:4 reserved Reserved
tbits:1 dlt Disable Latency Timer
{}
or pci_mctr (Offset 43) PCI Master Control
<byte 12931>
utiny value As byte
endunion pci_mctr (Offset 43) PCI Master Control
{}
or pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12928>
ulong value As longword
endunion pcicfg_reg_40 (Offset 40) PCI RESERVED/ ROMCTR/MCTR
<byte 12932>
union pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12932>
{field (By field)}
<byte 12932>
union pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12932>
{field (By field)}
<byte 12932>
tbits:1 rst PCI Interface Soft Reset
tbits:7 reserved Reserved
{}
or pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12932>
utiny value As byte
endunion pci_softrst (Offset 44) PCI Interface Reset Control
<byte 12933>
union pci_intpend (Offset 45) PCI Interrupt
<byte 12933>
{field (By field)}
<byte 12933>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_intpend (Offset 45) PCI Interrupt
<byte 12933>
utiny value As byte
endunion pci_intpend (Offset 45) PCI Interrupt
<byte 12934>
union pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12934>
{field (By field)}
<byte 12934>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12934>
utiny value As byte
endunion pci_inten (Offset 46) PCI Interrupt Enable Pending
<byte 12935>
union pci_instat (Offset 47) PCI Interrupt Status
<byte 12935>
{field (By field)}
<byte 12935>
tbits:1 per PCI Error Detected Interrupt
tbits:1 der Device Error Detected Interrupt
tbits:1 fint Function Interrupt
tbits:2 reserved1 Reserved
tbits:1 ube Unsupported Byte Enables
tbits:2 reserved Reserved
{}
or pci_instat (Offset 47) PCI Interrupt Status
<byte 12935>
utiny value As byte
endunion pci_instat (Offset 47) PCI Interrupt Status
{}
or pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12932>
ulong value As longword
endunion pcicfg_reg_44 (Offset 44) PCI SOFTRST/ INTPEND/INTEN/INSTAT
<byte 12936>
{pci_rsvd48_4b ((Offset 48) Reserved)}
<byte 12936>
ulong value
{}
<byte 12940>
{pci_rsvd4c_4f ((Offset 4C) Reserved)}
<byte 12940>
ulong value
{}
<byte 12944>
union pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12944>
{field (By field)}
<byte 12944>
union pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12944>
{field (By field)}
<byte 12944>
tbits:8 cap_id Capability structure identifier.
{}
or pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12944>
utiny value As byte
endunion pci_cap_id (Offset 50) PCI Capabilities Identifier
<byte 12945>
union pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12945>
{field (By field)}
<byte 12945>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12945>
utiny value As byte
endunion pci_cap_nextp (Offset 51) PCI Power Management Next Capabilities
<byte 12946>
union pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12946>
{field (By field)}
<byte 12946>
bits:3 ver PCI Power Management Specification Version
bits:1 clk PME Clock
bits:1 aps Auxilliary Power Source
bits:1 dsi Device Specific Initialization
bits:3 rsvd Reserved
bits:1 d1 D1 Support
bits:1 d2 D2 Support
bits:5 pme PME Support
{}
or pci_pmc (Offset 52) PCI Power Management Capabilities
<byte 12946>
ushort value As word
endunion pci_pmc (Offset 52) PCI Power Management Capabilities
{}
or pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12944>
ulong value As longword
endunion pcicfg_reg_50 (Offset 50) PCI CAPID/ CAPNEXT/PMC
<byte 12948>
union pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12948>
{field (By field)}
<byte 12948>
lbits:2 pst Power State
lbits:6 reserved1 Reserved
lbits:1 pen PME Enable
lbits:4 sel Data Select
lbits:2 scl Data Scale
lbits:1 pme PME Status
lbits:16 reserved Reserved
{}
or pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12948>
ulong value As word
endunion pci_pmcs (Offset 54) PCI Power Management Control and Status
<byte 12952>
union pci_par (Offset 58) PCI Programmable Address Register
<byte 12952>
{field (By field)}
<byte 12952>
lbits:20 ra ROM/RAM Address
lbits:11 rsvd Reserved
lbits:1 inc Increment For DWord aligned addresses
{}
or pci_par (Offset 58) PCI Programmable Address Register
<byte 12952>
ulong value As longword
endunion pci_par (Offset 58) PCI Programmable Address Register
<byte 12956>
union pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12956>
{field (By field)}
<byte 12956>
lbits:32 data Read/Write Data
{}
or pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12956>
ulong value As longword
endunion pci_dar (Offset 5C) PCI Programmable Data Register
<byte 12960>
{pci_rsvd60_6f ((Offset 60) Reserved)}
<byte 12960>
ulong value
{}
<byte 12964>
union pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12964>
{field (By field)}
<byte 12964>
union pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12964>
{field (By field)}
<byte 12964>
tbits:8 cap_id Capability structure identifier.
{}
or pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12964>
utiny value As byte
endunion pci_msi_cap_id (Offset 64) PCI Message Signaled Interrupts Capabilities Identifier
<byte 12965>
union pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12965>
{field (By field)}
<byte 12965>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12965>
utiny value As byte
endunion pci_msi_next_cap (Offset 65) PCI Message Signaled Interrupts Next Capability
<byte 12966>
union pci_mc (Offset 66) PCI Message Control Register
<byte 12966>
{field (By field)}
<byte 12966>
bits:1 men Message Signaled Interrupts Enable
bits:3 mmc Multiple Message Capable
bits:3 mme Multiple Message Enable
bits:1 c64 64 Bit Address Capable Read
bits:8 rsvd Reserved
{}
or pci_mc (Offset 66) PCI Message Control Register
<byte 12966>
ushort value As word
endunion pci_mc (Offset 66) PCI Message Control Register
{}
or pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12964>
ulong value As longword
endunion pcicfg_reg_64 (Offset 64) PCI MSICAPID/ MSINEXTCAP/MC
<byte 12968>
union pci_ma (Offset 68) PCI Message Address
<byte 12968>
{field (By field)}
<byte 12968>
lbits:2 rsvd Reserved
lbits:30 address Message Address
{}
or pci_ma (Offset 68) PCI Message Address
<byte 12968>
ulong value As longword
endunion pci_ma (Offset 68) PCI Message Address
<byte 12972>
union pci_mua (Offset 6C) PCI Message Upper Address
<byte 12972>
{field (By field)}
<byte 12972>
lbits:32 address Message Upper Address
{}
or pci_mua (Offset 6C) PCI Message Upper Address
<byte 12972>
ulong value As longword
endunion pci_mua (Offset 6C) PCI Message Upper Address
<byte 12976>
union pci_md (Offset 70) PCI Message Data
<byte 12976>
{field (By field)}
<byte 12976>
lbits:16 mid Message ID
lbits:16 rsvd Reserved
{}
or pci_md (Offset 70) PCI Message Data
<byte 12976>
ulong value As longword
endunion pci_md (Offset 70) PCI Message Data
<byte 12980>
union pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12980>
{field (By field)}
<byte 12980>
union pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12980>
{field (By field)}
<byte 12980>
tbits:8 cap_id Capability structure identifier.
{}
or pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12980>
utiny value As byte
endunion pci_x_cap_id (Offset 74) PCI-X Capabilities Identifier
<byte 12981>
union pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12981>
{field (By field)}
<byte 12981>
tbits:8 offset Offset to the first item in the capabilities linked list
{}
or pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12981>
utiny value As byte
endunion pci_x_next_cap (Offset 75) PCI Next Capability Register
<byte 12982>
union pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12982>
{field (By field)}
<byte 12982>
bits:1 dper Data Parity Error Recovery
bits:1 ero Enable Relaxed Ordering
bits:2 mbc Maximum Memory Read Byte Count
bits:3 mos Maximum Outstanding Split Transactions
bits:9 rsvd Reserved
{}
or pci_x_cmd (Offset 76) PCI-X Command Register
<byte 12982>
ushort value As word
endunion pci_x_cmd (Offset 76) PCI-X Command Register
{}
or pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12980>
ulong value As longword
endunion pcicfg_reg_74 (Offset 74) PCI XCAPID/ XNEXTCAP/XCMD
<byte 12984>
union pci_x_s (Offset 78) PCI-X Status Register
<byte 12984>
{field (By field)}
<byte 12984>
lbits:3 fn Function Number
lbits:5 dn Device Number
lbits:8 bn Bus Number
lbits:1 d64 64-bit Device
lbits:1 c133 133 MHz Capable
lbits:1 scd Split Completion Discarded
lbits:1 usc Unexpected Split Completion
lbits:1 dc Device Complexity
lbits:2 dmbc Designed Maximum Memory Read Byte Count
lbits:3 dmos Designed Maximum Outstanding Split Transactions
lbits:3 dmcr Designed Maximum Cumulative Read Size
lbits:1 rcse Received Split Completion Error Message
lbits:2 rsvd Reserved
{}
or pci_x_s (Offset 78) PCI-X Status Register
<byte 12984>
ulong value As longword
endunion pci_x_s (Offset 78) PCI-X Status Register
{}
endunion pcicfg[9] Tachyon DX2+ PCI Configuration Registers
<byte 12988>
union ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 12988>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 12988>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 12988>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 12988>
{field (By field)}
<byte 12988>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 12988>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 12992>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 12992>
{field (By field)}
<byte 12992>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 12992>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 12996>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 12996>
{field (By field)}
<byte 12996>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 12996>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13000>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13000>
{field (By field)}
<byte 13000>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13000>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13004>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13004>
{field (By field)}
<byte 13004>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13004>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13008>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13008>
{field (By field)}
<byte 13008>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13008>
{field (By field)}
<byte 13008>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13008>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13010>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13010>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13008>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13012>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13012>
ulong value
{}
<byte 13016>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13016>
ulong value
{}
<byte 13020>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13020>
{field (By field)}
<byte 13020>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13020>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13024>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13024>
{field (By field)}
<byte 13024>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13024>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13028>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13028>
{field (By field)}
<byte 13028>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13028>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13032>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13032>
{field (By field)}
<byte 13032>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13032>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[0] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13036>
union ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13036>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13036>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13036>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13036>
{field (By field)}
<byte 13036>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13036>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13040>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13040>
{field (By field)}
<byte 13040>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13040>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13044>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13044>
{field (By field)}
<byte 13044>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13044>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13048>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13048>
{field (By field)}
<byte 13048>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13048>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13052>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13052>
{field (By field)}
<byte 13052>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13052>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13056>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13056>
{field (By field)}
<byte 13056>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13056>
{field (By field)}
<byte 13056>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13056>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13058>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13058>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13056>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13060>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13060>
ulong value
{}
<byte 13064>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13064>
ulong value
{}
<byte 13068>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13068>
{field (By field)}
<byte 13068>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13068>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13072>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13072>
{field (By field)}
<byte 13072>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13072>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13076>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13076>
{field (By field)}
<byte 13076>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13076>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13080>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13080>
{field (By field)}
<byte 13080>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13080>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[1] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13084>
union ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13084>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13084>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13084>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13084>
{field (By field)}
<byte 13084>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13084>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13088>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13088>
{field (By field)}
<byte 13088>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13088>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13092>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13092>
{field (By field)}
<byte 13092>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13092>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13096>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13096>
{field (By field)}
<byte 13096>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13096>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13100>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13100>
{field (By field)}
<byte 13100>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13100>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13104>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13104>
{field (By field)}
<byte 13104>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13104>
{field (By field)}
<byte 13104>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13104>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13106>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13106>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13104>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13108>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13108>
ulong value
{}
<byte 13112>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13112>
ulong value
{}
<byte 13116>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13116>
{field (By field)}
<byte 13116>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13116>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13120>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13120>
{field (By field)}
<byte 13120>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13120>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13124>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13124>
{field (By field)}
<byte 13124>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13124>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13128>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13128>
{field (By field)}
<byte 13128>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13128>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[2] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13132>
union ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13132>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13132>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13132>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13132>
{field (By field)}
<byte 13132>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13132>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13136>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13136>
{field (By field)}
<byte 13136>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13136>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13140>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13140>
{field (By field)}
<byte 13140>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13140>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13144>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13144>
{field (By field)}
<byte 13144>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13144>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13148>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13148>
{field (By field)}
<byte 13148>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13148>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13152>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13152>
{field (By field)}
<byte 13152>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13152>
{field (By field)}
<byte 13152>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13152>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13154>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13154>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13152>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13156>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13156>
ulong value
{}
<byte 13160>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13160>
ulong value
{}
<byte 13164>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13164>
{field (By field)}
<byte 13164>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13164>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13168>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13168>
{field (By field)}
<byte 13168>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13168>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13172>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13172>
{field (By field)}
<byte 13172>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13172>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13176>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13176>
{field (By field)}
<byte 13176>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13176>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[3] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13180>
union ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13180>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13180>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13180>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13180>
{field (By field)}
<byte 13180>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13180>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13184>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13184>
{field (By field)}
<byte 13184>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13184>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13188>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13188>
{field (By field)}
<byte 13188>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13188>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13192>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13192>
{field (By field)}
<byte 13192>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13192>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13196>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13196>
{field (By field)}
<byte 13196>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13196>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13200>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13200>
{field (By field)}
<byte 13200>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13200>
{field (By field)}
<byte 13200>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13200>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13202>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13202>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13200>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13204>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13204>
ulong value
{}
<byte 13208>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13208>
ulong value
{}
<byte 13212>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13212>
{field (By field)}
<byte 13212>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13212>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13216>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13216>
{field (By field)}
<byte 13216>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13216>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13220>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13220>
{field (By field)}
<byte 13220>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13220>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13224>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13224>
{field (By field)}
<byte 13224>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13224>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[4] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13228>
union ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13228>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13228>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13228>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13228>
{field (By field)}
<byte 13228>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13228>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13232>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13232>
{field (By field)}
<byte 13232>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13232>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13236>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13236>
{field (By field)}
<byte 13236>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13236>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13240>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13240>
{field (By field)}
<byte 13240>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13240>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13244>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13244>
{field (By field)}
<byte 13244>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13244>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13248>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13248>
{field (By field)}
<byte 13248>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13248>
{field (By field)}
<byte 13248>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13248>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13250>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13250>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13248>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13252>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13252>
ulong value
{}
<byte 13256>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13256>
ulong value
{}
<byte 13260>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13260>
{field (By field)}
<byte 13260>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13260>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13264>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13264>
{field (By field)}
<byte 13264>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13264>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13268>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13268>
{field (By field)}
<byte 13268>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13268>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13272>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13272>
{field (By field)}
<byte 13272>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13272>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[5] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13276>
union ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13276>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13276>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13276>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13276>
{field (By field)}
<byte 13276>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13276>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13280>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13280>
{field (By field)}
<byte 13280>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13280>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13284>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13284>
{field (By field)}
<byte 13284>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13284>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13288>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13288>
{field (By field)}
<byte 13288>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13288>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13292>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13292>
{field (By field)}
<byte 13292>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13292>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13296>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13296>
{field (By field)}
<byte 13296>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13296>
{field (By field)}
<byte 13296>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13296>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13298>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13298>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13296>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13300>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13300>
ulong value
{}
<byte 13304>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13304>
ulong value
{}
<byte 13308>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13308>
{field (By field)}
<byte 13308>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13308>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13312>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13312>
{field (By field)}
<byte 13312>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13312>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13316>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13316>
{field (By field)}
<byte 13316>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13316>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13320>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13320>
{field (By field)}
<byte 13320>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13320>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[6] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13324>
union ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13324>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13324>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13324>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13324>
{field (By field)}
<byte 13324>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13324>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13328>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13328>
{field (By field)}
<byte 13328>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13328>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13332>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13332>
{field (By field)}
<byte 13332>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13332>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13336>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13336>
{field (By field)}
<byte 13336>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13336>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13340>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13340>
{field (By field)}
<byte 13340>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13340>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13344>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13344>
{field (By field)}
<byte 13344>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13344>
{field (By field)}
<byte 13344>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13344>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13346>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13346>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13344>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13348>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13348>
ulong value
{}
<byte 13352>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13352>
ulong value
{}
<byte 13356>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13356>
{field (By field)}
<byte 13356>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13356>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13360>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13360>
{field (By field)}
<byte 13360>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13360>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13364>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13364>
{field (By field)}
<byte 13364>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13364>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13368>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13368>
{field (By field)}
<byte 13368>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13368>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[7] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13372>
union ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13372>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13372>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13372>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13372>
{field (By field)}
<byte 13372>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13372>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13376>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13376>
{field (By field)}
<byte 13376>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13376>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13380>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13380>
{field (By field)}
<byte 13380>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13380>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13384>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13384>
{field (By field)}
<byte 13384>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13384>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13388>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13388>
{field (By field)}
<byte 13388>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13388>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13392>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13392>
{field (By field)}
<byte 13392>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13392>
{field (By field)}
<byte 13392>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13392>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13394>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13394>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13392>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13396>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13396>
ulong value
{}
<byte 13400>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13400>
ulong value
{}
<byte 13404>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13404>
{field (By field)}
<byte 13404>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13404>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13408>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13408>
{field (By field)}
<byte 13408>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13408>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13412>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13412>
{field (By field)}
<byte 13412>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13412>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13416>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13416>
{field (By field)}
<byte 13416>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13416>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[8] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13420>
union ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13420>
ulong[12] ncfghia Tachyon DX2+ PCI Non-Configuration Registers -- High As Longwords
or ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13420>
{ncfghi (Tachyon DX2+ PCI Non-Configuration Registers -- High By Field)}
<byte 13420>
union ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13420>
{field (By field)}
<byte 13420>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13420>
ulong value As longword
endunion ncfghi_cintpend (Offset 0x400) Combined Interrupt Pending Register
<byte 13424>
union ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13424>
{field (By field)}
<byte 13424>
lbits:1 per0 PCI Error Detected Interrupt Function 0
lbits:1 der0 Device Error Detected Interrupt Function 0
lbits:1 int0 Function 0 Interrupt
lbits:2 reserved3 Reserved
lbits:1 ube0 Unsupported Byte Enable Function 0
lbits:2 reserved2 Reserved
lbits:1 per1 PCI Error Detected Interrupt Function 1
lbits:1 der1 Device Error Detected Interrupt Function 1
lbits:1 int1 Function 1 Interrupt
lbits:2 reserved1 Reserved
lbits:1 ube1 Unsupported Byte Enable Function 1
lbits:18 reserved Reserved
{}
or ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13424>
ulong value As longword
endunion ncfghi_cinten (Offset 0x404) Combined Interrupt Enable Register
<byte 13428>
union ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13428>
{field (By field)}
<byte 13428>
lbits:12 qf1 Quiesce Function 1
lbits:12 qf0 Quiesce Function 0
lbits:8 reserved Reserved
{}
or ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13428>
ulong value As longword
endunion ncfghi_gaac (Offset 0x408) Global Arbitration Algorithm Configuration Register
<byte 13432>
union ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13432>
{field (By field)}
<byte 13432>
lbits:1 ror Reissue on Retry
lbits:8 reserved3 Reserved
lbits:1 rod Reissue on Disconnect
lbits:1 gsr Global Soft Reset
lbits:2 reserved2 Reserved
lbits:1 omw Optimize Memory Write
lbits:10 reserved1 Reserved
lbits:1 isr iTR Soft Reset
lbits:1 nse No Snoop Enable
lbits:6 reserved Reserved
{}
or ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13432>
ulong value As longword
endunion ncfghi_gcr (Offset 0x40C) Global Control Register
<byte 13436>
union ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13436>
{field (By field)}
<byte 13436>
lbits:3 pfom PCI/PCI-X Frequency and Operating Mode
lbits:8 reserved2 Reserved
lbits:1 pebr Parity Error from Boot RAM
lbits:1 rra Reserved Region Access
lbits:1 dmcs Driver Mode Control Status
lbits:1 reserved1 Reserved
lbits:1 madr3 Memory Address 3
lbits:1 rcs Reference Clock Stable
lbits:15 reserved Reserved
{}
or ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13436>
ulong value As longword
endunion ncfghi_gsr (Offset 0x410) Global Status Register
<byte 13440>
union ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13440>
{field (By field)}
<byte 13440>
union ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13440>
{field (By field)}
<byte 13440>
bits:1 dusc Disable USC Check
bits:1 reserved1 Reserved
bits:1 en698 Enable DX698
bits:1 en711 Enable DX711
bits:1 en762 Enable DX762
bits:1 en820 Enable DX820
bits:1 reserved Reserved
bits:1 dofc Disable Outbound FIFO CRC Checking
bits:1 difc Disable Inbound FIFO CRC Checking
bits:7 nd Not Defined
{}
or ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13440>
ushort value As word
endunion ncfghi_bwr (Offset 0x414) Global Bug Work-Around Register
<byte 13442>
{ncfghi_rsvd416_417 ((Offset 0x416) Reserved)}
<byte 13442>
ushort value
{}
{}
or ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13440>
ulong value As longword
endunion ncfghi_reg_414 (Offset 0x414) BWR/RESERVED
<byte 13444>
{ncfghi_rsvd418_41B ((Offset 0x418) Reserved)}
<byte 13444>
ulong value
{}
<byte 13448>
{ncfghi_rsvd41C_41F ((Offset 0x41C) Reserved)}
<byte 13448>
ulong value
{}
<byte 13452>
union ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13452>
{field (By field)}
<byte 13452>
lbits:32 address Address
{}
or ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13452>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslblo (Offset 420) No Snoop Lower Boundary Register Low
<byte 13456>
union ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13456>
{field (By field)}
<byte 13456>
lbits:32 address Address
{}
or ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13456>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nslbhi (Offset 424) No Snoop Lower Boundary Register High
<byte 13460>
union ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13460>
{field (By field)}
<byte 13460>
lbits:32 address Address
{}
or ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13460>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsublo (Offset 428) No Snoop Upper Boundary Register Low
<byte 13464>
union ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13464>
{field (By field)}
<byte 13464>
lbits:32 address Address
{}
or ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
<byte 13464>
ulong value As longword (Bits 31:0 {Low} Bit 63:32 {High}
endunion ncfghi_nsubhi (Offset 42C) No Snoop Upper Boundary Register High
{}
endunion ncfghi[9] Tachyon DX2+ PCI Non-Configuration Registers High
<byte 13468>
union gbic_sid[0] GBIC Small Form Factor Serial ID data
<byte 13468>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[0] GBIC Small Form Factor Serial ID data
<byte 13468>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 13468>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 13468>
utiny transceiver0 Transceiver code 0
<byte 13469>
utiny connector Connector type
<byte 13470>
utiny ext_identifier Extended identifier
<byte 13471>
utiny identifier Identifier, transceiver type
<byte 13472>
utiny transceiver4 Transceiver code 4
<byte 13473>
utiny transceiver3 Transceiver code 3
<byte 13474>
utiny transceiver2 Transceiver code 2
<byte 13475>
utiny transceiver1 Transceiver code 1
<byte 13476>
utiny encoding Encoding
<byte 13477>
utiny transceiver7 Transceiver code 7
<byte 13478>
utiny transceiver6 Transceiver code 6
<byte 13479>
utiny transceiver5 Transceiver code 5
<byte 13480>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 13481>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 13482>
utiny reserved Reserved
<byte 13483>
utiny br_nom Baud rate, nominal
<byte 13484>
utiny reserved1 Reserved
<byte 13485>
utiny distance_cu CU, Distance (1m units)
<byte 13486>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 13487>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 13488>
utiny[16] vendor_name Vendor name
<byte 13504>
utiny[3] vendor_oui Vendor OUI
<byte 13507>
utiny reserved2 Reserved
<byte 13508>
utiny[16] vendor_pn Vendor part number
<byte 13524>
utiny[4] vendor_rev Vendor revision
<byte 13528>
utiny ccid CCID check code (Addresses 0-62)
<byte 13529>
utiny[3] reserved3 Reserved
{}
<byte 13532>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 13532>
utiny br_min Baud rate, mmin (% lower margin)
<byte 13533>
utiny br_max Baud rate, max (% upper margin)
<byte 13534>
utiny[2] options Options
<byte 13536>
utiny[16] vendor_sn Vendor serial number
<byte 13552>
utiny[8] date_code Date code
<byte 13560>
utiny ccex CCEX check code (Addresses 64-94)
<byte 13561>
utiny[3] reserved Reserved
{}
<byte 13564>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 13564>
utiny[32] vendor_specific_data
{}
<byte 13596>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 13596>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 13597>
utiny spare available to use
<byte 13598>
utiny calc_ccex Saved software calculated CCEX
<byte 13599>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[0] GBIC Small Form Factor Serial ID data
<byte 13600>
union gbic_sid[1] GBIC Small Form Factor Serial ID data
<byte 13600>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[1] GBIC Small Form Factor Serial ID data
<byte 13600>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 13600>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 13600>
utiny transceiver0 Transceiver code 0
<byte 13601>
utiny connector Connector type
<byte 13602>
utiny ext_identifier Extended identifier
<byte 13603>
utiny identifier Identifier, transceiver type
<byte 13604>
utiny transceiver4 Transceiver code 4
<byte 13605>
utiny transceiver3 Transceiver code 3
<byte 13606>
utiny transceiver2 Transceiver code 2
<byte 13607>
utiny transceiver1 Transceiver code 1
<byte 13608>
utiny encoding Encoding
<byte 13609>
utiny transceiver7 Transceiver code 7
<byte 13610>
utiny transceiver6 Transceiver code 6
<byte 13611>
utiny transceiver5 Transceiver code 5
<byte 13612>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 13613>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 13614>
utiny reserved Reserved
<byte 13615>
utiny br_nom Baud rate, nominal
<byte 13616>
utiny reserved1 Reserved
<byte 13617>
utiny distance_cu CU, Distance (1m units)
<byte 13618>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 13619>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 13620>
utiny[16] vendor_name Vendor name
<byte 13636>
utiny[3] vendor_oui Vendor OUI
<byte 13639>
utiny reserved2 Reserved
<byte 13640>
utiny[16] vendor_pn Vendor part number
<byte 13656>
utiny[4] vendor_rev Vendor revision
<byte 13660>
utiny ccid CCID check code (Addresses 0-62)
<byte 13661>
utiny[3] reserved3 Reserved
{}
<byte 13664>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 13664>
utiny br_min Baud rate, mmin (% lower margin)
<byte 13665>
utiny br_max Baud rate, max (% upper margin)
<byte 13666>
utiny[2] options Options
<byte 13668>
utiny[16] vendor_sn Vendor serial number
<byte 13684>
utiny[8] date_code Date code
<byte 13692>
utiny ccex CCEX check code (Addresses 64-94)
<byte 13693>
utiny[3] reserved Reserved
{}
<byte 13696>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 13696>
utiny[32] vendor_specific_data
{}
<byte 13728>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 13728>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 13729>
utiny spare available to use
<byte 13730>
utiny calc_ccex Saved software calculated CCEX
<byte 13731>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[1] GBIC Small Form Factor Serial ID data
<byte 13732>
union gbic_sid[2] GBIC Small Form Factor Serial ID data
<byte 13732>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[2] GBIC Small Form Factor Serial ID data
<byte 13732>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 13732>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 13732>
utiny transceiver0 Transceiver code 0
<byte 13733>
utiny connector Connector type
<byte 13734>
utiny ext_identifier Extended identifier
<byte 13735>
utiny identifier Identifier, transceiver type
<byte 13736>
utiny transceiver4 Transceiver code 4
<byte 13737>
utiny transceiver3 Transceiver code 3
<byte 13738>
utiny transceiver2 Transceiver code 2
<byte 13739>
utiny transceiver1 Transceiver code 1
<byte 13740>
utiny encoding Encoding
<byte 13741>
utiny transceiver7 Transceiver code 7
<byte 13742>
utiny transceiver6 Transceiver code 6
<byte 13743>
utiny transceiver5 Transceiver code 5
<byte 13744>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 13745>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 13746>
utiny reserved Reserved
<byte 13747>
utiny br_nom Baud rate, nominal
<byte 13748>
utiny reserved1 Reserved
<byte 13749>
utiny distance_cu CU, Distance (1m units)
<byte 13750>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 13751>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 13752>
utiny[16] vendor_name Vendor name
<byte 13768>
utiny[3] vendor_oui Vendor OUI
<byte 13771>
utiny reserved2 Reserved
<byte 13772>
utiny[16] vendor_pn Vendor part number
<byte 13788>
utiny[4] vendor_rev Vendor revision
<byte 13792>
utiny ccid CCID check code (Addresses 0-62)
<byte 13793>
utiny[3] reserved3 Reserved
{}
<byte 13796>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 13796>
utiny br_min Baud rate, mmin (% lower margin)
<byte 13797>
utiny br_max Baud rate, max (% upper margin)
<byte 13798>
utiny[2] options Options
<byte 13800>
utiny[16] vendor_sn Vendor serial number
<byte 13816>
utiny[8] date_code Date code
<byte 13824>
utiny ccex CCEX check code (Addresses 64-94)
<byte 13825>
utiny[3] reserved Reserved
{}
<byte 13828>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 13828>
utiny[32] vendor_specific_data
{}
<byte 13860>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 13860>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 13861>
utiny spare available to use
<byte 13862>
utiny calc_ccex Saved software calculated CCEX
<byte 13863>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[2] GBIC Small Form Factor Serial ID data
<byte 13864>
union gbic_sid[3] GBIC Small Form Factor Serial ID data
<byte 13864>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[3] GBIC Small Form Factor Serial ID data
<byte 13864>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 13864>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 13864>
utiny transceiver0 Transceiver code 0
<byte 13865>
utiny connector Connector type
<byte 13866>
utiny ext_identifier Extended identifier
<byte 13867>
utiny identifier Identifier, transceiver type
<byte 13868>
utiny transceiver4 Transceiver code 4
<byte 13869>
utiny transceiver3 Transceiver code 3
<byte 13870>
utiny transceiver2 Transceiver code 2
<byte 13871>
utiny transceiver1 Transceiver code 1
<byte 13872>
utiny encoding Encoding
<byte 13873>
utiny transceiver7 Transceiver code 7
<byte 13874>
utiny transceiver6 Transceiver code 6
<byte 13875>
utiny transceiver5 Transceiver code 5
<byte 13876>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 13877>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 13878>
utiny reserved Reserved
<byte 13879>
utiny br_nom Baud rate, nominal
<byte 13880>
utiny reserved1 Reserved
<byte 13881>
utiny distance_cu CU, Distance (1m units)
<byte 13882>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 13883>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 13884>
utiny[16] vendor_name Vendor name
<byte 13900>
utiny[3] vendor_oui Vendor OUI
<byte 13903>
utiny reserved2 Reserved
<byte 13904>
utiny[16] vendor_pn Vendor part number
<byte 13920>
utiny[4] vendor_rev Vendor revision
<byte 13924>
utiny ccid CCID check code (Addresses 0-62)
<byte 13925>
utiny[3] reserved3 Reserved
{}
<byte 13928>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 13928>
utiny br_min Baud rate, mmin (% lower margin)
<byte 13929>
utiny br_max Baud rate, max (% upper margin)
<byte 13930>
utiny[2] options Options
<byte 13932>
utiny[16] vendor_sn Vendor serial number
<byte 13948>
utiny[8] date_code Date code
<byte 13956>
utiny ccex CCEX check code (Addresses 64-94)
<byte 13957>
utiny[3] reserved Reserved
{}
<byte 13960>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 13960>
utiny[32] vendor_specific_data
{}
<byte 13992>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 13992>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 13993>
utiny spare available to use
<byte 13994>
utiny calc_ccex Saved software calculated CCEX
<byte 13995>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[3] GBIC Small Form Factor Serial ID data
<byte 13996>
union gbic_sid[4] GBIC Small Form Factor Serial ID data
<byte 13996>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[4] GBIC Small Form Factor Serial ID data
<byte 13996>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 13996>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 13996>
utiny transceiver0 Transceiver code 0
<byte 13997>
utiny connector Connector type
<byte 13998>
utiny ext_identifier Extended identifier
<byte 13999>
utiny identifier Identifier, transceiver type
<byte 14000>
utiny transceiver4 Transceiver code 4
<byte 14001>
utiny transceiver3 Transceiver code 3
<byte 14002>
utiny transceiver2 Transceiver code 2
<byte 14003>
utiny transceiver1 Transceiver code 1
<byte 14004>
utiny encoding Encoding
<byte 14005>
utiny transceiver7 Transceiver code 7
<byte 14006>
utiny transceiver6 Transceiver code 6
<byte 14007>
utiny transceiver5 Transceiver code 5
<byte 14008>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 14009>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 14010>
utiny reserved Reserved
<byte 14011>
utiny br_nom Baud rate, nominal
<byte 14012>
utiny reserved1 Reserved
<byte 14013>
utiny distance_cu CU, Distance (1m units)
<byte 14014>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 14015>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 14016>
utiny[16] vendor_name Vendor name
<byte 14032>
utiny[3] vendor_oui Vendor OUI
<byte 14035>
utiny reserved2 Reserved
<byte 14036>
utiny[16] vendor_pn Vendor part number
<byte 14052>
utiny[4] vendor_rev Vendor revision
<byte 14056>
utiny ccid CCID check code (Addresses 0-62)
<byte 14057>
utiny[3] reserved3 Reserved
{}
<byte 14060>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 14060>
utiny br_min Baud rate, mmin (% lower margin)
<byte 14061>
utiny br_max Baud rate, max (% upper margin)
<byte 14062>
utiny[2] options Options
<byte 14064>
utiny[16] vendor_sn Vendor serial number
<byte 14080>
utiny[8] date_code Date code
<byte 14088>
utiny ccex CCEX check code (Addresses 64-94)
<byte 14089>
utiny[3] reserved Reserved
{}
<byte 14092>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 14092>
utiny[32] vendor_specific_data
{}
<byte 14124>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 14124>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 14125>
utiny spare available to use
<byte 14126>
utiny calc_ccex Saved software calculated CCEX
<byte 14127>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[4] GBIC Small Form Factor Serial ID data
<byte 14128>
union gbic_sid[5] GBIC Small Form Factor Serial ID data
<byte 14128>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[5] GBIC Small Form Factor Serial ID data
<byte 14128>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 14128>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 14128>
utiny transceiver0 Transceiver code 0
<byte 14129>
utiny connector Connector type
<byte 14130>
utiny ext_identifier Extended identifier
<byte 14131>
utiny identifier Identifier, transceiver type
<byte 14132>
utiny transceiver4 Transceiver code 4
<byte 14133>
utiny transceiver3 Transceiver code 3
<byte 14134>
utiny transceiver2 Transceiver code 2
<byte 14135>
utiny transceiver1 Transceiver code 1
<byte 14136>
utiny encoding Encoding
<byte 14137>
utiny transceiver7 Transceiver code 7
<byte 14138>
utiny transceiver6 Transceiver code 6
<byte 14139>
utiny transceiver5 Transceiver code 5
<byte 14140>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 14141>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 14142>
utiny reserved Reserved
<byte 14143>
utiny br_nom Baud rate, nominal
<byte 14144>
utiny reserved1 Reserved
<byte 14145>
utiny distance_cu CU, Distance (1m units)
<byte 14146>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 14147>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 14148>
utiny[16] vendor_name Vendor name
<byte 14164>
utiny[3] vendor_oui Vendor OUI
<byte 14167>
utiny reserved2 Reserved
<byte 14168>
utiny[16] vendor_pn Vendor part number
<byte 14184>
utiny[4] vendor_rev Vendor revision
<byte 14188>
utiny ccid CCID check code (Addresses 0-62)
<byte 14189>
utiny[3] reserved3 Reserved
{}
<byte 14192>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 14192>
utiny br_min Baud rate, mmin (% lower margin)
<byte 14193>
utiny br_max Baud rate, max (% upper margin)
<byte 14194>
utiny[2] options Options
<byte 14196>
utiny[16] vendor_sn Vendor serial number
<byte 14212>
utiny[8] date_code Date code
<byte 14220>
utiny ccex CCEX check code (Addresses 64-94)
<byte 14221>
utiny[3] reserved Reserved
{}
<byte 14224>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 14224>
utiny[32] vendor_specific_data
{}
<byte 14256>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 14256>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 14257>
utiny spare available to use
<byte 14258>
utiny calc_ccex Saved software calculated CCEX
<byte 14259>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[5] GBIC Small Form Factor Serial ID data
<byte 14260>
union gbic_sid[6] GBIC Small Form Factor Serial ID data
<byte 14260>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[6] GBIC Small Form Factor Serial ID data
<byte 14260>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 14260>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 14260>
utiny transceiver0 Transceiver code 0
<byte 14261>
utiny connector Connector type
<byte 14262>
utiny ext_identifier Extended identifier
<byte 14263>
utiny identifier Identifier, transceiver type
<byte 14264>
utiny transceiver4 Transceiver code 4
<byte 14265>
utiny transceiver3 Transceiver code 3
<byte 14266>
utiny transceiver2 Transceiver code 2
<byte 14267>
utiny transceiver1 Transceiver code 1
<byte 14268>
utiny encoding Encoding
<byte 14269>
utiny transceiver7 Transceiver code 7
<byte 14270>
utiny transceiver6 Transceiver code 6
<byte 14271>
utiny transceiver5 Transceiver code 5
<byte 14272>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 14273>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 14274>
utiny reserved Reserved
<byte 14275>
utiny br_nom Baud rate, nominal
<byte 14276>
utiny reserved1 Reserved
<byte 14277>
utiny distance_cu CU, Distance (1m units)
<byte 14278>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 14279>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 14280>
utiny[16] vendor_name Vendor name
<byte 14296>
utiny[3] vendor_oui Vendor OUI
<byte 14299>
utiny reserved2 Reserved
<byte 14300>
utiny[16] vendor_pn Vendor part number
<byte 14316>
utiny[4] vendor_rev Vendor revision
<byte 14320>
utiny ccid CCID check code (Addresses 0-62)
<byte 14321>
utiny[3] reserved3 Reserved
{}
<byte 14324>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 14324>
utiny br_min Baud rate, mmin (% lower margin)
<byte 14325>
utiny br_max Baud rate, max (% upper margin)
<byte 14326>
utiny[2] options Options
<byte 14328>
utiny[16] vendor_sn Vendor serial number
<byte 14344>
utiny[8] date_code Date code
<byte 14352>
utiny ccex CCEX check code (Addresses 64-94)
<byte 14353>
utiny[3] reserved Reserved
{}
<byte 14356>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 14356>
utiny[32] vendor_specific_data
{}
<byte 14388>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 14388>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 14389>
utiny spare available to use
<byte 14390>
utiny calc_ccex Saved software calculated CCEX
<byte 14391>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[6] GBIC Small Form Factor Serial ID data
<byte 14392>
union gbic_sid[7] GBIC Small Form Factor Serial ID data
<byte 14392>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[7] GBIC Small Form Factor Serial ID data
<byte 14392>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 14392>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 14392>
utiny transceiver0 Transceiver code 0
<byte 14393>
utiny connector Connector type
<byte 14394>
utiny ext_identifier Extended identifier
<byte 14395>
utiny identifier Identifier, transceiver type
<byte 14396>
utiny transceiver4 Transceiver code 4
<byte 14397>
utiny transceiver3 Transceiver code 3
<byte 14398>
utiny transceiver2 Transceiver code 2
<byte 14399>
utiny transceiver1 Transceiver code 1
<byte 14400>
utiny encoding Encoding
<byte 14401>
utiny transceiver7 Transceiver code 7
<byte 14402>
utiny transceiver6 Transceiver code 6
<byte 14403>
utiny transceiver5 Transceiver code 5
<byte 14404>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 14405>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 14406>
utiny reserved Reserved
<byte 14407>
utiny br_nom Baud rate, nominal
<byte 14408>
utiny reserved1 Reserved
<byte 14409>
utiny distance_cu CU, Distance (1m units)
<byte 14410>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 14411>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 14412>
utiny[16] vendor_name Vendor name
<byte 14428>
utiny[3] vendor_oui Vendor OUI
<byte 14431>
utiny reserved2 Reserved
<byte 14432>
utiny[16] vendor_pn Vendor part number
<byte 14448>
utiny[4] vendor_rev Vendor revision
<byte 14452>
utiny ccid CCID check code (Addresses 0-62)
<byte 14453>
utiny[3] reserved3 Reserved
{}
<byte 14456>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 14456>
utiny br_min Baud rate, mmin (% lower margin)
<byte 14457>
utiny br_max Baud rate, max (% upper margin)
<byte 14458>
utiny[2] options Options
<byte 14460>
utiny[16] vendor_sn Vendor serial number
<byte 14476>
utiny[8] date_code Date code
<byte 14484>
utiny ccex CCEX check code (Addresses 64-94)
<byte 14485>
utiny[3] reserved Reserved
{}
<byte 14488>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 14488>
utiny[32] vendor_specific_data
{}
<byte 14520>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 14520>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 14521>
utiny spare available to use
<byte 14522>
utiny calc_ccex Saved software calculated CCEX
<byte 14523>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[7] GBIC Small Form Factor Serial ID data
<byte 14524>
union gbic_sid[8] GBIC Small Form Factor Serial ID data
<byte 14524>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[8] GBIC Small Form Factor Serial ID data
<byte 14524>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 14524>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 14524>
utiny transceiver0 Transceiver code 0
<byte 14525>
utiny connector Connector type
<byte 14526>
utiny ext_identifier Extended identifier
<byte 14527>
utiny identifier Identifier, transceiver type
<byte 14528>
utiny transceiver4 Transceiver code 4
<byte 14529>
utiny transceiver3 Transceiver code 3
<byte 14530>
utiny transceiver2 Transceiver code 2
<byte 14531>
utiny transceiver1 Transceiver code 1
<byte 14532>
utiny encoding Encoding
<byte 14533>
utiny transceiver7 Transceiver code 7
<byte 14534>
utiny transceiver6 Transceiver code 6
<byte 14535>
utiny transceiver5 Transceiver code 5
<byte 14536>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 14537>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 14538>
utiny reserved Reserved
<byte 14539>
utiny br_nom Baud rate, nominal
<byte 14540>
utiny reserved1 Reserved
<byte 14541>
utiny distance_cu CU, Distance (1m units)
<byte 14542>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 14543>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 14544>
utiny[16] vendor_name Vendor name
<byte 14560>
utiny[3] vendor_oui Vendor OUI
<byte 14563>
utiny reserved2 Reserved
<byte 14564>
utiny[16] vendor_pn Vendor part number
<byte 14580>
utiny[4] vendor_rev Vendor revision
<byte 14584>
utiny ccid CCID check code (Addresses 0-62)
<byte 14585>
utiny[3] reserved3 Reserved
{}
<byte 14588>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 14588>
utiny br_min Baud rate, mmin (% lower margin)
<byte 14589>
utiny br_max Baud rate, max (% upper margin)
<byte 14590>
utiny[2] options Options
<byte 14592>
utiny[16] vendor_sn Vendor serial number
<byte 14608>
utiny[8] date_code Date code
<byte 14616>
utiny ccex CCEX check code (Addresses 64-94)
<byte 14617>
utiny[3] reserved Reserved
{}
<byte 14620>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 14620>
utiny[32] vendor_specific_data
{}
<byte 14652>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 14652>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 14653>
utiny spare available to use
<byte 14654>
utiny calc_ccex Saved software calculated CCEX
<byte 14655>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[8] GBIC Small Form Factor Serial ID data
<byte 14656>
union gbic_sid[9] GBIC Small Form Factor Serial ID data
<byte 14656>
ulong[33] gbic_sida GBIC Small Form Factor Serial ID Data As Longwords
or gbic_sid[9] GBIC Small Form Factor Serial ID data
<byte 14656>
{gbic_sid (GBIC Small Form Factor Serial ID Data By Field)}
<byte 14656>
{base_id (Base ID Fields (Addresses 0-63))}
<byte 14656>
utiny transceiver0 Transceiver code 0
<byte 14657>
utiny connector Connector type
<byte 14658>
utiny ext_identifier Extended identifier
<byte 14659>
utiny identifier Identifier, transceiver type
<byte 14660>
utiny transceiver4 Transceiver code 4
<byte 14661>
utiny transceiver3 Transceiver code 3
<byte 14662>
utiny transceiver2 Transceiver code 2
<byte 14663>
utiny transceiver1 Transceiver code 1
<byte 14664>
utiny encoding Encoding
<byte 14665>
utiny transceiver7 Transceiver code 7
<byte 14666>
utiny transceiver6 Transceiver code 6
<byte 14667>
utiny transceiver5 Transceiver code 5
<byte 14668>
utiny distance_9u_100m 9u, Distance (100m units)
<byte 14669>
utiny distance_9u_km 9u, Distance (1000m units)
<byte 14670>
utiny reserved Reserved
<byte 14671>
utiny br_nom Baud rate, nominal
<byte 14672>
utiny reserved1 Reserved
<byte 14673>
utiny distance_cu CU, Distance (1m units)
<byte 14674>
utiny distance_60u_10m 60u, Distance (10m units)
<byte 14675>
utiny distance_50u_10m 50u, Distance (10m units)
<byte 14676>
utiny[16] vendor_name Vendor name
<byte 14692>
utiny[3] vendor_oui Vendor OUI
<byte 14695>
utiny reserved2 Reserved
<byte 14696>
utiny[16] vendor_pn Vendor part number
<byte 14712>
utiny[4] vendor_rev Vendor revision
<byte 14716>
utiny ccid CCID check code (Addresses 0-62)
<byte 14717>
utiny[3] reserved3 Reserved
{}
<byte 14720>
{extn_id (Extended ID Fields (Addresses 64-95))}
<byte 14720>
utiny br_min Baud rate, mmin (% lower margin)
<byte 14721>
utiny br_max Baud rate, max (% upper margin)
<byte 14722>
utiny[2] options Options
<byte 14724>
utiny[16] vendor_sn Vendor serial number
<byte 14740>
utiny[8] date_code Date code
<byte 14748>
utiny ccex CCEX check code (Addresses 64-94)
<byte 14749>
utiny[3] reserved Reserved
{}
<byte 14752>
{vend_id (Vendor Specific ID Fields (Addresses 96-127))}
<byte 14752>
utiny[32] vendor_specific_data
{}
<byte 14784>
{saved (Saved information (not part of SFF Serial Data EEPROM information)}
<byte 14784>
utiny status Tachyon port diagnostic Check Code test results: 0 = Both check codes passed, 1 = CCID check code failed (addresses 0-62), 2 = CCEX check code failed (addresses 64-94), 3 = Both check codes failed, -1 = Serial ID has not been read yet. NOTE: There is no check code for addresses 96-127.
<byte 14785>
utiny spare available to use
<byte 14786>
utiny calc_ccex Saved software calculated CCEX
<byte 14787>
utiny calc_ccid Saved software calculated CCID
{}
{}
endunion gbic_sid[9] GBIC Small Form Factor Serial ID data
{}
{}
<byte 14788>
{recursive_event[0] (Recursive entry array)}
<byte 14788>
ulong tt Trap type
<byte 14792>
ulong tc Termination code
<byte 14796>
ulong srr0 SRR0 register
<byte 14800>
ulong srr1 SRR1 register
<byte 14804>
ulong cr CR register
<byte 14808>
ulong xer XER register
<byte 14812>
ulong ctr CTR register
<byte 14816>
ulong lr LR register
<byte 14820>
ulong exception Exception code
<byte 14824>
ulong count Exception count
{}
<byte 14828>
{recursive_event[1] (Recursive entry array)}
<byte 14828>
ulong tt Trap type
<byte 14832>
ulong tc Termination code
<byte 14836>
ulong srr0 SRR0 register
<byte 14840>
ulong srr1 SRR1 register
<byte 14844>
ulong cr CR register
<byte 14848>
ulong xer XER register
<byte 14852>
ulong ctr CTR register
<byte 14856>
ulong lr LR register
<byte 14860>
ulong exception Exception code
<byte 14864>
ulong count Exception count
{}
<byte 14868>
{recursive_event[2] (Recursive entry array)}
<byte 14868>
ulong tt Trap type
<byte 14872>
ulong tc Termination code
<byte 14876>
ulong srr0 SRR0 register
<byte 14880>
ulong srr1 SRR1 register
<byte 14884>
ulong cr CR register
<byte 14888>
ulong xer XER register
<byte 14892>
ulong ctr CTR register
<byte 14896>
ulong lr LR register
<byte 14900>
ulong exception Exception code
<byte 14904>
ulong count Exception count
{}
<byte 14908>
{recursive_event[3] (Recursive entry array)}
<byte 14908>
ulong tt Trap type
<byte 14912>
ulong tc Termination code
<byte 14916>
ulong srr0 SRR0 register
<byte 14920>
ulong srr1 SRR1 register
<byte 14924>
ulong cr CR register
<byte 14928>
ulong xer XER register
<byte 14932>
ulong ctr CTR register
<byte 14936>
ulong lr LR register
<byte 14940>
ulong exception Exception code
<byte 14944>
ulong count Exception count
{}
<byte 14948>
{recursive_event[4] (Recursive entry array)}
<byte 14948>
ulong tt Trap type
<byte 14952>
ulong tc Termination code
<byte 14956>
ulong srr0 SRR0 register
<byte 14960>
ulong srr1 SRR1 register
<byte 14964>
ulong cr CR register
<byte 14968>
ulong xer XER register
<byte 14972>
ulong ctr CTR register
<byte 14976>
ulong lr LR register
<byte 14980>
ulong exception Exception code
<byte 14984>
ulong count Exception count
{}
<byte 14988>
{recursive_event[5] (Recursive entry array)}
<byte 14988>
ulong tt Trap type
<byte 14992>
ulong tc Termination code
<byte 14996>
ulong srr0 SRR0 register
<byte 15000>
ulong srr1 SRR1 register
<byte 15004>
ulong cr CR register
<byte 15008>
ulong xer XER register
<byte 15012>
ulong ctr CTR register
<byte 15016>
ulong lr LR register
<byte 15020>
ulong exception Exception code
<byte 15024>
ulong count Exception count
{}
<byte 15028>
{recursive_event[6] (Recursive entry array)}
<byte 15028>
ulong tt Trap type
<byte 15032>
ulong tc Termination code
<byte 15036>
ulong srr0 SRR0 register
<byte 15040>
ulong srr1 SRR1 register
<byte 15044>
ulong cr CR register
<byte 15048>
ulong xer XER register
<byte 15052>
ulong ctr CTR register
<byte 15056>
ulong lr LR register
<byte 15060>
ulong exception Exception code
<byte 15064>
ulong count Exception count
{}
<byte 15068>
{recursive_event[7] (Recursive entry array)}
<byte 15068>
ulong tt Trap type
<byte 15072>
ulong tc Termination code
<byte 15076>
ulong srr0 SRR0 register
<byte 15080>
ulong srr1 SRR1 register
<byte 15084>
ulong cr CR register
<byte 15088>
ulong xer XER register
<byte 15092>
ulong ctr CTR register
<byte 15096>
ulong lr LR register
<byte 15100>
ulong exception Exception code
<byte 15104>
ulong count Exception count
{}
<byte 15108>
{recursive_event[8] (Recursive entry array)}
<byte 15108>
ulong tt Trap type
<byte 15112>
ulong tc Termination code
<byte 15116>
ulong srr0 SRR0 register
<byte 15120>
ulong srr1 SRR1 register
<byte 15124>
ulong cr CR register
<byte 15128>
ulong xer XER register
<byte 15132>
ulong ctr CTR register
<byte 15136>
ulong lr LR register
<byte 15140>
ulong exception Exception code
<byte 15144>
ulong count Exception count
{}
<byte 15148>
{recursive_event[9] (Recursive entry array)}
<byte 15148>
ulong tt Trap type
<byte 15152>
ulong tc Termination code
<byte 15156>
ulong srr0 SRR0 register
<byte 15160>
ulong srr1 SRR1 register
<byte 15164>
ulong cr CR register
<byte 15168>
ulong xer XER register
<byte 15172>
ulong ctr CTR register
<byte 15176>
ulong lr LR register
<byte 15180>
ulong exception Exception code
<byte 15184>
ulong count Exception count
{}
<byte 15188>
{recursive_event[10] (Recursive entry array)}
<byte 15188>
ulong tt Trap type
<byte 15192>
ulong tc Termination code
<byte 15196>
ulong srr0 SRR0 register
<byte 15200>
ulong srr1 SRR1 register
<byte 15204>
ulong cr CR register
<byte 15208>
ulong xer XER register
<byte 15212>
ulong ctr CTR register
<byte 15216>
ulong lr LR register
<byte 15220>
ulong exception Exception code
<byte 15224>
ulong count Exception count
{}
<byte 15228>
{recursive_event[11] (Recursive entry array)}
<byte 15228>
ulong tt Trap type
<byte 15232>
ulong tc Termination code
<byte 15236>
ulong srr0 SRR0 register
<byte 15240>
ulong srr1 SRR1 register
<byte 15244>
ulong cr CR register
<byte 15248>
ulong xer XER register
<byte 15252>
ulong ctr CTR register
<byte 15256>
ulong lr LR register
<byte 15260>
ulong exception Exception code
<byte 15264>
ulong count Exception count
{}
<byte 15268>
{recursive_event[12] (Recursive entry array)}
<byte 15268>
ulong tt Trap type
<byte 15272>
ulong tc Termination code
<byte 15276>
ulong srr0 SRR0 register
<byte 15280>
ulong srr1 SRR1 register
<byte 15284>
ulong cr CR register
<byte 15288>
ulong xer XER register
<byte 15292>
ulong ctr CTR register
<byte 15296>
ulong lr LR register
<byte 15300>
ulong exception Exception code
<byte 15304>
ulong count Exception count
{}
<byte 15308>
{recursive_event[13] (Recursive entry array)}
<byte 15308>
ulong tt Trap type
<byte 15312>
ulong tc Termination code
<byte 15316>
ulong srr0 SRR0 register
<byte 15320>
ulong srr1 SRR1 register
<byte 15324>
ulong cr CR register
<byte 15328>
ulong xer XER register
<byte 15332>
ulong ctr CTR register
<byte 15336>
ulong lr LR register
<byte 15340>
ulong exception Exception code
<byte 15344>
ulong count Exception count
{}
<byte 15348>
{recursive_event[14] (Recursive entry array)}
<byte 15348>
ulong tt Trap type
<byte 15352>
ulong tc Termination code
<byte 15356>
ulong srr0 SRR0 register
<byte 15360>
ulong srr1 SRR1 register
<byte 15364>
ulong cr CR register
<byte 15368>
ulong xer XER register
<byte 15372>
ulong ctr CTR register
<byte 15376>
ulong lr LR register
<byte 15380>
ulong exception Exception code
<byte 15384>
ulong count Exception count
{}
<byte 15388>
{recursive_event[15] (Recursive entry array)}
<byte 15388>
ulong tt Trap type
<byte 15392>
ulong tc Termination code
<byte 15396>
ulong srr0 SRR0 register
<byte 15400>
ulong srr1 SRR1 register
<byte 15404>
ulong cr CR register
<byte 15408>
ulong xer XER register
<byte 15412>
ulong ctr CTR register
<byte 15416>
ulong lr LR register
<byte 15420>
ulong exception Exception code
<byte 15424>
ulong count Exception count
{}
<byte 15428>
{recursive_event[16] (Recursive entry array)}
<byte 15428>
ulong tt Trap type
<byte 15432>
ulong tc Termination code
<byte 15436>
ulong srr0 SRR0 register
<byte 15440>
ulong srr1 SRR1 register
<byte 15444>
ulong cr CR register
<byte 15448>
ulong xer XER register
<byte 15452>
ulong ctr CTR register
<byte 15456>
ulong lr LR register
<byte 15460>
ulong exception Exception code
<byte 15464>
ulong count Exception count
{}
<byte 15468>
{recursive_event[17] (Recursive entry array)}
<byte 15468>
ulong tt Trap type
<byte 15472>
ulong tc Termination code
<byte 15476>
ulong srr0 SRR0 register
<byte 15480>
ulong srr1 SRR1 register
<byte 15484>
ulong cr CR register
<byte 15488>
ulong xer XER register
<byte 15492>
ulong ctr CTR register
<byte 15496>
ulong lr LR register
<byte 15500>
ulong exception Exception code
<byte 15504>
ulong count Exception count
{}
<byte 15508>
{recursive_event[18] (Recursive entry array)}
<byte 15508>
ulong tt Trap type
<byte 15512>
ulong tc Termination code
<byte 15516>
ulong srr0 SRR0 register
<byte 15520>
ulong srr1 SRR1 register
<byte 15524>
ulong cr CR register
<byte 15528>
ulong xer XER register
<byte 15532>
ulong ctr CTR register
<byte 15536>
ulong lr LR register
<byte 15540>
ulong exception Exception code
<byte 15544>
ulong count Exception count
{}
<byte 15548>
{recursive_event[19] (Recursive entry array)}
<byte 15548>
ulong tt Trap type
<byte 15552>
ulong tc Termination code
<byte 15556>
ulong srr0 SRR0 register
<byte 15560>
ulong srr1 SRR1 register
<byte 15564>
ulong cr CR register
<byte 15568>
ulong xer XER register
<byte 15572>
ulong ctr CTR register
<byte 15576>
ulong lr LR register
<byte 15580>
ulong exception Exception code
<byte 15584>
ulong count Exception count
{}
<byte 15588>
{recursive_event[20] (Recursive entry array)}
<byte 15588>
ulong tt Trap type
<byte 15592>
ulong tc Termination code
<byte 15596>
ulong srr0 SRR0 register
<byte 15600>
ulong srr1 SRR1 register
<byte 15604>
ulong cr CR register
<byte 15608>
ulong xer XER register
<byte 15612>
ulong ctr CTR register
<byte 15616>
ulong lr LR register
<byte 15620>
ulong exception Exception code
<byte 15624>
ulong count Exception count
{}
<byte 15628>
{recursive_event[21] (Recursive entry array)}
<byte 15628>
ulong tt Trap type
<byte 15632>
ulong tc Termination code
<byte 15636>
ulong srr0 SRR0 register
<byte 15640>
ulong srr1 SRR1 register
<byte 15644>
ulong cr CR register
<byte 15648>
ulong xer XER register
<byte 15652>
ulong ctr CTR register
<byte 15656>
ulong lr LR register
<byte 15660>
ulong exception Exception code
<byte 15664>
ulong count Exception count
{}
<byte 15668>
{recursive_event[22] (Recursive entry array)}
<byte 15668>
ulong tt Trap type
<byte 15672>
ulong tc Termination code
<byte 15676>
ulong srr0 SRR0 register
<byte 15680>
ulong srr1 SRR1 register
<byte 15684>
ulong cr CR register
<byte 15688>
ulong xer XER register
<byte 15692>
ulong ctr CTR register
<byte 15696>
ulong lr LR register
<byte 15700>
ulong exception Exception code
<byte 15704>
ulong count Exception count
{}
<byte 15708>
{recursive_event[23] (Recursive entry array)}
<byte 15708>
ulong tt Trap type
<byte 15712>
ulong tc Termination code
<byte 15716>
ulong srr0 SRR0 register
<byte 15720>
ulong srr1 SRR1 register
<byte 15724>
ulong cr CR register
<byte 15728>
ulong xer XER register
<byte 15732>
ulong ctr CTR register
<byte 15736>
ulong lr LR register
<byte 15740>
ulong exception Exception code
<byte 15744>
ulong count Exception count
{}
<byte 15748>
{recursive_event[24] (Recursive entry array)}
<byte 15748>
ulong tt Trap type
<byte 15752>
ulong tc Termination code
<byte 15756>
ulong srr0 SRR0 register
<byte 15760>
ulong srr1 SRR1 register
<byte 15764>
ulong cr CR register
<byte 15768>
ulong xer XER register
<byte 15772>
ulong ctr CTR register
<byte 15776>
ulong lr LR register
<byte 15780>
ulong exception Exception code
<byte 15784>
ulong count Exception count
{}
<byte 15788>
{recursive_event[25] (Recursive entry array)}
<byte 15788>
ulong tt Trap type
<byte 15792>
ulong tc Termination code
<byte 15796>
ulong srr0 SRR0 register
<byte 15800>
ulong srr1 SRR1 register
<byte 15804>
ulong cr CR register
<byte 15808>
ulong xer XER register
<byte 15812>
ulong ctr CTR register
<byte 15816>
ulong lr LR register
<byte 15820>
ulong exception Exception code
<byte 15824>
ulong count Exception count
{}
<byte 15828>
{recursive_event[26] (Recursive entry array)}
<byte 15828>
ulong tt Trap type
<byte 15832>
ulong tc Termination code
<byte 15836>
ulong srr0 SRR0 register
<byte 15840>
ulong srr1 SRR1 register
<byte 15844>
ulong cr CR register
<byte 15848>
ulong xer XER register
<byte 15852>
ulong ctr CTR register
<byte 15856>
ulong lr LR register
<byte 15860>
ulong exception Exception code
<byte 15864>
ulong count Exception count
{}
<byte 15868>
{recursive_event[27] (Recursive entry array)}
<byte 15868>
ulong tt Trap type
<byte 15872>
ulong tc Termination code
<byte 15876>
ulong srr0 SRR0 register
<byte 15880>
ulong srr1 SRR1 register
<byte 15884>
ulong cr CR register
<byte 15888>
ulong xer XER register
<byte 15892>
ulong ctr CTR register
<byte 15896>
ulong lr LR register
<byte 15900>
ulong exception Exception code
<byte 15904>
ulong count Exception count
{}
<byte 15908>
{recursive_event[28] (Recursive entry array)}
<byte 15908>
ulong tt Trap type
<byte 15912>
ulong tc Termination code
<byte 15916>
ulong srr0 SRR0 register
<byte 15920>
ulong srr1 SRR1 register
<byte 15924>
ulong cr CR register
<byte 15928>
ulong xer XER register
<byte 15932>
ulong ctr CTR register
<byte 15936>
ulong lr LR register
<byte 15940>
ulong exception Exception code
<byte 15944>
ulong count Exception count
{}
<byte 15948>
{recursive_event[29] (Recursive entry array)}
<byte 15948>
ulong tt Trap type
<byte 15952>
ulong tc Termination code
<byte 15956>
ulong srr0 SRR0 register
<byte 15960>
ulong srr1 SRR1 register
<byte 15964>
ulong cr CR register
<byte 15968>
ulong xer XER register
<byte 15972>
ulong ctr CTR register
<byte 15976>
ulong lr LR register
<byte 15980>
ulong exception Exception code
<byte 15984>
ulong count Exception count
{}
<byte 15988>
{recursive_event[30] (Recursive entry array)}
<byte 15988>
ulong tt Trap type
<byte 15992>
ulong tc Termination code
<byte 15996>
ulong srr0 SRR0 register
<byte 16000>
ulong srr1 SRR1 register
<byte 16004>
ulong cr CR register
<byte 16008>
ulong xer XER register
<byte 16012>
ulong ctr CTR register
<byte 16016>
ulong lr LR register
<byte 16020>
ulong exception Exception code
<byte 16024>
ulong count Exception count
{}
<byte 16028>
{recursive_event[31] (Recursive entry array)}
<byte 16028>
ulong tt Trap type
<byte 16032>
ulong tc Termination code
<byte 16036>
ulong srr0 SRR0 register
<byte 16040>
ulong srr1 SRR1 register
<byte 16044>
ulong cr CR register
<byte 16048>
ulong xer XER register
<byte 16052>
ulong ctr CTR register
<byte 16056>
ulong lr LR register
<byte 16060>
ulong exception Exception code
<byte 16064>
ulong count Exception count
{}
<byte 16068>
{recursive_event[32] (Recursive entry array)}
<byte 16068>
ulong tt Trap type
<byte 16072>
ulong tc Termination code
<byte 16076>
ulong srr0 SRR0 register
<byte 16080>
ulong srr1 SRR1 register
<byte 16084>
ulong cr CR register
<byte 16088>
ulong xer XER register
<byte 16092>
ulong ctr CTR register
<byte 16096>
ulong lr LR register
<byte 16100>
ulong exception Exception code
<byte 16104>
ulong count Exception count
{}
<byte 16108>
{unexpected_event[0] (Unexpected event array)}
<byte 16108>
ulong type Unexpected event type
<byte 16112>
ulong pto Post-Termination Operation Indicator
<byte 16116>
ulong[10] param Unexpected event parameters
{}
<byte 16156>
{unexpected_event[1] (Unexpected event array)}
<byte 16156>
ulong type Unexpected event type
<byte 16160>
ulong pto Post-Termination Operation Indicator
<byte 16164>
ulong[10] param Unexpected event parameters
{}
<byte 16204>
{unexpected_event[2] (Unexpected event array)}
<byte 16204>
ulong type Unexpected event type
<byte 16208>
ulong pto Post-Termination Operation Indicator
<byte 16212>
ulong[10] param Unexpected event parameters
{}
<byte 16252>
{unexpected_event[3] (Unexpected event array)}
<byte 16252>
ulong type Unexpected event type
<byte 16256>
ulong pto Post-Termination Operation Indicator
<byte 16260>
ulong[10] param Unexpected event parameters
{}
<byte 16300>
{first_event (First event information)}
<byte 16300>
ulong tt Trap type
<byte 16304>
ulong tc Termination code
<byte 16308>
ulong srr0 SRR0 register
<byte 16312>
ulong srr1 SRR1 register
<byte 16316>
ulong cr CR register
<byte 16320>
ulong xer XER register
<byte 16324>
ulong ctr CTR register
<byte 16328>
ulong lr LR register
<byte 16332>
ulong exception Exception code
<byte 16336>
ulong count Exception count
{}
<byte 16340>
ulonglong brcookie Back revision cookie
{}
<byte 16348>
{ltecb (Last Termination Event Control Block)}
<byte 16348>
utiny recursive_notlogged Recursive entry not yet logged count
<byte 16349>
utiny info_notlogged Last Termination Event Information not yet logged
<byte 16350>
utiny reserved Reserved
<byte 16351>
utiny ltecb_revision Last Termination Event Control Block Revision number
<byte 16352>
utiny unexpected_logged Unexpected event already logged count
<byte 16353>
utiny unexpected_notlogged Unexpected event not yet logged count
<byte 16354>
utiny unexpected_event_index Unexpected event array index
<byte 16355>
utiny recursive_logged Recursive entry already logged count
<byte 16356>
ulong info_edc Last Termination Event Information EDC
{}
{}
<byte 16360>
do_not_display[24] union_pad Union Element Padding (DO NOT DISPLAY!)
or u Last Termination Event Block Union
<byte 0>
utiny[16384] union_pad Union Element Padding (DO NOT DISPLAY!)
endunion u Last Termination Event Block Union
{}
FSWGAS
EVENT CODE TRANSLATION BLOCKS:
EC BLOCK: 0102000d SCID_EXEC_TOD_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Action: %[exec_tod]", eip0D.action);
TRANSLATE("Current date/time: %[scmitim]", eip0D.ctime);
TRANSLATE("Previous date/time: %[scmitim]", eip0D.ptime);
ENDTRANSLATIONBLOCK
EC BLOCK: 0300200a SCID_SCS_CBIC_FAILURE
TRANSLATIONBLOCK
CONDITIONAL(
eip0A.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB", eip0A.dimm_size );
TRANSLATE("Controller: %[wwn]", eip0A.node_name);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 0301400b SCID_SCS_DDRIVE_INOP
TRANSLATIONBLOCK
TRANSLATE("Device: %[uuid]", eip0B.device);
TRANSLATE("Port ID: %s", eip0B.cerp_id);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Rack: %d.", eip0B.rack_num),
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Enclosure: %d.", eip0B.dencl_num)
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Bay: %d.", eip0B.bay)
);
TRANSLATE(
"Reason code: 0x%04X (%[drv_inop])",
eip0B.reason_code,
eip0B.reason_code
);
CONDITIONAL(eip0B.flags.quorum_disk != 0,
TRANSLATE(
"Quorum space write sequence: %d.",
eip0B.quorum_sequence
)
);
CONDITIONAL(eip0B.flags.inq_state != 0,
TRANSLATE(
"Inquiry data is valid (get more details)"
);
TRANSLATE(
"Device capacity (blocks): %d.",
eip0B.capacity
)
);
CONDITIONAL(eip0B.rss_flags.member_migrating != 0,
TRANSLATE(
"Redundant Storage Set member is migrating"
)
);
CONDITIONAL(eip0B.rss_flags.member_missing != 0,
TRANSLATE(
"Redundant Storage Set member is missing"
)
);
CONDITIONAL(eip0B.rss_flags.member_abnormal != 0,
TRANSLATE(
"Redundant Storage Set member state: %d.",
eip0B.member_state
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 03024f0b SCID_SCS_TOO_MANY_DISKS
TRANSLATIONBLOCK
TRANSLATE("Device: %[uuid]", eip0B.device);
TRANSLATE("Port ID: %s", eip0B.cerp_id);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Rack: %d.", eip0B.rack_num),
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Enclosure: %d.", eip0B.dencl_num)
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Bay: %d.", eip0B.bay)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0303000a SCID_SCS_START_OF_BOOT
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip0A.node_name);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 0304000a SCID_SCS_REALIZE_CELL_TRANSITION
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip0A.node_name);
TRANSLATE("Storage System: %[tag]", eip0A.scell_tag);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 0305000a SCID_SCS_FINISHED_JOINING_SLAVE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip0A.node_name);
TRANSLATE("Storage System: %[tag]", eip0A.scell_tag);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 0306000a SCID_SCS_FINISHED_SLAVE_LEAVE
TRANSLATIONBLOCK
CONDITIONAL(eip0A.node_name.lo != 0,
TRANSLATE("Controller: %[wwn]", eip0A.node_name),
TRANSLATE("Controller node name not known")
);
TRANSLATE("Storage System: %[tag]", eip0A.scell_tag);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 0307000a SCID_SCS_MASTER_FAILOVER
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip0A.node_name);
TRANSLATE("Storage System: %[tag]", eip0A.scell_tag);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 0308000a SCID_SCS_NSC_BROUGHT_IN
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip0A.node_name);
TRANSLATE("Storage System: %[tag]", eip0A.scell_tag);
TRANSLATE("DebugFlags: %08X PrintFlags: %08X",
eip0A.debug_flags, eip0A.print_flags);
ENDTRANSLATIONBLOCK
EC BLOCK: 03090018 SCID_SCS_MIGRATION_START
TRANSLATIONBLOCK
CONDITIONAL(eip18.source_migr == 0x06,
TRANSLATE("Merge started")
);
CONDITIONAL(eip18.source_migr == 0x0A,
TRANSLATE("Split started")
);
TRANSLATE("Disk Group tag: %[tag]", eip18.ldad_tag);
TRANSLATE("Source Redundant Storage Set: %04X", eip18.source_rss);
TRANSLATE("Target Redundant Storage Set: %04X", eip18.target_rss);
TRANSLATE("Source migration flags: %04x", eip18.source_migr);
TRANSLATE("Target migration flags: %04x", eip18.target_migr);
TRANSLATE("Source volumes: %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.smembers[0], eip18.smembers[1], eip18.smembers[2],
eip18.smembers[3], eip18.smembers[4], eip18.smembers[5],
eip18.smembers[6], eip18.smembers[7]);
TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.smembers[8], eip18.smembers[9], eip18.smembers[10],
eip18.smembers[11], eip18.smembers[12],
eip18.smembers[13], eip18.smembers[14],
eip18.smembers[15]);
TRANSLATE("Target volumes: %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.tmembers[0], eip18.tmembers[1], eip18.tmembers[2],
eip18.tmembers[3], eip18.tmembers[4], eip18.tmembers[5],
eip18.tmembers[6], eip18.tmembers[7]);
TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.tmembers[8], eip18.tmembers[9], eip18.tmembers[10],
eip18.tmembers[11], eip18.tmembers[12],
eip18.tmembers[13], eip18.tmembers[14],
eip18.tmembers[15]);
ENDTRANSLATIONBLOCK
EC BLOCK: 030a0018 SCID_SCS_MIGRATION_END
TRANSLATIONBLOCK
CONDITIONAL(eip18.source_migr == 0x06,
TRANSLATE("Merge finished")
);
CONDITIONAL(eip18.source_migr == 0x0A,
TRANSLATE("Split finished")
);
TRANSLATE("Disk Group tag: %[tag]", eip18.ldad_tag);
TRANSLATE("Source Redundant Storage Set: %04X", eip18.source_rss);
TRANSLATE("Target Redundant Storage Set: %04X", eip18.target_rss);
TRANSLATE("Source migration flags: %04x", eip18.source_migr);
TRANSLATE("Target migration flags: %04x", eip18.target_migr);
TRANSLATE("Source volumes: %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.smembers[0], eip18.smembers[1], eip18.smembers[2],
eip18.smembers[3], eip18.smembers[4], eip18.smembers[5],
eip18.smembers[6], eip18.smembers[7]);
TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.smembers[8], eip18.smembers[9], eip18.smembers[10],
eip18.smembers[11], eip18.smembers[12],
eip18.smembers[13], eip18.smembers[14],
eip18.smembers[15]);
TRANSLATE("Target volumes: %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.tmembers[0], eip18.tmembers[1], eip18.tmembers[2],
eip18.tmembers[3], eip18.tmembers[4], eip18.tmembers[5],
eip18.tmembers[6], eip18.tmembers[7]);
TRANSLATE(" %02X %02X %02X %02X %02X %02X %02X %02X",
eip18.tmembers[8], eip18.tmembers[9], eip18.tmembers[10],
eip18.tmembers[11], eip18.tmembers[12],
eip18.tmembers[13], eip18.tmembers[14],
eip18.tmembers[15]);
ENDTRANSLATIONBLOCK
EC BLOCK: 030b4f0b SCID_SCS_DRIVE_FAIL_DURING_REALIZE
TRANSLATIONBLOCK
TRANSLATE("Device: %[uuid]", eip0B.device);
TRANSLATE("Port ID: %s", eip0B.cerp_id);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Rack: %d.", eip0B.rack_num),
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Enclosure: %d.", eip0B.dencl_num)
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Bay: %d.", eip0B.bay)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 030c001e SCID_SCS_FLAGS_CHANGED
TRANSLATIONBLOCK
TRANSLATE("DebugFlags: %08X PrintFlags: %08X Caller PC : %08X",
eip1E.data[0], eip1E.data[1], eip1E.data[2]);
ENDTRANSLATIONBLOCK
EC BLOCK: 030d001e SCID_SCS_CSM_HANG_PROCESS
TRANSLATIONBLOCK
CONDITIONAL(eip1E.data[0] != 0,
TRANSLATE("Process: %s %02d", eip1E.info, eip1E.data[0])
);
CONDITIONAL(eip1E.data[0] == 0,
TRANSLATE("Process: %s", eip1E.info)
);
CONDITIONAL(eip1E.data[1] != 0,
TRANSLATE("Stack[0]: %08x (%s)", eip1E.data[1],
XLATE_PC_CURRENT(eip1E.data[1]))
);
CONDITIONAL(eip1E.data[2] != 0,
TRANSLATE("Stack[1]: %08x (%s)", eip1E.data[2],
XLATE_PC_CURRENT(eip1E.data[2]))
);
CONDITIONAL(eip1E.data[3] != 0,
TRANSLATE("Stack[2]: %08x (%s)", eip1E.data[3],
XLATE_PC_CURRENT(eip1E.data[3]))
);
CONDITIONAL(eip1E.data[4] != 0,
TRANSLATE("Stack[3]: %08x (%s)", eip1E.data[4],
XLATE_PC_CURRENT(eip1E.data[4]))
);
CONDITIONAL(eip1E.data[5] != 0,
TRANSLATE("Stack[4]: %08x (%s)", eip1E.data[5],
XLATE_PC_CURRENT(eip1E.data[5]))
);
CONDITIONAL(eip1E.data[6] != 0,
TRANSLATE("Stack[5]: %08x (%s)", eip1E.data[6],
XLATE_PC_CURRENT(eip1E.data[6]))
);
CONDITIONAL(eip1E.data[7] != 0,
TRANSLATE("Stack[6]: %08x (%s)", eip1E.data[7],
XLATE_PC_CURRENT(eip1E.data[7]))
);
CONDITIONAL(eip1E.data[8] != 0,
TRANSLATE("Stack[7]: %08x (%s)", eip1E.data[8],
XLATE_PC_CURRENT(eip1E.data[8]))
);
CONDITIONAL(eip1E.data[9] != 0,
TRANSLATE("Stack[8]: %08x (%s)", eip1E.data[9],
XLATE_PC_CURRENT(eip1E.data[9]))
);
CONDITIONAL(eip1E.data[10] != 0,
TRANSLATE("Stack[9]: %08x (%s)", eip1E.data[10],
XLATE_PC_CURRENT(eip1E.data[10]))
);
CONDITIONAL(eip1E.data[11] != 0,
TRANSLATE("Stack[10]: %08x (%s)", eip1E.data[11],
XLATE_PC_CURRENT(eip1E.data[11]))
);
CONDITIONAL(eip1E.data[12] != 0,
TRANSLATE("Stack[11]: %08x (%s)", eip1E.data[12],
XLATE_PC_CURRENT(eip1E.data[12]))
);
CONDITIONAL(eip1E.data[13] != 0,
TRANSLATE("Stack[12]: %08x (%s)", eip1E.data[13],
XLATE_PC_CURRENT(eip1E.data[13]))
);
CONDITIONAL(eip1E.data[14] != 0,
TRANSLATE("Stack[13]: %08x (%s)", eip1E.data[14],
XLATE_PC_CURRENT(eip1E.data[14]))
);
CONDITIONAL(eip1E.data[15] != 0,
TRANSLATE("Stack[14]: %08x (%s)", eip1E.data[15],
XLATE_PC_CURRENT(eip1E.data[15]))
);
CONDITIONAL(eip1E.data[16] != 0,
TRANSLATE("Stack[15]: %08x (%s)", eip1E.data[16],
XLATE_PC_CURRENT(eip1E.data[16]))
);
CONDITIONAL(eip1E.data[17] != 0,
TRANSLATE("Stack[16]: %08x (%s)", eip1E.data[17],
XLATE_PC_CURRENT(eip1E.data[17]))
);
CONDITIONAL(eip1E.data[18] != 0,
TRANSLATE("Stack[17]: %08x (%s)", eip1E.data[18],
XLATE_PC_CURRENT(eip1E.data[18]))
);
CONDITIONAL(eip1E.data[19] != 0,
TRANSLATE("Stack[18]: %08x (%s)", eip1E.data[19],
XLATE_PC_CURRENT(eip1E.data[19]))
);
CONDITIONAL(eip1E.data[20] != 0,
TRANSLATE("Stack[19]: %08x (%s)", eip1E.data[20],
XLATE_PC_CURRENT(eip1E.data[20]))
);
CONDITIONAL(eip1E.data[21] != 0,
TRANSLATE("Stack[20]: %08x (%s)", eip1E.data[21],
XLATE_PC_CURRENT(eip1E.data[21]))
);
CONDITIONAL(eip1E.data[22] != 0,
TRANSLATE("Stack[21]: %08x (%s)", eip1E.data[22],
XLATE_PC_CURRENT(eip1E.data[22]))
);
CONDITIONAL(eip1E.data[23] != 0,
TRANSLATE("Stack[22]: %08x (%s)", eip1E.data[23],
XLATE_PC_CURRENT(eip1E.data[23]))
);
ENDTRANSLATIONBLOCK
EC BLOCK: 030e070b SCID_SCS_ID_WRITE_DRIVE_CHANGED
TRANSLATIONBLOCK
TRANSLATE("Device about to write: %[uuid]", eip0B.device);
TRANSLATE("Port ID: %s", eip0B.cerp_id);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Rack: %d.", eip0B.rack_num),
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Enclosure: %d.", eip0B.dencl_num)
);
CONDITIONAL(eip0B.dencl_num != 99,
TRANSLATE("Bay: %d.", eip0B.bay)
);
TRANSLATE(
"Reason code: 0x%04X (%[drv_inop])",
eip0B.reason_code,
eip0B.reason_code
);
CONDITIONAL(eip0B.flags.quorum_disk != 0,
TRANSLATE(
"Quorum space write sequence: %d.",
eip0B.quorum_sequence
)
);
CONDITIONAL(eip0B.flags.inq_state != 0,
TRANSLATE(
"Inquiry data is valid (get more details)"
);
TRANSLATE(
"Device capacity (blocks): %d.",
eip0B.capacity
)
);
CONDITIONAL(eip0B.rss_flags.member_migrating != 0,
TRANSLATE(
"Redundant Storage Set member is migrating"
)
);
CONDITIONAL(eip0B.rss_flags.member_missing != 0,
TRANSLATE(
"Redundant Storage Set member is missing"
)
);
CONDITIONAL(eip0B.rss_flags.member_abnormal != 0,
TRANSLATE(
"Redundant Storage Set member state: %d.",
eip0B.member_state
)
);
TRANSLATE("Device we should have written: %[uuid]", eip0B.second_device);
TRANSLATE("Device fnb: 0x%08X", eip0B.second_fnb_ptr);
TRANSLATE("Device poid, vol: 0x%04X, 0x%04X",
eip0B.poid, eip0B.volnoid);
ENDTRANSLATIONBLOCK
EC BLOCK: 030f001e SCID_SCS_ROHS_COMPLIANCE
TRANSLATIONBLOCK
CONDITIONAL(eip1E.data[0] != 0,
TRANSLATE(
"The HSV210 controller is RoHS
compliant."
)
);
CONDITIONAL(eip1E.data[0] == 0,
TRANSLATE(
"The HSV210 controller is not
RoHS compliant."
)
);
CONDITIONAL(eip1E.data[1] == 1,
TRANSLATE(
"The HSV210 controller is a CR2
hardware build."
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0310001f SCID_SCS_UNIT_FAILOVER
TRANSLATIONBLOCK
TRANSLATE("Logical Disk: %[tag]", eip1F.ld_tag);
TRANSLATE("Derived Unit: %[tag]", eip1F.du_tag);
TRANSLATE("Storage System Virtual Disk: %[tag]", eip1F.scvd_tag);
TRANSLATE("Prev Controller: %[wwn]", eip1F.prev_wwn);
TRANSLATE("Current Controller: %[wwn]", eip1F.current_wwn);
ENDTRANSLATIONBLOCK
EC BLOCK: 03114420 SCID_SCS_FABRIC_ON_LOOP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip20.node_name);
TRANSLATE("FC port: %d", eip20.port);
TRANSLATE("Port state: %d", eip20.data);
ENDTRANSLATIONBLOCK
EC BLOCK: 03120021 SCID_SCS_LDISK_ATTACH_DONE
TRANSLATIONBLOCK
TRANSLATE("Logical Disk: %[tag]", eip21.target_tag);
TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag);
TRANSLATE("Type: %[scmi_logical_disk_snap_attach_type]", eip21.operation);
TRANSLATE("Status: %d", eip21.status);
CONDITIONAL(eip21.status == 0, TRANSLATE("Success"));
CONDITIONAL(eip21.status != 0, TRANSLATE("Error"));
ENDTRANSLATIONBLOCK
EC BLOCK: 03130021 SCID_SCS_LDISK_SNAPCLONE_UNSHARE_DONE
TRANSLATIONBLOCK
TRANSLATE("Snapclone Logical Disk: %[tag]", eip21.target_tag);
TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag);
ENDTRANSLATIONBLOCK
EC BLOCK: 03140021 SCID_SCS_MIRROR_CLONE_DETACH_DONE
TRANSLATIONBLOCK
TRANSLATE("Mirror Clone Logical Disk: %[tag]", eip21.target_tag);
TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag);
TRANSLATE(
"State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]",
eip21.prev_state, eip21.new_state);
TRANSLATE("Status: %d", eip21.status);
CONDITIONAL(eip21.status == 0, TRANSLATE("Success"));
CONDITIONAL(eip21.status != 0, TRANSLATE("Error"));
ENDTRANSLATIONBLOCK
EC BLOCK: 03150021 SCID_SCS_MIRROR_CLONE_FRACTURE_DONE
TRANSLATIONBLOCK
TRANSLATE("Mirror Clone Logical Disk: %[tag]", eip21.target_tag);
TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag);
TRANSLATE("Status: %d", eip21.status);
CONDITIONAL(eip21.status == 0, TRANSLATE("Success"));
CONDITIONAL(eip21.status != 0, TRANSLATE("Error"));
ENDTRANSLATIONBLOCK
EC BLOCK: 03160021 SCID_SCS_MIRROR_CLONE_RESYNC_DONE
TRANSLATIONBLOCK
TRANSLATE("Mirror Clone Logical Disk: %[tag]", eip21.target_tag);
TRANSLATE("Parent Logical Disk: %[tag]", eip21.parent_tag);
ENDTRANSLATIONBLOCK
EC BLOCK: 03170021 SCID_SCS_LDISK_INSTANT_RESTORE_DONE
TRANSLATIONBLOCK
TRANSLATE("Original Logical Disk: %[tag]", eip21.target_tag);
TRANSLATE("Source Logical Disk: %[tag]", eip21.parent_tag);
TRANSLATE("Status: %d", eip21.status);
CONDITIONAL(eip21.status == 0, TRANSLATE("Success"));
CONDITIONAL(eip21.status != 0, TRANSLATE("Error"));
CONDITIONAL(
eip21.operation == 1,
TRANSLATE("This was a high performance instant restore operation")
);
CONDITIONAL(
eip21.operation != 1,
TRANSLATE("This was a normal performance instant restore operation")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0400031c SCID_FM_TE
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1C.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1C.lter.termination_event.u.value,
eip1C.lter.ctrlr_model_id,
eip1C.lter.baselevel_id,
eip1C.lter.sw_version
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 0,
TRANSLATE(
"Termination parameter[0]: 0x%08x",
eip1C.lter.termination_event.params.param[0]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 1,
TRANSLATE(
"Termination parameter[1]: 0x%08x",
eip1C.lter.termination_event.params.param[1]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 2,
TRANSLATE(
"Termination parameter[2]: 0x%08x",
eip1C.lter.termination_event.params.param[2]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 3,
TRANSLATE(
"Termination parameter[3]: 0x%08x",
eip1C.lter.termination_event.params.param[3]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 4,
TRANSLATE(
"Termination parameter[4]: 0x%08x",
eip1C.lter.termination_event.params.param[4]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 5,
TRANSLATE(
"Termination parameter[5]: 0x%08x",
eip1C.lter.termination_event.params.param[5]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 6,
TRANSLATE(
"Termination parameter[6]: 0x%08x",
eip1C.lter.termination_event.params.param[6]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 7,
TRANSLATE(
"Termination parameter[7]: 0x%08x",
eip1C.lter.termination_event.params.param[7]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 8,
TRANSLATE(
"Termination parameter[8]: 0x%08x",
eip1C.lter.termination_event.params.param[8]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 9,
TRANSLATE(
"Termination parameter[9]: 0x%08x",
eip1C.lter.termination_event.params.param[9]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 10,
TRANSLATE(
"Termination parameter[10]: 0x%08x",
eip1C.lter.termination_event.params.param[10]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 11,
TRANSLATE(
"Termination parameter[11]: 0x%08x",
eip1C.lter.termination_event.params.param[11]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 12,
TRANSLATE(
"Termination parameter[12]: 0x%08x",
eip1C.lter.termination_event.params.param[12]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 13,
TRANSLATE(
"Termination parameter[13]: 0x%08x",
eip1C.lter.termination_event.params.param[13]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 14,
TRANSLATE(
"Termination parameter[14]: 0x%08x",
eip1C.lter.termination_event.params.param[14]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 15,
TRANSLATE(
"Termination parameter[15]: 0x%08x",
eip1C.lter.termination_event.params.param[15]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 16,
TRANSLATE(
"Termination parameter[16]: 0x%08x",
eip1C.lter.termination_event.params.param[16]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 17,
TRANSLATE(
"Termination parameter[17]: 0x%08x",
eip1C.lter.termination_event.params.param[17]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 18,
TRANSLATE(
"Termination parameter[18]: 0x%08x",
eip1C.lter.termination_event.params.param[18]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 19,
TRANSLATE(
"Termination parameter[19]: 0x%08x",
eip1C.lter.termination_event.params.param[19]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 20,
TRANSLATE(
"Termination parameter[20]: 0x%08x",
eip1C.lter.termination_event.params.param[20]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 21,
TRANSLATE(
"Termination parameter[21]: 0x%08x",
eip1C.lter.termination_event.params.param[21]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 22,
TRANSLATE(
"Termination parameter[22]: 0x%08x",
eip1C.lter.termination_event.params.param[22]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 23,
TRANSLATE(
"Termination parameter[23]: 0x%08x",
eip1C.lter.termination_event.params.param[23]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 24,
TRANSLATE(
"Termination parameter[24]: 0x%08x",
eip1C.lter.termination_event.params.param[24]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 25,
TRANSLATE(
"Termination parameter[25]: 0x%08x",
eip1C.lter.termination_event.params.param[25]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 26,
TRANSLATE(
"Termination parameter[26]: 0x%08x",
eip1C.lter.termination_event.params.param[26]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 27,
TRANSLATE(
"Termination parameter[27]: 0x%08x",
eip1C.lter.termination_event.params.param[27]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 28,
TRANSLATE(
"Termination parameter[28]: 0x%08x",
eip1C.lter.termination_event.params.param[28]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 29,
TRANSLATE(
"Termination parameter[29]: 0x%08x",
eip1C.lter.termination_event.params.param[29]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 30,
TRANSLATE(
"Termination parameter[30]: 0x%08x",
eip1C.lter.termination_event.params.param[30]
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1C.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: 0x%08x",
eip1C.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1C.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip1C.lter.terminating_ctrlr
);
TRANSLATE(
"Termination event sequence number: %d.",
eip1C.lter.seq
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1C.lter.sw_version
);
TRANSLATE(
"Terminating controller's baselevel ID: %s",
eip1C.lter.baselevel_id
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1C.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0401031c SCID_FM_LAST_GASP
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1C.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1C.lter.termination_event.u.value,
eip1C.lter.ctrlr_model_id,
eip1C.lter.baselevel_id,
eip1C.lter.sw_version
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 0,
TRANSLATE(
"Termination parameter[0]: 0x%08x",
eip1C.lter.termination_event.params.param[0]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 1,
TRANSLATE(
"Termination parameter[1]: 0x%08x",
eip1C.lter.termination_event.params.param[1]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 2,
TRANSLATE(
"Termination parameter[2]: 0x%08x",
eip1C.lter.termination_event.params.param[2]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 3,
TRANSLATE(
"Termination parameter[3]: 0x%08x",
eip1C.lter.termination_event.params.param[3]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 4,
TRANSLATE(
"Termination parameter[4]: 0x%08x",
eip1C.lter.termination_event.params.param[4]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 5,
TRANSLATE(
"Termination parameter[5]: 0x%08x",
eip1C.lter.termination_event.params.param[5]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 6,
TRANSLATE(
"Termination parameter[6]: 0x%08x",
eip1C.lter.termination_event.params.param[6]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 7,
TRANSLATE(
"Termination parameter[7]: 0x%08x",
eip1C.lter.termination_event.params.param[7]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 8,
TRANSLATE(
"Termination parameter[8]: 0x%08x",
eip1C.lter.termination_event.params.param[8]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 9,
TRANSLATE(
"Termination parameter[9]: 0x%08x",
eip1C.lter.termination_event.params.param[9]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 10,
TRANSLATE(
"Termination parameter[10]: 0x%08x",
eip1C.lter.termination_event.params.param[10]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 11,
TRANSLATE(
"Termination parameter[11]: 0x%08x",
eip1C.lter.termination_event.params.param[11]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 12,
TRANSLATE(
"Termination parameter[12]: 0x%08x",
eip1C.lter.termination_event.params.param[12]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 13,
TRANSLATE(
"Termination parameter[13]: 0x%08x",
eip1C.lter.termination_event.params.param[13]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 14,
TRANSLATE(
"Termination parameter[14]: 0x%08x",
eip1C.lter.termination_event.params.param[14]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 15,
TRANSLATE(
"Termination parameter[15]: 0x%08x",
eip1C.lter.termination_event.params.param[15]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 16,
TRANSLATE(
"Termination parameter[16]: 0x%08x",
eip1C.lter.termination_event.params.param[16]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 17,
TRANSLATE(
"Termination parameter[17]: 0x%08x",
eip1C.lter.termination_event.params.param[17]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 18,
TRANSLATE(
"Termination parameter[18]: 0x%08x",
eip1C.lter.termination_event.params.param[18]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 19,
TRANSLATE(
"Termination parameter[19]: 0x%08x",
eip1C.lter.termination_event.params.param[19]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 20,
TRANSLATE(
"Termination parameter[20]: 0x%08x",
eip1C.lter.termination_event.params.param[20]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 21,
TRANSLATE(
"Termination parameter[21]: 0x%08x",
eip1C.lter.termination_event.params.param[21]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 22,
TRANSLATE(
"Termination parameter[22]: 0x%08x",
eip1C.lter.termination_event.params.param[22]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 23,
TRANSLATE(
"Termination parameter[23]: 0x%08x",
eip1C.lter.termination_event.params.param[23]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 24,
TRANSLATE(
"Termination parameter[24]: 0x%08x",
eip1C.lter.termination_event.params.param[24]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 25,
TRANSLATE(
"Termination parameter[25]: 0x%08x",
eip1C.lter.termination_event.params.param[25]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 26,
TRANSLATE(
"Termination parameter[26]: 0x%08x",
eip1C.lter.termination_event.params.param[26]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 27,
TRANSLATE(
"Termination parameter[27]: 0x%08x",
eip1C.lter.termination_event.params.param[27]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 28,
TRANSLATE(
"Termination parameter[28]: 0x%08x",
eip1C.lter.termination_event.params.param[28]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 29,
TRANSLATE(
"Termination parameter[29]: 0x%08x",
eip1C.lter.termination_event.params.param[29]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 30,
TRANSLATE(
"Termination parameter[30]: 0x%08x",
eip1C.lter.termination_event.params.param[30]
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1C.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: %08x",
eip1C.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1C.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip1C.lter.terminating_ctrlr
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1C.lter.sw_version
);
TRANSLATE(
"Terminating controller's baselevel ID: %s",
eip1C.lter.baselevel_id
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1C.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04020101 SCID_FM_TPRE
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip01.ru.lter.termination_event.u.value,
XLATE_TC_FLO(
eip01.ru.lter.termination_event.u.value,
eip01.ru.lter.ctrlr_model_id,
eip01.ru.lter.baselevel_id,
eip01.ru.lter.sw_version
)
);
TRANSLATE(
"Termination location: 0x%08x",
eip01.ru.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip01.ru.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip01.ru.lter.terminating_ctrlr
);
TRANSLATE(
"Terminating controller's software version: %s",
eip01.ru.lter.sw_version
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip01.ru.lter.uptime
);
TRANSLATE(
"Post termination operation: %d. (%[fm_terminate_routines])",
eip01.ru.lter.reuea_index,
eip01.ru.lter.reuea_index
);
TRANSLATE(
"Trap type: 0x%08x",
eip01.rei.tt
);
TRANSLATE(
"Termination code: 0x%08x",
eip01.rei.tc
);
TRANSLATE(
"SRR0 register: 0x%08x",
eip01.rei.srr0
);
TRANSLATE(
"LR register: 0x%08x",
eip01.rei.lr
);
TRANSLATE(
"Exception code: 0x%08x",
eip01.rei.exception
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04030102 SCID_FM_TPUE
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip02.ru.lter.termination_event.u.value,
XLATE_TC_FLO(
eip02.ru.lter.termination_event.u.value,
eip02.ru.lter.ctrlr_model_id,
eip02.ru.lter.baselevel_id,
eip02.ru.lter.sw_version
)
);
TRANSLATE(
"Termination location: 0x%08x",
eip02.ru.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip02.ru.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip02.ru.lter.terminating_ctrlr
);
TRANSLATE(
"Terminating controller's software version: %s",
eip02.ru.lter.sw_version
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip02.ru.lter.uptime
);
TRANSLATE(
"Unexpected event type: %d. (%[fm_ue])",
eip02.uei.type,
eip02.uei.type
);
TRANSLATE(
"Post termination operation: %d. (%[fm_terminate_routines])",
eip02.uei.pto,
eip02.uei.pto
);
TRANSLATE(
"Parameter[0]: 0x%08x",
eip02.uei.param[0]
);
TRANSLATE(
"Parameter[1]: 0x%08x",
eip02.uei.param[1]
);
TRANSLATE(
"Parameter[2]: 0x%08x",
eip02.uei.param[2]
);
TRANSLATE(
"Parameter[3]: 0x%08x",
eip02.uei.param[3]
);
TRANSLATE(
"Parameter[3]: 0x%08x",
eip02.uei.param[3]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04040003 SCID_FM_SCEL_VALIDATED
TRANSLATIONBLOCK
CONDITIONAL(
eip03.cinfo.scelcbi.status == 0,
TRANSLATE("Status: 0. (No problems found)"),
TRANSLATE(
"Unexpected status: %d.",
eip03.cinfo.scelcbi.status
)
);
TRANSLATE(
"Current offset: %d.",
eip03.cinfo.scelcbi.current_offset
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.seq_reset != 0,
TRANSLATE("Sequence number reset"),
TRANSLATE("Sequence number not reset")
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.wrapped != 0,
TRANSLATE("Events wrapped"),
TRANSLATE("Events not wrapped")
);
TRANSLATE(
"Current EDBN: %d.",
eip03.cinfo.scelcbi.current_edbn
);
TRANSLATE(
"Start EDBN: %d.",
eip03.cinfo.scelcbi.start_edbn
);
TRANSLATE(
"End EDBN: %d.",
eip03.cinfo.scelcbi.end_edbn
);
TRANSLATE(
"Sequence reset EDBN: %d.",
eip03.cinfo.scelcbi.seq_reset_edbn
);
TRANSLATE(
"Event count: %d.",
eip03.cinfo.scelcbi.event_count
);
TRANSLATE(
"Sequence number: %d.",
eip03.cinfo.scelcbi.sequence_number
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.scelmi.index
);
TRANSLATE(
"Zero test buffer pointer: 0x%08x",
eip03.minfo.scelmi.utp
);
TRANSLATE(
"Current event pointer: 0x%08x",
eip03.minfo.scelmi.current_eventp
);
TRANSLATE(
"Current EDBN: %d.",
eip03.minfo.scelmi.current_edbn
);
TRANSLATE(
"Current sequence number: %d.",
eip03.minfo.scelmi.current_seqn
);
TRANSLATE(
"Previous offset: %d., 0x%04x",
eip03.minfo.scelmi.previous_offset,
eip03.minfo.scelmi.previous_offset
);
TRANSLATE(
"Current offset: %d., 0x%04x",
eip03.minfo.scelmi.current_offset,
eip03.minfo.scelmi.current_offset
);
TRANSLATE(
"Previous EDBN: %d.",
eip03.minfo.scelmi.previous_edbn
);
TRANSLATE(
"Previous sequence number: %d.",
eip03.minfo.scelmi.previous_seqn
);
CONDITIONAL(
eip03.minfo.scelmi.end_found != 0,
TRANSLATE("End found"),
TRANSLATE("End not found")
);
CONDITIONAL(
eip03.minfo.scelmi.accept_new_to_old != 0,
TRANSLATE("New to old acceptable"),
TRANSLATE("New to old not acceptable")
);
CONDITIONAL(
eip03.minfo.scelmi.unequal_found != 0,
TRANSLATE("Sequence number not as expected"),
TRANSLATE("Sequence number as expected")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.scelmi.iostatus,
eip03.minfo.scelmi.iostatus
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04050003 SCID_FM_SCEL_INITED
TRANSLATIONBLOCK
TRANSLATE(
"Status: 0x%02x (%[fm_mpvfc])",
eip03.cinfo.scelcbi.status,
eip03.cinfo.scelcbi.status
);
TRANSLATE(
"Current offset: %d.",
eip03.cinfo.scelcbi.current_offset
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.seq_reset != 0,
TRANSLATE("Sequence number reset"),
TRANSLATE("Sequence number not reset")
);
CONDITIONAL(
eip03.cinfo.scelcbi.flags.wrapped != 0,
TRANSLATE("Events wrapped"),
TRANSLATE("Events not wrapped")
);
TRANSLATE(
"Current EDBN: %d.",
eip03.cinfo.scelcbi.current_edbn
);
TRANSLATE(
"Start EDBN: %d.",
eip03.cinfo.scelcbi.start_edbn
);
TRANSLATE(
"End EDBN: %d.",
eip03.cinfo.scelcbi.end_edbn
);
TRANSLATE(
"Sequence reset EDBN: %d.",
eip03.cinfo.scelcbi.seq_reset_edbn
);
TRANSLATE(
"Event count: %d.",
eip03.cinfo.scelcbi.event_count
);
TRANSLATE(
"Sequence number: %d.",
eip03.cinfo.scelcbi.sequence_number
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.scelmi.index
);
TRANSLATE(
"Zero test buffer pointer: 0x%08x",
eip03.minfo.scelmi.utp
);
TRANSLATE(
"Current event pointer: 0x%08x",
eip03.minfo.scelmi.current_eventp
);
TRANSLATE(
"Current EDBN: %d.",
eip03.minfo.scelmi.current_edbn
);
TRANSLATE(
"Current sequence number: %d.",
eip03.minfo.scelmi.current_seqn
);
TRANSLATE(
"Previous offset: %d., 0x%04X",
eip03.minfo.scelmi.previous_offset,
eip03.minfo.scelmi.previous_offset
);
TRANSLATE(
"Current offset: %d., 0x%04X",
eip03.minfo.scelmi.current_offset,
eip03.minfo.scelmi.current_offset
);
TRANSLATE(
"Previous EDBN: %d.",
eip03.minfo.scelmi.previous_edbn
);
TRANSLATE(
"Previous sequence number: %d.",
eip03.minfo.scelmi.previous_seqn
);
CONDITIONAL(
eip03.minfo.scelmi.end_found != 0,
TRANSLATE("End found"),
TRANSLATE("End not found")
);
CONDITIONAL(
eip03.minfo.scelmi.accept_new_to_old != 0,
TRANSLATE("New to old acceptable"),
TRANSLATE("New to old not acceptable")
);
CONDITIONAL(
eip03.minfo.scelmi.unequal_found != 0,
TRANSLATE("Sequence number not as expected"),
TRANSLATE("Sequence number as expected")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.scelmi.iostatus,
eip03.minfo.scelmi.iostatus
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04060803 SCID_FM_LOCAL_EVENTS_NR
TRANSLATIONBLOCK
TRANSLATE(
"Local events not reported: %d.",
eip03.ainfo.events_not_reported
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04070803 SCID_FM_REMOTE_EVENTS_NR
TRANSLATIONBLOCK
TRANSLATE(
"Remote events not reported: %d.",
eip03.ainfo.events_not_reported
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04080003 SCID_FM_SCTEL_INACC
TRANSLATIONBLOCK
TRANSLATE(
"Status: 0x%02x (%[fm_mpvfc])",
eip03.cinfo.sctelcbi.status,
eip03.cinfo.sctelcbi.status
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0,
TRANSLATE("B events wrapped"),
TRANSLATE("B events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0,
TRANSLATE("B events valid"),
TRANSLATE("B events not valid")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0,
TRANSLATE("A events wrapped"),
TRANSLATE("A events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_valid != 0,
TRANSLATE("A events valid"),
TRANSLATE("A events not valid")
);
TRANSLATE(
"A Controller: %[uuid]",
eip03.cinfo.sctelcbi.actrlr_id
);
TRANSLATE(
"A MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.actrlr_mru_edbn
);
TRANSLATE(
"B Controller: %[uuid]",
eip03.cinfo.sctelcbi.bctrlr_id
);
TRANSLATE(
"B MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.bctrlr_mru_edbn
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.sctelmi.index
);
TRANSLATE(
"Current TEDBN: %d.",
eip03.minfo.sctelmi.current_edbn
);
TRANSLATE(
"End TEDBN: %d.",
eip03.minfo.sctelmi.end_edbn
);
CONDITIONAL(
eip03.minfo.sctelmi.actrlr != 0,
TRANSLATE("Is A controller"),
TRANSLATE("Is not A controller")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.sctelmi.iostatus,
eip03.minfo.sctelmi.iostatus
);
TRANSLATE(
"Hold buffer offset: %d., 0x%08x",
eip03.minfo.sctelmi.hold_offset,
eip03.minfo.sctelmi.hold_offset
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04090003 SCID_FM_SCTEL_VALIDATED
TRANSLATIONBLOCK
CONDITIONAL(
eip03.cinfo.sctelcbi.status == 0,
TRANSLATE("Status: 0. (No problems found)"),
TRANSLATE(
"Unexpected status: %d.",
eip03.cinfo.sctelcbi.status
)
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0,
TRANSLATE("B events wrapped"),
TRANSLATE("B events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0,
TRANSLATE("B events valid"),
TRANSLATE("B events not valid")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0,
TRANSLATE("A events wrapped"),
TRANSLATE("A events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_valid != 0,
TRANSLATE("A events valid"),
TRANSLATE("A events not valid")
);
TRANSLATE(
"A Controller: %[uuid]",
eip03.cinfo.sctelcbi.actrlr_id
);
TRANSLATE(
"A MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.actrlr_mru_edbn
);
TRANSLATE(
"B Controller: %[uuid]",
eip03.cinfo.sctelcbi.bctrlr_id
);
TRANSLATE(
"B MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.bctrlr_mru_edbn
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.sctelmi.index
);
TRANSLATE(
"Current TEDBN: %d.",
eip03.minfo.sctelmi.current_edbn
);
TRANSLATE(
"End TEDBN: %d.",
eip03.minfo.sctelmi.end_edbn
);
CONDITIONAL(
eip03.minfo.sctelmi.actrlr != 0,
TRANSLATE("Is A controller"),
TRANSLATE("Is not A controller")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.sctelmi.iostatus,
eip03.minfo.sctelmi.iostatus
);
TRANSLATE(
"Hold buffer offset: %d., 0x%08x",
eip03.minfo.sctelmi.hold_offset,
eip03.minfo.sctelmi.hold_offset
);
ENDTRANSLATIONBLOCK
EC BLOCK: 040a0003 SCID_FM_SCTEL_INITED
TRANSLATIONBLOCK
TRANSLATE(
"Status: 0x%02x (%[fm_mpvfc])",
eip03.cinfo.sctelcbi.status,
eip03.cinfo.sctelcbi.status
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0,
TRANSLATE("B events wrapped"),
TRANSLATE("B events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0,
TRANSLATE("B events valid"),
TRANSLATE("B events not valid")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0,
TRANSLATE("A events wrapped"),
TRANSLATE("A events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_valid != 0,
TRANSLATE("A events valid"),
TRANSLATE("A events not valid")
);
TRANSLATE(
"A Controller: %[uuid]",
eip03.cinfo.sctelcbi.actrlr_id
);
TRANSLATE(
"A MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.actrlr_mru_edbn
);
TRANSLATE(
"B Controller: %[uuid]",
eip03.cinfo.sctelcbi.bctrlr_id
);
TRANSLATE(
"B MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.bctrlr_mru_edbn
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.sctelmi.index
);
TRANSLATE(
"Current TEDBN: %d.",
eip03.minfo.sctelmi.current_edbn
);
TRANSLATE(
"End TEDBN: %d.",
eip03.minfo.sctelmi.end_edbn
);
CONDITIONAL(
eip03.minfo.sctelmi.actrlr != 0,
TRANSLATE("Is A controller"),
TRANSLATE("Is not A controller")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.sctelmi.iostatus,
eip03.minfo.sctelmi.iostatus
);
TRANSLATE(
"Hold buffer offset: %d., 0x%08x",
eip03.minfo.sctelmi.hold_offset,
eip03.minfo.sctelmi.hold_offset
);
ENDTRANSLATIONBLOCK
EC BLOCK: 040b0003 SCID_FM_SCTEL_UPDATED
TRANSLATIONBLOCK
CONDITIONAL(
eip03.cinfo.sctelcbi.status == 0,
TRANSLATE("Status: 0. (No problems found)"),
TRANSLATE(
"Unexpected status: %d.",
eip03.cinfo.sctelcbi.status
)
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0,
TRANSLATE("B events wrapped"),
TRANSLATE("B events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0,
TRANSLATE("B events valid"),
TRANSLATE("B events not valid")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0,
TRANSLATE("A events wrapped"),
TRANSLATE("A events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_valid != 0,
TRANSLATE("A events valid"),
TRANSLATE("A events not valid")
);
TRANSLATE(
"A Controller: %[uuid]",
eip03.cinfo.sctelcbi.actrlr_id
);
TRANSLATE(
"A MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.actrlr_mru_edbn
);
TRANSLATE(
"B Controller: %[uuid]",
eip03.cinfo.sctelcbi.bctrlr_id
);
TRANSLATE(
"B MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.bctrlr_mru_edbn
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.sctelmi.index
);
TRANSLATE(
"Current TEDBN: %d.",
eip03.minfo.sctelmi.current_edbn
);
TRANSLATE(
"End TEDBN: %d.",
eip03.minfo.sctelmi.end_edbn
);
CONDITIONAL(
eip03.minfo.sctelmi.actrlr != 0,
TRANSLATE("Is A controller"),
TRANSLATE("Is not A controller")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.sctelmi.iostatus,
eip03.minfo.sctelmi.iostatus
);
TRANSLATE(
"Hold buffer offset: %d., 0x%08x",
eip03.minfo.sctelmi.hold_offset,
eip03.minfo.sctelmi.hold_offset
);
ENDTRANSLATIONBLOCK
EC BLOCK: 040c0803 SCID_FM_BAD_REMOTE_EVENT
TRANSLATIONBLOCK
TRANSLATE(
"EIP event code: 0x%08x",
eip03.ainfo.remote_event.u.value
);
TRANSLATE(
"EIP type: 0x%02x",
eip03.ainfo.remote_event.type
);
TRANSLATE(
"EIP revision number: 0x%02x",
eip03.ainfo.remote_event.revision
);
TRANSLATE("EIP count: %d.", eip03.ainfo.remote_event.count);
ENDTRANSLATIONBLOCK
EC BLOCK: 040d0003 SCID_FM_QUIESCED
TRANSLATIONBLOCK
TRANSLATE(
"Quiescent type: %[fm_quiesce]",
eip03.ainfo.quiesce_type
);
ENDTRANSLATIONBLOCK
EC BLOCK: 040e031c SCID_FM_TE_CPLD
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1C.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1C.lter.termination_event.u.value,
eip1C.lter.ctrlr_model_id,
eip1C.lter.baselevel_id,
eip1C.lter.sw_version
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 0,
TRANSLATE(
"Termination parameter[0]: 0x%08x",
eip1C.lter.termination_event.params.param[0]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 1,
TRANSLATE(
"Termination parameter[1]: 0x%08x",
eip1C.lter.termination_event.params.param[1]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 2,
TRANSLATE(
"Termination parameter[2]: 0x%08x",
eip1C.lter.termination_event.params.param[2]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 3,
TRANSLATE(
"Termination parameter[3]: 0x%08x",
eip1C.lter.termination_event.params.param[3]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 4,
TRANSLATE(
"Termination parameter[4]: 0x%08x",
eip1C.lter.termination_event.params.param[4]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 5,
TRANSLATE(
"Termination parameter[5]: 0x%08x",
eip1C.lter.termination_event.params.param[5]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 6,
TRANSLATE(
"Termination parameter[6]: 0x%08x",
eip1C.lter.termination_event.params.param[6]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 7,
TRANSLATE(
"Termination parameter[7]: 0x%08x",
eip1C.lter.termination_event.params.param[7]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 8,
TRANSLATE(
"Termination parameter[8]: 0x%08x",
eip1C.lter.termination_event.params.param[8]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 9,
TRANSLATE(
"Termination parameter[9]: 0x%08x",
eip1C.lter.termination_event.params.param[9]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 10,
TRANSLATE(
"Termination parameter[10]: 0x%08x",
eip1C.lter.termination_event.params.param[10]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 11,
TRANSLATE(
"Termination parameter[11]: 0x%08x",
eip1C.lter.termination_event.params.param[11]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 12,
TRANSLATE(
"Termination parameter[12]: 0x%08x",
eip1C.lter.termination_event.params.param[12]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 13,
TRANSLATE(
"Termination parameter[13]: 0x%08x",
eip1C.lter.termination_event.params.param[13]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 14,
TRANSLATE(
"Termination parameter[14]: 0x%08x",
eip1C.lter.termination_event.params.param[14]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 15,
TRANSLATE(
"Termination parameter[15]: 0x%08x",
eip1C.lter.termination_event.params.param[15]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 16,
TRANSLATE(
"Termination parameter[16]: 0x%08x",
eip1C.lter.termination_event.params.param[16]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 17,
TRANSLATE(
"Termination parameter[17]: 0x%08x",
eip1C.lter.termination_event.params.param[17]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 18,
TRANSLATE(
"Termination parameter[18]: 0x%08x",
eip1C.lter.termination_event.params.param[18]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 19,
TRANSLATE(
"Termination parameter[19]: 0x%08x",
eip1C.lter.termination_event.params.param[19]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 20,
TRANSLATE(
"Termination parameter[20]: 0x%08x",
eip1C.lter.termination_event.params.param[20]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 21,
TRANSLATE(
"Termination parameter[21]: 0x%08x",
eip1C.lter.termination_event.params.param[21]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 22,
TRANSLATE(
"Termination parameter[22]: 0x%08x",
eip1C.lter.termination_event.params.param[22]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 23,
TRANSLATE(
"Termination parameter[23]: 0x%08x",
eip1C.lter.termination_event.params.param[23]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 24,
TRANSLATE(
"Termination parameter[24]: 0x%08x",
eip1C.lter.termination_event.params.param[24]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 25,
TRANSLATE(
"Termination parameter[25]: 0x%08x",
eip1C.lter.termination_event.params.param[25]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 26,
TRANSLATE(
"Termination parameter[26]: 0x%08x",
eip1C.lter.termination_event.params.param[26]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 27,
TRANSLATE(
"Termination parameter[27]: 0x%08x",
eip1C.lter.termination_event.params.param[27]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 28,
TRANSLATE(
"Termination parameter[28]: 0x%08x",
eip1C.lter.termination_event.params.param[28]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 29,
TRANSLATE(
"Termination parameter[29]: 0x%08x",
eip1C.lter.termination_event.params.param[29]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 30,
TRANSLATE(
"Termination parameter[30]: 0x%08x",
eip1C.lter.termination_event.params.param[30]
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1C.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: 0x%08x",
eip1C.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1C.lter.termination_time
);
TRANSLATE(
"Second terminating controller: %[scmi_obj_hnd]",
eip1C.lter.terminating_ctrlr
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1C.lter.sw_version
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1C.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 040f0003 SCID_FM_TEISP_SENT
TRANSLATIONBLOCK
CONDITIONAL(
eip03.cinfo.sctelcbi.status == 0,
TRANSLATE("Status: 0. (No problems found)"),
TRANSLATE(
"Unexpected status: %d.",
eip03.cinfo.sctelcbi.status
)
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_wrapped != 0,
TRANSLATE("B events wrapped"),
TRANSLATE("B events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.bctrlr_valid != 0,
TRANSLATE("B events valid"),
TRANSLATE("B events not valid")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_wrapped != 0,
TRANSLATE("A events wrapped"),
TRANSLATE("A events not wrapped")
);
CONDITIONAL(
eip03.cinfo.sctelcbi.flags.actrlr_valid != 0,
TRANSLATE("A events valid"),
TRANSLATE("A events not valid")
);
TRANSLATE(
"A Controller: %[uuid]",
eip03.cinfo.sctelcbi.actrlr_id
);
TRANSLATE(
"A MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.actrlr_mru_edbn
);
TRANSLATE(
"B Controller: %[uuid]",
eip03.cinfo.sctelcbi.bctrlr_id
);
TRANSLATE(
"B MRU TEDBN: %d.",
eip03.cinfo.sctelcbi.bctrlr_mru_edbn
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.sctelmi.index
);
TRANSLATE(
"Current TEDBN: %d.",
eip03.minfo.sctelmi.current_edbn
);
TRANSLATE(
"End TEDBN: %d.",
eip03.minfo.sctelmi.end_edbn
);
CONDITIONAL(
eip03.minfo.sctelmi.actrlr != 0,
TRANSLATE("Is A controller"),
TRANSLATE("Is not A controller")
);
TRANSLATE(
"I/O status: %d., 0x%08x",
eip03.minfo.sctelmi.iostatus,
eip03.minfo.sctelmi.iostatus
);
TRANSLATE(
"Hold buffer offset: %d., 0x%08x",
eip03.minfo.sctelmi.hold_offset,
eip03.minfo.sctelmi.hold_offset
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04100803 SCID_FM_LOCAL_ISR_EVENTS_NR
TRANSLATIONBLOCK
TRANSLATE(
"ISR events not reported: %d.",
eip03.ainfo.events_not_reported
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04110803 SCID_FM_REMOTE_ISR_EVENTS_NR
TRANSLATIONBLOCK
TRANSLATE(
"ISR events not reported: %d.",
eip03.ainfo.events_not_reported
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04120003 SCID_FM_LER_INTERVAL_CHANGED
TRANSLATIONBLOCK
CONDITIONAL(
eip03.minfo.lerinfo.reporting_interval != 0,
TRANSLATE(
"Last event reporting enabled, interval: %d. minutes",
eip03.minfo.lerinfo.reporting_interval * 15
),
TRANSLATE("Last event reporting disabled")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04130003 SCID_FM_LAST_EVENT_REPORTED
TRANSLATIONBLOCK
TRANSLATE("Last event information - ");
TRANSLATE(
" Reporting interval: %d. minutes",
eip03.minfo.lerinfo.reporting_interval * 15
);
TRANSLATE(
" Sequence number: %d.",
eip03.minfo.lerinfo.sequence_number
);
TRANSLATE(
" Report time: %[scmitim]",
eip03.minfo.lerinfo.report_time
);
TRANSLATE(
" Event code: %08X",
eip03.minfo.lerinfo.header.u.value
);
TRANSLATE("Primary controller last 30 seconds activity summary - ");
TRANSLATE(
" Total requests per second: %d.",
eip03.cinfo.stats30.total.rps
);
TRANSLATE(
" Total KB per second: %d.",
eip03.cinfo.stats30.total.kbs
);
TRANSLATE(
" Host requests per second: %d.",
eip03.cinfo.stats30.host.rps
);
TRANSLATE(
" Host KB per second: %d.",
eip03.cinfo.stats30.host.kbs
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0414031d SCID_FM_TE_OLD
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1D.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1D.lter.termination_event.u.value,
eip1D.lter.ctrlr_model_id,
eip1D.lter.baselevel_id,
eip1D.lter.sw_version
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1D.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: 0x%08x",
eip1D.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1D.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip1D.lter.terminating_ctrlr
);
TRANSLATE(
"Termination event sequence number: %d.",
eip1D.lter.seq
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1D.lter.sw_version
);
TRANSLATE(
"Terminating controller's baselevel ID: %s",
eip1D.lter.baselevel_id
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1D.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0415031d SCID_FM_LAST_GASP_OLD
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1D.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1D.lter.termination_event.u.value,
eip1D.lter.ctrlr_model_id,
eip1D.lter.baselevel_id,
eip1D.lter.sw_version
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1D.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: %08x",
eip1D.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1D.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip1D.lter.terminating_ctrlr
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1D.lter.sw_version
);
TRANSLATE(
"Terminating controller's baselevel ID: %s",
eip1D.lter.baselevel_id
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1D.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0416031d SCID_FM_TE_CPLD_OLD
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1D.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1D.lter.termination_event.u.value,
eip1D.lter.ctrlr_model_id,
eip1D.lter.baselevel_id,
eip1D.lter.sw_version
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1D.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: 0x%08x",
eip1D.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1D.lter.termination_time
);
TRANSLATE(
"Second terminating controller: %[scmi_obj_hnd]",
eip1D.lter.terminating_ctrlr
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1D.lter.sw_version
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1D.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04180003 SCID_FM_MEAL_VALIDATED
TRANSLATIONBLOCK
CONDITIONAL(
eip03.cinfo.mealcbi.status == 0,
TRANSLATE("Status: 0. (No problems found)"),
TRANSLATE(
"Unexpected status: %d.",
eip03.cinfo.mealcbi.status
)
);
TRANSLATE(
"Current offset: %d.",
eip03.cinfo.mealcbi.current_offset
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.seq_reset != 0,
TRANSLATE("Sequence number reset"),
TRANSLATE("Sequence number not reset")
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.wrapped != 0,
TRANSLATE("Events wrapped"),
TRANSLATE("Events not wrapped")
);
TRANSLATE(
"Current EDBN: %d.",
eip03.cinfo.mealcbi.current_edbn
);
TRANSLATE(
"Start EDBN: %d.",
eip03.cinfo.mealcbi.start_edbn
);
TRANSLATE(
"End EDBN: %d.",
eip03.cinfo.mealcbi.end_edbn
);
TRANSLATE(
"Sequence reset EDBN: %d.",
eip03.cinfo.mealcbi.seq_reset_edbn
);
TRANSLATE(
"Event count: %d.",
eip03.cinfo.mealcbi.event_count
);
TRANSLATE(
"Sequence number: %d.",
eip03.cinfo.mealcbi.sequence_number
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.mealmi.index
);
TRANSLATE(
"Zero test buffer pointer: 0x%08x",
eip03.minfo.mealmi.utp
);
TRANSLATE(
"Current event pointer: 0x%08x",
eip03.minfo.mealmi.current_eventp
);
TRANSLATE(
"Current EDBN: %d.",
eip03.minfo.mealmi.current_edbn
);
TRANSLATE(
"Current sequence number: %d.",
eip03.minfo.mealmi.current_seqn
);
TRANSLATE(
"Previous offset: %d., 0x%04x",
eip03.minfo.mealmi.previous_offset,
eip03.minfo.mealmi.previous_offset
);
TRANSLATE(
"Current offset: %d., 0x%04x",
eip03.minfo.mealmi.current_offset,
eip03.minfo.mealmi.current_offset
);
TRANSLATE(
"Previous EDBN: %d.",
eip03.minfo.mealmi.previous_edbn
);
TRANSLATE(
"Previous sequence number: %d.",
eip03.minfo.mealmi.previous_seqn
);
TRANSLATE(
"First sequence number: %d.",
eip03.minfo.mealmi.first_seqn
);
CONDITIONAL(
eip03.minfo.mealmi.end_found != 0,
TRANSLATE("End found"),
TRANSLATE("End not found")
);
CONDITIONAL(
eip03.minfo.mealmi.accept_new_to_old != 0,
TRANSLATE("New to old acceptable"),
TRANSLATE("New to old not acceptable")
);
CONDITIONAL(
eip03.minfo.mealmi.unequal_found != 0,
TRANSLATE("Sequence number not as expected"),
TRANSLATE("Sequence number as expected")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 04190003 SCID_FM_MEAL_INITED
TRANSLATIONBLOCK
TRANSLATE(
"Status: 0x%02x (%[fm_mpvfc])",
eip03.cinfo.mealcbi.status,
eip03.cinfo.mealcbi.status
);
TRANSLATE(
"Current offset: %d.",
eip03.cinfo.mealcbi.current_offset
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.time_set != 0,
TRANSLATE("Time set"),
TRANSLATE("Time not set")
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.time_synched != 0,
TRANSLATE("Time synchronized"),
TRANSLATE("Time not synchronized")
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.seq_reset != 0,
TRANSLATE("Sequence number reset"),
TRANSLATE("Sequence number not reset")
);
CONDITIONAL(
eip03.cinfo.mealcbi.flags.wrapped != 0,
TRANSLATE("Events wrapped"),
TRANSLATE("Events not wrapped")
);
TRANSLATE(
"Current EDBN: %d.",
eip03.cinfo.mealcbi.current_edbn
);
TRANSLATE(
"Start EDBN: %d.",
eip03.cinfo.mealcbi.start_edbn
);
TRANSLATE(
"End EDBN: %d.",
eip03.cinfo.mealcbi.end_edbn
);
TRANSLATE(
"Sequence reset EDBN: %d.",
eip03.cinfo.mealcbi.seq_reset_edbn
);
TRANSLATE(
"Event count: %d.",
eip03.cinfo.mealcbi.event_count
);
TRANSLATE(
"Sequence number: %d.",
eip03.cinfo.mealcbi.sequence_number
);
TRANSLATE(
"Loop index: %d.",
eip03.minfo.mealmi.index
);
TRANSLATE(
"Zero test buffer pointer: 0x%08x",
eip03.minfo.mealmi.utp
);
TRANSLATE(
"Current event pointer: 0x%08x",
eip03.minfo.mealmi.current_eventp
);
TRANSLATE(
"Current EDBN: %d.",
eip03.minfo.mealmi.current_edbn
);
TRANSLATE(
"Current sequence number: %d.",
eip03.minfo.mealmi.current_seqn
);
TRANSLATE(
"Previous offset: %d., 0x%04X",
eip03.minfo.mealmi.previous_offset,
eip03.minfo.mealmi.previous_offset
);
TRANSLATE(
"Current offset: %d., 0x%04X",
eip03.minfo.mealmi.current_offset,
eip03.minfo.mealmi.current_offset
);
TRANSLATE(
"Previous EDBN: %d.",
eip03.minfo.mealmi.previous_edbn
);
TRANSLATE(
"Previous sequence number: %d.",
eip03.minfo.mealmi.previous_seqn
);
TRANSLATE(
"First sequence number: %d.",
eip03.minfo.mealmi.first_seqn
);
CONDITIONAL(
eip03.minfo.mealmi.end_found != 0,
TRANSLATE("End found"),
TRANSLATE("End not found")
);
CONDITIONAL(
eip03.minfo.mealmi.accept_new_to_old != 0,
TRANSLATE("New to old acceptable"),
TRANSLATE("New to old not acceptable")
);
CONDITIONAL(
eip03.minfo.mealmi.unequal_found != 0,
TRANSLATE("Sequence number not as expected"),
TRANSLATE("Sequence number as expected")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 041a031c SCID_FM_TE_PRETEND
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1C.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1C.lter.termination_event.u.value,
eip1C.lter.ctrlr_model_id,
eip1C.lter.baselevel_id,
eip1C.lter.sw_version
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 0,
TRANSLATE(
"Termination parameter[0]: 0x%08x",
eip1C.lter.termination_event.params.param[0]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 1,
TRANSLATE(
"Termination parameter[1]: 0x%08x",
eip1C.lter.termination_event.params.param[1]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 2,
TRANSLATE(
"Termination parameter[2]: 0x%08x",
eip1C.lter.termination_event.params.param[2]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 3,
TRANSLATE(
"Termination parameter[3]: 0x%08x",
eip1C.lter.termination_event.params.param[3]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 4,
TRANSLATE(
"Termination parameter[4]: 0x%08x",
eip1C.lter.termination_event.params.param[4]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 5,
TRANSLATE(
"Termination parameter[5]: 0x%08x",
eip1C.lter.termination_event.params.param[5]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 6,
TRANSLATE(
"Termination parameter[6]: 0x%08x",
eip1C.lter.termination_event.params.param[6]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 7,
TRANSLATE(
"Termination parameter[7]: 0x%08x",
eip1C.lter.termination_event.params.param[7]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 8,
TRANSLATE(
"Termination parameter[8]: 0x%08x",
eip1C.lter.termination_event.params.param[8]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 9,
TRANSLATE(
"Termination parameter[9]: 0x%08x",
eip1C.lter.termination_event.params.param[9]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 10,
TRANSLATE(
"Termination parameter[10]: 0x%08x",
eip1C.lter.termination_event.params.param[10]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 11,
TRANSLATE(
"Termination parameter[11]: 0x%08x",
eip1C.lter.termination_event.params.param[11]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 12,
TRANSLATE(
"Termination parameter[12]: 0x%08x",
eip1C.lter.termination_event.params.param[12]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 13,
TRANSLATE(
"Termination parameter[13]: 0x%08x",
eip1C.lter.termination_event.params.param[13]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 14,
TRANSLATE(
"Termination parameter[14]: 0x%08x",
eip1C.lter.termination_event.params.param[14]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 15,
TRANSLATE(
"Termination parameter[15]: 0x%08x",
eip1C.lter.termination_event.params.param[15]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 16,
TRANSLATE(
"Termination parameter[16]: 0x%08x",
eip1C.lter.termination_event.params.param[16]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 17,
TRANSLATE(
"Termination parameter[17]: 0x%08x",
eip1C.lter.termination_event.params.param[17]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 18,
TRANSLATE(
"Termination parameter[18]: 0x%08x",
eip1C.lter.termination_event.params.param[18]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 19,
TRANSLATE(
"Termination parameter[19]: 0x%08x",
eip1C.lter.termination_event.params.param[19]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 20,
TRANSLATE(
"Termination parameter[20]: 0x%08x",
eip1C.lter.termination_event.params.param[20]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 21,
TRANSLATE(
"Termination parameter[21]: 0x%08x",
eip1C.lter.termination_event.params.param[21]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 22,
TRANSLATE(
"Termination parameter[22]: 0x%08x",
eip1C.lter.termination_event.params.param[22]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 23,
TRANSLATE(
"Termination parameter[23]: 0x%08x",
eip1C.lter.termination_event.params.param[23]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 24,
TRANSLATE(
"Termination parameter[24]: 0x%08x",
eip1C.lter.termination_event.params.param[24]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 25,
TRANSLATE(
"Termination parameter[25]: 0x%08x",
eip1C.lter.termination_event.params.param[25]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 26,
TRANSLATE(
"Termination parameter[26]: 0x%08x",
eip1C.lter.termination_event.params.param[26]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 27,
TRANSLATE(
"Termination parameter[27]: 0x%08x",
eip1C.lter.termination_event.params.param[27]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 28,
TRANSLATE(
"Termination parameter[28]: 0x%08x",
eip1C.lter.termination_event.params.param[28]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 29,
TRANSLATE(
"Termination parameter[29]: 0x%08x",
eip1C.lter.termination_event.params.param[29]
)
);
CONDITIONAL(
eip1C.header.revision > 0 &&
eip1C.lter.termination_event.u.code.parc > 30,
TRANSLATE(
"Termination parameter[30]: 0x%08x",
eip1C.lter.termination_event.params.param[30]
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1C.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: 0x%08x",
eip1C.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1C.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip1C.lter.terminating_ctrlr
);
TRANSLATE(
"Termination event sequence number: %d.",
eip1C.lter.seq
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1C.lter.sw_version
);
TRANSLATE(
"Terminating controller's baselevel ID: %s",
eip1C.lter.baselevel_id
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1C.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 041b031d SCID_FM_TE_OLD_PRETEND
TRANSLATIONBLOCK
TRANSLATE(
"Termination code: 0x%08x (%s)",
eip1D.lter.termination_event.u.value,
XLATE_TC_FLO(
eip1D.lter.termination_event.u.value,
eip1D.lter.ctrlr_model_id,
eip1D.lter.baselevel_id,
eip1D.lter.sw_version
)
);
TRANSLATE(
"Termination corrective action code: 0x%02x",
eip1D.lter.termination_event.u.code.cac
);
TRANSLATE(
"Termination location: 0x%08x",
eip1D.lter.termination_event.termination_location
);
TRANSLATE(
"Termination date/time: %[scmitim]",
eip1D.lter.termination_time
);
TRANSLATE(
"Terminating controller: %[scmi_obj_hnd]",
eip1D.lter.terminating_ctrlr
);
TRANSLATE(
"Termination event sequence number: %d.",
eip1D.lter.seq
);
TRANSLATE(
"Terminating controller's software version: %s",
eip1D.lter.sw_version
);
TRANSLATE(
"Terminating controller's baselevel ID: %s",
eip1D.lter.baselevel_id
);
TRANSLATE(
"Controller uptime: %y. seconds",
eip1D.lter.uptime
);
ENDTRANSLATIONBLOCK
EC BLOCK: 06000009 SCID_FCS_SMART_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE(
"Sense Key: %1X (%[scsi_sensekey])",
eip09.error.sense_data.sense_key,
eip09.error.sense_data.sense_key
);
TRANSLATE(
"ASC: 0x%02x ASCQ: 0x%02x (%[scsi_asc_ascq])",
eip09.error.sense_data.asc_ascq.asc_ascqb.asc,
eip09.error.sense_data.asc_ascq.asc_ascqb.asq,
eip09.error.sense_data.asc_ascq.asc_ascqw
);
TRANSLATE(
"FRU Code: 0x%02x",
eip09.error.sense_data.fru_code
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06014a08 SCID_FCS_LINK_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
TRANSLATE("Failure cause: %[fcs_fail]", eip08.failure_cause);
TRANSLATE("Producer index: 0x%04x", eip08.peq_prod_index);
TRANSLATE("Consumer index: 0x%04x", eip08.peq_cons_index);
TRANSLATE("Frozen index: 0x%04x", eip08.peq_frz_prod_index);
TRANSLATE("Port event block(s):");
CONDITIONAL( eip08.peb[0].type != 0,
TRANSLATE(
" [0] Type: %08X Context: %08X",
eip08.peb[0].type,
eip08.peb[0].context
)
);
CONDITIONAL( eip08.peb[1].type != 0,
TRANSLATE(
" [1] Type: %08X Context: %08X",
eip08.peb[1].type,
eip08.peb[1].context
)
);
CONDITIONAL( eip08.peb[2].type != 0,
TRANSLATE(
" [2] Type: %08X Context: %08X",
eip08.peb[2].type,
eip08.peb[2].context
)
);
CONDITIONAL( eip08.peb[3].type != 0,
TRANSLATE(
" [3] Type: %08X Context: %08X",
eip08.peb[3].type,
eip08.peb[3].context
)
);
CONDITIONAL( eip08.peb[4].type != 0,
TRANSLATE(
" [4] Type: %08X Context: %08X",
eip08.peb[4].type,
eip08.peb[4].context
)
);
CONDITIONAL( eip08.peb[5].type != 0,
TRANSLATE(
" [5] Type: %08X Context: %08X",
eip08.peb[5].type,
eip08.peb[5].context
)
);
CONDITIONAL( eip08.peb[6].type != 0,
TRANSLATE(
" [6] Type: %08X Context: %08X",
eip08.peb[6].type,
eip08.peb[6].context
)
);
CONDITIONAL( eip08.peb[7].type != 0,
TRANSLATE(
" [7] Type: %08X Context: %08X",
eip08.peb[7].type,
eip08.peb[7].context
)
);
TRANSLATE("Retry Timer: %d seconds", eip08.time );
ENDTRANSLATIONBLOCK
EC BLOCK: 06020009 SCID_FCS_CHECK_CONDITION
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE(
"Sense Key: %1X (%[scsi_sensekey])",
eip09.error.sense_data.sense_key,
eip09.error.sense_data.sense_key
);
TRANSLATE(
"ASC: 0x%02x ASCQ: 0x%02x (%[scsi_asc_ascq])",
eip09.error.sense_data.asc_ascq.asc_ascqb.asc,
eip09.error.sense_data.asc_ascq.asc_ascqb.asq,
eip09.error.sense_data.asc_ascq.asc_ascqw
);
TRANSLATE(
"FRU Code: 0x%02x",
eip09.error.sense_data.fru_code
);
TRANSLATE( "%s", XLATE_EIP09_LBA( eip09.cmd ) );
TRANSLATE(
"Info: 0x%02x%02x%02x%02x",
eip09.error.sense_data.info_0,
eip09.error.sense_data.info_1,
eip09.error.sense_data.info_2,
eip09.error.sense_data.info_3
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06034713 SCID_FCS_DATA_EXCHANGE_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("Intended recipient: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Number of timeouts detected: %d.", eip13.num_times);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06044812 SCID_FCS_UNEXPECTED_WORK
TRANSLATIONBLOCK
TRANSLATE("Sender: %[tag]", eip12.device);
TRANSLATE("Port ID: %s", eip12.cerp_id);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip12.dencl_num - 100
)
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip12.bay - 100)
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip12.dencl_num)
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num < 99,
TRANSLATE("Bay: %d.", eip12.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip12.al_pa);
TRANSLATE(
"Command descriptor block and Fibre Channel header information:"
);
TRANSLATE("hdr_cdb[0]: %08X", eip12.hdr_cdb[0]);
TRANSLATE("hdr_cdb[1]: %08X", eip12.hdr_cdb[1]);
TRANSLATE("hdr_cdb[2]: %08X", eip12.hdr_cdb[2]);
TRANSLATE("hdr_cdb[3]: %08X", eip12.hdr_cdb[3]);
TRANSLATE("hdr_cdb[4]: %08X", eip12.hdr_cdb[4]);
TRANSLATE("hdr_cdb[5]: %08X", eip12.hdr_cdb[5]);
TRANSLATE("hdr_cdb[6]: %08X", eip12.hdr_cdb[6]);
TRANSLATE("hdr_cdb[7]: %08X", eip12.hdr_cdb[7]);
TRANSLATE("hdr_cdb[8]: %08X", eip12.hdr_cdb[8]);
TRANSLATE("hdr_cdb[9]: %08X", eip12.hdr_cdb[9]);
TRANSLATE("hdr_cdb[10]: %08X", eip12.hdr_cdb[10]);
TRANSLATE("hdr_cdb[11]: %08X", eip12.hdr_cdb[11]);
TRANSLATE("hdr_cdb[12]: %08X", eip12.hdr_cdb[12]);
TRANSLATE("hdr_cdb[13]: %08X", eip12.hdr_cdb[13]);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip12.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip12.bypassb);
ENDTRANSLATIONBLOCK
EC BLOCK: 06054909 SCID_FCS_BAD_ALPA
TRANSLATIONBLOCK
TRANSLATE("Intended target: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06074709 SCID_FCS_TDS_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06080007 SCID_FCS_LINK_ERRORS
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip07.cerp_id);
TRANSLATE("Non-zero error counts:");
CONDITIONAL( eip07.loss_of_signal != 0,
TRANSLATE("Loss of signal: %d.", eip07.loss_of_signal)
);
CONDITIONAL( eip07.bad_rx_char != 0,
TRANSLATE("Bad RX character: %d.", eip07.bad_rx_char)
);
CONDITIONAL( eip07.loss_of_sync != 0,
TRANSLATE("Loss of synch: %d.", eip07.loss_of_sync)
);
CONDITIONAL( eip07.link_fail != 0,
TRANSLATE("Link failure: %d.", eip07.link_fail)
);
CONDITIONAL( eip07.rx_eofa != 0,
TRANSLATE("RX EOFa delimiter: %d.", eip07.rx_eofa)
);
CONDITIONAL( eip07.dis_frm != 0,
TRANSLATE("Discarded frame: %d.", eip07.dis_frm)
);
CONDITIONAL( eip07.bad_crc != 0,
TRANSLATE("Frames with bad CRC and valid EOF: %d.", eip07.bad_crc)
);
CONDITIONAL( eip07.proto_err != 0,
TRANSLATE("N_Port protocol error: %d.", eip07.proto_err)
);
CONDITIONAL( eip07.exp_frm != 0,
TRANSLATE("Expired outbound frame: %d.", eip07.exp_frm)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 06090013 SCID_FCS_SMART_FAILURE_COUNT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Number of failure prediction threshold exceeded errors: %d.",
eip13.num_times
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 060a0013 SCID_FCS_CHECK_CONDITION_COUNT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Number of check condition errors in last minute: %d.",
eip13.num_times
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
ENDTRANSLATIONBLOCK
EC BLOCK: 060b4709 SCID_FCS_NONDATA_EXCH_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 060c0013 SCID_FCS_LOOP_SWITCH
TRANSLATIONBLOCK
CONDITIONAL(
eip13.switch_type == 1 ,
TRANSLATE("Switch Type: 3XX Family")
);
CONDITIONAL(
eip13.switch_type == 2 ,
TRANSLATE("Switch Type: 8XX Family")
);
CONDITIONAL(
eip13.switch_type == 2 ,
TRANSLATE("Node Name: %[tag]", eip13.device)
);
CONDITIONAL(
eip13.switch_type == 2 ,
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa)
);
TRANSLATE("Port ID: %s", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 060d0013 SCID_FCS_DRIVE_PHYSICAL_LOCATION
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 060e9613 SCID_FCS_NO_EMU_CODE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 060f4013 SCID_FCS_DRIVE_SEEN_ON_ESI
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06109b13 SCID_FCS_EMU_NOT_COMMUNICATE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06120008 SCID_FCS_EMU_RETRIES_EXHAUSTED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
TRANSLATE("Enclosure: %d.", eip08.peq_prod_index);
TRANSLATE("Bay: %d.", eip08.failure_cause);
CONDITIONAL(eip08.peq_cons_index == 0, TRANSLATE("Loop: A"));
CONDITIONAL(eip08.peq_cons_index == 1, TRANSLATE("Loop: B"));
TRANSLATE("Retried task: 0x%04x", eip08.peq_frz_prod_index);
TRANSLATE("Task list to be sent to Drive Enclosure Environmental Monitoring Unit:");
CONDITIONAL( eip08.peb[0].type != 0,
TRANSLATE(
" [0] Type: %08X Context: %08X",
eip08.peb[0].type,
eip08.peb[0].context
)
);
CONDITIONAL( eip08.peb[1].type != 0,
TRANSLATE(
" [1] Type: %08X Context: %08X",
eip08.peb[1].type,
eip08.peb[1].context
)
);
CONDITIONAL( eip08.peb[2].type != 0,
TRANSLATE(
" [2] Type: %08X Context: %08X",
eip08.peb[2].type,
eip08.peb[2].context
)
);
CONDITIONAL( eip08.peb[3].type != 0,
TRANSLATE(
" [3] Type: %08X Context: %08X",
eip08.peb[3].type,
eip08.peb[3].context
)
);
CONDITIONAL( eip08.peb[4].type != 0,
TRANSLATE(
" [4] Type: %08X Context: %08X",
eip08.peb[4].type,
eip08.peb[4].context
)
);
CONDITIONAL( eip08.peb[5].type != 0,
TRANSLATE(
" [5] Type: %08X Context: %08X",
eip08.peb[5].type,
eip08.peb[5].context
)
);
CONDITIONAL( eip08.peb[6].type != 0,
TRANSLATE(
" [6] Type: %08X Context: %08X",
eip08.peb[6].type,
eip08.peb[6].context
)
);
CONDITIONAL( eip08.peb[7].type != 0,
TRANSLATE(
" [7] Type: %08X Context: %08X",
eip08.peb[7].type,
eip08.peb[7].context
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 06130013 SCID_FCS_EMU_COMMUNICATE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06149813 SCID_FCS_TOO_MANY_SHELVES
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06159913 SCID_FCS_PORT_CONNECTION_SWAPPED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06169713 SCID_FCS_CABINET_NOT_CONNECTED
TRANSLATIONBLOCK
TRANSLATE("Controller ID not available");
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06180013 SCID_FCS_EMU_CODE_LOAD_START
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06190013 SCID_FCS_EMU_CODE_LOAD_DONE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 061a0009 SCID_FCS_DRIVE_SOFT_ERRORS
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 061b0013 SCID_FCS_CABINET_CONNECTED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 061c4709 SCID_FCS_FRAME_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 061d4709 SCID_FCS_DROPPED_FRAME
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 061e4c13 SCID_FCS_DRIVE_SPOF
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Good port ID: %s", eip13.cerp_id);
TRANSLATE("Missing port ID: %s", eip13.missing_cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 061f0013 SCID_FCS_DRIVE_SPOF_FIXED
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06204013 SCID_FCS_UNSUPPORTED_DRIVE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06210013 SCID_FCS_WRONG_BLOCK_SIZE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06230013 SCID_FCS_LINK_IS_RESTARTED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06240013 SCID_FCS_POST_LINK_FAIL_DD
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06254313 SCID_FCS_WRONG_HARD_ALPA
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("Expected AL_PA: %04x", eip13.al_pa);
TRANSLATE("Actual AL_PA: %04x", eip13.num_times);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06268913 SCID_FCS_HARD_ALPA_THIEF
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("Stolen AL_PA: %04x", eip13.al_pa);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06270113 SCID_FCS_SOFT_ALPA
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip13.bay - 100)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip13.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip13.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06280008 SCID_FCS_EMU_OB_RETRIES_EXHAUSTED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
TRANSLATE("Enclosure: %d.", eip08.peq_prod_index);
TRANSLATE("Bay: %d.", eip08.failure_cause);
CONDITIONAL(eip08.peq_cons_index == 0, TRANSLATE("Loop: A"));
CONDITIONAL(eip08.peq_cons_index == 1, TRANSLATE("Loop: B"));
TRANSLATE("Retried task: 0x%04x", eip08.peq_frz_prod_index);
TRANSLATE("Task list:");
CONDITIONAL( eip08.peb[0].type != 0,
TRANSLATE(
" [0] Type: %08X Context: %08X",
eip08.peb[0].type,
eip08.peb[0].context
)
);
CONDITIONAL( eip08.peb[1].type != 0,
TRANSLATE(
" [1] Type: %08X Context: %08X",
eip08.peb[1].type,
eip08.peb[1].context
)
);
CONDITIONAL( eip08.peb[2].type != 0,
TRANSLATE(
" [2] Type: %08X Context: %08X",
eip08.peb[2].type,
eip08.peb[2].context
)
);
CONDITIONAL( eip08.peb[3].type != 0,
TRANSLATE(
" [3] Type: %08X Context: %08X",
eip08.peb[3].type,
eip08.peb[3].context
)
);
CONDITIONAL( eip08.peb[4].type != 0,
TRANSLATE(
" [4] Type: %08X Context: %08X",
eip08.peb[4].type,
eip08.peb[4].context
)
);
CONDITIONAL( eip08.peb[5].type != 0,
TRANSLATE(
" [5] Type: %08X Context: %08X",
eip08.peb[5].type,
eip08.peb[5].context
)
);
CONDITIONAL( eip08.peb[6].type != 0,
TRANSLATE(
" [6] Type: %08X Context: %08X",
eip08.peb[6].type,
eip08.peb[6].context
)
);
CONDITIONAL( eip08.peb[7].type != 0,
TRANSLATE(
" [7] Type: %08X Context: %08X",
eip08.peb[7].type,
eip08.peb[7].context
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 06290009 SCID_FCS_ABORT
TRANSLATIONBLOCK
TRANSLATE("Intended target: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 062a0009 SCID_FCS_RRQ
TRANSLATIONBLOCK
TRANSLATE("Intended target: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 062b4004 SCID_FCS_DRIVE_BRICK
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("Bypass method: %[fcs_mtl]", eip04.bypass_reason);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 062c0012 SCID_FCS_BBR
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip12.device);
TRANSLATE("Port ID: %s", eip12.cerp_id);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip12.dencl_num - 100
)
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip12.bay - 100)
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip12.dencl_num)
);
CONDITIONAL(eip12.al_pa != 0x01 &&
eip12.al_pa != 0x02 &&
eip12.al_pa != 0xEE &&
eip12.dencl_num < 99,
TRANSLATE("Bay: %d.", eip12.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip12.al_pa);
TRANSLATE("Media defects:");
CONDITIONAL( eip12.hdr_cdb[0] != 0,
TRANSLATE(
" [0] LBA: %08X",
eip12.hdr_cdb[0]
)
);
CONDITIONAL( eip12.hdr_cdb[1] != 0,
TRANSLATE(
" [1] LBA: %08X",
eip12.hdr_cdb[1]
)
);
CONDITIONAL( eip12.hdr_cdb[2] != 0,
TRANSLATE(
" [2] LBA: %08X",
eip12.hdr_cdb[2]
)
);
CONDITIONAL( eip12.hdr_cdb[3] != 0,
TRANSLATE(
" [3] LBA: %08X",
eip12.hdr_cdb[3]
)
);
CONDITIONAL( eip12.hdr_cdb[4] != 0,
TRANSLATE(
" [4] LBA: %08X",
eip12.hdr_cdb[4]
)
);
CONDITIONAL( eip12.hdr_cdb[5] != 0,
TRANSLATE(
" [5] LBA: %08X",
eip12.hdr_cdb[5]
)
);
CONDITIONAL( eip12.hdr_cdb[6] != 0,
TRANSLATE(
" [6] LBA: %08X",
eip12.hdr_cdb[6]
)
);
CONDITIONAL( eip12.hdr_cdb[7] != 0,
TRANSLATE(
" [7] LBA: %08X",
eip12.hdr_cdb[7]
)
);
CONDITIONAL( eip12.hdr_cdb[8] != 0,
TRANSLATE(
" [8] LBA: %08X",
eip12.hdr_cdb[8]
)
);
CONDITIONAL( eip12.hdr_cdb[9] != 0,
TRANSLATE(
" [9] LBA: %08X",
eip12.hdr_cdb[9]
)
);
CONDITIONAL( eip12.hdr_cdb[10] != 0,
TRANSLATE(
" [10] LBA: %08X",
eip12.hdr_cdb[10]
)
);
CONDITIONAL( eip12.hdr_cdb[11] != 0,
TRANSLATE(
" [11] LBA: %08X",
eip12.hdr_cdb[11]
)
);
CONDITIONAL( eip12.hdr_cdb[12] != 0,
TRANSLATE(
" [12] LBA: %08X",
eip12.hdr_cdb[12]
)
);
CONDITIONAL( eip12.hdr_cdb[13] != 0,
TRANSLATE(
" [13] LBA: %08X",
eip12.hdr_cdb[13]
)
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip12.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip12.bypassb);
ENDTRANSLATIONBLOCK
EC BLOCK: 062d0012 SCID_FCS_DIRECTED_LIP
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip12.cerp_id);
TRANSLATE("AL_PA: 0x%04x", eip12.al_pa);
TRANSLATE("LIP Type:");
CONDITIONAL( eip12.hdr_cdb[0] == 0,
TRANSLATE(
" LIP(F7,F7)"
)
);
CONDITIONAL( eip12.hdr_cdb[0] == 1,
TRANSLATE(
" DIRECTED RESET"
)
);
TRANSLATE("Caller PC: 0x%08X", eip12.hdr_cdb[1]);
ENDTRANSLATIONBLOCK
EC BLOCK: 062e0012 SCID_FCS_LIP_F8
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip12.cerp_id);
TRANSLATE("Controller affected: %[tag]", eip12.device);
CONDITIONAL( eip12.hdr_cdb[0] != 0,
TRANSLATE(
" [0] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[0]
)
);
CONDITIONAL( eip12.hdr_cdb[1] != 0,
TRANSLATE(
" [1] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[1]
)
);
CONDITIONAL( eip12.hdr_cdb[2] != 0,
TRANSLATE(
" [2] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[2]
)
);
CONDITIONAL( eip12.hdr_cdb[3] != 0,
TRANSLATE(
" [3] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[3]
)
);
CONDITIONAL( eip12.hdr_cdb[4] != 0,
TRANSLATE(
" [4] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[4]
)
);
CONDITIONAL( eip12.hdr_cdb[5] != 0,
TRANSLATE(
" [5] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[5]
)
);
CONDITIONAL( eip12.hdr_cdb[6] != 0,
TRANSLATE(
" [6] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[6]
)
);
CONDITIONAL( eip12.hdr_cdb[7] != 0,
TRANSLATE(
" [7] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[7]
)
);
CONDITIONAL( eip12.hdr_cdb[8] != 0,
TRANSLATE(
" [8] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[8]
)
);
CONDITIONAL( eip12.hdr_cdb[9] != 0,
TRANSLATE(
" [9] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[9]
)
);
CONDITIONAL( eip12.hdr_cdb[10] != 0,
TRANSLATE(
" [10] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[10]
)
);
CONDITIONAL( eip12.hdr_cdb[11] != 0,
TRANSLATE(
" [11] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[11]
)
);
CONDITIONAL( eip12.hdr_cdb[12] != 0,
TRANSLATE(
" [12] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[12]
)
);
CONDITIONAL( eip12.hdr_cdb[13] != 0,
TRANSLATE(
" [13] Count/AL_PA (ccccaaaa): %08X",
eip12.hdr_cdb[13]
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 06304e13 SCID_FCS_SHELF_SPOF
TRANSLATIONBLOCK
TRANSLATE("Enclosure: %[tag]", eip13.device);
TRANSLATE("Good port ID: %s", eip13.cerp_id);
TRANSLATE("Missing port ID: %s", eip13.missing_cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("AL_PA: 0x%04x", eip13.al_pa);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06310013 SCID_FCS_SHELF_SPOF_FIXED
TRANSLATIONBLOCK
TRANSLATE("Enclosure: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06324e13 SCID_FCS_PORT_SPOF
TRANSLATIONBLOCK
TRANSLATE("Good port ID: %s", eip13.cerp_id);
TRANSLATE("Missing port ID: %s", eip13.missing_cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06330013 SCID_FCS_PORT_SPOF_FIXED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06340013 SCID_FCS_ENABLE_DP
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06354d04 SCID_FCS_UNKNOWN_FIRMWARE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip04.al_pa);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Latest known revision: %s", eip04.new_rev);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06364d04 SCID_FCS_UNSUPPORTED_FIRMWARE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip04.al_pa);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Latest known revision: %s", eip04.new_rev);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 0637c404 SCID_FCS_LATER_FIRMWARE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip04.al_pa);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Latest known revision: %s", eip04.new_rev);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 0638c404 SCID_FCS_NEWER_FIRMWARE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip04.al_pa);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Latest known revision: %s", eip04.new_rev);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip04.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip04.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06394008 SCID_FCS_LOOP_RECOVERY_SLOT_BYPASSED
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Cabinet ID: %d", eip08.recovery.cab);
TRANSLATE("Enclosure ID: %d", eip08.recovery.shelf);
TRANSLATE("Bay: %d", eip08.recovery.slot);
ENDTRANSLATIONBLOCK
EC BLOCK: 063a0008 SCID_FCS_LOOP_RECOVERY_ENTERED
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Reason Code: %d", eip08.failure_cause);
CONDITIONAL(eip08.failure_cause == 0x03,
TRANSLATE("LID Recovery"));
CONDITIONAL(eip08.failure_cause == 0x05,
TRANSLATE("DDD Recovery"));
ENDTRANSLATIONBLOCK
EC BLOCK: 063b0008 SCID_FCS_LOOP_RECOVERY_EXIT
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Recovery Status: 0x%x", eip08.failure_cause);
CONDITIONAL(eip08.failure_cause == 0,
TRANSLATE("Recovery Status Text: Success"));
CONDITIONAL(eip08.failure_cause == 1,
TRANSLATE("Recovery Status Text: Exhausted retry count for FNB"));
CONDITIONAL(eip08.failure_cause == 2,
TRANSLATE("Recovery Status Text: No valid FNBs"));
CONDITIONAL(eip08.failure_cause == 3,
TRANSLATE("Recovery Status Text: No open DUB gates"));
CONDITIONAL(eip08.failure_cause == 4,
TRANSLATE("Recovery Status Text: Fibre channel error"));
CONDITIONAL(eip08.failure_cause == 5,
TRANSLATE("Recovery Status Text: CBIC codeload in progress"));
CONDITIONAL(eip08.failure_cause == 6,
TRANSLATE("Recovery Status Text: CBIC communications over IIC"));
CONDITIONAL(eip08.failure_cause == 7,
TRANSLATE("Recovery Status Text: Failed to enter FCS Maint Mode"));
CONDITIONAL(eip08.failure_cause == 8,
TRANSLATE("Recovery Status Text: Partial success"));
CONDITIONAL(eip08.failure_cause == 9,
TRANSLATE("Recovery Status Text: Task aborted"));
CONDITIONAL(eip08.failure_cause == 10,
TRANSLATE("Recovery Status Text: No progress made"));
CONDITIONAL(eip08.failure_cause == 11,
TRANSLATE("Recovery Status Text: Semaphore wait timed out"));
CONDITIONAL(eip08.failure_cause == 12,
TRANSLATE("Recovery Status Text: Exceeded max failure threshold for loop recovery"));
CONDITIONAL(eip08.failure_cause == 13,
TRANSLATE("Recovery Status Text: User disabled loop recoveries"));
ENDTRANSLATIONBLOCK
EC BLOCK: 063c0008 SCID_FCS_LOOP_RECOVERY_ABORT
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Progress: %x", eip08.recovery.progress);
TRANSLATE("Abort Status: %x", eip08.failure_cause);
ENDTRANSLATIONBLOCK
EC BLOCK: 063d9b09 SCID_FCS_SHELF_ONLY_OB
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 063ec513 SCID_FCS_SHELF_ONLY_IB
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[tag]", eip13.device);
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack and enclosure not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip13.dencl_num - 100
)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip13.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 063f9c13 SCID_FCS_DRIVE_EMU_NOT_COMMUNICATE
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip13.cerp_id);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num != 99,
TRANSLATE("Rack: %d.", eip13.rack_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num != 99,
TRANSLATE("Enclosure: %d.", eip13.dencl_num)
);
CONDITIONAL(eip13.al_pa != 0x01 &&
eip13.al_pa != 0x02 &&
eip13.al_pa != 0xEE &&
eip13.dencl_num != 99,
TRANSLATE("Bay: %d.", eip13.bay)
);
TRANSLATE("physical disk drive: %[tag]", eip13.device);
ENDTRANSLATIONBLOCK
EC BLOCK: 06404d04 SCID_FCS_PROVISIONAL_DRIVE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip04.al_pa);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Latest known revision: %s", eip04.new_rev);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06410017 SCID_FCS_LOOP_CONFIG
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip17.cerp_id);
TRANSLATE("Map ID: %u", eip17.map_id);
TRANSLATE("Loop map page: %d of %d", eip17.page, eip17.total_pages);
TRANSLATE("Entries in this page: %d", eip17.entries);
CONDITIONAL(eip17.loop_map[0] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[00] ALPA: 0x%X", eip17.loop_map[0])
);
CONDITIONAL(eip17.loop_map[0] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[92] ALPA: 0x%X", eip17.loop_map[0])
);
CONDITIONAL(eip17.loop_map[1] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[01] ALPA: 0x%X", eip17.loop_map[1])
);
CONDITIONAL(eip17.loop_map[1] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[93] ALPA: 0x%X", eip17.loop_map[1])
);
CONDITIONAL(eip17.loop_map[2] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[02] ALPA: 0x%X", eip17.loop_map[2])
);
CONDITIONAL(eip17.loop_map[2] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[94] ALPA: 0x%X", eip17.loop_map[2])
);
CONDITIONAL(eip17.loop_map[3] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[03] ALPA: 0x%X", eip17.loop_map[3])
);
CONDITIONAL(eip17.loop_map[3] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[95] ALPA: 0x%X", eip17.loop_map[3])
);
CONDITIONAL(eip17.loop_map[4] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[04] ALPA: 0x%X", eip17.loop_map[4])
);
CONDITIONAL(eip17.loop_map[4] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[96] ALPA: 0x%X", eip17.loop_map[4])
);
CONDITIONAL(eip17.loop_map[5] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[05] ALPA: 0x%X", eip17.loop_map[5])
);
CONDITIONAL(eip17.loop_map[5] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[97] ALPA: 0x%X", eip17.loop_map[5])
);
CONDITIONAL(eip17.loop_map[6] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[06] ALPA: 0x%X", eip17.loop_map[6])
);
CONDITIONAL(eip17.loop_map[6] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[98] ALPA: 0x%X", eip17.loop_map[6])
);
CONDITIONAL(eip17.loop_map[7] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[07] ALPA: 0x%X", eip17.loop_map[7])
);
CONDITIONAL(eip17.loop_map[7] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[99] ALPA: 0x%X", eip17.loop_map[7])
);
CONDITIONAL(eip17.loop_map[8] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[08] ALPA: 0x%X", eip17.loop_map[8])
);
CONDITIONAL(eip17.loop_map[8] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[100] ALPA: 0x%X", eip17.loop_map[8])
);
CONDITIONAL(eip17.loop_map[9] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[09] ALPA: 0x%X", eip17.loop_map[9])
);
CONDITIONAL(eip17.loop_map[9] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[101] ALPA: 0x%X", eip17.loop_map[9])
);
CONDITIONAL(eip17.loop_map[10] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[10] ALPA: 0x%X", eip17.loop_map[10])
);
CONDITIONAL(eip17.loop_map[10] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[102] ALPA: 0x%X", eip17.loop_map[10])
);
CONDITIONAL(eip17.loop_map[11] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[11] ALPA: 0x%X", eip17.loop_map[11])
);
CONDITIONAL(eip17.loop_map[11] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[103] ALPA: 0x%X", eip17.loop_map[11])
);
CONDITIONAL(eip17.loop_map[12] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[12] ALPA: 0x%X", eip17.loop_map[12])
);
CONDITIONAL(eip17.loop_map[12] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[104] ALPA: 0x%X", eip17.loop_map[12])
);
CONDITIONAL(eip17.loop_map[13] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[13] ALPA: 0x%X", eip17.loop_map[13])
);
CONDITIONAL(eip17.loop_map[13] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[105] ALPA: 0x%X", eip17.loop_map[13])
);
CONDITIONAL(eip17.loop_map[14] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[14] ALPA: 0x%X", eip17.loop_map[14])
);
CONDITIONAL(eip17.loop_map[14] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[106] ALPA: 0x%X", eip17.loop_map[14])
);
CONDITIONAL(eip17.loop_map[15] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[15] ALPA: 0x%X", eip17.loop_map[15])
);
CONDITIONAL(eip17.loop_map[15] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[107] ALPA: 0x%X", eip17.loop_map[15])
);
CONDITIONAL(eip17.loop_map[16] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[16] ALPA: 0x%X", eip17.loop_map[16])
);
CONDITIONAL(eip17.loop_map[16] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[108] ALPA: 0x%X", eip17.loop_map[16])
);
CONDITIONAL(eip17.loop_map[17] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[17] ALPA: 0x%X", eip17.loop_map[17])
);
CONDITIONAL(eip17.loop_map[17] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[109] ALPA: 0x%X", eip17.loop_map[17])
);
CONDITIONAL(eip17.loop_map[18] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[18] ALPA: 0x%X", eip17.loop_map[18])
);
CONDITIONAL(eip17.loop_map[18] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[110] ALPA: 0x%X", eip17.loop_map[18])
);
CONDITIONAL(eip17.loop_map[19] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[19] ALPA: 0x%X", eip17.loop_map[19])
);
CONDITIONAL(eip17.loop_map[19] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[111] ALPA: 0x%X", eip17.loop_map[19])
);
CONDITIONAL(eip17.loop_map[20] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[20] ALPA: 0x%X", eip17.loop_map[20])
);
CONDITIONAL(eip17.loop_map[20] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[112] ALPA: 0x%X", eip17.loop_map[20])
);
CONDITIONAL(eip17.loop_map[21] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[21] ALPA: 0x%X", eip17.loop_map[21])
);
CONDITIONAL(eip17.loop_map[21] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[113] ALPA: 0x%X", eip17.loop_map[21])
);
CONDITIONAL(eip17.loop_map[22] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[22] ALPA: 0x%X", eip17.loop_map[22])
);
CONDITIONAL(eip17.loop_map[22] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[114] ALPA: 0x%X", eip17.loop_map[22])
);
CONDITIONAL(eip17.loop_map[23] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[23] ALPA: 0x%X", eip17.loop_map[23])
);
CONDITIONAL(eip17.loop_map[23] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[115] ALPA: 0x%X", eip17.loop_map[23])
);
CONDITIONAL(eip17.loop_map[24] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[24] ALPA: 0x%X", eip17.loop_map[24])
);
CONDITIONAL(eip17.loop_map[24] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[116] ALPA: 0x%X", eip17.loop_map[24])
);
CONDITIONAL(eip17.loop_map[25] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[25] ALPA: 0x%X", eip17.loop_map[25])
);
CONDITIONAL(eip17.loop_map[25] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[117] ALPA: 0x%X", eip17.loop_map[25])
);
CONDITIONAL(eip17.loop_map[26] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[26] ALPA: 0x%X", eip17.loop_map[26])
);
CONDITIONAL(eip17.loop_map[26] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[118] ALPA: 0x%X", eip17.loop_map[26])
);
CONDITIONAL(eip17.loop_map[27] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[27] ALPA: 0x%X", eip17.loop_map[27])
);
CONDITIONAL(eip17.loop_map[27] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[119] ALPA: 0x%X", eip17.loop_map[27])
);
CONDITIONAL(eip17.loop_map[28] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[28] ALPA: 0x%X", eip17.loop_map[28])
);
CONDITIONAL(eip17.loop_map[28] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[120] ALPA: 0x%X", eip17.loop_map[28])
);
CONDITIONAL(eip17.loop_map[29] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[29] ALPA: 0x%X", eip17.loop_map[29])
);
CONDITIONAL(eip17.loop_map[29] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[121] ALPA: 0x%X", eip17.loop_map[29])
);
CONDITIONAL(eip17.loop_map[30] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[30] ALPA: 0x%X", eip17.loop_map[30])
);
CONDITIONAL(eip17.loop_map[30] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[122] ALPA: 0x%X", eip17.loop_map[30])
);
CONDITIONAL(eip17.loop_map[31] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[31] ALPA: 0x%X", eip17.loop_map[31])
);
CONDITIONAL(eip17.loop_map[31] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[123] ALPA: 0x%X", eip17.loop_map[31])
);
CONDITIONAL(eip17.loop_map[32] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[32] ALPA: 0x%X", eip17.loop_map[32])
);
CONDITIONAL(eip17.loop_map[32] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[124] ALPA: 0x%X", eip17.loop_map[32])
);
CONDITIONAL(eip17.loop_map[33] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[33] ALPA: 0x%X", eip17.loop_map[33])
);
CONDITIONAL(eip17.loop_map[33] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[125] ALPA: 0x%X", eip17.loop_map[33])
);
CONDITIONAL(eip17.loop_map[34] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[34] ALPA: 0x%X", eip17.loop_map[34])
);
CONDITIONAL(eip17.loop_map[34] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[126] ALPA: 0x%X", eip17.loop_map[34])
);
CONDITIONAL(eip17.loop_map[35] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[35] ALPA: 0x%X", eip17.loop_map[35])
);
CONDITIONAL(eip17.loop_map[35] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[127] ALPA: 0x%X", eip17.loop_map[35])
);
CONDITIONAL(eip17.loop_map[36] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[36] ALPA: 0x%X", eip17.loop_map[36])
);
CONDITIONAL(eip17.loop_map[36] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[128] ALPA: 0x%X", eip17.loop_map[36])
);
CONDITIONAL(eip17.loop_map[37] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[37] ALPA: 0x%X", eip17.loop_map[37])
);
CONDITIONAL(eip17.loop_map[37] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[129] ALPA: 0x%X", eip17.loop_map[37])
);
CONDITIONAL(eip17.loop_map[38] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[38] ALPA: 0x%X", eip17.loop_map[38])
);
CONDITIONAL(eip17.loop_map[38] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[130] ALPA: 0x%X", eip17.loop_map[38])
);
CONDITIONAL(eip17.loop_map[39] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[39] ALPA: 0x%X", eip17.loop_map[39])
);
CONDITIONAL(eip17.loop_map[39] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[131] ALPA: 0x%X", eip17.loop_map[39])
);
CONDITIONAL(eip17.loop_map[40] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[40] ALPA: 0x%X", eip17.loop_map[40])
);
CONDITIONAL(eip17.loop_map[40] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[132] ALPA: 0x%X", eip17.loop_map[40])
);
CONDITIONAL(eip17.loop_map[41] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[41] ALPA: 0x%X", eip17.loop_map[41])
);
CONDITIONAL(eip17.loop_map[41] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[133] ALPA: 0x%X", eip17.loop_map[41])
);
CONDITIONAL(eip17.loop_map[42] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[42] ALPA: 0x%X", eip17.loop_map[42])
);
CONDITIONAL(eip17.loop_map[42] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[134] ALPA: 0x%X", eip17.loop_map[42])
);
CONDITIONAL(eip17.loop_map[43] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[43] ALPA: 0x%X", eip17.loop_map[43])
);
CONDITIONAL(eip17.loop_map[43] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[135] ALPA: 0x%X", eip17.loop_map[43])
);
CONDITIONAL(eip17.loop_map[44] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[44] ALPA: 0x%X", eip17.loop_map[44])
);
CONDITIONAL(eip17.loop_map[44] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[136] ALPA: 0x%X", eip17.loop_map[44])
);
CONDITIONAL(eip17.loop_map[45] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[45] ALPA: 0x%X", eip17.loop_map[45])
);
CONDITIONAL(eip17.loop_map[45] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[137] ALPA: 0x%X", eip17.loop_map[45])
);
CONDITIONAL(eip17.loop_map[46] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[46] ALPA: 0x%X", eip17.loop_map[46])
);
CONDITIONAL(eip17.loop_map[46] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[138] ALPA: 0x%X", eip17.loop_map[46])
);
CONDITIONAL(eip17.loop_map[47] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[47] ALPA: 0x%X", eip17.loop_map[47])
);
CONDITIONAL(eip17.loop_map[47] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[139] ALPA: 0x%X", eip17.loop_map[47])
);
CONDITIONAL(eip17.loop_map[48] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[48] ALPA: 0x%X", eip17.loop_map[48])
);
CONDITIONAL(eip17.loop_map[48] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[140] ALPA: 0x%X", eip17.loop_map[48])
);
CONDITIONAL(eip17.loop_map[49] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[49] ALPA: 0x%X", eip17.loop_map[49])
);
CONDITIONAL(eip17.loop_map[49] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[141] ALPA: 0x%X", eip17.loop_map[49])
);
CONDITIONAL(eip17.loop_map[50] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[50] ALPA: 0x%X", eip17.loop_map[50])
);
CONDITIONAL(eip17.loop_map[50] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[142] ALPA: 0x%X", eip17.loop_map[50])
);
CONDITIONAL(eip17.loop_map[51] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[51] ALPA: 0x%X", eip17.loop_map[51])
);
CONDITIONAL(eip17.loop_map[51] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[143] ALPA: 0x%X", eip17.loop_map[51])
);
CONDITIONAL(eip17.loop_map[52] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[52] ALPA: 0x%X", eip17.loop_map[52])
);
CONDITIONAL(eip17.loop_map[52] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[144] ALPA: 0x%X", eip17.loop_map[52])
);
CONDITIONAL(eip17.loop_map[53] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[53] ALPA: 0x%X", eip17.loop_map[53])
);
CONDITIONAL(eip17.loop_map[53] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[145] ALPA: 0x%X", eip17.loop_map[53])
);
CONDITIONAL(eip17.loop_map[54] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[54] ALPA: 0x%X", eip17.loop_map[54])
);
CONDITIONAL(eip17.loop_map[54] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[146] ALPA: 0x%X", eip17.loop_map[54])
);
CONDITIONAL(eip17.loop_map[55] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[55] ALPA: 0x%X", eip17.loop_map[55])
);
CONDITIONAL(eip17.loop_map[55] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[147] ALPA: 0x%X", eip17.loop_map[55])
);
CONDITIONAL(eip17.loop_map[56] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[56] ALPA: 0x%X", eip17.loop_map[56])
);
CONDITIONAL(eip17.loop_map[56] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[148] ALPA: 0x%X", eip17.loop_map[56])
);
CONDITIONAL(eip17.loop_map[57] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[57] ALPA: 0x%X", eip17.loop_map[57])
);
CONDITIONAL(eip17.loop_map[57] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[149] ALPA: 0x%X", eip17.loop_map[57])
);
CONDITIONAL(eip17.loop_map[58] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[58] ALPA: 0x%X", eip17.loop_map[58])
);
CONDITIONAL(eip17.loop_map[58] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[150] ALPA: 0x%X", eip17.loop_map[58])
);
CONDITIONAL(eip17.loop_map[59] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[59] ALPA: 0x%X", eip17.loop_map[59])
);
CONDITIONAL(eip17.loop_map[59] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[151] ALPA: 0x%X", eip17.loop_map[59])
);
CONDITIONAL(eip17.loop_map[60] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[60] ALPA: 0x%X", eip17.loop_map[60])
);
CONDITIONAL(eip17.loop_map[60] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[152] ALPA: 0x%X", eip17.loop_map[60])
);
CONDITIONAL(eip17.loop_map[61] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[61] ALPA: 0x%X", eip17.loop_map[61])
);
CONDITIONAL(eip17.loop_map[61] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[153] ALPA: 0x%X", eip17.loop_map[61])
);
CONDITIONAL(eip17.loop_map[62] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[62] ALPA: 0x%X", eip17.loop_map[62])
);
CONDITIONAL(eip17.loop_map[62] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[154] ALPA: 0x%X", eip17.loop_map[62])
);
CONDITIONAL(eip17.loop_map[63] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[63] ALPA: 0x%X", eip17.loop_map[63])
);
CONDITIONAL(eip17.loop_map[63] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[155] ALPA: 0x%X", eip17.loop_map[63])
);
CONDITIONAL(eip17.loop_map[64] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[64] ALPA: 0x%X", eip17.loop_map[64])
);
CONDITIONAL(eip17.loop_map[64] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[156] ALPA: 0x%X", eip17.loop_map[64])
);
CONDITIONAL(eip17.loop_map[65] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[65] ALPA: 0x%X", eip17.loop_map[65])
);
CONDITIONAL(eip17.loop_map[65] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[157] ALPA: 0x%X", eip17.loop_map[65])
);
CONDITIONAL(eip17.loop_map[66] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[66] ALPA: 0x%X", eip17.loop_map[66])
);
CONDITIONAL(eip17.loop_map[66] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[158] ALPA: 0x%X", eip17.loop_map[66])
);
CONDITIONAL(eip17.loop_map[67] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[67] ALPA: 0x%X", eip17.loop_map[67])
);
CONDITIONAL(eip17.loop_map[67] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[159] ALPA: 0x%X", eip17.loop_map[67])
);
CONDITIONAL(eip17.loop_map[68] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[68] ALPA: 0x%X", eip17.loop_map[68])
);
CONDITIONAL(eip17.loop_map[68] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[160] ALPA: 0x%X", eip17.loop_map[68])
);
CONDITIONAL(eip17.loop_map[69] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[69] ALPA: 0x%X", eip17.loop_map[69])
);
CONDITIONAL(eip17.loop_map[69] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[161] ALPA: 0x%X", eip17.loop_map[69])
);
CONDITIONAL(eip17.loop_map[70] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[70] ALPA: 0x%X", eip17.loop_map[70])
);
CONDITIONAL(eip17.loop_map[70] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[162] ALPA: 0x%X", eip17.loop_map[70])
);
CONDITIONAL(eip17.loop_map[71] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[71] ALPA: 0x%X", eip17.loop_map[71])
);
CONDITIONAL(eip17.loop_map[71] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[163] ALPA: 0x%X", eip17.loop_map[71])
);
CONDITIONAL(eip17.loop_map[72] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[72] ALPA: 0x%X", eip17.loop_map[72])
);
CONDITIONAL(eip17.loop_map[72] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[164] ALPA: 0x%X", eip17.loop_map[72])
);
CONDITIONAL(eip17.loop_map[73] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[73] ALPA: 0x%X", eip17.loop_map[73])
);
CONDITIONAL(eip17.loop_map[73] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[165] ALPA: 0x%X", eip17.loop_map[73])
);
CONDITIONAL(eip17.loop_map[74] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[74] ALPA: 0x%X", eip17.loop_map[74])
);
CONDITIONAL(eip17.loop_map[74] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[166] ALPA: 0x%X", eip17.loop_map[74])
);
CONDITIONAL(eip17.loop_map[75] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[75] ALPA: 0x%X", eip17.loop_map[75])
);
CONDITIONAL(eip17.loop_map[75] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[167] ALPA: 0x%X", eip17.loop_map[75])
);
CONDITIONAL(eip17.loop_map[76] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[76] ALPA: 0x%X", eip17.loop_map[76])
);
CONDITIONAL(eip17.loop_map[76] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[168] ALPA: 0x%X", eip17.loop_map[76])
);
CONDITIONAL(eip17.loop_map[77] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[77] ALPA: 0x%X", eip17.loop_map[77])
);
CONDITIONAL(eip17.loop_map[77] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[169] ALPA: 0x%X", eip17.loop_map[77])
);
CONDITIONAL(eip17.loop_map[78] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[78] ALPA: 0x%X", eip17.loop_map[78])
);
CONDITIONAL(eip17.loop_map[78] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[170] ALPA: 0x%X", eip17.loop_map[78])
);
CONDITIONAL(eip17.loop_map[79] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[79] ALPA: 0x%X", eip17.loop_map[79])
);
CONDITIONAL(eip17.loop_map[79] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[171] ALPA: 0x%X", eip17.loop_map[79])
);
CONDITIONAL(eip17.loop_map[80] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[80] ALPA: 0x%X", eip17.loop_map[80])
);
CONDITIONAL(eip17.loop_map[80] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[172] ALPA: 0x%X", eip17.loop_map[80])
);
CONDITIONAL(eip17.loop_map[81] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[81] ALPA: 0x%X", eip17.loop_map[81])
);
CONDITIONAL(eip17.loop_map[81] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[173] ALPA: 0x%X", eip17.loop_map[81])
);
CONDITIONAL(eip17.loop_map[82] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[82] ALPA: 0x%X", eip17.loop_map[82])
);
CONDITIONAL(eip17.loop_map[82] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[174] ALPA: 0x%X", eip17.loop_map[82])
);
CONDITIONAL(eip17.loop_map[83] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[83] ALPA: 0x%X", eip17.loop_map[83])
);
CONDITIONAL(eip17.loop_map[83] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[175] ALPA: 0x%X", eip17.loop_map[83])
);
CONDITIONAL(eip17.loop_map[84] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[84] ALPA: 0x%X", eip17.loop_map[84])
);
CONDITIONAL(eip17.loop_map[84] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[176] ALPA: 0x%X", eip17.loop_map[84])
);
CONDITIONAL(eip17.loop_map[85] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[85] ALPA: 0x%X", eip17.loop_map[85])
);
CONDITIONAL(eip17.loop_map[85] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[177] ALPA: 0x%X", eip17.loop_map[85])
);
CONDITIONAL(eip17.loop_map[86] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[86] ALPA: 0x%X", eip17.loop_map[86])
);
CONDITIONAL(eip17.loop_map[86] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[178] ALPA: 0x%X", eip17.loop_map[86])
);
CONDITIONAL(eip17.loop_map[87] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[87] ALPA: 0x%X", eip17.loop_map[87])
);
CONDITIONAL(eip17.loop_map[87] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[179] ALPA: 0x%X", eip17.loop_map[87])
);
CONDITIONAL(eip17.loop_map[88] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[88] ALPA: 0x%X", eip17.loop_map[88])
);
CONDITIONAL(eip17.loop_map[88] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[180] ALPA: 0x%X", eip17.loop_map[88])
);
CONDITIONAL(eip17.loop_map[89] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[89] ALPA: 0x%X", eip17.loop_map[89])
);
CONDITIONAL(eip17.loop_map[89] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[181] ALPA: 0x%X", eip17.loop_map[89])
);
CONDITIONAL(eip17.loop_map[90] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[90] ALPA: 0x%X", eip17.loop_map[90])
);
CONDITIONAL(eip17.loop_map[90] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[182] ALPA: 0x%X", eip17.loop_map[90])
);
CONDITIONAL(eip17.loop_map[91] != 0xFF &&
eip17.page == 1,
TRANSLATE("Loop Map[91] ALPA: 0x%X", eip17.loop_map[91])
);
CONDITIONAL(eip17.loop_map[91] != 0xFF &&
eip17.page == 2,
TRANSLATE("Loop Map[183] ALPA: 0x%X", eip17.loop_map[91])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 06420009 SCID_FCS_PASSTHRU_CMD
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06440008 SCID_FCS_LOOP_RECOVERY_SHELF
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Enclosure ID: %d", eip08.recovery.shelf);
ENDTRANSLATIONBLOCK
EC BLOCK: 06450008 SCID_FCS_LOOP_RECOVERY_SUSPECT
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Cabinet ID: %d", eip08.recovery.cab);
TRANSLATE("Enclosure ID: %d", eip08.recovery.shelf);
TRANSLATE("Bay: %d", eip08.recovery.slot);
ENDTRANSLATIONBLOCK
EC BLOCK: 06460008 SCID_FCS_LOOP_RECOVERY_CAB_ERROR
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 06480008 SCID_FCS_LOOP_RECOVERY_BYPASS_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Unbypass Failure Enclosure Mask: %x", eip08.failure_cause);
ENDTRANSLATIONBLOCK
EC BLOCK: 06490008 SCID_FCS_ENCLOSURE_RECOVERY_ENTERED
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Cab: %d, Enclosure %d", eip08.recovery.cab, eip08.recovery.shelf);
ENDTRANSLATIONBLOCK
EC BLOCK: 064a0008 SCID_FCS_ENCLOSURE_RECOVERY_EXIT
TRANSLATIONBLOCK
TRANSLATE("Port IDs: %s %s", eip08.cerp_id, eip08.other_cerp_id);
TRANSLATE("Cab: %d, Enclosure %d", eip08.recovery.cab, eip08.recovery.shelf);
TRANSLATE("Recovery Status: %x", eip08.failure_cause);
ENDTRANSLATIONBLOCK
EC BLOCK: 064b0008 SCID_FCS_LOOP_RECOVERY
TRANSLATIONBLOCK
TRANSLATE("Loop Recoveries Flag: %d", eip08.recovery.progress);
CONDITIONAL(eip08.recovery.progress == 0x01,
TRANSLATE("ENABLE Loop Recovery Operations"));
CONDITIONAL(eip08.recovery.progress == 0x00,
TRANSLATE("DISABLE Loop Recovery Operations"));
ENDTRANSLATIONBLOCK
EC BLOCK: 064c0004 SCID_FCS_DSL_DRIVE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("Failure Reason Code: %d", eip04.bypass_reason);
ENDTRANSLATIONBLOCK
EC BLOCK: 064d0008 SCID_FCS_CODELOAD_COMPLETE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
EC BLOCK: 064e0009 SCID_FCS_NON_ZERO_RSP_CODE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip09.device);
TRANSLATE("Port ID: %s", eip09.cerp_id);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip09.dencl_num - 100
)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip09.bay - 100)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip09.dencl_num)
);
CONDITIONAL(eip09.al_pa != 0x01 &&
eip09.al_pa != 0x02 &&
eip09.al_pa != 0xEE &&
eip09.dencl_num < 99,
TRANSLATE("Bay: %d.", eip09.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip09.al_pa);
TRANSLATE("%s", XLATE_EIP09_OPCODE(
eip09.fed_class,
eip09.cmd.cdb10.opcode
)
);
TRANSLATE(
"RSP Code: 0x%02x",
eip09.error.sense_data.fru_code
);
TRANSLATE("Bay Bypass Mask Loop A 0x%X",eip09.bypassa);
TRANSLATE("Bay Bypass Mask Loop B 0x%X",eip09.bypassb);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip09.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 0700b515 SCID_CS_ALLOCATION_STALL
TRANSLATIONBLOCK
TRANSLATE("Virtual Disk: %[tag]", eip15.tag1);
TRANSLATE("Disk Group: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 0,
TRANSLATE("State: Attempting to retry allocation")
);
CONDITIONAL(eip15.state == 1,
TRANSLATE("State: Awaiting a leveling event")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0701b515 SCID_CS_EXPANSION_STALL
TRANSLATIONBLOCK
TRANSLATE("Virtual Disk: %[tag]", eip15.tag1);
TRANSLATE("Disk Group: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 0,
TRANSLATE("State: Attempting to retry allocation")
);
CONDITIONAL(eip15.state == 1,
TRANSLATE("State: Awaiting a leveling event")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 07020015 SCID_CS_LEVELING_START
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[tag]", eip15.tag1);
ENDTRANSLATIONBLOCK
EC BLOCK: 07030015 SCID_CS_LEVELING_END
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[tag]", eip15.tag1);
CONDITIONAL(eip15.state == 0,
TRANSLATE("Not Level"),
TRANSLATE("Level")
);
CONDITIONAL(eip15.status == 0,
TRANSLATE("No Data Moved"),
TRANSLATE("Data Moved")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 07040015 SCID_CS_MEMBER_MANAGER_OP_START
TRANSLATIONBLOCK
CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Volume identity unavailable"),
TRANSLATE("Volume: %[tag]", eip15.tag1)
);
TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 2,
TRANSLATE("State: Reconstructing")
);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Migrating")
);
CONDITIONAL(eip15.state == 6,
TRANSLATE("State: Reverting")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 07050015 SCID_CS_MEMBER_MANAGER_OP_END
TRANSLATIONBLOCK
CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Volume identity unavailable"),
TRANSLATE("Volume: %[tag]", eip15.tag1)
);
TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 2,
TRANSLATE("State: Reconstructing")
);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Migrating")
);
CONDITIONAL(eip15.state == 6,
TRANSLATE("State: Reverting")
);
CONDITIONAL(eip15.status == 1,
TRANSLATE("Status: success")
);
CONDITIONAL(eip15.status == 2,
TRANSLATE("Status: RAID0 reconstruct failed")
);
CONDITIONAL(eip15.status == 4,
TRANSLATE("Status: RAID5 reconstruct failed")
);
CONDITIONAL(eip15.status == 8,
TRANSLATE("Status: RAID1 reconstruct failed")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 07060015 SCID_CS_MIGRATION_START
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[tag]", eip15.tag1);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Merge began")
);
CONDITIONAL(eip15.state == 8,
TRANSLATE("State: Split began")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 07070015 SCID_CS_MIGRATION_END
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[tag]", eip15.tag1);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Merge complete")
);
CONDITIONAL(eip15.state == 8,
TRANSLATE("State: Split complete")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 07080015 SCID_CS_DELETION_FAILED
TRANSLATIONBLOCK
TRANSLATE("Virtual Disk: %[tag]", eip15.tag1);
TRANSLATE("Disk group: %[tag]", eip15.tag2);
TRANSLATE("Status: %d", eip15.status);
ENDTRANSLATIONBLOCK
EC BLOCK: 0709b515 SCID_CS_MEMBER_MANAGER_OP_STALL
TRANSLATIONBLOCK
CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Volume identity unavailable"),
TRANSLATE("Volume: %[tag]", eip15.tag1)
);
TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Migrating")
);
CONDITIONAL(eip15.status == 1,
TRANSLATE("Status: Awaiting additional storage")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 070a0015 SCID_CS_MEMBER_MANAGER_OP_RESTART
TRANSLATIONBLOCK
CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Volume identity unavailable"),
TRANSLATE("Volume: %[tag]", eip15.tag1)
);
TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Migrating")
);
CONDITIONAL(eip15.status == 0,
TRANSLATE("Status: Retrying the operation")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 070b0015 SCID_CS_METADATA_INCONSISTENCY
TRANSLATIONBLOCK
CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Volume identity unavailable"),
TRANSLATE("Volume: %[tag]", eip15.tag1)
);
CONDITIONAL(eip15.tag2 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Logical Disk identity unavailable"),
TRANSLATE("Logical Disk: %[tag]", eip15.tag2)
);
CONDITIONAL(eip15.state == 0,
TRANSLATE("State: Physical Segment Deallocated")
);
CONDITIONAL(eip15.state == 1,
TRANSLATE("State: Unreferenced Physical Segment")
);
CONDITIONAL(eip15.state == 2,
TRANSLATE("State: Multi-referenced Physical Segment")
);
CONDITIONAL(eip15.state == 3,
TRANSLATE("State: NULL rsdm_ptr in update_lmap_shared")
);
CONDITIONAL(eip15.status == 0,
TRANSLATE("Status: OK")
);
CONDITIONAL(eip15.status == 1,
TRANSLATE("Status: FAILURE")
);
CONDITIONAL(eip15.status == 3 &&
eip15.state == 3,
TRANSLATE("LD is overcommitted")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 070d0015 SCID_CS_MEMBER_MANAGER_OP_ERROR
TRANSLATIONBLOCK
TRANSLATE("Logical Disk: %[tag]", eip15.tag1);
TRANSLATE("Volume: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 2,
TRANSLATE("State: Reconstructing")
);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Migrating")
);
CONDITIONAL(eip15.state == 6,
TRANSLATE("State: Reverting")
);
TRANSLATE("Error: 0x%x", eip15.status);
TRANSLATE("Error: 0x01 = Missing Drive");
TRANSLATE("Error: 0x02 = Invalid RAID type");
TRANSLATE("Error: 0x04 = Invalid member management opeartion");
TRANSLATE("Error: 0x08 = Invalid RStore");
TRANSLATE("Error: 0x10 = LD Realization Failed");
ENDTRANSLATIONBLOCK
EC BLOCK: 09010005 SCID_SCMI_PS_CONDITION_CHANGE_NOACT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09020005 SCID_SCMI_VOL_CONDITION_CHANGE_NOACT
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]",
eip05.add_handle
);
TRANSLATE(
"State: %[scmi_volume_condition] --> %[scmi_volume_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)",
eip05.attribute.value.u16[6],
eip05.attribute.value.u16[6]
);
TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)",
eip05.attribute.value.u16[7],
eip05.attribute.value.u16[7]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09030005 SCID_SCMI_LDISK_CONDITION_CHANGE_NOACT
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09040005 SCID_SCMI_NSC_CONDITION_CHANGE_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_nsc_condition] --> %[scmi_nsc_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09050005 SCID_SCMI_NSC_CACHE_BATT_CONDITION_CHANGE_NOACT
TRANSLATIONBLOCK
TRANSLATE("Controller containing battery: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0906bf05 SCID_SCMI_VOL_CONDITION_CHANGE_MISSING
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]",
eip05.add_handle
);
TRANSLATE(
"State: %[scmi_volume_condition] --> %[scmi_volume_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)",
eip05.attribute.value.u16[6],
eip05.attribute.value.u16[6]
);
TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)",
eip05.attribute.value.u16[7],
eip05.attribute.value.u16[7]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09070005 SCID_SCMI_NSC_FC_PORT_CONDITION_CHANGE_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Fibre Channel port: %s (%d.)",
eip05.attribute.value.str,
eip05.secondary_id
);
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_nsc_fc_port_condition] --> %[scmi_nsc_fc_port_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0908b405 SCID_SCMI_LDAD_OCCUPANCY_HIGHWATER
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE("State: Normal --> Threshold reached");
ENDTRANSLATIONBLOCK
EC BLOCK: 09090005 SCID_SCMI_VOL_INSUFF_RESOURCE_CHANGE_SUFFICIENT
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]",
eip05.add_handle
);
TRANSLATE(
"State: %[scmi_volume_resource_availability_condition] --> %[scmi_volume_resource_availability_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)",
eip05.attribute.value.u16[6],
eip05.attribute.value.u16[6]
);
TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)",
eip05.attribute.value.u16[7],
eip05.attribute.value.u16[7]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 090a0005 SCID_SCMI_LDISK_DATA_LOST_CHANGE_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_data_availability_condition] --> %[scmi_logical_disk_data_availability_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 090c0005 SCID_SCMI_LDISK_SNAPCLONE_UNSHARE_DONE
TRANSLATIONBLOCK
TRANSLATE("Snapclone Logical Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Noid of parent internal Logical Disk: 0x%04x",
eip05.secondary_id
);
ENDTRANSLATIONBLOCK
EC BLOCK: 090d0005 SCID_SCMI_VOL_QUORUM_DISK_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_volume_quorum_disk_condition] --> %[scmi_volume_quorum_disk_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 090e3605 SCID_SCMI_NSC_TEMP_TRIP_REACHED
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Sensor 1 current temperature: %d. degrees Celsius",
eip05.value.ul1
);
TRANSLATE(
"Sensor 2 adjusted temperature: %d. degrees Celsius",
eip05.value.ul2
);
TRANSLATE(
"Trip point temperature: %d. degrees Celsius",
eip05.secondary_id
);
ENDTRANSLATIONBLOCK
EC BLOCK: 090f2e05 SCID_SCMI_NSC_CLOSE_TO_TEMP_TRIP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Sensor 1 current temperature: %d. degrees Celsius",
eip05.value.ul1
);
TRANSLATE(
"Sensor 2 adjusted temperature: %d. degrees Celsius",
eip05.value.ul2
);
TRANSLATE(
"Trip point temperature: %d. degrees Celsius",
eip05.secondary_id
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09110005 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_NPP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09122405 SCID_SCMI_NSC_FANA_SPEED_SLOW
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE("Current speed: %d. RPM", eip05.value.ul1);
TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 09132005 SCID_SCMI_NSC_VOLTAGE_OUT_OF_RANGE
TRANSLATIONBLOCK
CONDITIONAL(
eip05.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Out of range voltage: %d. millivolts", eip05.value.ul1);
TRANSLATE("Voltage threshold: %d. millivolts", eip05.secondary_id);
TRANSLATE("DIMM size: %d MB", eip05.add_data[0] );
ENDTRANSLATIONBLOCK
EC BLOCK: 0914bf05 SCID_SCMI_VOL_CONDITION_CHANGE_FAILED
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_volume_condition] --> %[scmi_volume_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)",
eip05.attribute.value.u16[6],
eip05.attribute.value.u16[6]
);
TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)",
eip05.attribute.value.u16[7],
eip05.attribute.value.u16[7]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0915b905 SCID_SCMI_NSC_CONDITION_CHANGE_FAILED
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_nsc_condition] --> %[scmi_nsc_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09160005 SCID_SCMI_NSC_TEMP_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Sensor 1 current temperature: %d. degrees Celsius",
eip05.value.ul1
);
TRANSLATE(
"Sensor 2 adjusted temperature: %d. degrees Celsius",
eip05.value.ul2
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09172805 SCID_SCMI_NSC_BATTERYA_PRESENT_CHANGE_PNP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09180005 SCID_SCMI_NSC_BATTERYA_IN_USE_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09190005 SCID_SCMI_NSC_VOLTAGE_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Normal range voltage: %d. millivolts", eip05.value.ul1);
TRANSLATE("Voltage threshold: %d. millivolts", eip05.secondary_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 091a2005 SCID_SCMI_NSC_VOLTAGE_REGULATOR_FAILURE
TRANSLATIONBLOCK
CONDITIONAL(
eip05.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("DIMM size: %d MB", eip05.add_data[0] );
ENDTRANSLATIONBLOCK
EC BLOCK: 091b0005 SCID_SCMI_LDAD_CONDITION_CHANGE_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 091c0005 SCID_SCMI_LDAD_OCCUPANCY_HIGHWATER_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE("State: Threshold reached --> Normal");
ENDTRANSLATIONBLOCK
EC BLOCK: 091d2205 SCID_SCMI_NSC_BATTERYA_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 091e0005 SCID_SCMI_NSC_BATTERYA_PRESENT_CHANGE_NPP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 091f2905 SCID_SCMI_NSC_BATTERYB_PRESENT_CHANGE_PNP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09200005 SCID_SCMI_NSC_BATTERYB_PRESENT_CHANGE_NPP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_present_condition] --> %[scmi_nsc_battery_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09210005 SCID_SCMI_NSC_BATTERYB_IN_USE_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09222305 SCID_SCMI_NSC_BATTERYB_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Battery assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_battery_use_condition] --> %[scmi_nsc_battery_use_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09232b05 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_PNP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09240005 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_NPP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09252505 SCID_SCMI_NSC_FANB_SPEED_SLOW
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE("Current speed: %d. RPM", eip05.value.ul1);
TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 09262c05 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_PNP__POWER_SUPPLY
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09270005 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_NPP__POWER_SUPPLY
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09282d05 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_PNP__POWER_SUPPLY
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09290005 SCID_SCMI_NSC_FANB_PRESENT_CHANGE_NPP__POWER_SUPPLY
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fanps_present_condition] --> %[scmi_nsc_fanps_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 092a2605 SCID_SCMI_NSC_FANA_SPEED_SLOW__POWER_SUPPLY
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id);
TRANSLATE("Current speed: %d. RPM", eip05.value.ul1);
TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 092b2705 SCID_SCMI_NSC_FANB_SPEED_SLOW__POWER_SUPPLY
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower/Power Supply assembly: %d.", eip05.secondary_id);
TRANSLATE("Current speed: %d. RPM", eip05.value.ul1);
TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 092c2f05 SCID_SCMI_NSC_CACHE_BATT_CONDITION_CHANGE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 092dbf05 SCID_SCMI_VOL_INSUFF_RESOURCE_CHANGE_INSUFFICIENT
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]",
eip05.add_handle
);
TRANSLATE(
"State: %[scmi_volume_resource_availability_condition] --> %[scmi_volume_resource_availability_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)",
eip05.attribute.value.u16[6],
eip05.attribute.value.u16[6]
);
TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)",
eip05.attribute.value.u16[7],
eip05.attribute.value.u16[7]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 092e0005 SCID_SCMI_NSC_LOGIN_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Storage System Management Interface command: %[scmi_object_function_code]",
eip05.value.ul1
);
TRANSLATE("Host Adapter: %[scmi_obj_hnd]", eip05.attribute.value.obj.handle);
TRANSLATE(
"Reject reason: %[scmi_response_status_value]",
eip05.secondary_id
);
ENDTRANSLATIONBLOCK
EC BLOCK: 092f0005 SCID_SCMI_NSC_COMMAND_ERROR_RETURN
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Storage System Management Interface command: %[scmi_object_function_code]",
eip05.value.ul1
);
TRANSLATE(
"Return code: %[scmi_response_status_value]",
eip05.value.ul2
);
TRANSLATE(
"Internal command version: 0x%08x",
eip05.secondary_id
);
TRANSLATE(
"Internal target: %[scmi_obj_hnd]",
eip05.add_handle
);
TRANSLATE(
"scmicp.parms.u32[0]: %d",
eip05.attribute.value.u32[0]
);
TRANSLATE(
"scmicp.parms.u32[1]: %d",
eip05.attribute.value.u32[1]
);
TRANSLATE(
"scmicp.parms.u32[2]: %d",
eip05.attribute.value.u32[2]
);
TRANSLATE(
"scmicp.parms.u32[3]: %d",
eip05.attribute.value.u32[3]
);
TRANSLATE(
"scmicp.parms.u32[4]: %d",
eip05.attribute.value.u32[4]
);
TRANSLATE(
"scmicp.parms.u32[5]: %d",
eip05.attribute.value.u32[5]
);
TRANSLATE(
"Remote Error: %d",
eip05.add_data[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09300005 SCID_SCMI_NSC_LOOP_MAPGEN_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Loop pair: %d.", eip05.secondary_id);
TRANSLATE(
"Map generation number change: %d. --> %d.",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09314205 SCID_SCMI_PS_CONDITION_CHANGE_DEGRADED
TRANSLATIONBLOCK
TRANSLATE("physical disk drive: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09324005 SCID_SCMI_PS_CONDITION_CHANGE_FAILED
TRANSLATIONBLOCK
TRANSLATE("physical disk drive: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0933000e SCID_SCMI_DU_CREATED
TRANSLATIONBLOCK
TRANSLATE("Derived Unit: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE("Associated Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0E.attribute.value.obj.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0934000e SCID_SCMI_LDISK_CREATED
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE(
"Disk Group: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Size in blocks: %y.",
eip0E.attribute.value.u64[0]
);
TRANSLATE(
"Redundancy type: %[scmi_logical_disk_redundancy_type]",
eip0E.attribute.value.u32[2]
);
TRANSLATE(
"%[scmi_logical_disk_type]",
eip0E.attribute.value.u32[3]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0935000e SCID_SCMI_LDAD_CREATED
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip0E.handle
);
TRANSLATE("Number of disks in group: %d.",
eip0E.attribute.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0936000e SCID_SCMI_PS_DISCOVERED
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip0E.handle
);
CONDITIONAL(eip0E.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip0E.attribute.value.u32[0])
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip0E.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0937000e SCID_SCMI_PU_CREATED
TRANSLATIONBLOCK
TRANSLATE("Presented unit: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE(
"Associated Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0E.attribute.value.obj.handle
);
TRANSLATE(
"Host path: %[scmi_obj_hnd]",
eip0E.add_handle2
);
TRANSLATE(
"Host LUN number [0]: 0x%08x",
eip0E.add_data[0]
);
TRANSLATE(
"Host LUN number [1]: 0x%08x",
eip0E.add_data[1]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0938000e SCID_SCMI_SCELL_CLIENT_CREATED
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Host Path: %[scmi_obj_hnd]",
eip0E.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0939000e SCID_SCMI_SCVD_CREATED
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0E.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 093a000e SCID_SCMI_VOL_CREATED
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE("Associated physical disk drive: %[scmi_obj_hnd]",
eip0E.add_handle
);
CONDITIONAL(eip0E.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip0E.attribute.value.u32[0])
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip0E.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 093b000e SCID_SCMI_DU_DELETED
TRANSLATIONBLOCK
TRANSLATE("Derived unit: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE(
"Associated Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0E.attribute.value.obj.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 093c000e SCID_SCMI_LDISK_DELETED
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip0E.handle);
ENDTRANSLATIONBLOCK
EC BLOCK: 093d000e SCID_SCMI_LDAD_DELETED
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip0E.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 093e420e SCID_SCMI_PS_DISAPPEARED
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip0E.handle
);
CONDITIONAL(eip0E.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip0E.attribute.value.u32[0])
);
CONDITIONAL(eip0E.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip0E.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 093f000e SCID_SCMI_PU_DELETED
TRANSLATIONBLOCK
TRANSLATE("Presented unit: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE(
"Associated Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0E.attribute.value.obj.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0940000e SCID_SCMI_SCELL_CLIENT_DELETED
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Host Path: %[scmi_obj_hnd]",
eip0E.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0941000e SCID_SCMI_SCVD_DELETED
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0E.handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0E.add_handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0943000e SCID_SCMI_SCELL_OTHER_JOINED
TRANSLATIONBLOCK
CONDITIONAL(
eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Controller ID not available"),
TRANSLATE("Controller: %[scmi_obj_hnd]", eip0E.handle)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0944ba0e SCID_SCMI_SCELL_OTHER_GONE
TRANSLATIONBLOCK
CONDITIONAL(
eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Controller ID not available"),
TRANSLATE("Controller: %[scmi_obj_hnd]", eip0E.handle)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0945000e SCID_SCMI_SCELL_DELETED
TRANSLATIONBLOCK
CONDITIONAL(
eip0E.handle eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Storage System ID not available"),
TRANSLATE("Storage System: %[scmi_obj_hnd]",
eip0E.add_handle
)
);
CONDITIONAL(
eip0E.add_handle eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Controller ID not available"),
TRANSLATE("Controller: %[scmi_obj_hnd]", eip0E.add_handle)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0946000e SCID_SCMI_GROUP_CREATED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0E.handle
);
TRANSLATE( "Mode: %[scmi_group_drm_mode]",eip0E.add_data[0] );
ENDTRANSLATIONBLOCK
EC BLOCK: 0947000e SCID_SCMI_GROUP_DELETED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0E.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0948000e SCID_SCMI_SNAP_LD_CREATED
TRANSLATIONBLOCK
TRANSLATE("Associated snapshot Virtual Disk: %[scmi_obj_hnd]",
eip0E.handle
);
TRANSLATE(
"Disk Group: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Size in blocks: %y.",
eip0E.attribute.value.u64[0]
);
TRANSLATE(
"Redundancy type: %[scmi_logical_disk_redundancy_type]",
eip0E.attribute.value.u32[2]
);
TRANSLATE("Parent Logical Disk: %[scmi_obj_hnd]", eip0E.add_handle2);
ENDTRANSLATIONBLOCK
EC BLOCK: 0949000e SCID_SCMI_CLONE_LD_CREATED
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk copy: %[scmi_obj_hnd]",
eip0E.handle
);
TRANSLATE(
"Disk Group: %[scmi_obj_hnd]",
eip0E.add_handle
);
TRANSLATE(
"Size in blocks: %y.",
eip0E.attribute.value.u64[0]
);
TRANSLATE(
"Redundancy type: %[scmi_logical_disk_redundancy_type]",
eip0E.attribute.value.u32[2]
);
TRANSLATE("Parent Logical Disk: %[scmi_obj_hnd]", eip0E.add_handle2);
ENDTRANSLATIONBLOCK
EC BLOCK: 094a000e SCID_SCMI_GROUP_DELETE_INCOMPLETE
TRANSLATIONBLOCK
TRANSLATE(
"Destination Data Replication Group: %[scmi_obj_hnd]",
eip0E.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 094b000e SCID_SCMI_VOL_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Volume: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE("Associated Disk Group: %[scmi_obj_hnd]",
eip0E.add_handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 094c000e SCID_SCMI_RMTNODE_CREATED
TRANSLATIONBLOCK
TRANSLATE("Remote Node: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE("Storage System UUID: %[scmi_obj_hnd]",
eip0E.add_handle);
ENDTRANSLATIONBLOCK
EC BLOCK: 094d000e SCID_SCMI_RMTNODE_DELETED
TRANSLATIONBLOCK
TRANSLATE("Remote Node: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE("Storage System UUID: %[scmi_obj_hnd]",
eip0E.add_handle);
ENDTRANSLATIONBLOCK
EC BLOCK: 094e000e SCID_SCMI_RMTNODE_UPDATED
TRANSLATIONBLOCK
TRANSLATE("Remote Node: %[scmi_obj_hnd]", eip0E.handle);
TRANSLATE("Storage System UUID: %[scmi_obj_hnd]",
eip0E.add_handle);
ENDTRANSLATIONBLOCK
EC BLOCK: 0965000f SCID_SCMI_SCELL_CLIENT_MODE_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Host Path: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Mode: %[scmi_client_mode] --> %[scmi_client_mode]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0966000f SCID_SCMI_STORAGECELL_TIME_SET
TRANSLATIONBLOCK
CONDITIONAL(
eip0F.handle eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE(
"Storage System identity unavailable"
),
TRANSLATE(
"Storage System: %[scmi_obj_hnd]",
eip0F.handle
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0967000f SCID_SCMI_PU_LUN_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Presented unit: %[scmi_obj_hnd]", eip0F.handle);
TRANSLATE(
"LUN: %y. --> %y.",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
TRANSLATE("Storage System Virtual Disk noid: 0x%04x", eip0F.secondary_id.Id);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0968000f SCID_SCMI_STORAGECELL_DEV_ADDITION_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Storage System: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Policy: %[scmi_storagecell_device_addition_policy] --> %[scmi_storagecell_device_addition_policy]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0969000f SCID_SCMI_SCVD_QUIESCED_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
TRANSLATE(
"State: %[scmi_scvd_quiescent_condition] --> %[scmi_scvd_quiescent_condition]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 096a000f SCID_SCMI_SCVD_STATE_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
TRANSLATE(
"State: %[scmi_state] --> %[scmi_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 096b000f SCID_SCMI_SCVD_CACHE_POLICY_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
TRANSLATE(
"Write cache policy: %[scmi_write_disk_cache_policy_type] --> %[scmi_write_disk_cache_policy_type]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
TRANSLATE(
"Read cache policy: %[scmi_read_disk_cache_policy_type] --> %[scmi_read_disk_cache_policy_type]",
eip0F.old_attr.value.u32[1],
eip0F.new_attr.value.u32[1]
);
TRANSLATE(
"Cache mirroring policy: %[scmi_mirror_disk_cache_policy_type] --> %[scmi_mirror_disk_cache_policy_type]",
eip0F.old_attr.value.u32[2],
eip0F.new_attr.value.u32[2]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 096c000f SCID_SCMI_VOL_USAGE_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Volume: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_volume_usage] --> %[scmi_volume_usage]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
CONDITIONAL(
eip0F.old_attr.value.u32[0] == 1 ||
eip0F.new_attr.value.u32[0] == 1,
TRANSLATE(
"Disk Group: %[scmi_obj_hnd]",
eip0F.add_handle
)
);
TRANSLATE("Redundant Storage Set Identification: 0x%04x, (%d)",
eip0F.secondary_id.rss_data.Id,
eip0F.secondary_id.rss_data.Id
);
TRANSLATE("Redundant Storage Set Index: 0x%04x, (%d)",
eip0F.secondary_id.rss_data.Index,
eip0F.secondary_id.rss_data.Index
);
ENDTRANSLATIONBLOCK
EC BLOCK: 096d000f SCID_SCMI_LDAD_SPARE_CHANGE
TRANSLATIONBLOCK
TRANSLATE(
"Disk Group: %[scmi_obj_hnd]",
eip0F.handle
);
CONDITIONAL(
eip0F.new_attr.value.u32[0] > eip0F.old_attr.value.u32[0],
TRANSLATE(
"Disk Failure Protection Level increased"
),
TRANSLATE(
"Disk Failure Protection Level decreased"
)
);
TRANSLATE(
"Disk Failure Protection Level: %d. --> %d.",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 096e000f SCID_SCMI_DU_WRITE_PROTECTED_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Derived unit: %[scmi_obj_hnd]", eip0F.handle);
TRANSLATE(
"State: %[scmi_du_write_protect_condition] --> %[scmi_du_write_protect_condition]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
TRANSLATE("Storage System Virtual Disk noid: 0x%04x", eip0F.secondary_id.Id);
TRANSLATE(
"Associated Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0970460f SCID_SCMI_PS_DRIVE_PORT_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE("Port: %s", eip0F.new_attr.value.str);
CONDITIONAL(eip0F.old_attr.value.u32[1] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip0F.old_attr.value.u32[1] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip0F.old_attr.value.u32[1] != 99,
TRANSLATE("Enclosure: %d.", eip0F.old_attr.value.u32[1])
);
CONDITIONAL(eip0F.old_attr.value.u32[1] != 99,
TRANSLATE("Bay: %d.", eip0F.old_attr.value.u32[2])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0971000f SCID_SCMI_NSC_SHUTDOWN_REQUEST
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip0F.handle);
TRANSLATE(
"Restart type: %[scmi_nsc_restart_option]",
eip0F.old_attr.value.u32[0]
);
TRANSLATE(
"Other controller action: %[scmi_nsc_shutdown_other_option]",
eip0F.old_attr.value.u32[1]
);
TRANSLATE(
"Controller power state: %[scmi_nsc_shutdown_poweroff_option]",
eip0F.old_attr.value.u32[2]
);
TRANSLATE(
"Physical disk drive enclosures power state: %[scmi_nsc_shutdown_encl_poweroff_option]",
eip0F.old_attr.value.u32[3]
);
TRANSLATE(
"Battery assembly state: %[scmi_nsc_shutdown_battass_option]",
eip0F.old_attr.value.u32[4]
);
TRANSLATE(
"Shutdown delay: %d. seconds",
eip0F.old_attr.value.u32[5]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0972000f SCID_SCMI_NSC_SHUTDOWN
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip0F.handle);
TRANSLATE(
"Cache memory shutdown result: %[scmi_shutdown]",
eip0F.old_attr.value.u32[0]
);
TRANSLATE(
"Cache memory shutdown internal status: %d.",
eip0F.old_attr.value.u32[1]
);
TRANSLATE(
"Physical disk drive enclosures power off result: %[scmi_shutdown]",
eip0F.old_attr.value.u32[2]
);
TRANSLATE(
"Physical disk drive enclosures power off internal status: %[scmi_shutdown]",
eip0F.old_attr.value.u32[3]
);
TRANSLATE(
"Battery assemblies disable result: %[scmi_shutdown]",
eip0F.old_attr.value.u32[4]
);
TRANSLATE(
"Battery assemblies disable failure mode: %[scmi_nsc_shutdown_battass_failure_mode]",
eip0F.old_attr.value.u32[5]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0973000f SCID_SCMI_DRM_FAILSAFE_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_state] --> %[scmi_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0974000f SCID_SCMI_DRM_MODE_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Mode: %[scmi_group_drm_mode] --> %[scmi_group_drm_mode]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0975000f SCID_SCMI_DRM_OPERATION_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Actual State: %[scmi_group_operation_type] --> %[scmi_group_operation_type]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
TRANSLATE(
"Requested State: %[scmi_group_operation_type] --> %[scmi_group_operation_type]",
eip0F.old_attr.value.u32[1],
eip0F.new_attr.value.u32[1]
);
TRANSLATE(
"Async Rundown State: %[scmi_rundown_flag] --> %[scmi_rundown_flag]",
eip0F.old_attr.value.u32[2],
eip0F.new_attr.value.u32[2]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0976000f SCID_SCMI_DRM_READ_ONLY_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Attribute: %[scmi_group_readonly_type] --> %[scmi_group_readonly_type]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0977000f SCID_SCMI_DRM_SITE_FAILOVER_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Role: %[scmi_group_drm_mode] --> %[scmi_group_drm_mode]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0978000f SCID_SCMI_DRM_SUSPEND_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0979000f SCID_SCMI_DRM_SCVD_ADDED_TO_GROUP
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 097a000f SCID_SCMI_DRM_SCVD_REMOVED_FROM_GROUP
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"Storage System Virtual Disk: %[scmi_obj_hnd]",
eip0F.add_handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 097b000f SCID_SCMI_DRM_AUTO_SUSPEND_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_auto_suspend_state] --> %[scmi_group_auto_suspend_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 097c000f SCID_SCMI_DRM_DEST_PRESENT_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_dest_present_state] --> %[scmi_group_dest_present_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 097d000f SCID_SCMI_PS_FLAGS_CHANGED
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE("Old ps_flags value: 0x%08x.", eip0F.old_attr.value.u32[0]);
TRANSLATE("New ps_flags value: 0x%08x.", eip0F.new_attr.value.u32[0]);
ENDTRANSLATIONBLOCK
EC BLOCK: 097e000f SCID_SCMI_DRM_DEFER_COPY_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_defer_copy_state] --> %[scmi_group_defer_copy_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 097f000f SCID_SCMI_DRM_LINK_DOWN_SUSPEND_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0980000f SCID_SCMI_DRM_SITE_FAILOVER_SUSPEND_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0981000f SCID_SCMI_DRM_DEFER_COPY_SUSPEND_CHANGED
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip0F.handle
);
TRANSLATE(
"State: %[scmi_group_suspend_state] --> %[scmi_group_suspend_state]",
eip0F.old_attr.value.u32[0],
eip0F.new_attr.value.u32[0]
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09c85105 SCID_SCMI_LDISK_DATA_LOST_CHANGE_DATA_LOST
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_data_availability_condition] --> %[scmi_logical_disk_data_availability_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09c95105 SCID_SCMI_LDAD_CONDITION_CHANGE_INOP
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09ca5105 SCID_SCMI_LDISK_CONDITION_CHANGE_FAILED
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09cb5005 SCID_SCMI_LDISK_CONDITION_CHANGE_OVERCOMMIT
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09cc5105 SCID_SCMI_LDISK_CONDITION_CHANGE_DATA_LOST
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09cdc305 SCID_SCMI_NSC_FC_PORT_CONDITION_CHANGE_FAILED
TRANSLATIONBLOCK
CONDITIONAL(
eip05.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Port: %s",
eip05.attribute.value.str
);
TRANSLATE(
"State: %[scmi_nsc_fc_port_condition] --> %[scmi_nsc_fc_port_condition]",
eip05.value.ul2,
eip05.value.ul1
);
TRANSLATE("DIMM size: %d MB", eip05.add_data[0] );
ENDTRANSLATIONBLOCK
EC BLOCK: 09ce0005 SCID_SCMI_LDAD_CONDITION_CHANGE_INOP_MARKED
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_ldad_condition] --> %[scmi_ldad_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09cf4105 SCID_SCMI_PS_CONDITION_CHANGE_NOT_PRESENT
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d00005 SCID_SCMI_NSC_ICON_YELLOW_OFF_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d1b905 SCID_SCMI_NSC_ICON_YELLOW_ON_CHANGE
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d22a05 SCID_SCMI_NSC_FANA_PRESENT_CHANGE_PNP
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE(
"State: %[scmi_nsc_fan_present_condition] --> %[scmi_nsc_fan_present_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d35105 SCID_SCMI_DRM_GROUP_INOP
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_group_drm_ld_state] --> %[scmi_group_drm_ld_state]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d40005 SCID_SCMI_DRM_GROUP_OPERATIVE
TRANSLATIONBLOCK
TRANSLATE(
"Data Replication Group: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_group_drm_ld_state] --> %[scmi_group_drm_ld_state]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d50005 SCID_SCMI_PS_CONDITION_CHANGE_SPOF
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[scmi_obj_hnd]",
eip05.handle
);
TRANSLATE(
"State: %[scmi_physical_store_condition] --> %[scmi_physical_store_condition]",
eip05.value.ul2,
eip05.value.ul1
);
CONDITIONAL(eip05.attribute.value.u32[0] == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Enclosure: %d.", eip05.attribute.value.u32[0])
);
CONDITIONAL(eip05.attribute.value.u32[0] != 99,
TRANSLATE("Bay: %d.", eip05.attribute.value.u32[1])
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d63705 SCID_SCMI_NSC_TEMP_SNSR_DONT_AGREE
TRANSLATIONBLOCK
CONDITIONAL(
eip05.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"Sensor 1 current reading: %d. degrees Celsius",
eip05.value.ul1
);
TRANSLATE(
"Sensor 2 current reading: %d. degrees Celsius",
eip05.value.ul2
);
TRANSLATE("DIMM size: %d MB", eip05.add_data[0] );
ENDTRANSLATIONBLOCK
EC BLOCK: 09d73705 SCID_SCMI_NSC_TEMP_SNSR_FAILURE
TRANSLATIONBLOCK
CONDITIONAL(
eip05.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("I2C status: %x", eip05.value.ul1);
TRANSLATE("DIMM size: %d MB", eip05.add_data[0] );
ENDTRANSLATIONBLOCK
EC BLOCK: 09d8b605 SCID_SCMI_SRC_LOST
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09d90005 SCID_SCMI_SRC_ATTAINED
TRANSLATIONBLOCK
TRANSLATE("Disk Group: %[scmi_obj_hnd]",
eip05.handle
);
ENDTRANSLATIONBLOCK
EC BLOCK: 09da0005 SCID_SCMI_NSC_FANA_SPEED_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE("Current speed: %d. RPM", eip05.value.ul1);
TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 09db0005 SCID_SCMI_NSC_FANB_SPEED_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Blower assembly: %d.", eip05.secondary_id);
TRANSLATE("Current speed: %d. RPM", eip05.value.ul1);
TRANSLATE("Lowest acceptable speed: %d. RPM", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 09dc0b05 SCID_SCMI_NSC_POWERDOWN_NEEDED
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("New version: 0x%x.", eip05.value.ul1);
TRANSLATE("Old version: 0x%x.", eip05.value.ul2);
ENDTRANSLATIONBLOCK
EC BLOCK: 09dd0005 SCID_SCMI_NSC_MAINTENANCE_INVOKE_CALL
TRANSLATIONBLOCK
TRANSLATE("Controller: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE("Function Called: 0x%x.", eip05.value.ul1);
TRANSLATE("Parameter 1: 0x%x.", eip05.value.ul2);
TRANSLATE("Parameter 2: 0x%x.", eip05.add_data[0]);
TRANSLATE("Parameter 3: 0x%x.", eip05.add_data[1]);
ENDTRANSLATIONBLOCK
EC BLOCK: 09de5205 SCID_SCMI_LDISK_CONDITION_CHANGE_INVALIDATED
TRANSLATIONBLOCK
TRANSLATE("Associated Virtual Disk: %[scmi_obj_hnd]", eip05.handle);
TRANSLATE(
"State: %[scmi_logical_disk_condition] --> %[scmi_logical_disk_condition]",
eip05.value.ul2,
eip05.value.ul1
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b000010 SCID_SYS_RESYNCH
TRANSLATIONBLOCK
TRANSLATE("Controller: %[wwn]", eip10.node_name);
TRANSLATE("Program Counter: 0x%08x", eip10.information.pc);
TRANSLATE(
"Code: %d., 0x%08x (%[rcse])",
eip10.information.code,
eip10.information.code,
eip10.information.code
);
TRANSLATE("Flags: 0x%08x", eip10.information.flags);
TRANSLATE("Flag meanings:");
TRANSLATE(
"0x00000001 = Do not turn off host port LASERs"
);
TRANSLATE(
"0x00000002 = Do not wait RA_TOV if source ids were not changed"
);
TRANSLATE(
"0x00000004 = Bypass all diagnostics"
);
TRANSLATE(
"0x00000008 = Bypass diagnostics and configuration"
);
TRANSLATE(
"0x00000010 = Do not prompt for GO"
);
TRANSLATE(
"0x00000020 = Bypass card boot and diagnostics"
);
TRANSLATE(
"0x00000040 = Use image in memory"
);
TRANSLATE(
"0x00000080 = Bypass device discovery"
);
TRANSLATE(
"0x00000100 = Realize from memory map"
);
TRANSLATE(
"0x00000200 = Preserve HELP cache"
);
TRANSLATE(
"0x00000400 = Emergency drive firmware upgrade"
);
TRANSLATE(
"0x00001000 = Preserve host port 0 at 2 gigabyte"
);
TRANSLATE(
"0x00002000 = Preserve host port 1 at 2 gigabyte"
);
TRANSLATE(
"0x02000000 = Use bypass to send resynchronization MFC"
);
TRANSLATE(
"0x04000000 = Storage System scrub by this controller"
);
TRANSLATE(
"0x08000000 = Storage System scrub by other controller"
);
TRANSLATE(
"0x10000000 = Log event after reboot"
);
TRANSLATE(
"0x20000000 = Storage System resynchronization"
);
TRANSLATE(
"0x40000000 = Fault Manager termination bypassed"
);
TRANSLATE(
"0x80000000 = Power on reboot occurred"
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b01b515 SCID_SYS_MIGRATE_DFW_STALLED
TRANSLATIONBLOCK
CONDITIONAL(eip15.tag1 eq '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Volume identity unavailable"),
TRANSLATE("Volume: %[tag]", eip15.tag1)
);
TRANSLATE("Physical Disk Drive: %[tag]", eip15.tag2);
CONDITIONAL(eip15.state == 4,
TRANSLATE("State: Migrating")
);
CONDITIONAL(eip15.status == 1,
TRANSLATE("Status: Awaiting additional storage")
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b020004 SCID_SYS_DCL_BEGIN
TRANSLATIONBLOCK
TRANSLATE("Model: %s",eip04.pid);
TRANSLATE("Target revision: %s",eip04.rev);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b040004 SCID_SYS_CODELOAD_DRIVE
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("Port ID: %s", eip04.cerp_id);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num == 99,
TRANSLATE("Rack, enclosure, and bay not known")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip04.dencl_num - 100
)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num > 99,
TRANSLATE("Last known bay: %d.", eip04.bay - 100)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip04.dencl_num)
);
CONDITIONAL(eip04.al_pa != 0x01 &&
eip04.al_pa != 0x02 &&
eip04.al_pa != 0xEE &&
eip04.dencl_num < 99,
TRANSLATE("Bay: %d.", eip04.bay)
);
TRANSLATE("AL_PA: 0x%04x", eip04.al_pa);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Target firmware revision: %s", eip04.new_rev);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b050004 SCID_SYS_DRIVE_LOADED
TRANSLATIONBLOCK
TRANSLATE("Physical disk drive: %[tag]", eip04.device);
TRANSLATE("SCSI Product ID: %s", eip04.pid);
TRANSLATE("Current firmware revision: %s", eip04.rev);
TRANSLATE("Target firmware revision: %s", eip04.new_rev);
TRANSLATE("Drive enclosures available on port %s may be found in the enclosures array in this event's detailed information", eip04.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b06001a SCID_SYS_CODELOAD
TRANSLATIONBLOCK
TRANSLATE("State: %s", eip1A.state);
TRANSLATE("AddState/Version: %s %s", eip1A.hardware, eip1A.versions);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b070b1a SCID_SYS_GLUE_POWERDOWN_NEEDED
TRANSLATIONBLOCK
TRANSLATE("State: %s", eip1A.state);
TRANSLATE("AddState/Version: %s %s", eip1A.hardware, eip1A.versions);
ENDTRANSLATIONBLOCK
EC BLOCK: 0b09001e SCID_SYS_PROCESS_WITH_WORK
TRANSLATIONBLOCK
CONDITIONAL(eip1E.data[0] != 0,
TRANSLATE("Process: %s %02d", eip1E.info, eip1E.data[0])
);
CONDITIONAL(eip1E.data[0] == 0,
TRANSLATE("Process: %s", eip1E.info)
);
CONDITIONAL(eip1E.data[1] != 0,
TRANSLATE("Stack[0]: %08x (%s)", eip1E.data[1],
XLATE_PC_CURRENT(eip1E.data[1]))
);
CONDITIONAL(eip1E.data[2] != 0,
TRANSLATE("Stack[1]: %08x (%s)", eip1E.data[2],
XLATE_PC_CURRENT(eip1E.data[2]))
);
CONDITIONAL(eip1E.data[3] != 0,
TRANSLATE("Stack[2]: %08x (%s)", eip1E.data[3],
XLATE_PC_CURRENT(eip1E.data[3]))
);
CONDITIONAL(eip1E.data[4] != 0,
TRANSLATE("Stack[3]: %08x (%s)", eip1E.data[4],
XLATE_PC_CURRENT(eip1E.data[4]))
);
CONDITIONAL(eip1E.data[5] != 0,
TRANSLATE("Stack[4]: %08x (%s)", eip1E.data[5],
XLATE_PC_CURRENT(eip1E.data[5]))
);
CONDITIONAL(eip1E.data[6] != 0,
TRANSLATE("Stack[5]: %08x (%s)", eip1E.data[6],
XLATE_PC_CURRENT(eip1E.data[6]))
);
CONDITIONAL(eip1E.data[7] != 0,
TRANSLATE("Stack[6]: %08x (%s)", eip1E.data[7],
XLATE_PC_CURRENT(eip1E.data[7]))
);
CONDITIONAL(eip1E.data[8] != 0,
TRANSLATE("Stack[7]: %08x (%s)", eip1E.data[8],
XLATE_PC_CURRENT(eip1E.data[8]))
);
CONDITIONAL(eip1E.data[9] != 0,
TRANSLATE("Stack[8]: %08x (%s)", eip1E.data[9],
XLATE_PC_CURRENT(eip1E.data[9]))
);
CONDITIONAL(eip1E.data[10] != 0,
TRANSLATE("Stack[9]: %08x (%s)", eip1E.data[10],
XLATE_PC_CURRENT(eip1E.data[10]))
);
CONDITIONAL(eip1E.data[11] != 0,
TRANSLATE("Stack[10]: %08x (%s)", eip1E.data[11],
XLATE_PC_CURRENT(eip1E.data[11]))
);
CONDITIONAL(eip1E.data[12] != 0,
TRANSLATE("Stack[11]: %08x (%s)", eip1E.data[12],
XLATE_PC_CURRENT(eip1E.data[12]))
);
CONDITIONAL(eip1E.data[13] != 0,
TRANSLATE("Stack[12]: %08x (%s)", eip1E.data[13],
XLATE_PC_CURRENT(eip1E.data[13]))
);
CONDITIONAL(eip1E.data[14] != 0,
TRANSLATE("Stack[13]: %08x (%s)", eip1E.data[14],
XLATE_PC_CURRENT(eip1E.data[14]))
);
CONDITIONAL(eip1E.data[15] != 0,
TRANSLATE("Stack[14]: %08x (%s)", eip1E.data[15],
XLATE_PC_CURRENT(eip1E.data[15]))
);
CONDITIONAL(eip1E.data[16] != 0,
TRANSLATE("Stack[15]: %08x (%s)", eip1E.data[16],
XLATE_PC_CURRENT(eip1E.data[16]))
);
CONDITIONAL(eip1E.data[17] != 0,
TRANSLATE("Stack[16]: %08x (%s)", eip1E.data[17],
XLATE_PC_CURRENT(eip1E.data[17]))
);
CONDITIONAL(eip1E.data[18] != 0,
TRANSLATE("Stack[17]: %08x (%s)", eip1E.data[18],
XLATE_PC_CURRENT(eip1E.data[18]))
);
CONDITIONAL(eip1E.data[19] != 0,
TRANSLATE("Stack[18]: %08x (%s)", eip1E.data[19],
XLATE_PC_CURRENT(eip1E.data[19]))
);
CONDITIONAL(eip1E.data[20] != 0,
TRANSLATE("Stack[19]: %08x (%s)", eip1E.data[20],
XLATE_PC_CURRENT(eip1E.data[20]))
);
CONDITIONAL(eip1E.data[21] != 0,
TRANSLATE("Stack[20]: %08x (%s)", eip1E.data[21],
XLATE_PC_CURRENT(eip1E.data[21]))
);
CONDITIONAL(eip1E.data[22] != 0,
TRANSLATE("Stack[21]: %08x (%s)", eip1E.data[22],
XLATE_PC_CURRENT(eip1E.data[22]))
);
CONDITIONAL(eip1E.data[23] != 0,
TRANSLATE("Stack[22]: %08x (%s)", eip1E.data[23],
XLATE_PC_CURRENT(eip1E.data[23]))
);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c03000c SCID_DRM_MERGING
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c045f0c SCID_DRM_FAILSAFE_LOCKED_SITE_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c05610c SCID_DRM_FAILSAFE_LOCKED_UNIT_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c06600c SCID_DRM_COPY_READ_ERROR
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid);
TRANSLATE("First block in error: 0x%08x", eip0C.vda);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c075f0c SCID_DRM_COPY_WRITE_SITE_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
TRANSLATE("First block in error: 0x%08x", eip0C.vda);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c08610c SCID_DRM_COPY_WRITE_UNIT_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
TRANSLATE("First block in error: 0x%08x", eip0C.vda);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c09620c SCID_DRM_LOG_FULL
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c0a000c SCID_DRM_LOG_RESET
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c0c000c SCID_DRM_MERGE_DONE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c0f000c SCID_DRM_FAILSAFE_CLEARED
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c10000c SCID_DRM_FULL_COPY
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c11000c SCID_DRM_SITE_FAILOVER_DEST_TO_SRC
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Destination Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Source Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c12000c SCID_DRM_SITE_FAILOVER_SRC_TO_DEST
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c160016 SCID_DRM_TIME_REPORT
TRANSLATIONBLOCK
TRANSLATE("Message sender: %[uuid]", eip16.sender);
TRANSLATE("Message receiver: %[uuid]", eip16.receiver);
TRANSLATE("Message receiver's partner: %[uuid]", eip16.receiver_partner);
TRANSLATE("Time message sent: %[scmitim]", eip16.sent_time);
TRANSLATE("Time message received: %[scmitim]", eip16.received_time);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c17630c SCID_DRM_COMM_PROTOCOL_MISMATCH
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid
);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c18640c SCID_DRM_SLOW_CROSS_SITE_RESPONSE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c19020c SCID_DRM_WRITE_COLLISION
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
TRANSLATE("First overlapping block in error: 0x%08x", eip0C.vda);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c1a000c SCID_DRM_COPY_DONE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c1b5f0c SCID_DRM_LOGGING_SITE_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c1c610c SCID_DRM_LOGGING_UNIT_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c1d000c SCID_DRM_LOG_INCONSISTENT
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c1e5f0c SCID_DRM_NOT_PRESENTING_UNITS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c1f000c SCID_DRM_REPRESENTING_UNITS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c20650c SCID_DRM_STUCK_CROSS_SITE_RESPONSE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c21660c SCID_DRM_STUCK_LOCAL_GSB_LOCK
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c22000c SCID_DRM_TUNNEL_OPENED
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid
);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c23670c SCID_DRM_SLOW_ISL_RESPONSE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c24000c SCID_DRM_LOGGING_UNIT_STALLED
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c25000c SCID_DRM_COPY_WRITE_UNIT_STALLED
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
TRANSLATE("First block in error: 0x%08x", eip0C.vda);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c26000c SCID_DRM_EXISTING_TUNNEL_OPENED
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid
);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c27000c SCID_DRM_TUNNEL_OPENED_BY_PEER
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid
);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c285f0c SCID_DRM_REMOTE_SITE_INACCESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c29000c SCID_DRM_TUNNEL_CLOSED_PREF_PORT
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid
);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c2a000c SCID_DRM_REMOTE_SITE_FOUND
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c2b600c SCID_DRM_MERGE_READ_ERROR
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c2c660c SCID_DRM_STUCK_DEST_GSB_LOCK
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Destination Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Source Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c2d000c SCID_DRM_DELETE_PORTWWN
TRANSLATIONBLOCK
TRANSLATE("Client Object: %[tag]", eip0C.group_uuid);
TRANSLATE("Host index: 0x%04x", eip0C.blocks);
TRANSLATE("Peer node: %[wwn]", eip0C.source_scvd_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c2e680c SCID_DRM_TOO_MANY_NODES
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
EC BLOCK: 0c2f000c SCID_DRM_AVAILABLE_NODES
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
EC BLOCK: 0c30000c SCID_DRM_INVALIDATE_LOG
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c31000c SCID_DRM_COPY_RESTART
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Source Virtual Disk: %[tag]", eip0C.source_scvd_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Destination Virtual Disk: %[tag]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c325f0c SCID_DRM_TUNNEL_CL_LNKDWN
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c335f0c SCID_DRM_TUNNEL_CL_STUCKTMO
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c345f0c SCID_DRM_TUNNEL_CL_FLTMO
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c35070c SCID_DRM_TUNNEL_CL_GSBLCK
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Destination Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c365f0c SCID_DRM_TUNNEL_CL_THRASH
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c375f0c SCID_DRM_TUNNEL_CL_PNGRTRY
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c38630c SCID_DRM_TUNNEL_CL_UNSUPPROTO
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c39000c SCID_DRM_TUNNEL_CL_TEARDOWN
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c3a5f0c SCID_DRM_TUNNEL_CL_OPENTMO
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c3b000c SCID_DRM_TUNNEL_CL_RMTREOPEN
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c3c000c SCID_DRM_TUNNEL_CL_RMTOPN_DP
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c3d5f0c SCID_DRM_TUNNEL_CL_RSNDTMO
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c3e000c SCID_DRM_TUNNEL_CL_RMTREQ
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c3f000c SCID_DRM_TUNNEL_CL_NEWSID
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c40690c SCID_DRM_TUNNEL_CL_INVALIDSN
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c41000c SCID_DRM_TUNNEL_CL_CHGPROTO
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c42000c SCID_DRM_TUNNEL_CL_PEERDEL
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c43000c SCID_DRM_TUNNEL_CL_MAINT13
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c49000c SCID_DRM_TUNNEL_CL_CCBDEL
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c4a000c SCID_DRM_CONN_RJT_RESYNC
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c4b000c SCID_DRM_CONN_RJT_NOSCELL
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c4c000c SCID_DRM_CONN_RJT_NOPATH
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c4d000c SCID_DRM_CONN_RJT_POLLING
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c4e000c SCID_DRM_CONN_RJT_NOTEVA
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c4f000c SCID_DRM_CONN_RJT_HOSTWWID
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c50000c SCID_DRM_CONN_RJT_BADUUID
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c51000c SCID_DRM_CONN_RJT_VERSION
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c52000c SCID_DRM_CONN_RJT_PRTDISABLE
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c53000c SCID_DRM_CONN_RJT_NORESRC
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c54000c SCID_DRM_CONN_RJT_NEWVER
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c550016 SCID_DRM_TIME_SENT
TRANSLATIONBLOCK
TRANSLATE("Message sender: %[uuid]", eip16.sender);
TRANSLATE("Message sender's partner: %[uuid]", eip16.receiver_partner);
TRANSLATE("Message receiver: %[uuid]", eip16.receiver);
TRANSLATE("Time message sent: %[scmitim]", eip16.sent_time);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c56000c SCID_DRM_FL_TIMEOUT_CHANGE
TRANSLATIONBLOCK
TRANSLATE("The DRM forced logging timeout value has changed from %d seconds to %d seconds.", eip0C.port, eip0C.side);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c57000c SCID_DRM_FL_TIMEOUT_RESET
TRANSLATIONBLOCK
TRANSLATE("The DRM forced logging timeout value has reset to %d seconds.",eip0C.side);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c58690c SCID_DRM_HIGH_ISL_RETRY_RATE
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c59690c SCID_DRM_HIGH_OUT_OF_ORDER_RATE
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c5a670c SCID_DRM_HIGH_ISL_PING_TIME
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c5b670c SCID_DRM_MIN_WRITE_RESOURCES
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c5c670c SCID_DRM_MIN_COPY_RESOURCES
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c5d000c SCID_DRM_ISL_QOS_HAS_IMPROVED
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c5e000c SCID_DRM_LOG_SHRINK_IN_PROGRESS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c5f000c SCID_DRM_LOG_SHRINK_FINISHED
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %[tag]", eip0C.group_name_uuid);
TRANSLATE("Source Data Replication Group: %[tag]", eip0C.group_uuid);
TRANSLATE("Data Replication Destination Storage System: %[tag]",
eip0C.peer_scell_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0c60000c SCID_DRM_HIGH_VDISK_RESPONSE
TRANSLATIONBLOCK
TRANSLATE("Port: %s", eip0C.cerp_id);
TRANSLATE("Controller: %d", eip0C.side);
TRANSLATE("Peer Storage System: %[tag]",
eip0C.peer_scell_uuid);
TRANSLATE("Peer port: %[wwn]", eip0C.dest_scvd_uuid);
ENDTRANSLATIONBLOCK
EC BLOCK: 0d000111 SCID_DEEMU_UNRECOGNIZED_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("alarm_error_code.field.reserved: 0x%02x",
eip11.alarm_error_code.field.reserved
);
TRANSLATE("alarm_error_code.field.ec: 0x%02x",
eip11.alarm_error_code.field.ec
);
TRANSLATE("alarm_error_code.field.en: 0x%02x",
eip11.alarm_error_code.field.en
);
TRANSLATE("alarm_error_code.field.et: 0x%02x",
eip11.alarm_error_code.field.et
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d014011 SCID_DEEMU_DRIVE_CFG_LINK_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Bay which detected problem: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d024111 SCID_DEEMU_DRIVE_MISSING
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected bay: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d034111 SCID_DEEMU_DRIVE_SLACTIVE_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected bay: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d044211 SCID_DEEMU_DRIVE_LINK_RATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected bay: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 4,
TRANSLATE("Problem detected on loop A")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 5,
TRANSLATE("Problem detected on loop B")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d330911 SCID_DEEMU_DEPSACI_LOST
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected power supply: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d348011 SCID_DEEMU_DEPS_MISSING
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected power supply: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d359a11 SCID_DEEMU_LOAD_BALANCE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected power supply: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d478311 SCID_DEEMU_DEBLWR_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected blower: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("Blower speed is out of range")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 2,
TRANSLATE("Blower speed is vastly out of range")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 3,
TRANSLATE("Blower has stopped")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 4,
TRANSLATE("Blower reported internal error")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d4b8211 SCID_DEEMU_DEBLWR_MISSING
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Affected blower: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d4c8411 SCID_DEEMU_DEBLWR_BOTH_MISSING
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Second missing blower: %d.",
eip11.alarm_error_code.field.en
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d5b8611 SCID_DEEMU_DETS_OOR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.en == 1,
TRANSLATE("Temperature sensor tripped by power supply 1 exhaust")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 2,
TRANSLATE("Temperature sensor tripped by power supply 2 exhaust")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 3,
TRANSLATE("Temperature sensor tripped by Drive Enclosure Environmental Monitoring Unit")
);
CONDITIONAL(eip11.alarm_error_code.field.en >= 4,
TRANSLATE("Temperature sensor tripped by drive bay %d.",
eip11.alarm_error_code.field.en - 3
)
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("Temperature range is near high critical")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 2,
TRANSLATE("Temperature range is above high critical")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 3,
TRANSLATE("Temperature range is near low critical")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 4,
TRANSLATE("Temperature range is reached low critical")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d5f8711 SCID_DEEMU_DETS_ATCRITICAL
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d6f8811 SCID_DEEMU_INTERNAL_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("An internal Drive Enclosure Environmental Monitoring Unit clock error has occurred")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 2,
TRANSLATE("The I2C bus not processing data and is unable to report status")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 5,
TRANSLATE("A backplane NVRAM error has occurred.")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d710011 SCID_DEEMU_INTERNAL_ERROR1
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 3,
TRANSLATE("Error is due to an enclosure power supply shutdown")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 16,
TRANSLATE("Error is due to corrupt Drive Enclosure Environmental Monitoring Unit ESI data")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d728a11 SCID_DEEMU_NOSES
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d7e8c11 SCID_DEEMU_INVNVRAM
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d7f8b11 SCID_DEEMU_INTERNAL_ERROR2
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 11,
TRANSLATE("Error cause: Drive Enclosure Environmental Monitoring Unit cannot write to NVRAM)")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 12,
TRANSLATE("Error cause: Drive Enclosure Environmental Monitoring Unit cannot read from NVRAM)")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 13,
TRANSLATE("Error cause: the Field Programmable Gate Array failed to load required information")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d828e11 SCID_DEEMU_ENCADDRBAD
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d838911 SCID_DEEMU_HARDBAD
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL( eip11.alarm_error_code.field.ec == 15,
TRANSLATE( "Error cause: Drive Enclosure Environmental Monitoring Unit hardware failure DP")
);
CONDITIONAL( eip11.alarm_error_code.field.ec == 18,
TRANSLATE( "Error cause: Drive Enclosure Environmental Monitoring Unit hardware failure BT")
);
CONDITIONAL( eip11.alarm_error_code.field.ec == 19,
TRANSLATE( "Error cause: Drive Enclosure Environmental Monitoring Unit hardware failure ESI")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d858f11 SCID_DEEMU_PSSHTDNFAILED
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0d8d9011 SCID_DEEMU_DEXCVR_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("Transceiver: %d.", eip11.alarm_error_code.field.en);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("Error cause: transceivers have invalid or incompatible type")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 2,
TRANSLATE("Error cause: transceiver cannot detect data signal")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 3,
TRANSLATE("Error cause: FC-AL bus fault involving transceiver")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 4,
TRANSLATE("Error cause: transceiver removed")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 5,
TRANSLATE("Error cause: transceiver detected invalid characters")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0da18111 SCID_DEEMU_DEVS_OOR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.en == 1,
TRANSLATE("Voltage sensor tripped by power supply 1: +5 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 2,
TRANSLATE("Voltage sensor tripped by power supply 1: +12 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 3,
TRANSLATE("Voltage sensor tripped by power supply 2: +5 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 4,
TRANSLATE("Voltage sensor tripped by power supply 2: +12 VDC")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0db58111 SCID_DEEMU_DECS_OOR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.en == 1,
TRANSLATE("Current sensor tripped by power supply 1: +5 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 2,
TRANSLATE("Current sensor tripped by power supply 1: +12 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 3,
TRANSLATE("Current sensor tripped by power supply 2: +5 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.en == 4,
TRANSLATE("Current sensor tripped by power supply 2: +12 VDC")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("The element current is appoaching the high current critical threshold")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 2,
TRANSLATE("The element current is above the high current critical threshold")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0dd89211 SCID_DEEMU_BACKPLANE_ERROR_AUTOREC
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0dd99111 SCID_DEEMU_BACKPLANE_ERROR_UNREC
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 11,
TRANSLATE("Error cause: cannot write to NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 12,
TRANSLATE("Error cause: cannot read from NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 13,
TRANSLATE("Error cause: NVRAM not properly initialized")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0ddd9311 SCID_DEEMU_DEIOM_ERROR_UNREC
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("I/O module: %d", eip11.alarm_error_code.field.en);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("Error cause: I/O module link speed unsupported")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 11,
TRANSLATE("Error cause: cannot write to I/O module NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 12,
TRANSLATE("Error cause: cannot read from I/O module NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 13,
TRANSLATE("Error cause: I/O module was removed")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0dde9511 SCID_DEEMU_DEIOM_NOCOMM_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("I/O module: %d", eip11.alarm_error_code.field.en);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("Error cause: I/O module link speed unsupported")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 11,
TRANSLATE("Error cause: cannot write to I/O module NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 12,
TRANSLATE("Error cause: cannot read from I/O module NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 13,
TRANSLATE("Error cause: I/O module was removed")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0dec9411 SCID_DEEMU_DEIOM_ERROR_AUTOREC
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("I/O module: %d", eip11.alarm_error_code.field.en);
CONDITIONAL(eip11.alarm_error_code.field.ec == 1,
TRANSLATE("Error cause: I/O module link speed unsupported")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 11,
TRANSLATE("Error cause: cannot write to I/O module NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 12,
TRANSLATE("Error cause: cannot read from I/O module NVRAM")
);
CONDITIONAL(eip11.alarm_error_code.field.ec == 13,
TRANSLATE("Error cause: I/O module was removed")
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0df00011 SCID_DEEMU_STATUS_CHANGE
TRANSLATIONBLOCK
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0df68811 SCID_DEEMU_COMM_ERROR
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("alarm_error_code.field.ec: 0x%02x",
eip11.alarm_error_code.field.ec
);
TRANSLATE("alarm_error_code.field.en: 0x%02x",
eip11.alarm_error_code.field.en
);
TRANSLATE("alarm_error_code.field.et: 0x%02x",
eip11.alarm_error_code.field.et
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0df70011 SCID_DEEMU_COMM_RECOVERY_COMPLETE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("alarm_error_code.field.ec: 0x%02x",
eip11.alarm_error_code.field.ec
);
TRANSLATE("alarm_error_code.field.en: 0x%02x",
eip11.alarm_error_code.field.en
);
TRANSLATE("alarm_error_code.field.et: 0x%02x",
eip11.alarm_error_code.field.et
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0df80011 SCID_DEEMU_COMM_INIT_COMPLETE
TRANSLATIONBLOCK
TRANSLATE("Enclosure identity: %[scmi_obj_hnd]", eip11.handle);
CONDITIONAL(eip11.dencl_num == 99,
TRANSLATE("Location unknown")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num < 99,
TRANSLATE("Enclosure: %d.", eip11.dencl_num)
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Rack number not valid in this release")
);
CONDITIONAL(eip11.dencl_num > 99,
TRANSLATE("Last known enclosure: %d.",
eip11.dencl_num - 100
)
);
TRANSLATE("alarm_error_code.field.ec: 0x%02x",
eip11.alarm_error_code.field.ec
);
TRANSLATE("alarm_error_code.field.en: 0x%02x",
eip11.alarm_error_code.field.en
);
TRANSLATE("alarm_error_code.field.et: 0x%02x",
eip11.alarm_error_code.field.et
);
CONDITIONAL(eip11.loop == 0, TRANSLATE("Drive enclosures available on loop A may be found in the enclosures array in this event's detailed information"), TRANSLATE("Drive enclosures available on loop B may be found in the enclosures array in this event's detailed information"));
ENDTRANSLATIONBLOCK
EC BLOCK: 0e000019 SCID_SDC_BATT_SYS_BOOT_STATUS
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("Battery System State : %[scmi_nsc_battery_system_condition]",
eip19.state.cur);
TRANSLATE("Battery System HUT : %d",eip19.status_data.cur);
TRANSLATE("Brick 0 State : %[scmi_battery_brick_state]",
eip19.comp_states[0]);
TRANSLATE("Brick 0 Overall Status : %[scmi_battery_brick_status_code]",
eip19.comp_status_codes[0]);
TRANSLATE("Brick 0 Combined Status : 0x%08X",eip19.comp_status_data[0]);
TRANSLATE("Brick 1 State : %[scmi_battery_brick_state]",
eip19.comp_states[1]);
TRANSLATE("Brick 1 Overall Status : %[scmi_battery_brick_status_code]",
eip19.comp_status_codes[1]);
TRANSLATE("Brick 1 Combined Status : 0x%08X",eip19.comp_status_data[1]);
TRANSLATE("Brick 2 State : %[scmi_battery_brick_state]",
eip19.comp_states[2]);
TRANSLATE("Brick 2 Overall Status : %[scmi_battery_brick_status_code]",
eip19.comp_status_codes[2]);
TRANSLATE("Brick 2 Combined Status : 0x%08X",eip19.comp_status_data[2]);
TRANSLATE("Brick 3 State : %[scmi_battery_brick_state]",
eip19.comp_states[3]);
TRANSLATE("Brick 3 Overall Status : %[scmi_battery_brick_status_code]",
eip19.comp_status_codes[3]);
TRANSLATE("Brick 3 Combined Status : 0x%08X",eip19.comp_status_data[3]);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e010019 SCID_SDC_BATT_BRICK_0_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur);
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e02cc19 SCID_SDC_BATT_BRICK_0_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e030019 SCID_SDC_BATT_BRICK_0_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e04c819 SCID_SDC_BATT_BRICK_0_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e050019 SCID_SDC_BATT_BRICK_1_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur);
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e06cd19 SCID_SDC_BATT_BRICK_1_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e070019 SCID_SDC_BATT_BRICK_1_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e08c919 SCID_SDC_BATT_BRICK_1_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e090019 SCID_SDC_BATT_BRICK_2_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur);
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e0ace19 SCID_SDC_BATT_BRICK_2_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e0b0019 SCID_SDC_BATT_BRICK_2_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e0cca19 SCID_SDC_BATT_BRICK_2_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e0d0019 SCID_SDC_BATT_BRICK_3_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur);
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e0ecf19 SCID_SDC_BATT_BRICK_3_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e0f0019 SCID_SDC_BATT_BRICK_3_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e10cb19 SCID_SDC_BATT_BRICK_3_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
CONDITIONAL(eip19.state.cur == eip19.state.old,
TRANSLATE("State : %[scmi_battery_brick_state]",
eip19.state.cur),
TRANSLATE("State : %[scmi_battery_brick_state] --> %[scmi_battery_brick_state]",
eip19.state.old,
eip19.state.cur)
);
CONDITIONAL(eip19.status_code.cur == eip19.status_code.old,
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code]",
eip19.status_code.cur),
TRANSLATE("Overall Status : %[scmi_battery_brick_status_code] --> %[scmi_battery_brick_status_code]",
eip19.status_code.old,
eip19.status_code.cur)
);
TRANSLATE("Combined Status: 0x%08X",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e110019 SCID_SDC_BATT_SYS_COND_GOOD
TRANSLATIONBLOCK
TRANSLATE("Battery System Hold-up Time is greater than %d hours",
eip19.status_code.cur);
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Hold-up time : %d --> %d (hours)",eip19.status_data.old,
eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e120019 SCID_SDC_BATT_SYS_COND_LOW
TRANSLATIONBLOCK
TRANSLATE("Battery System Hold-up Time is greater than %d and less than %d hours",
eip19.status_code.old,
eip19.status_code.cur);
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Hold-up time : %d --> %d (hours)",eip19.status_data.old,
eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e13d019 SCID_SDC_BATT_SYS_COND_BAD
TRANSLATIONBLOCK
TRANSLATE("Battery System Hold-up Time is zero hours");
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_nsc_battery_system_condition] --> %[scmi_nsc_battery_system_condition]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Hold-up time : %d --> %d (hours)",eip19.status_data.old,
eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e140019 SCID_SDC_BLOW_SYS_BOOT_STATUS
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("Blower 0 State : %[scmi_fan_status]",
eip19.comp_states[0]);
TRANSLATE("Blower 0 Initial Status : 0x%X",eip19.comp_status_codes[0]);
TRANSLATE("Blower 0 RPM : %d",eip19.comp_status_data[0]);
TRANSLATE("Blower 1 State : %[scmi_fan_status]",
eip19.comp_states[1]);
TRANSLATE("Blower 1 Initial Status : 0x%X",eip19.comp_status_codes[1]);
TRANSLATE("Blower 1 RPM : %d",eip19.comp_status_data[1]);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e150019 SCID_SDC_BLOWER_0_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status]",eip19.state.cur);
TRANSLATE("Status Code : 0x%X",eip19.status_code.cur);
TRANSLATE("RPM : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e16d419 SCID_SDC_BLOWER_0_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e170019 SCID_SDC_BLOWER_0_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Status Code : 0x%X",eip19.status_code.cur);
TRANSLATE("RPM : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e18d219 SCID_SDC_BLOWER_0_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Status Code : 0x%X",eip19.status_code.cur);
TRANSLATE("RPM : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e190019 SCID_SDC_BLOWER_1_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status]",eip19.state.cur);
TRANSLATE("Status Code : 0x%X",eip19.status_code.cur);
TRANSLATE("RPM : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e1ad519 SCID_SDC_BLOWER_1_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e1b0019 SCID_SDC_BLOWER_1_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Status Code : 0x%X",eip19.status_code.cur);
TRANSLATE("RPM : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e1cd319 SCID_SDC_BLOWER_1_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_fan_status] --> %[scmi_fan_status]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Status Code : 0x%X",eip19.status_code.cur);
TRANSLATE("RPM : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e1dda19 SCID_SDC_BATT_MEMORY_READ_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("Battery Brick Number : %d",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e1e0019 SCID_SDC_TEMP_SYS_BOOT_STATUS
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_temp_system_state]",eip19.state.cur);
TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]);
TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]);
TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]);
TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]);
TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e1f0019 SCID_SDC_TEMP_NORMAL
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_temp_system_state] --> %[scmi_temp_system_state]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]);
TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]);
TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]);
TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]);
TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e202e19 SCID_SDC_TEMP_CLOSE_TO_TEMP_TRIP
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_temp_system_state] --> %[scmi_temp_system_state]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]);
TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]);
TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]);
TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]);
TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e213619 SCID_SDC_TEMP_OVER_TEMP
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_temp_system_state] --> %[scmi_temp_system_state]",
eip19.state.old,
eip19.state.cur);
TRANSLATE("Sensor 1 : %d C",eip19.comp_status_data[0]);
TRANSLATE("Sensor 2 : %d C",eip19.comp_status_data[1]);
TRANSLATE("Sensor 3 : %d C",eip19.comp_status_data[2]);
TRANSLATE("Sensor Avg : %d C",eip19.comp_status_data[3]);
TRANSLATE("Trip Temp. : %d C",eip19.status_data.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e220019 SCID_SDC_PWR_SUPPLY_BOOT_STATUS
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("Power Supply 0 State : %[scmi_power_supply_state]",
eip19.comp_states[0]);
TRANSLATE("Power Supply 1 State : %[scmi_power_supply_state]",
eip19.comp_states[1]);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e230019 SCID_SDC_PWR_SUPPLY_0_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state]",eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e24d819 SCID_SDC_PWR_SUPPLY_0_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e250019 SCID_SDC_PWR_SUPPLY_0_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e26d619 SCID_SDC_PWR_SUPPLY_0_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e270019 SCID_SDC_PWR_SUPPLY_1_INSERTED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state]",eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e28d919 SCID_SDC_PWR_SUPPLY_1_REMOVED
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e290019 SCID_SDC_PWR_SUPPLY_1_UPDATE_GOOD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 0e2ad719 SCID_SDC_PWR_SUPPLY_1_UPDATE_BAD
TRANSLATIONBLOCK
TRANSLATE("Controller : %[scmi_obj_hnd]", eip19.handle);
TRANSLATE("State : %[scmi_power_supply_state] --> %[scmi_power_supply_state]",
eip19.state.old,
eip19.state.cur);
ENDTRANSLATIONBLOCK
EC BLOCK: 42000008 SCID_HP_FC_LINK_DOWN
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 42010008 SCID_HP_FC_LINK_FAILED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 42030007 SCID_HP_LINK_ERRORS
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip07.cerp_id);
CONDITIONAL( eip07.loss_of_signal != 0,
TRANSLATE("Loss of signal: %d.", eip07.loss_of_signal)
);
CONDITIONAL( eip07.bad_rx_char != 0,
TRANSLATE("Bad RX characters: %d.", eip07.bad_rx_char)
);
CONDITIONAL( eip07.loss_of_sync != 0,
TRANSLATE("Loss of synchs: %d.", eip07.loss_of_sync)
);
CONDITIONAL( eip07.link_fail != 0,
TRANSLATE("Link failures: %d.", eip07.link_fail)
);
CONDITIONAL( eip07.rx_eofa != 0,
TRANSLATE("RX EOFa delimiters: %d.", eip07.rx_eofa)
);
CONDITIONAL( eip07.dis_frm != 0,
TRANSLATE("Discarded frames: %d.", eip07.dis_frm)
);
CONDITIONAL( eip07.bad_crc != 0,
TRANSLATE("Frames with bad CRC and valid EOF: %d.", eip07.bad_crc)
);
CONDITIONAL( eip07.proto_err != 0,
TRANSLATE("N_Port protocol errors: %d.", eip07.proto_err)
);
CONDITIONAL( eip07.exp_frm != 0,
TRANSLATE("Expired outbound frames: %d.", eip07.exp_frm)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 42044a08 SCID_HP_LINK_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
TRANSLATE("Producer index: %04X", eip08.peq_prod_index);
TRANSLATE("Consumer index: %04X", eip08.peq_cons_index);
TRANSLATE("Frozen index: %04X", eip08.peq_frz_prod_index);
TRANSLATE("Port event block(s):");
CONDITIONAL( eip08.peb[0].type != 0,
TRANSLATE(
" [0] Type: %08X Context: %08X",
eip08.peb[0].type,
eip08.peb[0].context
)
);
CONDITIONAL( eip08.peb[1].type != 0,
TRANSLATE(
" [1] Type: %08X Context: %08X",
eip08.peb[1].type,
eip08.peb[1].context
)
);
CONDITIONAL( eip08.peb[2].type != 0,
TRANSLATE(
" [2] Type: %08X Context: %08X",
eip08.peb[2].type,
eip08.peb[2].context
)
);
CONDITIONAL( eip08.peb[3].type != 0,
TRANSLATE(
" [3] Type: %08X Context: %08X",
eip08.peb[3].type,
eip08.peb[3].context
)
);
CONDITIONAL( eip08.peb[4].type != 0,
TRANSLATE(
" [4] Type: %08X Context: %08X",
eip08.peb[4].type,
eip08.peb[4].context
)
);
CONDITIONAL( eip08.peb[5].type != 0,
TRANSLATE(
" [5] Type: %08X Context: %08X",
eip08.peb[5].type,
eip08.peb[5].context
)
);
CONDITIONAL( eip08.peb[6].type != 0,
TRANSLATE(
" [6] Type: %08X Context: %08X",
eip08.peb[6].type,
eip08.peb[6].context
)
);
CONDITIONAL( eip08.peb[7].type != 0,
TRANSLATE(
" [7] Type: %08X Context: %08X",
eip08.peb[7].type,
eip08.peb[7].context
)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 42050008 SCID_HP_FC_LINK_WEDGED
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 4206001b SCID_HP_UNIT_STALLED_TOO_LONG
TRANSLATIONBLOCK
TRANSLATE("Virtual Disk: %[tag]", eip1B.ld_tag);
CONDITIONAL(
eip1B.scvd_tag ne '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Associated Storage System Virtual Disk: %[tag]",
eip1B.scvd_tag)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 4207001b SCID_HP_LUN_TRANSITION
TRANSLATIONBLOCK
TRANSLATE("Virtual Disk: %[tag]", eip1B.ld_tag);
CONDITIONAL(
eip1B.scvd_tag ne '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Associated Storage System Virtual Disk: %[tag]",
eip1B.scvd_tag)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 42080008 SCID_HP_FREEZE_TACH
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 42090008 SCID_HP_SOFT_RESET_TACH
TRANSLATIONBLOCK
TRANSLATE("Port ID: %s", eip08.cerp_id);
ENDTRANSLATIONBLOCK
EC BLOCK: 420a001b SCID_HP_UNIT_STALLED_TOO_LONG_EXIT
TRANSLATIONBLOCK
TRANSLATE("Virtual Disk: %[tag]", eip1B.ld_tag);
CONDITIONAL(
eip1B.scvd_tag ne '0000-0000-0000-0000-0000-0000-0000-0000',
TRANSLATE("Associated Storage System Virtual Disk: %[tag]",
eip1B.scvd_tag)
);
ENDTRANSLATIONBLOCK
EC BLOCK: 83002014 SCID_DOG_FAILURE
TRANSLATIONBLOCK
CONDITIONAL(
eip14.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num);
CONDITIONAL(eip14.eep_error.TE_num == 0,
TRANSLATE("(Error reporting for pre-MIST tests)")
);
CONDITIONAL(eip14.eep_error.TE_num == 2,
TRANSLATE("(HW code check and Operator Control Panel setup)")
);
CONDITIONAL(eip14.eep_error.TE_num == 7,
TRANSLATE("(Cache Memory test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 12,
TRANSLATE("(Port 0 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 13,
TRANSLATE("(Port 1 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 14,
TRANSLATE("(Port 2 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 15,
TRANSLATE("(Port 3 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 16,
TRANSLATE("(Port 4 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 17,
TRANSLATE("(Port 5 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 18,
TRANSLATE("(Port 6 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 19,
TRANSLATE("(Port 7 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 20,
TRANSLATE("(Port 8 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 21,
TRANSLATE("(Port 9 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 22,
TRANSLATE("(All Ports test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 23,
TRANSLATE("(Port-to-Port test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 24,
TRANSLATE("(Config and Init Port regs)")
);
CONDITIONAL(eip14.eep_error.TE_num == 28,
TRANSLATE("(SDC test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 31,
TRANSLATE("(Hardware Revision test)")
);
TRANSLATE("Test number: %d.", eip14.eep_error.test_num);
TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count);
TRANSLATE("Error code: %08X", eip14.eep_error.error_code);
TRANSLATE("Address of error: %08X", eip14.eep_error.address);
TRANSLATE("Expected data: %08X", eip14.eep_error.expected);
TRANSLATE("Actual data: %08X", eip14.eep_error.actual);
TRANSLATE(
"Controller uptime of failure: %y.",
eip14.eep_error.uptime
);
TRANSLATE("DIMM size: %d MB", eip14.dimm_size );
ENDTRANSLATIONBLOCK
EC BLOCK: 83013014 SCID_DOG_FAILURE_GBIC
TRANSLATIONBLOCK
CONDITIONAL(
eip14.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num);
CONDITIONAL(eip14.eep_error.TE_num == 12,
TRANSLATE("(Port 0 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 13,
TRANSLATE("(Port 1 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 14,
TRANSLATE("(Port 2 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 15,
TRANSLATE("(Port 3 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 16,
TRANSLATE("(Port 4 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 17,
TRANSLATE("(Port 5 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 18,
TRANSLATE("(Port 6 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 19,
TRANSLATE("(Port 7 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 20,
TRANSLATE("(Port 8 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 21,
TRANSLATE("(Port 9 test)")
);
TRANSLATE("Test number: %d.", eip14.eep_error.test_num);
TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count);
TRANSLATE("Error code: %08X", eip14.eep_error.error_code);
TRANSLATE("Address of error: %08X", eip14.eep_error.address);
TRANSLATE("Expected data: %08X", eip14.eep_error.expected);
TRANSLATE("Actual data: %08X", eip14.eep_error.actual);
TRANSLATE(
"Controller uptime of failure: %y.",
eip14.eep_error.uptime
);
TRANSLATE("DIMM size: %d MB", eip14.dimm_size );
ENDTRANSLATIONBLOCK
EC BLOCK: 83073a14 SCID_DOG_FAILURE_GBIC_MISSING
TRANSLATIONBLOCK
CONDITIONAL(
eip14.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num);
CONDITIONAL(eip14.eep_error.TE_num == 12,
TRANSLATE("(Port 0 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 13,
TRANSLATE("(Port 1 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 14,
TRANSLATE("(Port 2 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 15,
TRANSLATE("(Port 3 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 16,
TRANSLATE("(Port 4 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 17,
TRANSLATE("(Port 5 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 18,
TRANSLATE("(Port 6 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 19,
TRANSLATE("(Port 7 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 20,
TRANSLATE("(Port 8 test)")
);
CONDITIONAL(eip14.eep_error.TE_num == 21,
TRANSLATE("(Port 9 test)")
);
TRANSLATE("Test number: %d.", eip14.eep_error.test_num);
TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count);
TRANSLATE("Error code: %08X", eip14.eep_error.error_code);
TRANSLATE("Address of error: %08X", eip14.eep_error.address);
TRANSLATE("Expected data: %08X", eip14.eep_error.expected);
TRANSLATE("Actual data: %08X", eip14.eep_error.actual);
TRANSLATE(
"Controller uptime of failure: %y.",
eip14.eep_error.uptime
);
TRANSLATE("DIMM size: %d MB", eip14.dimm_size );
ENDTRANSLATIONBLOCK
EC BLOCK: 83083b14 SCID_DOG_SRAM_TEST_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
eip14.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num);
TRANSLATE("Test number: %d.", eip14.eep_error.test_num);
TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count);
TRANSLATE("Error code: %08X", eip14.eep_error.error_code);
TRANSLATE("Address of error: %08X", eip14.eep_error.address);
TRANSLATE("Expected data: %08X", eip14.eep_error.expected);
TRANSLATE("Actual data: %08X", eip14.eep_error.actual);
TRANSLATE(
"Controller uptime of failure: %y.",
eip14.eep_error.uptime
);
TRANSLATE("DIMM size: %d MB", eip14.dimm_size );
ENDTRANSLATIONBLOCK
EC BLOCK: 83093b14 SCID_DOG_SRAM_PARITY_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
eip14.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num);
TRANSLATE("Test number: %d.", eip14.eep_error.test_num);
TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count);
TRANSLATE("Error code: %08X", eip14.eep_error.error_code);
TRANSLATE("Address of error: %08X", eip14.eep_error.address);
TRANSLATE("Expected data: %08X", eip14.eep_error.expected);
TRANSLATE("Actual data: %08X", eip14.eep_error.actual);
TRANSLATE(
"Controller uptime of failure: %y.",
eip14.eep_error.uptime
);
TRANSLATE("DIMM size: %d MB", eip14.dimm_size );
ENDTRANSLATIONBLOCK
EC BLOCK: 830a3b14 SCID_DOG_SRAM_PARITY_GEN_FAIL
TRANSLATIONBLOCK
CONDITIONAL(
eip14.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("Test Element: %d.", eip14.eep_error.TE_num);
TRANSLATE("Test number: %d.", eip14.eep_error.test_num);
TRANSLATE("Duplicate error count: %d.", eip14.eep_error.count);
TRANSLATE("Error code: %08X", eip14.eep_error.error_code);
TRANSLATE("Address of error: %08X", eip14.eep_error.address);
TRANSLATE("Expected data: %08X", eip14.eep_error.expected);
TRANSLATE("Actual data: %08X", eip14.eep_error.actual);
TRANSLATE(
"Controller uptime of failure: %y.",
eip14.eep_error.uptime
);
TRANSLATE("DIMM size: %d MB", eip14.dimm_size );
ENDTRANSLATIONBLOCK
TERMINATION CODE TRANSLATION BLOCKS:
TC BLOCK: 0101011f SCID_EXEC_FLT_UNKNOWN
TRANSLATIONBLOCK
TRANSLATE("TC [llistefc]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0102011f SCID_EXEC_FLT_DLQ_ENTRY_CHECK
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0103011f SCID_EXEC_FLT_TIMER_NOT_EXPIRED
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0104011f SCID_EXEC_FLT_NOT_A_TIMER
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0105011f SCID_EXEC_FLT_DLQ_LINKS_NOT_ZERO
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0106011f SCID_EXEC_FLT_DLQ_HEAD_CHECK
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0107011f SCID_EXEC_FLT_SQ_LINK_NOT_ZERO
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0108011f SCID_EXEC_FLT_NOT_A_BQUE
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0109011f SCID_EXEC_FLT_NOT_A_SEM
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 010a011f SCID_EXEC_FLT_NYI
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 010b011f SCID_EXEC_FLT_NOT_TWI_AS_EXPECTD
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 010c011f SCID_EXEC_FLT_TOO_MANY_LOG_CALLS
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 010d011f SCID_EXEC_FLT_UNKNOWN_LOG_CALL
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 010e011f SCID_EXEC_FLT_NOT_A_AQUE
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 010f011f SCID_EXEC_FLT_WAITERS_INVALID
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0110011f SCID_EXEC_FLT_NOT_A_GATE
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0111011f SCID_EXEC_FLT_RECEIVERS_INVALID
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0112011f SCID_EXEC_FLT_BQUE_HAS_ITEMS
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0113011f SCID_EXEC_FLT_NOT_A_ASEM
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0114011f SCID_EXEC_FLT_UNKNOWNSYSTEM_TRAP
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0115011f SCID_EXEC_FLT_ACTIVE_DMA_UNDRFLW
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0116011f SCID_EXEC_FLT_UNEXPECTED_CDB
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0117011f SCID_EXEC_FLT_BUFFER_IN_USE
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0118011f SCID_EXEC_FLT_BUFFER_IS_FREE
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0119011f SCID_EXEC_FLT_INTS_DISABLED
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 011a011f SCID_EXEC_FLT_ZERO_PAGE_CORRUPT
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 011b011f SCID_EXEC_FLT_DCBZNOTCLALND
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 011c0140 SCID_EXEC_FLT_CTRL_K_NOCC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 011d01c0 SCID_EXEC_FLT_CTRL_K_CC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 011e0120 SCID_EXEC_FLT_CTRL_R_NOCC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 011f01a0 SCID_EXEC_FLT_CTRL_R_CC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 01220105 SCID_EXEC_UNKNOWN_SMI
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("GLUE_SMI_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_SMI_39_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 01400100 SCID_EXEC_TIMER_NOT_BQUE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 015a0100 SCID_EXEC_SHEDULER_SUBP_QUE_EMPTY
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02000100 SCID_CA_INSUFF_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02010100 SCID_CA_BAD_GET_DATA
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02020100 SCID_CA_DEFINE_BQ_NO_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02030100 SCID_CA_DUPLICATE_DIRTY
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02040100 SCID_CA_BAD_MOP_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02050100 SCID_CA_BAD_UNIT_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02070100 SCID_CA_BROKEN_TWICE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02080100 SCID_CA_MIRROR_UUID_CHANGED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02090100 SCID_CA_INVALID_LOCK_META
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 020a0100 SCID_CA_INVALID_PARITY
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 020b0100 SCID_CA_BAD_POP_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 020c0100 SCID_CA_BAD_GCOP_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 020d0100 SCID_CA_NCA_CORRUPTED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 020e0100 SCID_CA_FREE_DIAG_BUF
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 020f0100 SCID_CA_IMPROPER_MWB_RECO
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02100100 SCID_CA_DIFF_MNODE_MFC_NCAE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02110100 SCID_CA_IMPROPER_MWBF_RECO
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02120100 SCID_CA_WRITE_HOLE_COLL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02150100 SCID_CA_CNODE_LEAK
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02160100 SCID_CA_VBUFF_LEAK
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 02180102 SCID_CA_BAD_PROXY_WRITE_STATE
TRANSLATIONBLOCK
TRANSLATE("Bad Proxy Write MFC State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("State value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 02190102 SCID_CA_BAD_PROXY_READ_STATE
TRANSLATIONBLOCK
TRANSLATE("Bad Proxy Read MFC State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("State value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 021a0102 SCID_CA_BAD_PROXY_VERIFY_STATE
TRANSLATIONBLOCK
TRANSLATE("Bad Proxy Verify MFC State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("State value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 021b0100 SCID_CA_NOT_ENOUGH_XDS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 021c0102 SCID_CA_INVALID_FLUSH_NODE
TRANSLATIONBLOCK
TRANSLATE("Flush Node Ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Block Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03010104 SCID_SCS_INTERNAL_ERROR_SINGLE
TRANSLATIONBLOCK
TRANSLATE("PC of termination call: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("PC-specific parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("PC-specific parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("PC-specific parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03020184 SCID_SCS_INTERNAL_ERROR_DUAL
TRANSLATIONBLOCK
TRANSLATE("PC of termination call: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("PC-specific parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("PC-specific parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("PC-specific parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03030102 SCID_SCS_BAD_SWITCH_VALUE
TRANSLATIONBLOCK
TRANSLATE("PC of termination call: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Switch value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03040102 SCID_SCS_QUORUM_ACCESS_FAILURE
TRANSLATIONBLOCK
TRANSLATE("PC of termination call: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("QW block address where access failed: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03060184 SCID_SCS_UNRECOVERABLE_ERROR
TRANSLATIONBLOCK
TRANSLATE("PC of termination call: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("PC-specific parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("PC-specific parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("PC-specific parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 030a0102 SCID_SCS_BAD_SCSDB_INDEX
TRANSLATIONBLOCK
TRANSLATE("area_offset: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("ds_index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 030b0101 SCID_SCS_BAD_SCSDB_AREA_OFF
TRANSLATIONBLOCK
TRANSLATE("area_offset: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 030c0100 SCID_SCS_SCSDB_CACHE_FULL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 030d0101 SCID_SCS_SCSDB_CACHE_FREE
TRANSLATIONBLOCK
TRANSLATE("cache page index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 030e0102 SCID_SCS_SCSDB_CACHE_FLUSH
TRANSLATIONBLOCK
TRANSLATE("cache page index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("page offset: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 030f0101 SCID_SCS_SCSDB_CACHE_COMMIT
TRANSLATIONBLOCK
TRANSLATE("cache page index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03100102 SCID_SCS_BAD_CVMDB_INDEX
TRANSLATIONBLOCK
TRANSLATE("area_offset: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("ds_index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03110101 SCID_SCS_BAD_CVMDB_AREA_OFF
TRANSLATIONBLOCK
TRANSLATE("area_offset: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03120100 SCID_SCS_CVMDB_CACHE_FULL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03130101 SCID_SCS_CVMDB_CACHE_FREE
TRANSLATIONBLOCK
TRANSLATE("Cache page index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03140102 SCID_SCS_CVMDB_CACHE_FLUSH
TRANSLATIONBLOCK
TRANSLATE("Cache page index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Page offset: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03150101 SCID_SCS_CVMDB_CACHE_COMMIT
TRANSLATIONBLOCK
TRANSLATE("Cache page index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03160100 SCID_SCS_PB_BUFFER_ALLOC_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 031f0100 SCID_SCS_FC_OP_DESCS_ALLOC_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 032a0000 SCID_SCS_MASTER_CONFLICT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 033c0106 SCID_SCS_BAD_RP_LOGIN_STATE
TRANSLATIONBLOCK
TRANSLATE("Invocation instance: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Port login state: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Local port: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Port id value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Port name (low): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Port name (high): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
ENDTRANSLATIONBLOCK
TC BLOCK: 033d0105 SCID_SCS_BAD_RP_LOGGEDIN_TMR_EXP
TRANSLATIONBLOCK
TRANSLATE("Port login state: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Local port: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Port id value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Port name (low): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Port name (high): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03500020 SCID_SCS_DEBUG_CRASH
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03510141 SCID_SCS_KILLED_BY_OTHER
TRANSLATIONBLOCK
TRANSLATE("Reason code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03520140 SCID_SCS_KILL_OTHER
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03640020 SCID_SCS_SHUTDOWN_RESTART
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03650060 SCID_SCS_SHUTDOWN_NORESTART
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03660060 SCID_SCS_SHUTDOWN_POWEROFF
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03670000 SCID_SCS_CRASH_RESTART
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03680040 SCID_SCS_CRASH_NORESTART
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 03690080 SCID_SCS_CRASH_RESTART_COUPLED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 036a00c0 SCID_SCS_CRASH_NORESTART_COUPLED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 036b0001 SCID_SCS_CANT_FAILOVER_FREEZING_UNIT
TRANSLATIONBLOCK
TRANSLATE("Unit noid: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 036c01c8 SCID_SCS_NOTIFY_DEV
TRANSLATIONBLOCK
TRANSLATE("Generic parameter 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Generic parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Generic parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Generic parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Generic parameter 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Generic parameter 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Generic parameter 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("Generic parameter 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03780101 SCID_SCS_CANT_REALIZE_XXXDB
TRANSLATIONBLOCK
TRANSLATE("Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 03790020 SCID_SCS_CODE_LOAD_RESTART
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0400011f SCID_FM_DEF_EXCEPTION
TRANSLATIONBLOCK
TRANSLATE("Ecde [llistppcec]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0401011f SCID_FM_MACHINE_CHECK
TRANSLATIONBLOCK
TRANSLATE("Glue chip interrupt bits [31:0]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Glue chip interrupt bits [63:32]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0402011f SCID_FM_DEBUG
TRANSLATIONBLOCK
TRANSLATE("Pointer to DEBUG purpose string: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0403047f SCID_FM_RECURSIVE_TE
TRANSLATIONBLOCK
TRANSLATE("Recursive event termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Recursive event termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Recursive event termination parameter 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Recursive event termination parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Recursive event termination parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Recursive event termination parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("Recursive event termination parameter 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("Recursive event termination parameter 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("Recursive event termination parameter 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("Recursive event termination parameter 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("Recursive event termination parameter 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("Recursive event termination parameter 9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("Recursive event termination parameter 10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("Recursive event termination parameter 11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("Recursive event termination parameter 12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("Recursive event termination parameter 13: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("Recursive event termination parameter 14: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("Recursive event termination parameter 15: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("Recursive event termination parameter 16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("Recursive event termination parameter 17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("Recursive event termination parameter 18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("Recursive event termination parameter 19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("Recursive event termination parameter 20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("Recursive event termination parameter 21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("Recursive event termination parameter 22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("Recursive event termination parameter 23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("Recursive event termination parameter 24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("Recursive event termination parameter 25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("Recursive event termination parameter 26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("Recursive event termination parameter 27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("Recursive event termination parameter 28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04050101 SCID_FM_UPDSCELABAE_EDBN_BAD
TRANSLATIONBLOCK
TRANSLATE("Event data block index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0406017f SCID_FM_LTE_RESET
TRANSLATIONBLOCK
TRANSLATE("In progress event termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("In progress event termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("In progress event termination parameter 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("In progress event termination parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("In progress event termination parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("In progress event termination parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("In progress event termination parameter 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("In progress event termination parameter 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("In progress event termination parameter 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("In progress event termination parameter 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("In progress event termination parameter 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("In progress event termination parameter 9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("In progress event termination parameter 10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("In progress event termination parameter 11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("In progress event termination parameter 12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("In progress event termination parameter 13: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("In progress event termination parameter 14: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("In progress event termination parameter 15: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("In progress event termination parameter 16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("In progress event termination parameter 17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("In progress event termination parameter 18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("In progress event termination parameter 19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("In progress event termination parameter 20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("In progress event termination parameter 21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("In progress event termination parameter 22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("In progress event termination parameter 23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("In progress event termination parameter 24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("In progress event termination parameter 25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("In progress event termination parameter 26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("In progress event termination parameter 27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("In progress event termination parameter 28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0407016a SCID_FM_PREMATURE_TERM
TRANSLATIONBLOCK
TRANSLATE("Trap type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("TC [llisttcc]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("CR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("XER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("CTR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("Exception code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("Exception count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04080582 SCID_FM_COUPLED_CRASH_DR
TRANSLATIONBLOCK
TRANSLATE("Other controller termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Other controller termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 040905a2 SCID_FM_COUPLED_CRASH_NDR
TRANSLATIONBLOCK
TRANSLATE("Other controller termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Other controller termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 040a05c2 SCID_FM_COUPLED_CRASH_DNR
TRANSLATIONBLOCK
TRANSLATE("Other controller termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Other controller termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 040b05e2 SCID_FM_COUPLED_CRASH_NDNR
TRANSLATIONBLOCK
TRANSLATE("Other controller termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Other controller termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 040c0582 SCID_FM_COUPLED_CRASH_BADDRCC
TRANSLATIONBLOCK
TRANSLATE("Other controller termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Other controller termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 040d0101 SCID_FM_UNRECOG_UPDSCELABAE_OP
TRANSLATIONBLOCK
TRANSLATE("Unrecognized value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
ENDTRANSLATIONBLOCK
TC BLOCK: 040e0100 SCID_FM_NOT_MASTER
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 040f0100 SCID_FM_IS_MASTER
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 04100182 SCID_FM_SCEL_NOT_ACTIVE
TRANSLATIONBLOCK
TRANSLATE("Local control flags: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Master control flags: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04110181 SCID_FM_CSLD_SCXEL_INACC
TRANSLATIONBLOCK
TRANSLATE("Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04120123 SCID_FM_ALL_LTE_RESET
TRANSLATIONBLOCK
TRANSLATE("Unexpected event type: %d. (%[fm_ue])",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Index: %d.",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Good entries: %d.",
teb.u.data.ltei.lter.termination_event.params.param[2]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04130107 SCID_FM_INVALID_STRUCT_TYPE
TRANSLATIONBLOCK
TRANSLATE("Unexpected value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Allowed value 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Allowed value 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Allowed value 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Allowed value 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Allowed value 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("Allowed value 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04140104 SCID_FM_EIP_OUT_OF_RANGE
TRANSLATIONBLOCK
TRANSLATE("Event code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Out-of-range EIP type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Minimum allowed EIP type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Maximum allowed EIP type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04150104 SCID_FM_EIP_TOO_BIG
TRANSLATIONBLOCK
TRANSLATE("Event code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("EIP type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("EIP size: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Maximum allowed EIP size: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04160103 SCID_FM_EIP_NOT_MULTLW
TRANSLATIONBLOCK
TRANSLATE("Event code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("EIP type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("EIP size: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04170107 SCID_FM_CSIO_REQUEST_INVALID
TRANSLATIONBLOCK
TRANSLATE("Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("I/O operation: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("NOID: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Block address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Number of blocks: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[5] == 0,
TRANSLATE("Buffer address supplied to CS: 0x00000000 (erase)"),
TRANSLATE("Buffer address supplied to CS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5])
);
TRANSLATE("PC of call to Container Services: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04180107 SCID_FM_CSIO_UNRECOG_STATUS
TRANSLATIONBLOCK
TRANSLATE("Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("I/O operation: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("NOID: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Block address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Number of blocks: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[5] == 0,
TRANSLATE("Buffer address supplied to CS: 0x00000000 (erase)"),
TRANSLATE("Buffer address supplied to CS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5])
);
TRANSLATE("PC of call to Container Services: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04190100 SCID_FM_RESTARTDEBUG
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 041a0100 SCID_FM_UNEXP_ACTIVEQ_EMPTY
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 041b0105 SCID_FM_CORRECT_EDBN_NOT_CACHED
TRANSLATIONBLOCK
TRANSLATE("Event data block number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Current event pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Event entry check status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Current event sequence number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Expected event sequence number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
ENDTRANSLATIONBLOCK
TC BLOCK: 041c0100 SCID_FM_NOT_SCMI_ETC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 041d0100 SCID_FM_NOT_SCMI
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 041e0102 SCID_FM_TEISP_BAD
TRANSLATIONBLOCK
TRANSLATE("Unexpected value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Expected value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 041f0a1f SCID_FM_LOW_MEM_ACC_V
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0420011f SCID_FM_WATCHDOG_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04210107 SCID_FM_CSIO_DRIVE_BROKEN_STATUS
TRANSLATIONBLOCK
TRANSLATE("Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("I/O operation: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("NOID: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Block address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Number of blocks: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[5] == 0,
TRANSLATE("Buffer address supplied to CS: 0x00000000 (erase)"),
TRANSLATE("Buffer address supplied to CS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5])
);
TRANSLATE("PC of call to Container Services: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04220102 SCID_FM_EC_ILLEGAL_SCID
TRANSLATIONBLOCK
TRANSLATE("Event code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Illegal software component: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04240960 SCID_FM_POWER_LOSS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 043f011f SCID_FM_PPC_EXCEPTION_0000
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0440011f SCID_FM_PPC_EXCEPTION_0100
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0441011f SCID_FM_PPC_EXCEPTION_0200
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0442011f SCID_FM_PPC_EXCEPTION_0300
TRANSLATIONBLOCK
TRANSLATE("DSISR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DAR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("DABR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0443011f SCID_FM_PPC_EXCEPTION_0400
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0444011f SCID_FM_PPC_EXCEPTION_0500
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0445011f SCID_FM_PPC_EXCEPTION_0600
TRANSLATIONBLOCK
TRANSLATE("DSISR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DAR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0446011f SCID_FM_PPC_EXCEPTION_0700
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0447011f SCID_FM_PPC_EXCEPTION_0800
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0448011f SCID_FM_PPC_EXCEPTION_0900
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0449011f SCID_FM_PPC_EXCEPTION_0A00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 044a011f SCID_FM_PPC_EXCEPTION_0B00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 044b011f SCID_FM_PPC_EXCEPTION_0C00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 044c011f SCID_FM_PPC_EXCEPTION_0D00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 044d011f SCID_FM_PPC_EXCEPTION_0E00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 044e011f SCID_FM_PPC_EXCEPTION_0F00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 044f011f SCID_FM_PPC_EXCEPTION_1000
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0450011f SCID_FM_PPC_EXCEPTION_1100
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0451011f SCID_FM_PPC_EXCEPTION_1200
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0452011f SCID_FM_PPC_EXCEPTION_1300
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0453011f SCID_FM_PPC_EXCEPTION_1400
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04540101 SCID_FM_BAD_EDBN_COUNT
TRANSLATIONBLOCK
TRANSLATE("Event data block count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 04550101 SCID_FM_BAD_REI_STATUS
TRANSLATIONBLOCK
TRANSLATE("Unexpected status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 04560102 SCID_FM_ACTIVEQ_EVENT_NA
TRANSLATIONBLOCK
TRANSLATE("Sequence number requested: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Number events reported valid for retrieval: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 04570105 SCID_FM_DIRECT_TERM_CALL
TRANSLATIONBLOCK
TRANSLATE("PC of direct call: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Stack pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Trap type parameter: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("TC parameter: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Save area parameter: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0458011f SCID_FM_PPC_EXCEPTION_1500
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0459011f SCID_FM_PPC_EXCEPTION_1600
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 045a011f SCID_FM_PPC_EXCEPTION_1700
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 045b011f SCID_FM_PPC_EXCEPTION_1800
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 045c011f SCID_FM_PPC_EXCEPTION_1900
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 045d011f SCID_FM_PPC_EXCEPTION_1A00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 045e011f SCID_FM_PPC_EXCEPTION_1B00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 045f011f SCID_FM_PPC_EXCEPTION_1C00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0460011f SCID_FM_PPC_EXCEPTION_1D00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0461011f SCID_FM_PPC_EXCEPTION_1E00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0462011f SCID_FM_PPC_EXCEPTION_1F00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0463011f SCID_FM_PPC_EXCEPTION_2000
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0464011f SCID_FM_PPC_EXCEPTION_2100
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0465011f SCID_FM_PPC_EXCEPTION_2200
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0466011f SCID_FM_PPC_EXCEPTION_2300
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0467011f SCID_FM_PPC_EXCEPTION_2400
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0468011f SCID_FM_PPC_EXCEPTION_2500
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0469011f SCID_FM_PPC_EXCEPTION_2600
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 046a011f SCID_FM_PPC_EXCEPTION_2700
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 046b011f SCID_FM_PPC_EXCEPTION_2800
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 046c011f SCID_FM_PPC_EXCEPTION_2900
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 046d011f SCID_FM_PPC_EXCEPTION_2A00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 046e011f SCID_FM_PPC_EXCEPTION_2B00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 046f011f SCID_FM_PPC_EXCEPTION_2C00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0470011f SCID_FM_PPC_EXCEPTION_2D00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0471011f SCID_FM_PPC_EXCEPTION_2E00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0472011f SCID_FM_PPC_EXCEPTION_2F00
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04730167 SCID_FM_BUILD_ADDRESS_MAP_ERROR
TRANSLATIONBLOCK
TRANSLATE("ADDRESS_MAP index: %d.",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter 1: %d. (0x%08x)",
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter 2: %d. (0x%08x)",
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter 3: %d. (0x%08x)",
teb.u.data.ltei.lter.termination_event.params.param[3],
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Parameter 4: %d. (0x%08x)",
teb.u.data.ltei.lter.termination_event.params.param[4],
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Parameter 5: %d. (0x%08x)",
teb.u.data.ltei.lter.termination_event.params.param[5],
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Parameter 6: %d. (0x%08x)",
teb.u.data.ltei.lter.termination_event.params.param[6],
teb.u.data.ltei.lter.termination_event.params.param[6] );
ENDTRANSLATIONBLOCK
TC BLOCK: 04740160 SCID_FM_ELPMA_NOTALLOC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0476013f SCID_FM_LTE_RESET_CMPLT
TRANSLATIONBLOCK
TRANSLATE("In progress event termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("In progress event termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("In progress event termination parameter 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("In progress event termination parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("In progress event termination parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("In progress event termination parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("In progress event termination parameter 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("In progress event termination parameter 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("In progress event termination parameter 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("In progress event termination parameter 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("In progress event termination parameter 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("In progress event termination parameter 9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("In progress event termination parameter 10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("In progress event termination parameter 11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("In progress event termination parameter 12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("In progress event termination parameter 13: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("In progress event termination parameter 14: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("In progress event termination parameter 15: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("In progress event termination parameter 16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("In progress event termination parameter 17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("In progress event termination parameter 18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("In progress event termination parameter 19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("In progress event termination parameter 20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("In progress event termination parameter 21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("In progress event termination parameter 22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("In progress event termination parameter 23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("In progress event termination parameter 24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("In progress event termination parameter 25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("In progress event termination parameter 26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("In progress event termination parameter 27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("In progress event termination parameter 28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0477013f SCID_FM_LTE_RESET_INTD
TRANSLATIONBLOCK
TRANSLATE("In progress event termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("In progress event termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("In progress event termination parameter 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("In progress event termination parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("In progress event termination parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("In progress event termination parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("In progress event termination parameter 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("In progress event termination parameter 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("In progress event termination parameter 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("In progress event termination parameter 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("In progress event termination parameter 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("In progress event termination parameter 9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("In progress event termination parameter 10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("In progress event termination parameter 11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("In progress event termination parameter 12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("In progress event termination parameter 13: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("In progress event termination parameter 14: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("In progress event termination parameter 15: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("In progress event termination parameter 16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("In progress event termination parameter 17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("In progress event termination parameter 18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("In progress event termination parameter 19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("In progress event termination parameter 20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("In progress event termination parameter 21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("In progress event termination parameter 22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("In progress event termination parameter 23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("In progress event termination parameter 24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("In progress event termination parameter 25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("In progress event termination parameter 26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("In progress event termination parameter 27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("In progress event termination parameter 28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0478393f SCID_FM_LTE_RESET_SPPC_RESET
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Reserved: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Reserved: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[3]
!= 0,
TRANSLATE(
"Previous termination event code[-1]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[4]
!= 0,
TRANSLATE(
"Previous termination event code[-2]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[5]
!= 0,
TRANSLATE(
"Previous termination event code[-3]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[6]
!= 0,
TRANSLATE(
"Previous termination event code[-4]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[7]
!= 0,
TRANSLATE(
"Previous termination event code[-5]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[8]
!= 0,
TRANSLATE(
"Previous termination event code[-6]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[9]
!= 0,
TRANSLATE(
"Previous termination event code[-7]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[10]
!= 0,
TRANSLATE(
"Previous termination event code[-9]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[11]
!= 0,
TRANSLATE(
"Previous termination event code[-10]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[12]
!= 0,
TRANSLATE(
"Previous termination event code[-11]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[13]
!= 0,
TRANSLATE(
"Previous termination event code[-12]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[14]
!= 0,
TRANSLATE(
"Previous termination event code[-13]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[15]
!= 0,
TRANSLATE(
"Previous termination event code[-14]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[16]
!= 0,
TRANSLATE(
"Previous termination event code[-15]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[17]
!= 0,
TRANSLATE(
"Previous termination event code[-16]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[18]
!= 0,
TRANSLATE(
"Previous termination event code[-17]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[19]
!= 0,
TRANSLATE(
"Previous termination event code[-18]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[20]
!= 0,
TRANSLATE(
"Previous termination event code[-19]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[21]
!= 0,
TRANSLATE(
"Previous termination event code[-20]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[22]
!= 0,
TRANSLATE(
"Previous termination event code[-21]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[23]
!= 0,
TRANSLATE(
"Previous termination event code[-22]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[25]
!= 0,
TRANSLATE(
"Previous termination event code[-23]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[26]
!= 0,
TRANSLATE(
"Previous termination event code[-24]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[27]
!= 0,
TRANSLATE(
"Previous termination event code[-25]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[28]
!= 0,
TRANSLATE(
"Previous termination event code[-26]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[29]
!= 0,
TRANSLATE(
"Previous termination event code[-27]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]
)
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[30]
!= 0,
TRANSLATE(
"Previous termination event code[-28]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]
)
);
ENDTRANSLATIONBLOCK
TC BLOCK: 04790020 SCID_FM_LTE_RESET_MMTSTEXECD
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 047a013f SCID_FM_LTE_RESET_UNEXP
TRANSLATIONBLOCK
TRANSLATE("Termination processing state value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Reserved: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("In progress event termination location: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("In progress event termination code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("In progress event termination parameter 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("In progress event termination parameter 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("In progress event termination parameter 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("In progress event termination parameter 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("In progress event termination parameter 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("In progress event termination parameter 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("In progress event termination parameter 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("In progress event termination parameter 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("In progress event termination parameter 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("In progress event termination parameter 9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("In progress event termination parameter 10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("In progress event termination parameter 11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("In progress event termination parameter 12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("In progress event termination parameter 13: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("In progress event termination parameter 14: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("In progress event termination parameter 15: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("In progress event termination parameter 16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("In progress event termination parameter 17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("In progress event termination parameter 18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("In progress event termination parameter 19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("In progress event termination parameter 20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("In progress event termination parameter 21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("In progress event termination parameter 22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("In progress event termination parameter 23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("In progress event termination parameter 24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("In progress event termination parameter 25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("In progress event termination parameter 26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 047b0022 SCID_FM_SCRUB_REQUESTED
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[0] == 15,
TRANSLATE("SCRUB was requested via OCP")
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[0] == 56,
TRANSLATE("SCRUB was requested via OCP")
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[0] == 99,
TRANSLATE("SCRUB was requested via SCMI")
);
CONDITIONAL(
teb.u.data.ltei.lter.termination_event.params.param[0] == 100,
TRANSLATE("SCRUB was requested via the Console")
);
TRANSLATE("Calling PC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04810130 SCID_FM_XL_WATCHDOG_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("GLUE_RESET_DIS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("GLUE_RESET_IN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("GLUE_SELF_RESET: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0482206f SCID_FM_CACHE_VTT_FAIL
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0483206f SCID_FM_DIMM_012_DC_NOT_OK
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0484206f SCID_FM_DIMM_3_DC_NOT_OK
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0485200f SCID_FM_60X_DPE
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04862010 SCID_FM_60X_APE
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0487390e SCID_FM_PPC_L1_ICACHE_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0488390e SCID_FM_PPC_L1_DCACHE_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0489390e SCID_FM_PPC_L2_CACHE_TAG_OR_DPE
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
ENDTRANSLATIONBLOCK
TC BLOCK: 048a2015 SCID_FM_60X_TIMEOUT_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("GLUE_TIMER_CTRL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("GLUE_PPC_SV (pre-Sprite3 only): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("GLUE_PPC_CT (pre-Sprite3 only): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_PC_REV (Sprite3 only): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_PC_WTT (Sprite3 only): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_PC_TT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
ENDTRANSLATIONBLOCK
TC BLOCK: 048b0030 SCID_FM_KILLED_BY_OTHER
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("GLUE_RESET_DIS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("GLUE_RESET_IN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("GLUE_SELF_RESET: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 048c0030 SCID_FM_RESET_BY_SELF
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("GLUE_RESET_DIS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("GLUE_RESET_IN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("GLUE_SELF_RESET: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 048d0030 SCID_FM_RESET_BY_BUTTON
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("GLUE_RESET_DIS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("GLUE_RESET_IN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("GLUE_SELF_RESET: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 048e0114 SCID_FM_ATLANTIS_60X_BAD_ADDR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
ENDTRANSLATIONBLOCK
TC BLOCK: 048f2015 SCID_FM_ATLANTIS_60X_TT_IV_BIRV
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04900114 SCID_FM_ATLANTIS_PROTECTION_ERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04913915 SCID_FM_ATLANTIS_ISRAM_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_SRAM_CONFIGURATION: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_SRAM_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_SRAM_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_SRAM_ERROR_ADDRESS_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_SRAM_ERROR_DATA_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("ATLANTIS_SRAM_ERROR_DATA_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("ATLANTIS_SRAM_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04922015 SCID_FM_ATLANTIS_PM_ECC_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_SDRAM_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_SDRAM_ERROR_DATA_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_SDRAM_ERROR_DATA_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_SDRAM_RECEIVED_ECC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_SDRAM_CALCULATED_ECC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("ATLANTIS_SDRAM_ECC_COUNTER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("ATLANTIS_SDRAM_ECC_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04930112 SCID_FM_ATLANTIS_DEV_BURST_ERROR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_DATA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04942013 SCID_FM_ATLANTIS_DEV_RDY_TIMEOUT
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_DATA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04952013 SCID_FM_ATLANTIS_DEV_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_DEVICE_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_DATA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_DEVICE_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04960112 SCID_FM_ATLANTIS_DMA_BAD_ADDR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04970112 SCID_FM_ATLANTIS_DMA_ACCESS_PROT
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04980112 SCID_FM_ATLANTIS_DMA_WRT_PRO_ERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04990112 SCID_FM_ATLANTIS_DMA_DSCRPT_ACC
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_IDMA_INTERRUPT_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_IDMA_ERROR_ADDRESS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_IDMA_CROSSBAR_TIMEOUT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_IDMA_ERROR_SELECT: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 049a010f SCID_FM_SPRITE_60X_TIMEOUT_PCIX
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
ENDTRANSLATIONBLOCK
TC BLOCK: 049b2010 SCID_FM_SPRITE_LAST_ENTRY_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 049c2010 SCID_FM_SPRITE_60X_ALIGNMENT_ERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 049d3910 SCID_FM_SPRITE_QUEUE_RD_DPE
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
ENDTRANSLATIONBLOCK
TC BLOCK: 049e010f SCID_FM_SPRITE_PCIX_ACCESS_ERROR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
ENDTRANSLATIONBLOCK
TC BLOCK: 049f2011 SCID_FM_SPRITE_QUEUE_INVAL_DEST
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Q_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a0011b SCID_FM_SPRITE_XORDMA_TIMEOUT
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_X_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_X_TMO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_X_CB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_X_PI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_X_CI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_X_CC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_X_USA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_X_SA0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_X_SA1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_X_SA2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_X_SA3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_X_UDA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("SPRITE_X_DA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a1011b SCID_FM_SPRITE_XORDMA_SFRAME_ERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_X_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_X_TMO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_X_CB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_X_PI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_X_CI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_X_CC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_X_USA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_X_SA0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_X_SA1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_X_SA2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_X_SA3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_X_UDA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("SPRITE_X_DA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a2011b SCID_FM_SPRITE_XORDMA_EFRAME_ERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_X_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_X_TMO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_X_CB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_X_PI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_X_CI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_X_CC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_X_USA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_X_SA0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_X_SA1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_X_SA2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_X_SA3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_X_UDA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("SPRITE_X_DA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a3391c SCID_FM_SPRITE_XORDMA_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_X_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_X_TMO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_X_CB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_X_PI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_X_CI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_X_CC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_X_USA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_X_SA0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_X_SA1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_X_SA2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_X_SA3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("SPRITE_X_UDA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("SPRITE_X_DA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a4011b SCID_FM_SPRITE_XORDMA_INVAL_OP
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_X_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_X_TMO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_X_CB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_X_PI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_X_CI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_X_CC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_X_USA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_X_SA0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_X_SA1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_X_SA2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_X_SA3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_X_UDA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("SPRITE_X_DA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a5011b SCID_FM_SPRITE_XORDMA_CNT_ERROR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_X_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_X_TMO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_X_CB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_X_PI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_X_CI: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_X_CC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_X_USA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_X_SA0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_X_SA1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_X_SA2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_X_SA3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_X_UDA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("SPRITE_X_DA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a62011 SCID_FM_SPRITE_BAD_WRT_DATA_ERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_M_ES: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a73911 SCID_FM_SPRITE_CMD_OR_DATA_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_M_ES: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a82011 SCID_FM_SPRITE_NEW_CMD_BAD_ERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_M_ES: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04a92016 SCID_FM_SPRITE_CM_ECC_ERROR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PC_ERR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_M_ES: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_M_ESE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("SPRITE_M_ESO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("SPRITE_M_EAE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_M_EAO: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_M_ESC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04aa2012 SCID_FM_PCIX_NO_BOF_INVAL_DEST
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ab2012 SCID_FM_PCIX_XACTN_LEN_MISMATCH
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ac3912 SCID_FM_PCIX_XACTN_ENTRY_RPERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ad0111 SCID_FM_PCIX_BITE_COUNT_MISMATCH
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ae0111 SCID_FM_PCIX_TARGT_RCNT_EXCEEDED
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04af0111 SCID_FM_PCIX_INITR_RCNT_EXCEEDED
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b00111 SCID_FM_PCIX_SC_COUNT_EXCEEDED
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b10111 SCID_FM_PCIX_SC_ERR_MSG_RCVD
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b20111 SCID_FM_PCIX_UNEXPECTED_SC
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b30111 SCID_FM_PCIX_SC_INVAL_TERMINATN
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b40111 SCID_FM_PCIX_SC_WO_PREV_SR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b52012 SCID_FM_PCIX_PERR_ASSERTED
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b60112 SCID_FM_PCIX_BAD_ADDR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b72012 SCID_FM_PCIX_RCVD_TARG_ABORT
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b82012 SCID_FM_PCIX_SERR_ASSERTED
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04b92012 SCID_FM_PCIX_SERR_DETECTED
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("SPRITE_PCIX_BUS_0_or_1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_Pn_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_Pn_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("SPRITE_Pn_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ba011b SCID_FM_TACH_UNSUP_BYTE_ENA_ERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_PCI_REG_1FC: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04bb391b SCID_FM_TACH_OUTBOUND_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_TACH_STATUS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04bc391b SCID_FM_TACH_INBOUND_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_TACH_STATUS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04bd201c SCID_FM_TACH_DETECTED_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04be201c SCID_FM_TACH_SIGNALED_SERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04bf011b SCID_FM_TACH_RECEIVED_MABORT
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c0201c SCID_FM_TACH_RECEIVED_TABORT
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c1201c SCID_FM_TACH_SIGNALED_TABORT
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c2201c SCID_FM_TACH_MASTER_DATA_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_PCICFG_REG_04: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c3011b SCID_FM_TACH_UNEXP_SC_ERROR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_PCI_X_S: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c4011b SCID_FM_TACH_SC_DISCARDED_ERROR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_PCI_X_S: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c5391c SCID_FM_TACH_PERR_ON_SC_XACTION
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c6391c SCID_FM_TACH_PERR_ON_IN_DATA
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c7391c SCID_FM_TACH_PERR_ON_OUT_DATA
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c8201c SCID_FM_TACH_ATTRIBUTE_PERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04c9011b SCID_FM_TACH_SC_BYTE_CNT_EXCESS
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ca011b SCID_FM_TACH_RD_BYTE_CNT_EXCESS
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04cb011b SCID_FM_TACH_READ_FIFO_PERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04cc011b SCID_FM_TACH_WRITE_FIFO_PERR
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_FSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TACHn_ESCR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04cd011b SCID_FM_TACH_RSVD_REGION_ACCESS
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("REAL_PORT_NUMBER: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TACHn_GSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("SPRITE_PC_ADDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TACHn_TACH_CONTROL: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TACHn_FM_STATUSS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TACHn_FM_LINK_STAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TACHn_FM_LINK_STAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TACHn_FM_LINK_STAT3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TACHn_FM_CONFIG1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TACHn_FM_CONFIG2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TACHn_FM_CONFIG3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TACHn_INBOUND_RSTAT1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TACHn_INBOUND_RSTAT2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TACHn_FM_RCVD_AL_PA: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04ce010d SCID_FM_TACH_PERR_ON_SC
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04cf011a SCID_FM_XL_UNDECODED_MC
TRANSLATIONBLOCK
TRANSLATE("SRR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SRR1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("MSSSR0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("GLUE_MCP_31_0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("GLUE_MCP_47_32: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("ATLANTIS_MAIN_INTERRUPT_CAUSE_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SPRITE_PC_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("TACH01_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("TACH23_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("TACH45_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TACH67_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TACH89_CINTPEND: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("ATLANTIS_CPU_ERROR_CAUSE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("ATLANTIS_CPU0_ERROR_MASK: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("ATLANTIS_CPU_ERROR_ADDRESS_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_LOW: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("ATLANTIS_CPU_ERROR_DATA_HIGH: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("ATLANTIS_CPU_ERROR_PARITY: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("SPRITE_P0_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("SPRITE_P0_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("SPRITE_P0_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("SPRITE_P1_CSR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("SPRITE_P1_CSR2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("SPRITE_P1_EDR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04d00180 SCID_FM_MEALCP_INUSE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 04f6013f SCID_FM_USERAPNDR_TEST
TRANSLATIONBLOCK
TRANSLATE("TP[0]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("TP[1]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("TP[2]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("TP[3]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("TP[4]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("TP[5]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("TP[6]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("TP[7]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("TP[8]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("TP[9]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("TP[10]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TP[11]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TP[12]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TP[13]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TP[14]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TP[15]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TP[16]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TP[17]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TP[18]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TP[19]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TP[20]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TP[21]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TP[22]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TP[23]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TP[24]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TP[25]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TP[26]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TP[27]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("TP[28]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("TP[29]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("TP[30]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04f70000 SCID_FM_CTRL_Z_NOCC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 04f9017f SCID_FM_POFF_TEST
TRANSLATIONBLOCK
TRANSLATE("TP[0]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("TP[1]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("TP[2]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("TP[3]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("TP[4]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("TP[5]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("TP[6]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("TP[7]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("TP[8]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("TP[9]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("TP[10]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TP[11]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TP[12]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TP[13]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TP[14]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TP[15]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TP[16]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TP[17]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TP[18]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TP[19]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TP[20]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TP[21]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TP[22]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TP[23]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TP[24]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TP[25]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TP[26]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TP[27]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("TP[28]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("TP[29]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("TP[30]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04fa0100 SCID_FM_USERNP_TEST
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 04fb011f SCID_FM_USERAP_TEST
TRANSLATIONBLOCK
TRANSLATE("TP[0]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("TP[1]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("TP[2]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("TP[3]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("TP[4]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("TP[5]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("TP[6]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("TP[7]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("TP[8]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("TP[9]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("TP[10]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TP[11]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TP[12]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TP[13]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TP[14]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TP[15]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TP[16]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TP[17]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TP[18]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TP[19]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TP[20]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TP[21]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TP[22]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TP[23]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TP[24]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TP[25]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TP[26]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TP[27]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("TP[28]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("TP[29]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("TP[30]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04fc0100 SCID_FM_ISRNP_TEST
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 04fd011f SCID_FM_ISRAP_TEST
TRANSLATIONBLOCK
TRANSLATE("TP[0]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("TP[1]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("TP[2]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("TP[3]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("TP[4]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("TP[5]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("TP[6]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("TP[7]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("TP[8]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("TP[9]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("TP[10]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("TP[11]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("TP[12]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("TP[13]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("TP[14]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("TP[15]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("TP[16]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("TP[17]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("TP[18]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("TP[19]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("TP[20]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("TP[21]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("TP[22]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("TP[23]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("TP[24]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("TP[25]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("TP[26]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("TP[27]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("TP[28]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("TP[29]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("TP[30]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 04fe0100 SCID_FM_NYI
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 04ff011f SCID_FM_OLD_STYLE_BUGCHECK
TRANSLATIONBLOCK
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Undefined: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SRR1 (machine state): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Link Register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Stack Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("R31: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("R30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("R29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("R28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("R27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("R26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("R25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("R24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("R23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("R22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("R21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("R20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("R19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("R18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("R17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("R16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("R12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("R11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("R10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("R9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("R8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("R7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("R6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("R5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("R4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("R3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 06040100 SCID_FCS_INIT_MEM_SFQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06150100 SCID_FCS_INIT_FCS_DUMP
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 061c0100 SCID_FCS_INIT_MEM_IBQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 061d0100 SCID_FCS_INIT_MEM_MFC_COP_BUF
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06200100 SCID_FCS_INVAL_COMPL_MSG
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06230100 SCID_FCS_CLASS2_OUTB_FAILURE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0624011f SCID_FCS_HOST_PROGRAMMING_ERROR
TRANSLATIONBLOCK
TRANSLATE("Callback: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("SEST Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("CDB10B Opcode: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Loc: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28] );
TRANSLATE("SGL ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29] );
TRANSLATE("SGL Byte Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30] );
ENDTRANSLATIONBLOCK
TC BLOCK: 06280100 SCID_FCS_INVAL_PORT_EVENT_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06290100 SCID_FCS_UNKNOWN_FED_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 062a0100 SCID_FCS_UNKNOWN_LDN_FED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 062b0100 SCID_FCS_START_TIMER_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 062c0100 SCID_FCS_UNKNOWN_TIMER_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 062e0100 SCID_FCS_SEST_PROGM_ERROR
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 062f0100 SCID_FCS_UNKNOWN_EXCH_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06320100 SCID_FCS_PORT_OFFLINE_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06330100 SCID_FCS_OUT_RESERVED_FEDS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06340100 SCID_FCS_UNSUPPORTED_ELS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06360100 SCID_FCS_UNSUPPORTED_DRIVE_INIT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06380100 SCID_FCS_UNSUPPORTED_TDS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 063c0100 SCID_FCS_LBA_RANGE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06410100 SCID_FCS_UNKNOWN_STATUS_BYTE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06420100 SCID_FCS_NO_BACKEND_PORTS_AVAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06460100 SCID_FCS_UNSUPPORTED_SES_PAGE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06470100 SCID_FCS_BAD_STRING_IN_PAGE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 06500080 SCID_FCS_REMOTE_COUPLE_CRASH
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0651011f SCID_FCS_MFC_PROC_ACK_DSI_TRAP
TRANSLATIONBLOCK
TRANSLATE("MFC Port Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("rcvd_pcb_ptr: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("rcvd_d_id: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("out_credits: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("next_sn: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("last_rcvd_ack: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("delivered_sn: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("last_xferred_ack: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("flags: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("acked_sn: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("process_sn: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10] );
TRANSLATE("ack_cnt: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11] );
TRANSLATE("tunnel_idx: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12] );
TRANSLATE("in-tunnel 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13] );
TRANSLATE("in-tunnel 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14] );
TRANSLATE("in-tunnel 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15] );
TRANSLATE("in-tunnel 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16] );
TRANSLATE("in-tunnel 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17] );
TRANSLATE("in-tunnel 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18] );
TRANSLATE("in-tunnel 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19] );
TRANSLATE("in-tunnel 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20] );
TRANSLATE("in-tunnel 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21] );
TRANSLATE("out-tunnel 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22] );
TRANSLATE("out-tunnel 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23] );
TRANSLATE("out-tunnel 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24] );
TRANSLATE("out-tunnel 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25] );
TRANSLATE("out-tunnel 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26] );
TRANSLATE("out-tunnel 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27] );
TRANSLATE("out-tunnel 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28] );
TRANSLATE("out-tunnel 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29] );
TRANSLATE("out-tunnel 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30] );
ENDTRANSLATIONBLOCK
TC BLOCK: 07000100 SCID_CS_INSUFF_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07010100 SCID_CS_LMAP_ALLOC_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07020100 SCID_CS_LMAP_ALLOC_FAIL_2
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07030100 SCID_CS_INVALID_RAID_TYPE_INIT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07070100 SCID_CS_QS_READ_FAIL_1
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 070a0100 SCID_CS_RSD_ALLOC_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 070b0100 SCID_CS_BAD_REF_COUNT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 070c0100 SCID_CS_INVALID_OBJECT_FOR_IO
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 070d0100 SCID_CS_INVALID_IO_RANGE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07110100 SCID_CS_RAIDTYPE_NOTSUPPORTED_1
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07130100 SCID_CS_INVALID_RS_RAID_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07140100 SCID_CS_INVALID_STRUCT_MAINZQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07150100 SCID_CS_INVALID_STRUCT_LDSBZQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07160100 SCID_CS_INVALID_STRUCT_ODWORKQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07170100 SCID_CS_PBUFF_LEAK
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07180100 SCID_CS_XBUFF_LEAK
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07190100 SCID_CS_NOT_IMPLEMENTED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 071a0100 SCID_CS_WRONG_LDSB
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 071b0100 SCID_CS_WRONG_LDAD_LABORT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 071c0100 SCID_CS_INVALID_RM_MAP_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 071d0100 SCID_CS_RM_CACHE_HIT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 071e0100 SCID_CS_INVALID_PSEG_USAGE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 071f0100 SCID_CS_BAD_OBJ_CLASS_REG_REP
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07200100 SCID_CS_NO_CMAPS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07220100 SCID_CS_INVALID_CS_REQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07240100 SCID_CS_NO_REQS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07260100 SCID_CS_BAD_VOLNOID
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07290100 SCID_CS_MULTIPLE_TRANS_DETECTED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 072a0100 SCID_CS_TRANS_RECOV_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 072b0100 SCID_CS_RECOV_INVALID_TRANS_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 072d0100 SCID_CS_NO_TRANS_DETECTED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 072f0100 SCID_CS_ZERO_BAD_MEM_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07300100 SCID_CS_REGENS_NOT_COMPLETE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07340100 SCID_CS_BAD_OBJ_HANDLE_REQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07350100 SCID_CS_INVALID_OP_REQ_HANDLER1
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07370100 SCID_CS_BAD_VOLNOID_SPARING
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07380100 SCID_CS_NO_XDS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07390100 SCID_CS_INVALID_RTYPE_REGREASS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 073b0100 SCID_CS_UNKNOWN_TRANS_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 073c0100 SCID_CS_TRANS_INCONSISTENCY
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 073d0100 SCID_CS_INVALID_TRANS_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 073e0100 SCID_CS_INVALID_STRUCT_LEVELLDQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 073f0100 SCID_CS_INVALID_STRUCT_SPARERSQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07400100 SCID_CS_INVALID_STRUCT_CSREQQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07410100 SCID_CS_INVALID_STRUCT_PLDMCQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07420100 SCID_CS_NO_RLBS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07430100 SCID_CS_BAD_RLB_LIST
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07440100 SCID_CS_BAD_RLB_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07450100 SCID_CS_INVALID_STRUCT_CSLDQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07460100 SCID_CS_INVALID_STRUCT_CSEBITQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07480100 SCID_CS_NONMASTER_QSIO
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07490100 SCID_CS_NONMASTER_CSLDIO
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 074a0100 SCID_CS_INVALID_STRUCT_ACBWQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 074b0100 SCID_CS_INVALID_ACBW_OPCODE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 074c0100 SCID_CS_INVALID_STRUCT_MAINUNSHQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 074f0100 SCID_CS_INVALID_STRUCT_MIGRATE_WORKQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07500100 SCID_CS_INVALID_STRUCT_MIGRATE_RSQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07510100 SCID_CS_BAD_MEM_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07520100 SCID_CS_MELTDOWN
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07530100 SCID_CS_INVALID_STRUCT_ALB_LIST
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07540100 SCID_CS_RSTORE_NOT_UTILIZED_IN_MAP
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07550100 SCID_CS_INVALID_STRUCT_ALLOC_WQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07570100 SCID_CS_REALIZE_FAILED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07580100 SCID_CS_UNREALIZE_FAILED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07590100 SCID_CS_INIT_ALLOC_UNIT_REALIZED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 075b0100 SCID_CS_IO_FAILURE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 075d0100 SCID_CS_INVALID_STRUCT_CSCBITQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 075e0100 SCID_CS_INVALID_STRUCT_MAINODBGALOCQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 075f0100 SCID_CS_BAD_DUB_RSS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07600100 SCID_CS_INVALID_LD_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07610100 SCID_CS_BAD_DIP_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07620100 SCID_CS_DEALLOC_PSEG_FAILURE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07630100 SCID_CS_RESERVED_CAPACITY_FAILURE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07640100 SCID_CS_INVALID_STRUCT_REBUILD_PARITY
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07680100 SCID_CS_MEMBER_REMOVED_FROM_RSS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07690102 SCID_CS_BAD_MEMBER_MANAGER_STATE
TRANSLATIONBLOCK
TRANSLATE("Volume NOID: 0x%04x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 0,
TRANSLATE("MM Op: IDLE")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 1,
TRANSLATE("MM Op: REGEN S")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 2,
TRANSLATE("MM Op: REGEN D")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 3,
TRANSLATE("MM Op: REPLACE S")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 4,
TRANSLATE("MM Op: REPLACE D")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 5,
TRANSLATE("MM Op: RESTORE S")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 6,
TRANSLATE("MM Op: REVERT")
);
CONDITIONAL(teb.u.data.ltei.lter.termination_event.params.param[1] == 7,
TRANSLATE("MM Op: INIT")
);
ENDTRANSLATIONBLOCK
TC BLOCK: 076a0100 SCID_CS_NO_QUORUM_DISKS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 076b0100 SCID_CS_INVALID_PSEG_ALLOC_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 076c0100 SCID_CS_XMFC_FAILURE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 076d0100 SCID_CS_INVALID_XMFC_OPERATION
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 076e0100 SCID_CS_INVALID_TYPE_IN_RSDM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07700105 SCID_CS_CHKDSK_FAILED
TRANSLATIONBLOCK
TRANSLATE("Status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Op Code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Error Count: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Error Bits[0]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Error Bits[1]: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 07710100 SCID_CS_INVALID_STRUCT_MAINRESYNCQ
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07720100 SCID_CS_RESYNC_CONTROL_NOT_FOUND
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07730100 SCID_CS_UNEXPECTED_RSD
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07740100 SCID_CS_OUT_OF_ORDER_SHADOW_DATA
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 07750100 SCID_CS_UNEXPECTED_REALIZE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08010100 SCID_RS_BAD_EBIT_STATUS
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08020100 SCID_RS_BAD_MEMBER_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08030100 SCID_RS_BAD_RAID_TYPE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08040100 SCID_RS_REWRITE_UNSUPPORTED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08050100 SCID_RS_EMPTY_DMA_CONTEXT_Q
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08060100 SCID_RS_FULL_DMA_CONTEXT_Q
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08070100 SCID_RS_CANT_ALLOCATE_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08080100 SCID_RS_UNSUPPORTED_STRUCT
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 08090100 SCID_RS_SCDBS_CORRUPTED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 080a0100 SCID_RS_UNHANDLED_ERROR
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 080f0100 SCID_RS_OUTOFSYNC_DMA_CONTEXT_Q
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 09010100 SCID_SCMI_BQ_NO_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 09020100 SCID_SCMI_CP_NO_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 09040100 SCID_SCMI_INTERNAL_ERROR
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 09060100 SCID_SCMI_RES_BUF_NO_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 09080100 SCID_SCMI_CMDLCK_NO_MEM
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 09090100 SCID_SCMI_CMDLCK_INIT_FAIL
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b000100 SCID_SYS_BAD_XMFC_RESPONSE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b010100 SCID_SYS_BAD_MFC_VECTOR
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b020100 SCID_SYS_BAD_SACB_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b040100 SCID_SYS_BAD_UTIL_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b052001 SCID_SYS_EEPROM_FAILURE
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0b062001 SCID_SYS_UUID_RANGE_OVERFLOW
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0b080100 SCID_SYS_RESYNC_NOT_ALLOWED
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b092003 SCID_SYS_LCD_FAILURE
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Failure status: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Message code: %d",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0b0a0100 SCID_SYS_BAD_XMFC_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b100021 SCID_SYS_GLUE_CODE_RELOAD
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0b110020 SCID_SYS_RESYNC_NOW
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0b12db60 SCID_SYS_CODE_LOAD_DENIED
TRANSLATIONBLOCK
TRANSLATE(
"Master controllers code is incompatible with this hardware."
);
TRANSLATE(
"Upgrade the master controller before restarting this controller."
);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c010102 SCID_DRM_INVALID_DDS
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c03010c SCID_DRM_INVALID_GSB_DELETE_STATE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Group state (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("EETBs held to acknowledge (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("EETBs or MNODEs Held To Receive (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("Member List (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("Member Count (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[8]);
TRANSLATE("Control Waiter (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[9]);
TRANSLATE("Control Wait List empty (should be 1): %d",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("Copy In Progress (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[11]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c040101 SCID_DRM_RECOVERY_WRITE_DUPLICATE
TRANSLATIONBLOCK
TRANSLATE("Group Sequence Number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c050106 SCID_DRM_RECOVERY_WRITE_NOT_CACHED
TRANSLATIONBLOCK
TRANSLATE("LDSB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Group Sequence Number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Block Address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Blocks: %d",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Cache Node: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c060106 SCID_DRM_RECOVERY_WRITE_NOT_DIRTY
TRANSLATIONBLOCK
TRANSLATE("LDSB: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Group Sequence Number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Block Address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Blocks: %d",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Cache Node: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Cache Node State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c070106 SCID_DRM_RECOVERY_WRITE_LOST_GNODE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c080106 SCID_DRM_INVALID_SCRAG_MIRROR_RIE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("RIE Address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("RIE State Field: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c090106 SCID_DRM_INVALID_SCRAG_MIRROR_MEMBERS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Online count: %d",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("GCA Entry Address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c0a0106 SCID_DRM_INVALID_SCRAG_PRIMARY_RIE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("RIE Address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("RIE State (should be 0): %d",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c0b0106 SCID_DRM_INVALID_SCRAG_PRIMARY_MEMBERS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Online count: %d",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("GCA Entry Address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c0c0104 SCID_DRM_INVALID_GSB_DELETE_IO
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c0d0104 SCID_DRM_INVALID_GSB_INSERT
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c0e0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_1
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c0f0105 SCID_DRM_WRITE_LONG_E_SET_FAILED
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c100104 SCID_DRM_INVALID_ACQUIRE_DRRW
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c110105 SCID_DRM_LOST_GNODE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c130105 SCID_DRM_IO_FAILURE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Lock State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c140106 SCID_DRM_GSN_OUT_OF_SEQUENCE_2
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c150106 SCID_DRM_GSN_OUT_OF_SEQUENCE_3
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c160106 SCID_DRM_GSN_OUT_OF_SEQUENCE_4
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c170106 SCID_DRM_GSN_OUT_OF_SEQUENCE_5
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c180106 SCID_DRM_GSN_OUT_OF_SEQUENCE_6
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c190106 SCID_DRM_GSN_OUT_OF_SEQUENCE_7
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c1a0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_8
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c1b0106 SCID_DRM_GSN_OUT_OF_SEQUENCE_9
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c1c0107 SCID_DRM_GSN_OUT_OF_SEQUENCE_10
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("RIE State (should be 0): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c200106 SCID_DRM_GSN_OUT_OF_SEQUENCE_11
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c210106 SCID_DRM_GSN_OUT_OF_SEQUENCE_12
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Group Online GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("GSN to use + Write Resources Per Bundle: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c220108 SCID_DRM_GSN_OUT_OF_SEQUENCE_13
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Group Online GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("Group Mode: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("Log Flags: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c230105 SCID_DRM_UNEXPECTED_UNIT_CACHE_STATE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Unit Cache State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c240107 SCID_DRM_INVALID_SIDE
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Requested Side: %d",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("Actual Side: %d",
teb.u.data.ltei.lter.termination_event.params.param[6]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c270106 SCID_DRM_GSN_OUT_OF_SEQUENCE_14
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c280106 SCID_DRM_GSN_OUT_OF_SEQUENCE_15
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Expected GSN: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
ENDTRANSLATIONBLOCK
TC BLOCK: 0c290105 SCID_DRM_INVALID_DDS_ADD_MEMBER
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c2a0106 SCID_DRM_INVALID_DDS_ACK_DAS
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[5] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c2b0102 SCID_DRM_INVALID_DDS_ACK_WAIT
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c2c0102 SCID_DRM_INVALID_DDS_WAIT_DONE
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c2d0105 SCID_DRM_INVALID_DDS_DAS_BUILD
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c2e0105 SCID_DRM_INVALID_DDS_DSF_BUILD
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c2f0106 SCID_DRM_INVALID_DDS_DRRW_ACK
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[5] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c300105 SCID_DRM_INVALID_DDS_DRRW_BUILD
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c310105 SCID_DRM_INVALID_DDS_GOB_BUILD
TRANSLATIONBLOCK
TRANSLATE("Data Replication Group: %08x %08x %08x %08x",
teb.u.data.ltei.lter.termination_event.params.param[0],
teb.u.data.ltei.lter.termination_event.params.param[1],
teb.u.data.ltei.lter.termination_event.params.param[2],
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c320101 SCID_DRM_INVALID_DDS_MAIN
TRANSLATIONBLOCK
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c330103 SCID_DRM_INVALID_DDS_MANAGE
TRANSLATIONBLOCK
TRANSLATE("MFC function: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c340101 SCID_DRM_DUAL_MANAGE_EETB_IN_USE
TRANSLATIONBLOCK
TRANSLATE("MFC function: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c350101 SCID_DRM_DUAL_MANAGE_NULL_EETB
TRANSLATIONBLOCK
TRANSLATE("MFC function: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c360102 SCID_DRM_INVALID_DDS_SIMPLE
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c370102 SCID_DRM_INVALID_DDS_SIMPLE_WAIT
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c380102 SCID_DRM_INVALID_DDS_SIMPLE_BUILD
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c390102 SCID_DRM_INVALID_DDS_SOB_BUILD
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c3a0102 SCID_DRM_INVALID_DDS_LDSB_ACK_WAIT
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c3b0102 SCID_DRM_INVALID_DDS_LDSB_ACK_WAIT_RESP
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c3c0102 SCID_DRM_INVALID_DDS_MIRROR_BROKEN
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c3d0102 SCID_DRM_INVALID_DDS_MIRROR_REQUEST_ACK
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c3e0102 SCID_DRM_INVALID_DDS_MIRROR_BUILD
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c3f0102 SCID_DRM_INVALID_DDS_MIRROR_RSP_ACK
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c400102 SCID_DRM_INVALID_DDS_MIRROR_RSP_BUILD
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c410102 SCID_DRM_INVALID_DDS_SITE_FAILOVER
TRANSLATIONBLOCK
TRANSLATE("DDS Expected State: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c420102 SCID_DRM_INVALID_DDS_SYNCH_BUFFS_ACK
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c430102 SCID_DRM_INVALID_DDS_UPDATE_MDW_ACK
TRANSLATIONBLOCK
TRANSLATE("MFC Status: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("DDS State: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c450100 SCID_DRM_INVALID_CODE_PATH
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0c460103 SCID_DRM_CORRUPT_MFC_FRAME
TRANSLATIONBLOCK
TRANSLATE("FRAME_SIZE: %d",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("SLOT_INDEX: %d",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("FRAME_INDEX: %d",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c470104 SCID_DRM_HOST_ACB
TRANSLATIONBLOCK
TRANSLATE("ACB address: %x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("ACB index: %x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Port WWN (high): %x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Port WWN (low): %x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0c480100 SCID_DRM_INIT_FAIL_DDCB_ALLOC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0c490100 SCID_DRM_INIT_FAIL_RNSB_ALLOC
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0c4a0104 SCID_DRM_TEMP_ACB
TRANSLATIONBLOCK
TRANSLATE("ACB address: %x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("ACB index: %x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Port WWN (high): %x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Port WWN (low): %x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 0e000020 SCID_SDC_INVALID_BATT_SYS_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e010020 SCID_SDC_INVALID_HOLDUP_TIME
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e020020 SCID_SDC_INVALID_BRICK_NUMBER
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e030020 SCID_SDC_INVALID_BRICK_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e050020 SCID_SDC_INVALID_BLOWER_NUMBER
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e060020 SCID_SDC_INVALID_BLOWER_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e080020 SCID_SDC_INVALID_TEMPERATURE_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e090020 SCID_SDC_INVALID_PWR_SUPPLY_NUMBER
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e0a0020 SCID_SDC_INVALID_PWR_SUPPLY_STATE
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 0e0b0020 SCID_SDC_COMMAND_SEND_COLLISION
TRANSLATIONBLOCK
ENDTRANSLATIONBLOCK
TC BLOCK: 42000101 SCID_HP_INIT_FAIL_MEM_ALLOC
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42050103 SCID_HP_UNEXPECTED_CACHE_LOCK
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42060105 SCID_HP_UNEXPECTED_SCSI_COMMAND
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42070123 SCID_HP_DROP_DEAD_CNDR
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 420801a3 SCID_HP_DROP_DEAD_CCNDR
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 420901c3 SCID_HP_DROP_DEAD_DC
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 420c0184 SCID_HP_UNKNOWN_RSCSI_BUILD_CONTEXT
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 420d0182 SCID_HP_UNKNOWN_RSCSI_RECEIVE_CONTEXT
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 420e0181 SCID_HP_ICOPS_OUT_OF_MEMORY
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 420f0182 SCID_HP_ICOPS_UNKNOWN_BUILD_CONTEXT
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42100182 SCID_HP_ICOPS_UNKNOWN_RECIEVE_CONTEXT
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42120104 SCID_HP_ILLEGAL_INPROCQ
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42130101 SCID_HP_NO_CMD_HTBS
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42140102 SCID_HP_INVALID_RCV_DATA_CTX
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42150102 SCID_HP_CHMOD_NO_ACB
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42160102 SCID_HP_PRESENT_LUN_NO_ACB
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42190104 SCID_HP_INVALID_CCB_STATE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 421b0102 SCID_HP_INVALID_WORK_REQ_TYPE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 421c0101 SCID_HP_NO_WORK_REQUESTS
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 421e0102 SCID_HP_CMD_HTB_IN_USE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42230102 SCID_HP_UNPLUN_NO_ACB
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42250104 SCID_HP_BAD_ACB_DEL
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42260104 SCID_HP_NO_UA_TABLE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42270108 SCID_HP_UNKNOWN_PORT_EVENT
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42280102 SCID_HP_UNKNOWN_CM
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42290103 SCID_HP_ILLEGAL_SEST_ID
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 422a0103 SCID_HP_BAD_ALPA_ON_PTP
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 422b0103 SCID_HP_UNKNOWN_IDLE_STATUS
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 422c0003 SCID_HP_TACHYON_ERROR
TRANSLATIONBLOCK
TRANSLATE("Unique identifier 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Bad port number (zero-based): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("PCI interrupt status register: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 422d010a SCID_HP_UNKNOWN_IO_ERROR
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
ENDTRANSLATIONBLOCK
TC BLOCK: 422e0104 SCID_HP_ILLEGAL_LUN_ACCESS
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 422f0103 SCID_HP_UNKNOWN_INBOUND_STATUS
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42300103 SCID_HP_ILLEGAL_SCRIPT_RSP
TRANSLATIONBLOCK
TRANSLATE("Unique identifier 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Function that returned bad response: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Bad response: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42310102 SCID_HP_BAD_SCRIPT_ERROR_STATUS
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42320104 SCID_HP_DUPLICATE_LUN
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 4233010a SCID_HP_INVALID_IMMEDIATE_ERROR
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42340104 SCID_HP_INVALID_HTBX_STATE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42350104 SCID_HP_INVALID_UNQUIESCE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42360102 SCID_HP_INVALID_CSEL_STATE
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 42370183 SCID_HP_EVENT_NOTIFY_GAP
TRANSLATIONBLOCK
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Parameter to assist in analysis 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
ENDTRANSLATIONBLOCK
TC BLOCK: 4238011f SCID_HP_CSM_HANG
TRANSLATIONBLOCK
TRANSLATE("CSM stack 0: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("CSM stack 1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("CSM stack 2: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("CSM stack 3: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("CSM stack 4: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("CSM stack 5: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("CSM stack 6: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("CSM stack 7: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("CSM stack 8: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("CSM stack 9: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("CSM stack 10: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("CSM stack 11: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("CSM stack 12: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("CSM stack 13: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("CSM stack 14: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("CSM stack 15: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("CSM stack 16: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("CSM stack 17: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("CSM stack 18: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("CSM stack 19: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("CSM stack 20: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("CSM stack 21: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("CSM stack 22: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("CSM stack 23: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("CSM stack 24: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
TRANSLATE("CSM stack 25: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[25]);
TRANSLATE("CSM stack 26: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[26]);
TRANSLATE("CSM stack 27: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[27]);
TRANSLATE("CSM stack 28: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[28]);
TRANSLATE("CSM stack 29: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[29]);
TRANSLATE("CSM stack 30: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[30]);
ENDTRANSLATIONBLOCK
TC BLOCK: 42390184 SCID_HP_PROXY_BAD_STATE
TRANSLATIONBLOCK
TRANSLATE("Bad Proxy IO MFC State: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("State value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Expected state: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("HTB Pointer: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
ENDTRANSLATIONBLOCK
TC BLOCK: 423a0102 SCID_HP_TACHERR_BOGUS_PORT
TRANSLATIONBLOCK
TRANSLATE("Bogus port number (zero-based): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Bogus port number (zero-based): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 423b0102 SCID_HP_TACH_NOT_RESPONDING
TRANSLATIONBLOCK
TRANSLATE("Bad port number (zero-based): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Bad port number (zero-based): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
ENDTRANSLATIONBLOCK
TC BLOCK: 423c0306 SCID_HP_ADD_CA_ACB
TRANSLATIONBLOCK
TRANSLATE("ACB address: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("ACB index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("Data Replication Manager flag: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("New index: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Remote port wwn (high): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Remote port wwn (low): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
ENDTRANSLATIONBLOCK
TC BLOCK: 83002061 SCID_DOG_CANNOT_BRANCH_ERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
ENDTRANSLATIONBLOCK
TC BLOCK: 83012079 SCID_DOG_UNEXPECTED_VECTOR_ERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Pointer to ASCII error message: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("TE number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Test number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Error code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Address of BUD: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Exception type: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("SRR0 at interrupt: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("SRR1/MSR at interrupt: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("LR: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("UIC status: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
TRANSLATE("UIC mask: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[11]);
TRANSLATE("UIC critical: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[12]);
TRANSLATE("GLUE IS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[13]);
TRANSLATE("GLUE MCPE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[14]);
TRANSLATE("GLUE NPIS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[15]);
TRANSLATE("GLUE NPIE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[16]);
TRANSLATE("GLUE ACNS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[17]);
TRANSLATE("GLUE APNS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[18]);
TRANSLATE("GLUE FPIS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[19]);
TRANSLATE("GLUE FPIE: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[20]);
TRANSLATE("GLUE ACFS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[21]);
TRANSLATE("GLUE APFS: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[22]);
TRANSLATE("QSR ERRDET1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[23]);
TRANSLATE("QSR ERREN1: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[24]);
ENDTRANSLATIONBLOCK
TC BLOCK: 8302206b SCID_DOG_HARD_ERR
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0] );
TRANSLATE("Pointer to ASCII error message: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[1] );
TRANSLATE("TE number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2] );
TRANSLATE("Test number: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3] );
TRANSLATE("Error code: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4] );
TRANSLATE("Address of BUD: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5] );
TRANSLATE("Address of error: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6] );
TRANSLATE("Expected data (hi): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7] );
TRANSLATE("Expected data (lo): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8] );
TRANSLATE("Actual data (hi): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[9] );
TRANSLATE("Actual data (lo): 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[10]);
ENDTRANSLATIONBLOCK
TC BLOCK: 84032069 SCID_DRS_XL_EXCESSIVE_CM_CDES
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Cache memory size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Current number of detected errors: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Previous number of detected errors: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Number of seconds over which errors occurred: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
TRANSLATE("Sprite's m_ese, even ECC status, register value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[5]);
TRANSLATE("Sprite's m_eso, odd ECC status, register value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[6]);
TRANSLATE("Sprite's m_eae, even ECC address, register value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[7]);
TRANSLATE("Sprite's m_eae, odd ECC address, register value: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[8]);
ENDTRANSLATIONBLOCK
TC BLOCK: 84042065 SCID_DRS_XL_EXCESSIVE_PM_CDES
TRANSLATIONBLOCK
CONDITIONAL(
teb.u.data.ltei.lteihd.flags.spsctrlr == 1,
TRANSLATE(
"Single Power Supply HSV210 Controller"
)
);
TRANSLATE("DIMM size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[0]);
TRANSLATE("Cache memory size: %d MB",
teb.u.data.ltei.lter.termination_event.params.param[1]);
TRANSLATE("Current number of detected errors: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[2]);
TRANSLATE("Previous number of detected errors: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[3]);
TRANSLATE("Number of seconds over which errors occurred: 0x%08x",
teb.u.data.ltei.lter.termination_event.params.param[4]);
ENDTRANSLATIONBLOCK
DEFINITIONS:
%[scmi_nsc_restart_option]
0 = None -- no restart
1 = Regular -- full restart, host system connectivity is lost until the controller returns to normal operation
2 = Fast -- resynchronization, restart of the controller in a manner that has little or no impact on host system connectivity
%[scmi_nsc_battery_present_condition]
0 = Not present
1 = Present
%[scmi_group_auto_suspend_state]
1 = Connection between the Data Replication Source and Data Replication Destination is active.
2 = Connection between the Data Replication Source and Data Replication Destination is inactive.
%[scmi_nsc_fc_port_condition]
1 = Normal
2 = Failed
%[scmi_read_disk_cache_policy_type]
1 = Read cache on
2 = Read cache off
%[scmi_fan_status]
1 = Normal
2 = Elevated
3 = High
4 = Bad
5 = Unknown
6 = Not Present
%[scmi_rundown_flag]
0 = Flag is off, log is NOT in rundown mode, normal operation
1 = Flag is on, log is in rundown mode
%[scmi_nsc_shutdown_other_option]
0 = Remain operational
1 = Coupled shutdown
%[scmi_logical_disk_data_availability_condition]
0 = Data available
1 = Data lost
%[scmi_object_function_code]
1001 = Derived Unit Create
1002 = Derived Unit Discard
1003 = Derived Unit Get Device Identifier
1004 = Derived Unit Get Presented Units
1005 = Derived Unit Get Presented Units Count
1006 = Derived Unit Get Storage System Virtual Disk
1007 = Derived Unit Is Write Protected
1008 = Derived Unit Set Write Protected
1009 = Derived Unit Get Settable Id
1010 = Derived Unit Set Settable Id
1011 = *** 1011 no longer used *** Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
2001 = Logical Disk Clear Data Lost
2002 = *** 2002 not used ***
2003 = *** 2003 not used ***
2004 = Logical Disk Create
2005 = Logical Disk Discard
2006 = Logical Disk Get Allocated Capacity
2007 = Logical Disk Get Allocated Storage
2008 = Logical Disk Get Condition
2009 = Logical Disk Get Default SCM EP Id
2010 = Logical Disk Get Disk Group
2011 = Logical Disk Get Master Controller
2012 = *** 2012 not used ***
2013 = Logical Disk Get Redundancy
2014 = Logical Disk Get Reserved Capacity
2015 = Logical Disk Is Data Lost
2016 = Logical Disk Offline
2017 = Logical Disk Online
2018 = *** 2018 not used ***
2019 = *** 2019 not used ***
2020 = *** 2020 not used ***
2021 = *** 2021 not used ***
2022 = Logical Disk Set Reserved Capacity
2023 = Logical Disk Verify
2024 = *** 2024 not used ***
2025 = *** 2025 no longer used ***
2026 = *** 2026 no longer used ***
2027 = Logical Disk Get Successor Logical Disk
2028 = Logical Disk Snapclone
2029 = Logical Disk Snapshot
2030 = Logical Disk Get Predecessor Logical Disk
2031 = Logical Disk Get Preferred Controller
2032 = Logical Disk Set Preferred Controller
2033 = Logical Disk Get Logical Disk Type
2034 = Logical Disk Get LUN WWID
2035 = Logical Disk Set LUN WWID
2036 = Logical Disk Attach Snaps
2037 = Logical Disk Clear Container
2038 = Logical Disk Mirror Clone
2039 = Logical Disk Restore When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
3001 = Disk Group Create
3002 = Disk Group Discard
3003 = Disk Group Get Capacity
3004 = Disk Group Get Max Logical Disk Size
3005 = Disk Group Get Occupancy
3006 = Disk Group Get Occupancy Highwater
3007 = Disk Group Get Volumes
3008 = Disk Group Get Volumes Count
3009 = Disk Group Set Occupancy Highwater
3010 = Disk Group Get Management Logical Disk Size
3011 = Disk Group Read Management Logical Disk
3012 = Disk Group Write Management Logical Disk
3013 = Disk Group Get Spares Current
3014 = Disk Group Get Spares Goal
3015 = Disk Group Set Spares Goal
3016 = Disk Group Get Condition
3017 = Disk Group Resolve Condition
3018 = Disk Group Locate
3019 = Disk Group Create New
3020 = Disk Group Add Volumes
3021 = Disk Group Write Management Logical Disk Blocks
3022 = Disk Group Get Leveling Info
3023 = Disk Group Get SRC
3024 = Disk Group Locate RSS
3025 = Disk Group Get Volumes Info
3026 = Disk Group Set Requested SRC Mode
3027 = Disk Group Get LDAD info
3028 = Disk Group Get drive type
3029 = Disk Group Set Name Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
4001 = Controller Crash
4002 = Controller Generate Id
4003 = *** 4003 no longer used ***
4004 = *** 4004 no longer used ***
4005 = Controller Get Cache Capacity
4006 = Controller Get Cache Condition
4007 = Controller Get Condition
4008 = Controller Get Default SCM EP Id
4009 = Controller Get Fibre Channel Context Id
4010 = Controller Get Firmware Version
4011 = *** 4011 no longer used ***
4012 = Controller Get Identity
4013 = *** 4013 no longer used ***
4014 = *** 4014 no longer used ***
4015 = *** 4015 no longer used ***
4016 = Controller Get Loop Port Node Id
4017 = Controller Get Loop Port Node Type
4018 = Controller Get Loop Port Position
4019 = *** 4019 no longer used ***
4020 = *** 4020 no longer used ***
4021 = *** 4021 no longer used ***
4022 = *** 4022 no longer used ***
4023 = Controller Get Controllers
4024 = Controller Get Controllers Count
4025 = Controller Get Participation
4026 = Controller Get Storage System
4027 = Controller Get Supported Class Versions
4028 = Controller Maintenance Invoke Routine
4029 = Controller Maintenance Read Memory
4030 = Controller Read Dump
4031 = Controller Read ILF Log
4032 = Controller Set Default SCM EP Id
4033 = Controller Set ILF Log Mask
4034 = Controller Set Participation
4035 = Controller Shutdown
4036 = Controller Get Physical Stores
4037 = Controller Get Physical Stores Count
4038 = *** 4038 no longer used ***
4039 = Controller Get Unassigned Host Ports
4040 = Controller Get Unassigned Host Ports Count
4041 = Controller Get Enclosure Status
4042 = Controller Set Enclosure Fan High Speed Mode
4043 = Controller Set Enclosure Temp Trip Point
4044 = Controller Get Hardware Info
4045 = Controller Get Fibre Channel Node Id
4046 = Controller Get Fibre Channel Port Address
4047 = Controller Get Fibre Channel Port Condition
4048 = Controller Get Fibre Channel Port Id
4049 = Controller Get Fibre Channel Port Type
4050 = Controller Get ILF Component Mask
4051 = Controller Get ILF Component Class Mask
4052 = Controller Get ILF Disk Slot
4053 = Controller Set ILF Component Mask
4054 = Controller Set ILF Component Class Mask
4055 = Controller Set ILF Disk Slot
4056 = Controller Get Battery System Capacity
4057 = Controller Get Battery System Condition
4058 = Controller Get Battery Hardware Status
4059 = Controller Get UPS Condition
4060 = Controller Login
4061 = Controller Logout
4062 = Controller Save Firmware
4063 = Controller Use Firmware
4064 = Controller Locate
4065 = Controller Login Step1
4066 = Controller Login Step2
4067 = Controller Get Disk Enclosures
4068 = Controller Get Disk Enclosures Count
4069 = Controller Get Disk Enclosures Status
4070 = Controller Get Disk Enclosure Page
4071 = Controller Locate Disk Enclosure
4072 = Controller Set Disk Enclosure Audible Alarm
4073 = Controller Get Host Port Info
4074 = Controller Get Drive Code Load Info
4075 = Controller Get Loop Port Node Info
4076 = Controller Get Fibre Channel Port Info
4077 = Controller Get Physical Stores Info
4078 = Controller Read Termination Events
4079 = Controller Read Events Activeq
4080 = Controller Open Events Activeq
4081 = Controller Close Events Activeq
4082 = Controller Get Crash Dump Info
4083 = Controller Open Crash Dump
4084 = Controller Read Crash Dump
4085 = Controller Close Crash Dump
4086 = Controller Open ILF Memory
4087 = Controller Read ILF Memory
4088 = Controller Close ILF Memory
4089 = Controller Enable Loop Port
4090 = Controller Get Loop Port Node Error
4091 = Controller Clear Loop Port Node Error
4092 = Controller Start DILX
4093 = Controller Stop DILX
4094 = Controller Get DILX Summary
4095 = Controller Get ncs info
4096 = Controller Get memory size
4097 = Controller Free Unassigned Host Ports
4098 = Get EPBC Error counts
4099 = Controller Read CHECKPOINT Memory
4100 = Controller Close CHECKPOINT Memory
4101 = Controller Open CHECKPOINT Memory
4102 = Request log size Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
5001 = *** 5001 not used ***
5002 = *** 5002 not used ***
5003 = *** 5003 not used ***
5004 = *** 5004 not used *** When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
6001 = Physical Store Clear Failed
6002 = Physical Store Erase Volume
6003 = Physical Store Get Capacity
6004 = Physical Store Get Condition
6005 = Physical Store Get LUN
6006 = Physical Store Get Maintenance Mode
6007 = Physical Store Get Physical Device
6008 = Physical Store Get Volume
6009 = Physical Store Is Failed
6010 = Physical Store Is Failure Predicted
6011 = Physical Store Is Media Inaccessible
6012 = Physical Store Read Inquiry Strings
6013 = *** 6013 no longer used ***
6014 = Physical Store Read Volume Is Quorum Disk
6015 = Physical Store Read Volume Disk Group Id
6016 = Physical Store Read Volume Storage System Id
6017 = Physical Store Read Volume Storage System Name
6018 = Physical Store Send Command
6019 = Physical Store Set Maintenance Mode
6020 = Physical Store Read Node Id
6021 = Physical Store Locate
6022 = Physical Store Get drive type Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c
6023 = Physical Store Get drive type When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
7001 = Presented Unit Create
7002 = Presented Unit Discard
7003 = Presented Unit Get Derived Unit
7004 = Presented Unit Get LUN
7005 = Presented Unit Get Storage System Client
7006 = Presented Unit Set LUN
7007 = *** 7007 no longer used ***
7008 = *** 7008 no longer used ***
7009 = Presented Unit Get Reservation Type When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
8001 = Storage System Create
8002 = Storage System Discard
8003 = Storage System Get Context Id
8004 = *** 8004 no longer used ***
8005 = Storage System Get Device Addition Policy
8006 = *** 8006 not used ***
8007 = Storage System Get Events
8008 = *** 8008 no longer used ***
8009 = *** 8009 no longer used ***
8010 = Storage System Get Master Controller
8011 = *** 8011 no longer used ***
8012 = Storage System Get Name
8013 = *** 8013 no longer used ***
8014 = *** 8014 no longer used ***
8015 = Storage System Get Supported Class Versions
8016 = Storage System Get Time
8017 = Storage System Get Volume Replacement Delay
8018 = Storage System Lookup Object
8019 = Storage System Lookup Object Count
8020 = Storage System Prepare Create
8021 = *** 8021 no longer used ***
8022 = Storage System Set Device Addition Policy
8023 = *** 8023 no longer used ***
8024 = Storage System Set Name
8025 = *** 8025 no longer used ***
8026 = Storage System Set Time
8027 = Storage System Set Volume Replacement Delay
8028 = Storage System Translate Id To Handle
8029 = *** 8029 no longer used ***
8030 = Storage System Free Command Lock
8031 = Storage System Get Command Lock Description
8032 = Storage System Get Command Lock Status
8033 = Storage System Set Default Lock Timeout
8034 = Storage System Set Override Lock Timeout
8035 = Storage System Take Command Lock
8036 = Storage System Get SACD Settable Id
8037 = Storage System Set SACD Settable Id
8038 = Storage System Read Controller Termination Events
8039 = Storage System Sync Reset
8040 = *** 8040 not used ***
8041 = Storage System Get Ups Mode
8042 = Storage System Set Ups Mode
8043 = Storage System Resolve Condition
8044 = Storage System Get Connection Status
8045 = Storage System Get Performance Geometry
8046 = Storage System Get Performance Data
8047 = Storage System Create New
8048 = Storage System Get Logical Disks Info
8049 = Storage System Get Groups Info
8050 = Storage System Get Vdisk Info
8051 = Storage System Get Object Class Status
8052 = Storage System Update Object Class Status Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
9001 = *** 9001 no longer used ***
9002 = Storage System Client Create
9003 = Storage System Client Discard
9004 = Storage System Client Get Client Connections
9005 = Storage System Client Get Client Connections Count
9006 = *** 9006 no longer used ***
9007 = *** 9007 no longer used ***
9008 = *** 9008 no longer used ***
9009 = Storage System Client Add Port WWN
9010 = Storage System Client Get Port WWNs
9011 = Storage System Client Get Port WWNs Count
9012 = Storage System Client Remove Port WWN
9013 = Storage System Client Get Client Mode
9014 = Storage System Client Set Client Mode
9015 = Storage System Client Get Client Mode New
9016 = Storage System Client Set Client Mode New
9017 = Storage System Get Name
9018 = Storage System Set Name When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
10001 = Storage System Virtual Disk Create
10002 = Storage System Virtual Disk Disable
10003 = Storage System Virtual Disk Discard
10004 = Storage System Virtual Disk Enable
10005 = *** 10005 no longer used ***
10006 = Storage System Virtual Disk Get Capacity
10007 = Storage System Virtual Disk Get Derived Units
10008 = Storage System Virtual Disk Get Derived Units Count
10009 = Storage System Virtual Disk Get Logical Disk
10010 = Storage System Virtual Disk Get State
10011 = Storage System Virtual Disk Is Quiesced
10012 = *** 10012 no longer used ***
10013 = Storage System Virtual Disk Set Capacity
10014 = Storage System Virtual Disk Set Logical Disk
10015 = Storage System Virtual Disk Set Quiesced
10016 = Storage System Virtual Disk Get DRM Copy State
10017 = Storage System Virtual Disk Get Group Handle
10018 = Storage System Virtual Disk Is Log Unit
10019 = Storage System Virtual Disk Set Group
10020 = Storage System Virtual Disk Set Group None
10021 = Storage System Virtual Disk Get Disk Cache Policy
10022 = Storage System Virtual Disk Set Disk Cache Policy
10023 = Storage System Virtual Disk Get Remote Storage System Virtual Disk Count
10024 = Storage System Virtual Disk Get Remote Storage System Virtual Disks
10025 = Storage System Virtual Disk Set Name When adding new opcodes, first read comment above V_SCMI_cmd_table_index.
11001 = Volume Clear Failure Predicted
11002 = Volume Create
11003 = Volume Data Security Erase
11004 = Volume Fail Missing Blocks
11005 = Volume Get Capacity
11006 = Volume Get Condition
11007 = Volume Get Disk Group
11008 = Volume Get Occupancy
11009 = Volume Get Physical Store
11010 = Volume Get Requested Usage
11011 = Volume Get Usage
11012 = Volume Is Failure Predicted
11013 = Volume Is Insufficient Resources
11014 = Volume Is Quorum Disk
11015 = Volume Set Requested Usage
11016 = Volume Get RSS Info When adding new opcodes, first read comment above V_SCMI_cmd_table_index. Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c
12001 = Group Create
12002 = Group Discard
12003 = Group Get DRM Log State
12004 = Group Get Failsafe
12005 = Group Get Failsafe Locked
12006 = Group Get Log Storage System Virtual Disk Handle
12007 = Group Get Member Count
12008 = Group Get Members
12009 = Group Get Mode
12010 = Group Get Operation
12011 = Group Get Remote Storage System Count
12012 = Group Get Remote Storage Systems
12013 = Group Get Suspend
12014 = Group Set Site Failover
12015 = Group Set Mode
12016 = Group Set Failsafe
12017 = Group Set Operation
12018 = Group Set Suspend
12019 = Group Get Generation
12020 = Group Get Group Name
12021 = Group Get Read Only
12022 = Group Set Read Only
12023 = *** 12023 not used ***
12024 = *** 12024 not used ***
12025 = Group Get Comment
12026 = Group Get User Name
12027 = Group Set Comment
12028 = Group Set User Name
12029 = Group Get Capacity For Logging
12030 = Group Get Member Condition
12031 = 12031 No longer used
12032 = Group Invalidate Log
12033 = Group Set Max Log Size
12034 = Group Set Destination Presentation
12035 = Group Set Auto Suspend
12036 = V4 and later style Group Create
12037 = Group Get Info
12038 = Group Set Defer Copy When adding new opcodes, first read comment above V_SCMI_cmd_table_index. Defines in scmi_defs.h need to be changed as does the dispatch arrays in scmi_main.c
13001 = Remote Node Discard
13002 = Remote Node Get Info
13003 = Remote Node Purge
13004 = Remote Node Reset DRM Port Pref
13005 = Remote Node Set DRM Port Preferences
%[scmi_nsc_shutdown_poweroff_option]
0 = Remain in the power on state
1 = Power itself off
%[scmi_temp_system_state]
1 = Normal
2 = Critical
3 = Over Temperature
4 = Unknown
%[scmi_nsc_condition]
1 = Normal
2 = *** 2 not used ***
3 = Failed
%[scmi_volume_usage]
1 = Disk Group
2 = Reserved
3 = *** 3 no longer used ***
4 = Temporarily reserved for drive code load
5 = Temporarily reserved for drive code load
6 = Temporarily reserved for drive code load
7 = Temporarily reserved for drive code load
8 = Temporarily reserved for drive code load
9 = Temporarily reserved for drive code load
10 = Temporarily reserved for drive code load
11 = Temporarily reserved for drive code load
12 = Temporarily reserved for drive code load
13 = Temporarily reserved for drive code load
14 = Temporarily reserved for drive code load
15 = Temporarily reserved for drive code load
16 = Temporarily reserved for drive code load
17 = Temporarily reserved for drive code load
18 = Temporarily reserved for drive code load
19 = Temporarily reserved for drive code load
20 = Temporarily reserved for drive code load
%[scmi_volume_condition]
1 = Normal - Volume is present and operating normally
2 = Migrating - Data from this volume is being moved to other storage in this Disk Group
3 = Missing - Volume is inaccessible
4 = Reconstructing - Volume is inaccessible; redundant data is being regenerated and moved to other storage in this Disk Group
5 = Completing - This previously inaccessible volume has become accessible; data migration is being completed
6 = Reverting - This previously inaccessible volume has become accessible; data is being regenerated
7 = Failed - Volume is not being used in the Disk Group; disk errors are preventing normal usage
%[scmi_storagecell_device_addition_policy]
1 = Manual (Extrinsic)
2 = Automatic (Intrinsic)
%[scmi_write_disk_cache_policy_type]
1 = Writethrough
2 = Writeback
%[scmi_shutdown]
1 = Success
2 = Failure
3 = Not Applicable
%[scmi_power_supply_state]
1 = Good
2 = Bad
3 = Unknown
4 = Not Present
%[scmi_battery_brick_status_code]
0 = Unknown
16 = Too Old
32 = Charger Fault
48 = Faulted
64 = Temperature Fault
80 = Charging
96 = Charged
112 = Under Load Test
128 = Code Load
144 = Bad Charger
%[scmi_nsc_fanps_present_condition]
0 = Not present
1 = Present
%[scmi_group_operation_type]
1 = Synchronous
2 = Asynchronous
%[scmi_nsc_battery_use_condition]
0 = Not in use
1 = In use
%[scmi_physical_store_condition]
1 = Normal
2 = Degraded
3 = Failed
4 = Not present
5 = Single port on Fibre
%[scmi_nsc_shutdown_encl_poweroff_option]
0 = Remain in the power on state
1 = Powered off
%[scmi_logical_disk_type]
1 = Original Disk
2 = Space Efficient Snapshot
3 = Space Inefficient Snapshot
4 = Snapclone
5 = Unknown
6 = Empty Container
7 = Mirror Clone
%[scmi_group_drm_ld_state]
1 = Operative
2 = Inoperative
%[scmi_group_suspend_state]
1 = Connection between the Data Replication Source and Data Replication Destination is active.
2 = Connection between the Data Replication Source and Data Replication Destination is inactive.
%[scmi_ldad_condition]
1 = Normal
2 = Disk Group with no redundancy is inoperative
3 = Disk Group with parity redundancy is inoperative
4 = Disk Group with mirrored redundancy is inoperative
5 = Disk Group with no redundancy is inoperative, marked for re-use
6 = Disk Group with parity redundancy is inoperative, marked for re-use
7 = Disk Group with mirrored redundancy is inoperative, marked for re-use
%[scmi_volume_resource_availability_condition]
0 = Sufficient resources available
1 = Insufficient resources available
%[scmi_group_readonly_type]
0 = Data Replication Destination Storage System Virtual Disk disabled for read access.
1 = Data Replication Destination Storage System Virtual Disk enabled for read access.
%[scmi_group_drm_mode]
0 = Normal Active Source
1 = Normal Active Destination
2 = Active/Active (Master)
3 = Active/Active (Slave)
%[scmi_nsc_shutdown_battass_failure_mode]
0 = No failure indicated.
1 = Failed only on this controller
2 = Failed only on the other controller of the pair.
3 = Failed on both controllers.
%[scmi_battery_brick_state]
1 = Good
2 = Bad
3 = Unknown
4 = Not Present
%[scmi_volume_quorum_disk_condition]
0 = Not quorum disk
1 = Quorum disk
%[scmi_mirror_disk_cache_policy_type]
1 = Mirror
2 = No mirror
%[scmi_logical_disk_redundancy_type]
1 = Vraid0
2 = Vraid1
3 = Vraid5
%[scmi_nsc_fan_present_condition]
0 = Not present
1 = Present
%[scmi_group_dest_present_state]
0 = Data Replication Destination Storage System Virtual Disk disabled for destination presentation.
1 = Data Replication Destination Storage System Virtual Disk enabled for destination presentation.
%[scmi_logical_disk_condition]
1 = Normal
2 = Replacement delay in progress
3 = Redundancy lost, restore in progress
4 = Redundancy lost, restore stalled
5 = Failed
6 = Creation in progress
7 = Snapshot is inoperative due to lack of snapshot space
8 = Deletion in progress
9 = Capacity expand in progress + progress +
10 = Inoperative due to data lost
11 = Capacity reservation in progress
12 = Capacity unreservation in progress
13 = Snap deletion in progress
14 = Attaching empty container as snapclone in progress
15 = Attaching empty container as snapshot in progress
16 = Clearing container in progress
17 = Attaching empty container as mirror clone in progress
18 = Resyncing mirror clone in progress +
19 = Detaching mirror clone in progress +
20 = Fracture mirror clone in progress +
21 = Mirror clone fractured +
22 = Invalidated
23 = Source of instant restore +
24 = Target of instant restore +
25 = Instant restore taking place in tree +
26 = Capacity shrink in progress +
%[scmi_logical_disk_snap_attach_type]
0 = Snapshot
1 = SnapClone
2 = Mirror Clone
%[scmi_du_write_protect_condition]
0 = Write protect off
1 = Write protect on
%[scmi_state]
1 = Disabled
2 = Enabled
%[scmi_client_mode]
0 = Unknown
1 = User defined
2 = *** 2 not used ***
3 = WINNT with SecurePath
4 = VMS
5 = TRU64 UNIX
6 = Sun UNIX
7 = NetWare
8 = HP
9 = IBM
10 = LINUX
11 = SCO UNIX
12 = VMWARE
13 = Windows "Longhorn" Server
%[scmi_scvd_quiescent_condition]
0 = Not quiescent
1 = Quiescent
%[scmi_nsc_battery_system_condition]
1 = Good
2 = *** 2 not used ***
3 = Low
4 = *** 4 not used ***
5 = Bad
6 = Unkown
%[scmi_group_defer_copy_state]
1 = Connection between the Data Replication Source and Data Replication Destination is active.
2 = Connection between the Data Replication Source and Data Replication Destination is inactive.
%[scmi_nsc_shutdown_battass_option]
0 = Enabled
1 = Disabled
%[scmi_response_status_value]
0 = 0x00 Success
1 = 0x01 Already Exists
2 = 0x02 Buffer Too Small
3 = 0x03 Id Already Assigned
4 = 0x04 Insufficient Data Storage Available
5 = 0x05 Internal Error
6 = 0x06 Invalid Storage System State Logical Disk
7 = 0x07 Invalid Class
8 = 0x08 Invalid Function
9 = 0x09 Invalid Logical Disk Block State
10 = 0x0A Invalid Loop Configuration
11 = 0x0B Invalid Parameter
12 = 0x0C Invalid Parameter Handle
13 = 0x0D Invalid Parameter Id
14 = 0x0E Invalid Quorum Configuration
15 = 0x0F Invalid Target Handle
16 = 0x10 Invalid Target Id
17 = 0x11 Invalid Time
18 = 0x12 Media Inaccessible
19 = 0x13 No Fibre Channel Port
20 = 0x14 No Image
21 = 0x15 No Permission
22 = 0x16 No Storage System
23 = 0x17 Not Loop Port
24 = 0x18 Not Participating
25 = 0x19 Object In Use
26 = 0x1A Parameter Object Does Not Exist
27 = 0x1B Target Object Does Not Exist
28 = 0x1C Timeout
29 = 0x1D Unknown Id
30 = 0x1E Unknown Parameter Handle
31 = 0x1F Unrecoverable Media Error
32 = 0x20 Invalid State
33 = 0x21 Transport Error
34 = 0x22 Volume Missing
35 = 0x23 Invalid Cursor
36 = 0x24 Invalid Target Logical Disk
37 = 0x25 No More Events
38 = 0x26 Lock Busy
39 = 0x27 Time Not Set
40 = 0x28 Not Supported Version
41 = 0x29 No Logical Disk For Storage System Virtual Disk
42 = 0x2A Logical Disk Presented
43 = 0x2B Denied On Slave
44 = 0x2C Not DRM Licensed
45 = 0x2D Not DRM Member
46 = 0x2E Invalid DRM Mode
47 = 0x2F Is Copying
48 = 0x30 Login Needed
49 = 0x31 Login Failed
50 = 0x32 Already Logged In
51 = 0x33 Storage System Connection Down
52 = 0x34 Group Empty
53 = 0x35 Incompatible Attribute
54 = 0x36 Is DRM Member
55 = 0x37 Is Log Unit
56 = 0x38 Not Online
57 = 0x39 Not Presented
58 = 0x3A Other Controller Failed
59 = 0x3B Maximum Objects
60 = 0x3C Maximum Size
61 = 0x3D Password Mismatch
62 = 0x3E Is Merging
63 = 0x3F Is Logging
64 = 0x40 Is Suspended
65 = 0x41 Bad Image Header
66 = 0x42 Bad Image
67 = 0x43 Image Too Large
68 = 0x44 EMU Not Available
69 = 0x45 EMU Indefinite Delay
70 = 0x46 Image Incompatible
71 = 0x47 Bad Image Segment
72 = 0x48 Image Already Loaded
73 = 0x49 Image Write Error
74 = 0x4A Logical Disk Sharing
75 = 0x4B Bad Image Size
76 = 0x4C Image Load Busy
77 = 0x4D Volume Failure Predicted
78 = 0x4E Invalid Object Condition
79 = 0x4F Invalid Pred Logical Disk Condition
80 = 0x50 Invalid Volume Usage
81 = 0x51 Minimum Volumes In Disk Group
82 = 0x52 Shutdown In Progress
83 = 0x53 Not Ready
84 = 0x54 Is Snapshot
85 = 0x55 Incompatible Mirror Policy
86 = 0x56 Inoperative
87 = 0x57 Disk Group Inoperative
88 = 0x58 Storage System Inoperative
89 = 0x59 Failsafe Locked
90 = 0x5A Data Flush Incomplete
91 = 0x5B Redundancy Mirrored Inoperative
92 = 0x5C Duplicate LUN
93 = 0x5D Other Remote Controller Failed
94 = 0x5E Unknown Remote Unit
95 = 0x5F Unknown Remote Group
96 = 0x60 PLDMC Failed
97 = 0x61 Storage System Management Interface Lock Failed
98 = 0x62 Remote SCS Error
99 = 0x63 Storage System Connection Up
100 = 0x64 Login Needed Pwd Changed
101 = 0x65 Maximum Logins
102 = 0x66 Invalid Cookie
103 = 0x67 Login Timedout
104 = 0x68 Maximum Snapshot Depth
105 = 0x69 Attribute Mismatch
106 = 0x6A Password Not Set
107 = 0x6B Not Host Port
108 = 0x6C Duplicate LUN WWID
109 = 0x6D System Inoperative
110 = 0x6E Snapclone Active
111 = 0x6F EMU Load Busy
112 = 0x70 Duplicate User Name
113 = 0x71 Drive Reserved For Code Load
114 = 0x72 Already Presented
115 = 0x73 Invalid Remote Storage System
116 = 0x74 No Storage System Management Interface Lock
117 = 0x75 Maximum Members
118 = 0x76 Maximum Destinations
119 = 0x77 Empty User Name
120 = 0x78 Storage System Exists
121 = 0x79 Already Open
122 = 0x7A Session Not Open
123 = 0x7B Not Marked Inoperative
124 = 0x7C Media Not Available
125 = 0x7D Battery System Failed
126 = 0x7E Member Is Cache Data Lost
127 = 0x7F Internal Lock Collision
128 = 0x80 OCP error
129 = 0x81 Mirror temporarily offline
130 = 0x82 Failsafe Mode enabled
131 = 0x83 Drive FW load abort due to Vraid0 Vdisk
132 = 0x84 FC Ports Unavailable
133 = 0x85 Only two remote relations are allowed
134 = 0x86 The requested SRC mode is not possible
135 = 0x87 Src group discarded, but dest group NOT discarded
136 = 0x88 Invalid DRM Group Tunnel specified
137 = 0x89 Specified DRM Log size is too small
138 = 0x8A Invalid DRM Log LDAD specified
139 = 0x8B DRM Group is already read-only
140 = 0x8C DRM Group is already active-active
141 = 0x8D DILX is already running
142 = 0x8E DILX is not running
143 = 0x8F invalid user defined log size
144 = 0x90 Invalid second handle parameter passed to scmi
145 = 0x91 DRM Group already Auto Suspended.
146 = 0x92 Specified option is not implemented yet
147 = 0x93 DRM Group is already present_only
148 = 0x94 The PU NOID is invalid
149 = 0x95 SCS Internal Error
150 = 0x96 Invalid SCS Function Code
151 = 0x97 Unsupported SCS Function Code
152 = 0x98 Init PS Failed
153 = 0x99 Target BAD NOID
154 = 0x9A PStore Is Volume
155 = 0x9B Bad Volume Usage
156 = 0x9C Bad LDAD_Usage
157 = 0x9D No LDAD Handle
158 = 0x9E Bad Quorum Flag
159 = 0x9F SCS U_T_TAG Invalid
160 = 0xA0 SCS U_T_TAG Bad UUID
161 = 0xA1 Too Many PS Tags
162 = 0xA2 Bad Routine
163 = 0xA3 No Tag for NOID
164 = 0xA4 Bad Loop Num
165 = 0xA5 Too Many Port WWNS
166 = 0xA6 Port WWN Not Found
167 = 0xA7 No DU For PU
168 = 0xA8 No SCCL For PU
169 = 0xA9 Unsupported
170 = 0xAA SCS Operation Failed
171 = 0xAB Has Members
172 = 0xAC Incompatible Preferred Mask
173 = 0xAD Too Few Vol Tag
174 = 0xAE ILF Debug Flag Not Set
175 = 0xAF Invalid POID
176 = 0xB0 Too Few Drives
177 = 0xB1 Too Few PS Tags
178 = 0xB2 Unexpected SCS Error
179 = 0xB3 Unsupported Capacity
180 = 0xB4 One or both controllers do not have the required 512MB of memory.
181 = 0xB5 Insuffcient drives of required type to create LDAD
182 = 0xB6 LDAD contains mixed drive types.
183 = 0xB7 Operation already in on state
184 = 0xB8 Operation already in off state
185 = 0xB9 CS$LD_GET_VDISK_INFO failed.
186 = 0xBA No Derived Unit For Storage System Virtual Disk
187 = 0xBB Invalid on mixed DRM configuration
188 = 0xBC Invalid Port number spefified
189 = 0xBD DRM group does not exist
190 = 0xBE Target Object is inoperative
191 = 0xBF A read16 command requested that is unknown.
192 = 0xC0 The controller requested is not A or B
193 = 0xC1 A get special page scsi cmd requested an unknown page.
194 = 0xC2 Cannot set failsafe because async enabled
195 = 0xC3 The Logical Disk is not an empty container/not a mirror clone
196 = 0xC4 The source LD and empty container are in different LDAD's
197 = 0xC5 This operation is not allowed on an empty container
198 = 0xC6 This operation is not allowed in AA mode
199 = 0xC7 The redundancy specified for snap is not allowed
200 = 0xC8 The redundancy in a snapshot tree must be the consistent
201 = 0xC9 No path was found to DR destination
202 = 0xCA Nonexistent group for operation
203 = 0xCB Invalid async log size
204 = 0xCC Generic async log size failure going to async
205 = 0xCD Is not in syncronous mode
206 = 0xCE An instant restore operation is in progress on this LD (or others in tree).
207 = 0xCF The logical disk is a mirror clone
208 = 0xD0 The mirror clone is resyncing
209 = 0xD1 The logical disk has a mirror clone.
210 = 0xD2 Unknown Remote Node
211 = 0xD3 Instant Restore mode incompatible.
212 = 0xD4 The DRM group is not suspended.
213 = 0xD5 The Logical Disks are not in the same snapshot tree
214 = 0xD6 The operation is not allowed on an original Logical Disk.
215 = 0xD7 Recontructing or reverting is in progress in LDAD.
216 = 0xD8 Not enough quorum disks for redundancy to do drive codeload.
217 = 0xD9 The requested operation has already been done.
218 = 0xDA A drive is in maintenance mode.
219 = 0xDB Invalid snapshots are being deleted.
220 = 0xDC Temp Sync Set
221 = 0xDD Maximum instant restores - wait for one to finish.
222 = 0xDE SCELL Not Locked
223 = 0xDF SCELL Lock Busy
224 = 0xE0 DRM Group already set to Defer Copy.
225 = 0xE1 Related operation in set of operations has failed
226 = 0xE2 A Log Shrink is currently in progress
227 = 0xE3 A Log Dealloc is currently in progress
%[fcs_fail]
1 = Excessive exchange timeouts on loop
2 = Excessive link errors on loop
3 = Exhausted Link Down retries on loop with signal
4 = Exhausted Link Down retries on loop with loss of signal
5 = Excessive link inits on loop without completing device
%[scsi_asc_ascq]
0x0000 = No additional sense information
0x0001 = No index/sector signal
0x0002 = No seek complete
0x0003 = Peripheral device write fault
0x0004 = Logical unit not ready, cause not reportable
0x0006 = No reference position found
0x0007 = Multiple peripheral devices selected
0x0008 = Logical unit communication failure
0x0009 = Track following error
0x000A = Error log overflow
0x000C = Write error
0x0010 = Id crc or ecc error
0x0011 = Unrecovered read error
0x0012 = Address mark not found for id field
0x0013 = Address mark not found for data field
0x0014 = Recorded entity not found
0x0015 = Random positioning error
0x0016 = Data synchronization mark error
0x0017 = Recovered data with no error correction applied
0x0018 = Recovered data with error correction applied
0x0019 = Defect list error
0x001A = Parameter list length error
0x001B = Synchronous data transfer error
0x001C = Defect list not found
0x001D = Miscompare during verify operation
0x001E = Recovered id with ecc correction
0x001F = Read Defect command allocated space overflow
0x0020 = Invalid command operation code
0x0021 = Logical block address out of range
0x0022 = Illegal function
0x0022 = Present Only Read Violation
0x0024 = Invalid field in cdb
0x0025 = Logical unit not supported
0x0026 = Invalid field in parameter list
0x0027 = Write protected
0x0028 = Not ready to ready transition, medium may have changed
0x0029 = Power on, reset, or bus device reset occurred
0x002A = Parameters changed
0x002B = Copy cannot execute since host cannot disconnect
0x002C = Command sequence error
0x002D = Overwrite error on update in place
0x002F = Commands cleared by another initiator
0x0030 = Incompatible medium installed
0x0031 = Medium format corrupted
0x0032 = No defect spare location available
0x0033 = Tape length error
0x0035 = Unspecified enclosure services failure
0x0036 = Ribbon, ink, or toner failure
0x0037 = Rounded parameter
0x0039 = Saving parameters not supported
0x003A = Medium not present
0x003B = Sequential positioning error
0x003D = Invalid bits in identify message
0x003E = Logical unit has not self-configured yet
0x003F = Target operating conditions have changed
0x0040 = Ram failure
0x0041 = Data path failure
0x0042 = Power-on or self-test failure
0x0043 = Message error
0x0044 = Internal target failure
0x0045 = Select or reselect failure
0x0046 = Unsuccessful soft reset
0x0047 = SCSI parity error
0x0048 = Initiator detected error message received
0x0049 = Invalid message error
0x004A = Command phase error
0x004B = Data phase error
0x004C = Logical unit failed self-configuration
0x004E = Overlapped commands attempted
0x0050 = Write append error
0x0051 = Erase failure
0x0052 = Cartridge fault
0x0053 = Media load or eject failed
0x0054 = SCSI to host system interface failure
0x0055 = System resource failure
0x0057 = Unable to recover table-of-contents
0x0058 = Generation does not exist
0x0059 = Updated block read
0x005A = Operator request or state change input
0x005B = Log exception
0x005C = Rpl status change
0x005D = Failure prediction threshold exceeded
0x0060 = Lamp failure
0x0061 = Video acquisition error
0x0062 = Scan head positioning error
0x0063 = End of user area encountered on this track
0x0064 = Illegal mode for this track
0x0065 = Voltage fault
0x0080 = Vendor specific.
0x0081 = Reassign power fail recovery failed
0x0100 = Filemark detected
0x0103 = No write current
0x0104 = Logical unit is in process of becoming ready
0x0108 = Logical unit communication time-out
0x0109 = Tracking servo failure
0x010B = Temperature exceeded
0x010C = Recovered data - data auto-reallocated
0x0111 = Read retries exhausted
0x0114 = Record not found
0x0115 = Mechanical positioning error
0x0117 = Recovered data with retries
0x0118 = Recovered data with error correction & retries applied
0x0119 = Defect list not available
0x011C = Primary defect list not found
0x0121 = Invalid element address
0x0126 = Parameter not supported
0x0128 = Import or export element accessed
0x0129 = Power on occurred
0x012A = Mode parameters changed
0x012C = Too many windows specified
0x0130 = Cannot read medium - unknown format
0x0131 = Format command failed
0x0132 = Defect list update failure
0x0135 = Unsupported enclosure function
0x013B = Tape position error at beginning-of-medium
0x013F = Microcode has been changed
0x0140 = DRAM parity error
0x0150 = Write append position error
0x0153 = Unload tape failure
0x0155 = XOR cache not available
0x015A = Operator medium removal request
0x015B = Threshold condition met
0x015C = Spindles synchronized
0x0161 = Unable to acquire video
0x0200 = End-of-partition/medium detected
0x0203 = Excessive write errors
0x0204 = Logical unit not ready, initializing command required
0x0208 = Logical unit communication parity error
0x0209 = Focus servo failure
0x020C = Write error - auto reallocation failed
0x0211 = Error too long to correct
0x0214 = Filemark or setmark not found
0x0215 = Positioning error detected by read of medium
0x0217 = Recovered data with positive head offset
0x0218 = Recovered data - data auto-reallocated
0x0219 = Defect list error in primary list
0x021C = Grown defect list not found
0x0226 = Parameter value invalid
0x0229 = SCSI bus reset occurred
0x022A = Log parameters changed
0x022C = Invalid combination of windows specified
0x0230 = Cannot read medium - incompatible format
0x0235 = Enclosure services unavailable
0x023B = Tape position error at end-of-medium
0x023F = Changed operating definition
0x0240 = DRAM parity error
0x0250 = Position error related to timing
0x0253 = Medium removal prevented
0x025A = Operator selected write protect
0x025B = Log counter at maximum
0x025C = Spindles not synchronized
0x0261 = Out of focus
0x0300 = Setmark detected
0x0304 = Logical unit not ready, manual intervention required
0x0309 = Spindle servo failure
0x030C = Write error - recommend reassignment
0x030E = Invalid Field in Command Information Unit
0x0311 = Multiple read errors
0x0314 = End-of-data not found
0x0315 = End of user area encountered on this track
0x0317 = Recovered data with negative head offset
0x0318 = Recovered data with circ
0x0319 = Defect list error in grown list
0x0326 = Threshold parameters not supported
0x0329 = Bus device reset occurred
0x032A = Reservations Preempted
0x0330 = Cleaning cartridge installed
0x0335 = Enclosure transfer failure
0x033B = Tape or electronic vertical forms unit not ready
0x033F = Inquiry data has changed
0x035A = Operator selected write permit
0x035B = Log list codes exhausted
0x0400 = Beginning-of-partition/medium detected
0x0404 = Logical unit not ready, format in progress
0x0409 = Head Select Fault
0x0411 = Unrecovered read error - auto reallocate failed
0x0414 = Block sequence error
0x0417 = Recovered data with retries and/or circ applied
0x0418 = Recovered data with lec
0x0426 = Invalid release of persistent reservation
0x0429 = Internal reset
0x042A = Reservations Released
0x0435 = Enclosure transfer refused
0x043B = Slew failure
0x045D = exceeded -- disk reassign DST table
0x0500 = End-of-data detected
0x0511 = L-ec uncorrectable error
0x0517 = Recovered data using previous sector id
0x0518 = Recovered data - recommend reassignment
0x052A = Registrations preempted
0x053B = Paper jam
0x053F = Device identifier changed
0x053f = Device identifier has changed
0x055D = exceeded -- disk reassign AST table
0x0600 = I/O process terminated
0x0611 = Circ unrecovered error
0x0617 = Recovered data without ecc - data auto-reallocated
0x0618 = Recovered data - recommend rewrite
0x062A = Asymmetric access state changed
0x063B = Failed to sense top-of-form
0x065D = exceeded -- disk reassign DDT table
0x0711 = Data resynchronization error
0x0717 = Recovered data without ecc - recommend reassignment
0x0718 = Recovered data - data rewritten
0x072A = Asymmetric access state transition failed
0x073B = Failed to sense bottom-of-form
0x0811 = Incomplete block read
0x0817 = Recovered data without ecc - recommend rewrite
0x083B = Reposition error
0x0911 = No gap found
0x092A = Capacity data changed
0x093B = Read past end of medium
0x0A11 = Miscorrected error
0x0A3B = Read past beginning of medium
0x0B11 = Unrecovered read error - recommend reassignment
0x0B3B = Position past end of medium
0x0C11 = Unrecovered read error - recommend rewrite the data
0x0C3B = Position past beginning of medium
0x0D3B = Medium destination element full
0x0E19 = Defect list error -- fewer than 50% defect list copies
0x0E3B = Medium source element empty
0x0E3F = Reported LUNs data has changed
0x1100 = Audio play operation in progress
0x1200 = Audio play operation paused
0x1300 = Audio play operation successfully completed
0x1400 = Audio play operation stopped due to error
0x1500 = No current audio status to return
0x315D = Failure prediction threshold exceeded -- head failure
0x325D = Failure prediction threshold exceeded -- recovered data error rate
0x375D = Failure prediction threshold exceeded -- recovered TA
0x385D = Failure prediction threshold exceeded -- hard TA event
0x415D = Failure prediction threshold exceeded -- SSE DPF smoothing
0x435D = Failure prediction threshold exceeded -- seek DPF smoothing
0x455D = Failure prediction threshold exceeded -- track following errors
0x5B5D = Failure prediction threshold exceeded -- spinup DFP smoothing
0x803F = Read after write buffer contents changed
0x8047 = Fibre Channel Sequence Error -- frame not received by E_D_TOV
0x8080 = FC FIFO error during read transfer
0x8180 = FC FIFO error during write transfer
0x8280 = DISC FIFO error during read transfer
0x8380 = DISC FIFO error during write transfer
0x8480 = LBA seeded LRC error on read
0x8580 = LBA seeded LRC error on write
0x8603 = Write error - recommend reassignment
0x8680 = IOEDC error on read
0x8780 = IOEDC error on write
0x903F = Invalid CAP block -- servo Flash SAP HDA serial number does not match the ETF SAP HDA serial number
0x9131 = Format corrupted World Wide Name invalid
0x913F = World Wide Name mismatch
0x9726 = Invalid field parameter -- TMS firmware tag
0x9826 = Invalid field parameter -- check sum
0x9926 = Invalid field parameter -- firmware tag
0xEE5D = Failure prediction threshold exceeded -- no control table on disk
0xFF5D = False failure prediction threshold exceeded
%[scsi_sensekey]
0x0 = NO SENSE
0x1 = RECOVERED ERROR
0x2 = NOT READY
0x3 = MEDIUM ERROR
0x4 = HARDWARE ERROR
0x5 = ILLEGAL REQUEST
0x6 = UNIT ATTENTION
0x7 = DATA PROTECT
0x8 = BLANK CHECK
0x9 = Vendor Specific
0xA = COPY ABORTED
0xB = ABORTED COMMAND
0xC = EQUAL
0xD = VOLUME OVERFLOW
0xE = MISCOMPARE
0xF = RESERVED
%[scsi_cmds]
0x00 = TEST UNIT READY
0x01 = REZERO UNIT
0x03 = REQUEST SENSE
0x04 = FORMAT UNIT
0x07 = REASSIGN BLOCKS
0x08 = READ (6 byte)
0x0A = WRITE (6 byte)
0x0B = SEEK (6 byte)
0x12 = INQUIRY
0x14 = RECOVER BUFFERED DATA
0x15 = MODE SELECT (6 byte)
0x16 = RESERVE UNIT
0x17 = RELEASE UNIT
0x18 = COPY
0x1A = MODE SENSE (6 byte)
0x1B = START STOP UNIT
0x1C = RECEIVE DIAGNOSTIC RESULTS
0x1D = SEND DIAGNOSTIC
0x1E = PREVENT-ALLOW MEDIUM REMOVAL
0x25 = READ CAPACITY
0x28 = READ (10 byte)
0x2A = WRITE (10 byte)
0x2B = SEEK (10 byte)
0x2E = WRITE AND VERIFY (10 byte)
0x2F = VERIFY (10 byte)
0x30 = SEARCH DATA HIGH (10 byte)
0x31 = SEARCH DATA EQUAL (10 byte)
0x32 = SEARCH DATA LOW (10 byte)
0x33 = SET LIMITS (10 byte)
0x34 = PRE-FETCH
0x35 = SYNCHRONIZE CACHE
0x36 = LOCK-UNLOCK CACHE
0x37 = READ DEFECT DATA (10 byte)
0x38 = MEDIUM SCAN
0x39 = COMPARE
0x3A = COPY AND VERIFY
0x3B = WRITE BUFFER
0x3C = READ BUFFER
0x3E = READ LONG
0x3F = WRITE LONG
0x40 = CHANGE DEFINITION
0x41 = WRITE SAME
0x4C = LOG SELECT
0x4D = LOG SENSE
0x50 = XDWRITE (10 bytes)
0x51 = XPWRITE (10 bytes)
0x52 = XDREAD (10 bytes)
0x55 = MODE SELECT (10 byte)
0x56 = SCSI-3 SPC p.70
0x57 = SCSI-3 SPC p.88
0x5A = MODE SENSE (10 byte)
0x5E = PERSISTENT RESERVE IN
0x5F = PERSISTENT RESERVE OUT
0x81 = REBUILD
0x82 = REGENERATE
0x88 = READ (16 byte)
0x8A = WRITE (16 byte)
0x9E = READ CAPACITY (Jumbo Version)
0xA0 = REPORT LUNS
0xA8 = READ (12 byte)
0xAA = WRITE (12 byte)
0xAE = WRITE AND VERIFY (12 byte)
0xAF = VERIFY (12 byte)
0xB0 = SEARCH DATA HIGH (12 byte)
0xB1 = SEARCH DATA EQUAL (12 byte)
0xB2 = SEARCH DATA LOW (12 byte)
0xB3 = SET LIMITS (12 byte)
0xEB = WRITE ID
0xEC = REPORT ID
%[els_codes]
0x01 = Link service reject
0x02 = Accept
0x03 = N_Port login
0x04 = F_port login
0x05 = Logout
0x06 = Abort exchange
0x07 = Read connection status
0x08 = Read exchange status block
0x09 = Read sequence status block
0x0A = Read sequence initiative
0x0B = Establish streaming
0x0C = Estimate credit
0x0D = Advise credit
0x0E = Read timeout value
0x0F = Read link status
0x10 = Echo
0x11 = Test
0x12 = Reinstate recovery qualifier
0x13 = Read Exchange Concise
0x20 = Process login
0x21 = Process logout
0x22 = State change notification
0x23 = Test process login state
0x24 = Third party process logout
0x25 = Login Control List Management
0x30 = Get alias id
0x31 = Fabric activate alias id
0x32 = Fabric deactivate alias id
0x33 = N_Port activate alias id
0x34 = N_Port deactivate alias id
0x40 = Quality of service request
0x41 = Read virtual circuit status
0x50 = Discover N_Port service parms
0x51 = Discover F_Port service parms
0x52 = Discover address
0x53 = Report Node Capabilites
0x56 = Read Port Status Block
0x57 = Read Port List
0x58 = Bandwidth Allocation
0x59 = Bandwidth DeAllocation
0x60 = Fabric Address Notification
0x61 = Registered State Change Notification
0x62 = State Change Registration
0x63 = Report Node FC-4 Types
0x68 = Clock Sync Request
0x69 = Clock Sync Update
0x70 = Loop Initialize
0x71 = Loop Port Control
0x72 = Loop Status
0x77 = Request Topology Information
0x78 = Request Node Identification Information
0x79 = Registered Link Incident Record
0x7A = Link Incident Record Registration
0xF0 = Vendor Unique - SCS message
%[fm_terminate_routines]
0 = FM_TERMINATE_START
1 = FM_TERMINATE_PREP1
2 = FM_TERMINATE_LOAD_LTE_GLUE_REGS
3 = FM_TERMINATE_PREP2
4 = FM_TERMINATE_LOAD_LTE_INFO
5 = FM_TERMINATE_LOAD_LTE_POLMEMCTRLR_REGS
6 = FM_TERMINATE_LOAD_LTE_CACMEMCTRLR_REGS
7 = FM_TERMINATE_LOAD_LTE_TACHYON0_REGS
8 = FM_TERMINATE_LOAD_LTE_TACHYON1_REGS
9 = FM_TERMINATE_LOAD_LTE_TACHYON2_REGS
10 = FM_TERMINATE_LOAD_LTE_TACHYON3_REGS
11 = FM_TERMINATE_LOAD_LTE_TACHYON4_REGS
12 = FM_TERMINATE_LOAD_LTE_TACHYON5_REGS
13 = FM_TERMINATE_LOAD_LTE_TACHYON6_REGS
14 = FM_TERMINATE_LOAD_LTE_TACHYON7_REGS
15 = FM_TERMINATE_LOAD_LTE_TACHYON8_REGS
16 = FM_TERMINATE_LOAD_LTE_TACHYON9_REGS
17 = FM_TERMINATE_LOAD_LTE_TOY_REGS
18 = FM_TERMINATE_LOAD_LTE_UART1_REGS
19 = FM_TERMINATE_LOAD_LTE_UART2_REGS
20 = FM_TERMINATE_LOAD_LTE_UART3_REGS
21 = FM_TERMINATE_LOAD_LTE_UART4_REGS
22 = FM_TERMINATE_DECODER_REGS
23 = FM_TERMINATE_EXPANSION6
24 = FM_TERMINATE_EXPANSION7
25 = FM_TERMINATE_EXPANSION8
26 = FM_TERMINATE_CBIC_TALK_OFF
27 = FM_TERMINATE_DECODE_MACHINE_CHECK
28 = FM_TERMINATE_PRESERVE_EVENTS
29 = FM_TERMINATE_SEND_LAST_GASP
30 = FM_TERMINATE_CRASH_DUMP_PREP
31 = FM_TERMINATE_CRASH_DUMP
32 = FM_TERMINATE_COMPUTE_LTE_EDC
33 = FM_TERMINATE_RESTART_INIT
34 = FM_TERMINATE_RESTART_ACTION
35 = FM_TERMINATE_END
%[fm_ue]
0 = Unrecognized Unexpected Event code
1 = Power failure before initialization could complete
2 = Recursive termination before initialization could complete
3 = Terminated during the first part post-termination preparation
4 = Terminated during the load of the G3 Glue registers
5 = Terminated during the second part post-termination preparation
6 = Terminated during event report block load
7 = Terminated during initialization of all hardware components and software data structures in preparation for restart
8 = Terminated during execution of an unrecognized post-termination operation (premature)
9 = Power failure during execution of a post-termination operation
10 = No good entries found in Termination Event Array. (Note that this condition is expected following the first boot of a newly manufactured HSV210 controller. In that case this event can be safely ignored; no action is necessary.)
11 = The edc of one or more Last Termination Event Array entries is bad
12 = Last Termination Event Array entry control block revision is different
13 = Last Termination Event Array entry information block revision is different
14 = Last Termination Event Array entry up time value is greater than the system's up time value
15 = Last Termination Event Array entry up time value is less than the previous entry's up time value
16 = Last Termination Event Array entry sequence number value is less than the previous entry's sequence number value
17 = Detected an unrecognized dump/restart control code
18 = Failed to terminate the entity dump loop
19 = Unexpected dump entity size
20 = Unexpected elp processing stage code
21 = Number of Termination Parameters supplied not equal to maximum allowed as required
22 = Detected an unexpected address map companion block control code
23 = Original TP[0] value replaced by DIMM size load
24 = Unexpected meal commit stage code
%[fm_mpvfc]
0 = Success
1 = Cookie value is not as expected
2 = Event data overflows the buffer
3 = Event data size is not a multiple of 4 bytes, is less than the minimum, or is greater than the maximum
4 = Event Information Packet type is greater than the maximum
5 = Event information size is not a multiple of 4 bytes, is less than the minimum, is greater than the maximum, doesn't match the eip type size, or when combined with the entry header size doesn't equal the entry size
6 = Event code is zero
7 = Event is out of sequence (0)
8 = Dead space area at the end of a partially packed buffer contains a nonzero value
9 = An event data block containing a nonzero value was found after end of event data was detected
10 = Sequence number reset flag not set as expected
11 = The event log contains no entries
12 = Event data block read failed during maintenance verification
13 = Event data block read failed during maintenance completion
14 = Event data block erase failed during maintenance completion
15 = Control block read failed during maintenance verification
16 = Control block write failed during maintenance verification
17 = Event data block write failed during maintenance update
18 = Control block write failed during maintenance completion
19 = Storage System Termination Event Log related send was unsuccessful or the master found that the Storage System Termination Event Log is inaccessible
20 = Control block read failed during maintenance verification by the other HSV210 controller
21 = Control block read failed during update retrieval
22 = Event data block read failed during retrieval request
23 = Log has been prepared for re-initialization
24 = Event is out of sequence (1)
25 = Event is out of sequence (2)
26 = Event is out of sequence (3)
%[fm_quiesce]
0 = Make FM quiescent on both controllers
1 = Make FM quiescent on slave controller only
%[rcse]
0 = Requested by Storage System Management Interface use image
1 = Requested by CTRL_F
2 = Requested by Storage System Management Interface, shutdown
3 = Emergency drive firmware upgrade
4 = Emergency drive firmware upgrade done
5 = Attempt to check new device for System WWN
6 = Existing cell lost quorum
7 = Quorum disks have changed in existing cell
8 = An active cell has lost its quorum
9 = WWN has been found on new quorum
10 = ID has changed on a physical store
11 = System has been scrubbed
12 = Logged in port for ILF cannot be found
13 = The ILF disk is no longer logged in
14 = The ILF id block failed to write
15 = Scrub requested from OCP
16 = The system Disk Group changed
17 = An attempt to realize a logical disk failed
18 = The master crashed during a resync recovery window
19 = The master crashed during a resync window with no cell
20 = The slave failed before returning status of an unshare
21 = An operation to get a cmap failed
22 = A CVMDB access failed
23 = A cache metadata i/o failed
24 = An initiate logical disk expand failed
25 = An attempt to take a logical disk online failed
26 = A flush unit operation failed on the slave
27 = Recovery to handle too much frozen data
28 = An attempt to take a logical disk offline failed
29 = An attempt to unrealize a logical disk failed
30 = An attempt to update the RSSM on media failed
31 = Container Services failed to initiate a merge operation
32 = A new WWN was entered on the OCP
33 = Deadlock avoidance for drive code load
34 = A drive appeared while the system was inoperative
35 = A drive has failed a BBR check
36 = A drive has appeared which may fix a multi disk failure
37 = A failure was detected during hierarchy lookup
38 = A virtual disk could not be presented
39 = Quorum disk could not be found after a failover
40 = An attempt to realize the csld failed
41 = A storage cell went undetected during realization
42 = Quorum was lost during cell realization
43 = A drive disappeared during cell realization
44 = Cell realization failed but device discovery will not complete
45 = An attempt to realize the scscb failed
46 = A snapshot or snapclone tree was split across the master and slave
47 = A reduced quorum set was reconstructed
48 = A migration operation initiation failed
49 = An attempt to delete a logical disk failed
50 = An attempt to take a logical disk offline other failed
51 = An attempt to synch the mirror for a logical disk failed
52 = Container Services failed to initiate a split operation
53 = A virtual disk could not be unpresented
54 = An attempt to take a unit operative failed
55 = Debug flags are being committed
56 = Requested by the OCP
57 = DRM went offline
58 = DRM went offline with writes in progress
59 = A memory allocation failed
60 = A loop initiator disruptor drive was bypassed
61 = ID blocks on a drive were erased
62 = An attempt to realize the PLDMC failed
63 = A logical disk in an inoperative Disk Group was expected to be inoperative but was not
64 = An unshare operation failed
65 = An rss member failed during cell realization
66 = A Disk Group has become RAID 1 inoperative
67 = Requested by maintenance or SCS debug command
68 = A confirmation was refused on the OCP
69 = A confirmation was approved on the OCP
70 = An attempt to unmirror a logical disk failed
71 = An attempt to quiesce a unit failed
72 = Container Services failed to add a Disk Group
73 = Container Services failed to delete a Disk Group
74 = Print flags have changed
75 = Debug flags have changed
76 = The master failed while trying to get information from it
77 = An attempt to erase quorum failed
78 = An attempt to copy psars failed
79 = Container Services failed to initiate a marry operation
80 = An attempt to update or init rss meta failed so an attempt was made to fault a drive
81 = A system inoperative controller was activated by the master indicating that inoperative condition was fixed
82 = A drive has unexpectedly changed its worldwide name
83 = A drive has unexpectedly changed its worldwide name
84 = PRLI handler detected other controller reboot
85 = host port topology change detected
86 = Slave failed during staggered code load, so reboot now
87 = The configuration changed while the system was inoperative
88 = I/O commited, log inop so no place to put it, so reboot now
89 = About to write an ID block, but drive pointer changed
90 = Enter safe mode
91 = The slave failed before returning status of a mirrorclone resync
92 = Starting a mirror clone resync failed
93 = Couldn't clear the ldrm to finish fracture
94 = Starting a mirror clone fracture failed
95 = The slave failed before returning status of an instant restore
96 = Completing a LD restore failed
97 = Couldn't clear the ldrm to finish detach
98 = Starting a mirror clone detach failed
99 = Scrub requested from SCMI
100 = Scrub requested from CONSOLE
101 = Starting a lun shrink failed
256 = Active/Active write collision
257 = Trying to close tunnel with outstanding qsce operation
%[drv_inop]
0x0 = Unknown
0x001 = Container Services I/O failure
0x002 = Scrubber I/O failure
0x003 = Attempt to set CBIT on normal drive
0x004 = Attempt to set CBIT on merging drive
0x100 = Target Discovery Service Descriptor retry count exceeded
0x101 = Inoperable for Bad Block Replacement
0x102 = Soft error count exceeded
0x103 = Exchange timeout count exceeded
0x104 = Drive communication failure count exceeded
0x105 = Command retries exceeded
0x106 = Medium/Hardware Errors encountered on this physical disk drive
0x107 = Directed LIP threshold exceeded
0x108 = Transport error count threshold exceeded
0x109 = The user intentionally added this drive to the DSL
0x200 = Smart event from a physical disk drive not in Storage System
0x201 = Smart event from a physical disk drive not a Volume
0x202 = Smart event from a physical disk drive not a Redundant Storage Set
0x203 = Failure predicted from physical disk drive
0x204 = Cannot read from physical disk drive from the poll
0x205 = Failure predicted from physical disk drive while deleting Disk Group
0x206 = physical disk drive forced inoperative from maintenence command for temporary POID
0x207 = physical disk drive forced inoperative from maintenence command for POID
0x208 = Bad block recovery failed or cannot read FPAB
0x209 = Failure to remove volume from Storage System
0x20a = Failure to update metadata
0x20b = Failure to update metadata - physical disk drive is missing - will NOT be marked inoperable
0x210 = About to write ID block 0 to wrong physical disk drive
0x211 = About to write ID blocks to wrong physical disk drive
0x212 = About to write ID block 2 to wrong physical disk drive
0x213 = About to write ID blocks after retry to wrong physical disk drive
%[fcs_mtl]
1 = The physical disk drive left itself bypassed
2 = The Drive Enclosure Environmental Monitoring Unit bypassed the drive bay
%[cac_mnemonic]
0x00 = CAC_NO_ACTION
0x01 = CAC_NOTIFY_FUSION_DEV
0x02 = CAC_NOTIFY_OPSYS
0x03 = CAC_SEE_TC
0x04 = CAC_TC_RECURSED
0x05 = CAC_SEE_OTC
0x06 = CAC_SEE_ASSOC_TEVENT
0x07 = CAC_ADVISEW_FUSION_DEV
0x08 = CAC_ADVISEI_FUSION_DEV
0x09 = CAC_DETERMINE_PFC
0x0a = CAC_LOW_MEM_ACC_ADVICE
0x0b = CAC_GLUE_POWEROFF
0x20 = CAC_REPLACE_CB
0x22 = CAC_REPLACE_BATTA
0x23 = CAC_REPLACE_BATTB
0x24 = CAC_REPLACE_BLOWERA
0x25 = CAC_REPLACE_BLOWERB
0x26 = CAC_REPLACE_BLOWERPSA
0x27 = CAC_REPLACE_BLOWERPSB
0x28 = CAC_REP_REMOVED_BATTA
0x29 = CAC_REP_REMOVED_BATTB
0x2a = CAC_REP_REMOVED_BLWRA
0x2b = CAC_REP_REMOVED_BLWRB
0x2c = CAC_REP_REMOVED_BLWRPSA
0x2d = CAC_REP_REMOVED_BLWRPSB
0x2e = CAC_REDUCE_AMBIENT
0x2f = CAC_CHECK_BATTS
0x30 = CAC_GBIC_CHECK_FAILURE
0x36 = CAC_OVER_TEMP
0x37 = CAC_TEMP_UNDETERMINED
0x38 = CAC_REPLACE_BATTCAUTION
0x39 = CAC_RECUR_REPLACE_CB
0x3a = CAC_GBIC_NOT_PRESENT
0x3b = CAC_SRAM_TEST_ERROR
0x40 = CAC_REPLACE_DRIVE
0x41 = CAC_REP_REMOVED_DRIVE
0x42 = CAC_REMOVE_REPLACE_DRIVE
0x43 = CAC_MOVE_DRIVE
0x44 = CAC_PORT_FAILURE
0x46 = CAC_REPLACE_DRIVE_PORT
0x47 = CAC_FRAME_TIMEOUT
0x48 = CAC_UNEXPECTED_WORK
0x49 = CAC_BAD_ALPA
0x4a = CAC_LINK_FAILURE
0x4c = CAC_SPOF_DRIVE
0x4d = CAC_UPDATE_DRIVE_FW
0x4e = CAC_SPOF_SHELF
0x4f = CAC_REMOVE_DRIVE
0x50 = CAC_DELSCLD
0x51 = CAC_EVAL_LD
0x52 = CAC_IRDEL_LD
0x5f = CAC_CHECK_CONN
0x60 = CAC_CHECK_SRC_UNIT
0x61 = CAC_CHECK_DEST_UNIT
0x62 = CAC_CHECK_LOG
0x63 = CAC_CHECK_SITE_VERSIONS
0x64 = CAC_DRM_CHECK_REM_BACKEND
0x65 = CAC_DRM_RESTART_REM
0x66 = CAC_DRM_RESTART_LOCAL
0x67 = CAC_DRM_CHECK_ISL
0x68 = CAC_DRM_CHECK_RMTNODES
0x69 = CAC_DRM_CHECK_ISL_SWITCH
0x80 = CAC_REMOVE_REPLACE_DEPS
0x81 = CAC_REPLACE_DEPS
0x82 = CAC_REMOVE_REPLACE_DEBLWR
0x83 = CAC_REPLACE_DEBLWR
0x84 = CAC_REPLACE_DEBLWR_IMM
0x85 = CAC_DE_CTRLR_SHUTDN
0x86 = CAC_CORRECT_TEMP
0x87 = CAC_CORRECT_TEMP_IMM
0x88 = CAC_RESET_DEEMU
0x89 = CAC_REPLACE_DEEMU
0x8a = CAC_AUTOREC_DEEMU
0x8b = CAC_RECOVER_DEEMU_COMBO
0x8c = CAC_AUTOREC_COMBO_DEEMU
0x8d = CAC_DE_INITIALIZE
0x8e = CAC_DE_JB_TROUBLE
0x8f = CAC_DEMU_DISCOPS
0x90 = CAC_DE_CHECK_XCVR
0x91 = CAC_REPLACE_DE
0x92 = CAC_AUTOREC_DE
0x93 = CAC_REPLACE_DEIOM
0x94 = CAC_AUTOREC_DEIOM
0x95 = CAC_RESET_DEIOM
0x96 = CAC_UPLOAD_DEEMU_NEW_CODE
0x97 = CAC_CABINET_BUS_CABLE
0x98 = CAC_REDUCE_DE
0x99 = CAC_CHECK_DEIOM_CABLE
0x9a = CAC_CHECK_RACK_PDU
0x9b = CAC_MONITOR_DEEMU
0x9c = CAC_CYCLE_DRIVE_EMU
0xb4 = CAC_CHANGE_OCCUPANCY
0xb5 = CAC_CHANGE_LDAD_CONFIG
0xb6 = CAC_RESTORE_SPOFRC
0xb9 = CAC_EVAL_OTHER_NSC
0xba = CAC_EVAL_PWR_OTHER_NSC
0xbf = CAC_EVAL_VOL
0xc3 = CAC_EVAL_PORT
0xc4 = CAC_NEW_DRIVE_FW
0xc5 = CAC_CAB_BUS_CABLE
0xc8 = CAC_REPLACE_BATT0
0xc9 = CAC_REPLACE_BATT1
0xca = CAC_REPLACE_BATT2
0xcb = CAC_REPLACE_BATT3
0xcc = CAC_REP_REMOVED_BATT0
0xcd = CAC_REP_REMOVED_BATT1
0xce = CAC_REP_REMOVED_BATT2
0xcf = CAC_REP_REMOVED_BATT3
0xd0 = CAC_CHECK_BATTS_XL
0xd1 = CAC_REPLACE_BATTCAUTION_XL
0xd2 = CAC_REPLACE_BLOWER0
0xd3 = CAC_REPLACE_BLOWER1
0xd4 = CAC_REP_REMOVED_BLWR0
0xd5 = CAC_REP_REMOVED_BLWR1
0xd6 = CAC_CHECK_REPLACE_PS0
0xd7 = CAC_CHECK_REPLACE_PS1
0xd8 = CAC_REP_REMOVED_PS0
0xd9 = CAC_REP_REMOVED_PS1
0xda = CAC_CHECK_BATT_COMM
0xdb = CAC_MISMATCH_CODE
%[storage_usage]
0 = Unallocated
1 = Quorum Space
2 = CSLD Logical Data
3 = Primary Logical Disk
4 = Primary LD Metadata
5 = LD Base RSD (LDDIR)
6 = Physical Metadata
7 = DRM LOG OD storage
8 = Supported USAGE Types
%[exec_tod]
1 = TOY clock unavailable, this controller's time reset to default
2 = TOY clock time is less than previously stored time, this controller's time reset to default
3 = Bad EDC for previously stored time, this controller's time reset to default
4 = TOY clock not running, this controller's time reset to default
5 = TOY clock is accurate, this controller's time set to TOY clock time value
6 = This controller's time was set from policy memory metadata following a controller resynchronization operation
7 = This controller's time was set to the current time value
8 = Following Storage System time synchronization the primary controller requested that the secondary controller set its TOY clock to the current time value
9 = The secondary controller set its TOY clock to the current time value as requested by the primary controller
10 = This controller's TOY clock was set to the current time value
STRUCTURE REVISION LEVELS:
eip01: 3.
eip02: 3.
eip03: 5.
eip04: 6.
eip05: 4.
eip07: 1.
eip08: 3.
eip09: 5.
eip0A: 2.
eip0B: 4.
eip0C: 4.
eip0D: 1.
eip0E: 3.
eip0F: 2.
eip10: 0.
eip11: 3.
eip12: 2.
eip13: 5.
eip14: 2.
eip15: 0.
eip16: 0.
eip17: 1.
eip18: 0.
eip19: 0.
eip1A: 0.
eip1B: 1.
eip1C: 1.
eip1D: 0.
eip1E: 1.
eip1F: 0.
eip20: 0.
eip21: 0.
elp_event: 2.
lte_control_block: 1.
lte_info_block: 255.
MAPPING INFORMATION:
00030000 00000010 6ccb094c7e783b4a5abf4358
00030010 00000028 6ccb094c7e70314751b341
00030038 0000005c 6ccb094c7e63304e41b65556c0bb
00030094 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
0003009c 00000018 5bf63f6054431666518d7f67fa9eba12bd81ca55f9
000300b4 00000030 5bf63f6054431666518d7f67fa9eba12
000300e4 0000015c 4df5136c404101767c854f61fc99a1139689d0
00030240 0000002c 6dd5137f535e16667d93
0003026c 00000178 6dd51c50544111627a854f4dc1a78a149786ca59e14cf25efb9f
000303e4 000000ac 4df53c50485f1c775190757bf5b5a614839cd7
00030490 000001a0 6dd513664f5801
00030630 00000fdc 4df53c504052167663957c68e78f8a10879ac263fe67f74bfc
0003160c 00000068 4df53c50425d10627cbf666dfa99be3f919cc548fe
00031674 000001d0 4df5136c4e5d19666d94
00031844 00000084 6dd51369405a105c6d9262
000318c8 00001370 4df53c504250196051837f64f183bb0586b7d748ec67e5
00032c38 0000011c 6dd5137c5550016a7d94796ae0
00032d54 00000144 4df5137544431a5c6d8f7c65f689a1
00032e98 00000218 4df5136c4e5d19666d947f7b
000330b0 00000100 4df53c505244185c6d8c6256e798b005bd9cd65de360c95ce18aa9
000331b0 0000012c 4df53c505244185c6d8c6256f498a53f969ac552fe4cf551fb8d
000332dc 000000dc 4df53c504447146f51946268fd998a038c9cd7
000333b8 000000a4 4df53c50544111627a854f7de18bbb138b9ccd53e34cf550fa90ae21
0003345c 000000a4 4df5136c53402a626d8b
00033500 00000138 4df5136c53402a617b897c6d
00033638 00000068 4df5136c53432a626d8b
000336a0 00000138 4df5136c53432a617b897c6d
000337d8 000000f4 4df5137a52422a626d8b
000338cc 00000160 4df5137a52422a617b897c6d
00033a2c 000000f4 4df5137952422a626d8b
00033b20 000010b0 4df513624842165c63867356e398ba03879bd7
00034bd0 00000110 4df5137952422a617b897c6d
00034ce0 00000068 6dd5137d566e11776a
00034d48 0000003c 6dd5137d566e13666a
00034d84 0000003c 6dd5137d566e19716c
00034dc0 0000003c 6dd5137d566e1870698c
00034dfc 0000005c 6dd5137d566e0766638f666c
00034e58 0000003c 6dd5137d566e0670698c
00034e94 0000003c 6dd5137d566e0d67
00034ed0 0000003c 6dd5137d566e1b756c
00034f0c 0000003c 6dd5137d566e066d6f904f6afc9aac
00034f48 00000068 6dd5137d545f2a737c8f736ce0998a0e8d9f
00035008 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
00035010 00000924 4df5137d566e166b6b837b
00035934 00000178 4df53c
00035aac 00000068 4df53c5053441b5c7e927f6af699a63f8c87d3
00035b14 000000a0 6dd51c50515e067751977f7bf8
00035bb4 0000002c 6dd51c505044105c7d996356f289a1099481d045d270f74ffb8ba837
00035be0 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
00035be8 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
00035bf0 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
000385a0 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
000385a8 00000028 4afc226948562a747c89646c
000385d0 00000028 4afc226948562a716b8174
000385f8 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
00038600 0000010c 44f6216c5148
0003870c 00000128 44f621624e4710
00038834 0000018c 44f6217c4445
000389c0 00000028 4be9297d4e
000389e8 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
000389f0 000000ac 4ae7236e
00038a9c 0000011c 4ae7236e1705
00038bb8 00000578 4dfc13694e4318627a
00039130 00000130 59e125615557
00039260 00000064 5ae33e664f4513
000392c4 00000034 59e6386c495007
000392f8 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
00039300 000000b8 4afc227c4e5d105c678e797d
000393b8 00000014 4afc227c4e5d105c7e8f7c65
000393cc 000000c0 4afc227c4e5d105c7c85716d
0003948c 00000004 4afc227c4e5d105c7c85716dcc8cb9159180
00039490 00000244 4afc227c4e5d105c7992797df6
000396d4 000000f4 4afc227c4e5d105c7992797df6b5b30c979bcc
000397c8 00000030 4afc227c4e5d105c7d956379f684b1
000397f8 00000078 4afc227c4e5d105c6d8f7e7ae687b03f839bdd52ee4cf557ee8ca9
00039870 00000020 4afc227c4e5d105c6f847456e398b0068b90
000398b8 00000000 76cc3a6e7e500764
00039a10 00000101 76f0387651542a
00039b14 00000028 6ccb094c7e66344a5abf4440deaf91
00039b3c 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
00039b44 00000070 46f03c5040521e
00039bb4 000002e0 46f03c50485f1c77
00039e94 00000070 46f03c5052541b6751897e7dcc9eba3f8a86c050ff
00039f04 00000068 46f03c50484207
00039f6c 00000e6c 66d01c506577
0003add8 00000410 46f03c50485f015c668e7465e1
0003b63c 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
0003b644 00000004 40fd257b7e5e16735194716bff8fa6
0003c630 00000028 6ccb094c7e66344a5abf4440deaf91
0003c658 00000008 43e63f7b7e421c6f62994f6ffc988a038d85d455e176e460f89fa83cb9217e0f
0003c660 00000030 40fa2f504e52055c7d857e6dcc89ba0d8f89ca58
0003c690 000000b4 40fa2f504e52055c7992797df6b5a501858d
0003c744 000000b4 40fa2f504e52055c7c85716dcc9ab40787
0003c7f8 00000088 46f03c505144015c6a816468cc9ab40787
0003c880 00000024 46f03c505144015c6a816468cc9ab40787b7c645f976e5
0003c8a4 0000002c 46f03c504654015c6a816468cc9ab40787
0003c8d0 00000024 46f03c504654015c6a816468cc9ab40787b7c645f976e5
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003f0840 00000058 4dfa2d687e5c1c6d6a994f64fc84bc148d9a
003f0898 00000028 4afc227c4e5d105c61956465fa84b03f969b
003f3cf4 00000028 5ae73e6c4943
003f3d1c 0000005c 5ae73e7d425907
Download Driver Pack
After your driver has been downloaded, follow these simple steps to install it.
Expand the archive file (if the download file is in zip or rar format).
If the expanded file has an .exe extension, double click it and follow the installation instructions.
Otherwise, open Device Manager by right-clicking the Start menu and selecting Device Manager.
Find the device and model you want to update in the device list.
Double-click on it to open the Properties dialog box.
From the Properties dialog box, select the Driver tab.
Click the Update Driver button, then follow the instructions.
Very important: You must reboot your system to ensure that any driver updates have taken effect.
For more help, visit our Driver Support section for step-by-step videos on how to install drivers for every file type.