1. server_driver_lan_b_cm5751_7_7_4.exe Driver
2. RELEASE.TXT File Contents

RELEASE.TXT Driver File Contents (server_driver_lan_b_cm5751_7_7_4.exe)

                     Release Note for BCM5704S BOOT Code Firmware
                    ==================================================
Version 3.23: 

  1. Writes firmware id to shared memory rx_cpu_firmware_id field
  
    Enhancement:
      Phase1 & Phase2 code will write the firmware id to rx_cpu_firmware_id.
      
    Eng. Notes:
      bootcode phase1 will write value 0xfefe0008 to shared memory 0xc0c.
      bootcode phase2 will write value 0xfefe0009 to shared memory 0xc0c.
      When phase2 executes properly, the value phase1 wrote should be
      overwritten by phase2 code.  
      
Version 3.22: 

  1. Not to set bit 27 of MacCtrl.SerdesCfg
  
    Problem:
      bit 27 was set for secondary device
  
    Cause:
      For secondary device bit 27 of MacCtrl.SerdesCfg should not be set
      where the primary device needed to be set. The older bootcode was setting
      both devices unconditionally.
      
    Fix: 
      Added device check and only set for primary device
      
  2. Restored phy type in manufacture data block
  
    Problem: 
      PXE code needed this field to determine the phy type
    
    Fix: 
      Hard coded this field to be fiber type
                     

Version 3.21:

  1. Fixed revision identification problem
  
    Problem: 
      bootcode treated B0 as A1 revision
      
    Cause:
      The revision id bit (bit 25,0x6804) was a mirror image of bit 1 in
      revision register (0x68) in PCI config space. As result, revision id
      bit was rolled back to 0 for B0. Because of this, bootcode treated 
      chip revision B0 as A1.
      
    Fix:
      Use other reset default value bits to identify revision. 
      
Version 3.20:

  1. Removed PCI reset workaround
    
    Issue: 
      PCI reset workaround was needed in A1 silicon. Since all products
      use A1 silicon is LOM design. For LOM, the workaround was done in
      BIOS; therefore, the workaround was no longer needed in bootcode.

Version 3.19:
 
  1. The transmission level set to 1.2V

    Change Request: 
      Register 0x590 bit 0:11 value to be changed to 0x880.

    CQ#: 00008202

Version 3.18:

  1. Fixed WOL issue
    
    Problem: 
      After using restart option in Windows and restart computer to DOS. 
      Then, turn off the power, WOL will not work.

    Cause:   
      Since there was no power lose from Windows to DOS, the signature 
      deposited by driver was not cleared. Therefore, when power lose from 
      DOS, bootcode sees the WOL signature and was bypassing the WoL 
      initialization.
      
    Fix:     
      Changed bootcode to clear WoL signature if the startup does not have 
      driver signature.
      
    CQ#: 00008243
    
Version 3.17:

  1. Added ASF support

    Enhancement: Added ASF support
    Change:  Code is modified to check ASF setting in configuration. If 
             enabled, it will load ASF code into sratchpad and transfer 
             control to the ASF code.

Version 3.16:

  1. Fixed cable plug/unplug problem
  
    Problem: Once cable is unplugged and plugged back on within 1 second,
             the device cannot re-establish the link. 
    Cause:   When the switch port is in auto mode, when we unplug the cable
             in short period of time, it could be within the polling
             timeout loop. Then, it will miss the window to trigger the
             firmware to issue re-negotiation command.
    Fix:     Added extra logic to command re-negotiation at least once
             when there is link change.
  
  2. Enable aribiter before checking WoL signature
    
    Problem: From Windows shutdown, WoL wakes up fine to DOS. However, it
             will not work again when power off in DOS mode on the first 
             time.
    Cause:   The driver or any external software may turn off memory arbiter
             before the power goes down. Because of this, the shared memory
             becomes not accessible and the WoL signature deposited by 
             Windows driver was not able to be cleared by firmware at power
             down. Next time when powering down, since the signature is still
             there, the firmware will not touch WoL for WoL initialization;
             therefore, DOS WoL will not work after Windows shutdown. 
             Since the firmware will always clear the signature, the following
             shutdown, WoL will work again. 
    Fix:     Enable the arbiter before checking WoL signature. 
    
  3. Fixed CPU halt problem
  
    Problem: From the code review, there was another place CPU could be halted
             if there was WoL signature deposited by driver. Similar to 
             version 3.14, item 1 fix, CPU is needed to continue to run for 
             link negotiation.
    Fix:     Not to halt processor when driver WoL signature is deposited. 
    
Version 3.15:

  1. Fixed link problem.
  
    Problem: Some system cannot link up with fiber switch (CQ#7326)
    Cause:   The fix in v3.14, item 2, did not really fix the problem.
             The root cause was actually because of the workaround in
             v3.11, item 3, changing the voltage created this problem.
    Fix:     Since this problem was discovered in copper NIC and no one
             reported for the fiber NIC, removed the workaround in 
             Fiber NIC.
 
  2. Fixed b57diag data loopback test failure problem (test D1, D2)
  
    Problem: The version 3.14 caused the diagnostic to fail at test d1,d2.
             (CQ#7406)
    Cause:   In version 3.14, the device reset indication bit was not 
             passed from phase 1 to phase 2 correctly.
    Fix:     Fixed the software bug. 
  
Version 3.14:

  1. Fixed halted CPU problem. 
  
    Problem: During code review, a potential problem was discovered.
    Cause:   If WoL is enabled, at VAUX power mode, the RxCPU is halted.
             We needed to keep processor running even at VAUX only mode in
             order to monitor the link status. The potential problem if 
             processor is halted could be; After powering off the device, 
             removing the link and connect to non-autonegotiation capable 
             device may loose link. 
    Fix:     Not to halt processor even WoL is enabled. 

  2. Fixed link problem

    Problem: Some system cannot link up with fiber switch (CQ#7326)
    Cause:   The link detection loop was too small. This problem was
             introduced in 3.13. The timeout loop count was thought to be
             good for some system, but later discovered that it wasn't 
             good enough for other systems. 
    Fix:     Put back the timeout count as in version 3.12

Version 3.13: 

  1. Removed workaround for PCIX-133Mhz in Version 3.11, item 3 for CIOB-ES.

    Problem: CIOB-ES did not need this workaround. 
    Fix:     Removed the workaround for CIOBE.

  2. Fixed PXE hang problem

    Problem: When PXE is enabled, some system could not come up.
    Cause:   Autonegotiation timeout loop was taking too much time and caused
             BIOS PXE read timeout.
    Fix:     Added PXE event service in the timeout loop.

Version 3.12:

  1. Fixed Link blinking problem

    Problem: The fix, in 3.11 item 4, was not completely working in some case.
    Cause:   There was an algorithm fault that could cause infinity reset
             loop when link is changed. 
    Fix:     Added condition check that it will retry negotiation only when	it
             lose link. When the link is up, it will not reset the link. 

Version 3.11:

  1. Added support for Swapped TTmode

    Reason:  The future revision of chip added a new feature of Swapped TTMode
             in Dual MAC mode. This version is changed to support that mode.

  2. Restored PowerDissipated/PowerConsumed initialization.

    Problem: In revision A2, we found some devices CPU would hang after
             performing a write into PowerDissipated/PowerConsumed registers.
             To workaround the problem, the initialization was skipped in
             version 3.06 or later. Therefore, version 3.06 to 3.10 was not 
             supporting this feature. 
    Cause:   After ASIC team's investigation, they have concluded that it
             was simply bad chip failed to be screened off in ATE test.
    Fix:     Restored the PowerDissipated/PowerConsumed initialization so
             the function will work.

  3. Applied workaround for PCIX-133Mhz
  
    Problem: We had blue screen in PCIX-133Mhz system
    Cause:   Under this environment, there was setup time compatibility 
             issue with chipset which caused Address/Data bus parity error. 
    Fix:     By raising 2.5V to 2.7V and lower 1.2V to 1.14V could
             workaround this problem. This workaround is applied to all
             revisions, PCIX-133Mhz bus only.  
          
  4. Fixed Link blinking problem

    Problem: When cable is connected back to back, the link will be up and
             down and blinks forever.
    Cause:   The timeout value to detect the non-autonegotiation devices was 
             too short and cause race condition between both ports.
    Fix:     Extended timeout value.
             
Version 3.10:

  1. Fixed chip powered down bug

    Problem: When SECFG has both port WoL disabled and Window goes 
             Hibernate with one port WoL enabled and other disabled, 
             both port would be shut down.
    Cause:   When bootcode detects PCI power goes away and WoL was 
             not enabled by driver, it was trying to shutdown the port. 
             Since NVRAM indicating both port does not have WoL enabled, 
             the shutdown routine was trying to shutdown everything by 
             setting chip power down bit and caused the whole chip to 
             shutdown. 
    Fix:     When driver post signature for WoL, bootcode will not do 
             anything and let driver to handle everything. 

Version 3.09:

  1. Restored Dual Mac mode back to normal mode.

     Problem: The port swapped mode was not swapping TTmode primary port.
     Cause:   The current ASIC design cannot support TTmode and swapped
              mode at the same time. This cause the confusing of primary
              port.
     Fix:     Changed back the default value of dual Mac mode to normal mode

  2. Fixed PXE ROM size bug
    
    Problem: The secfg option 29, expansion ROM size was not taking effect.
    Cause:   Bootcode did not program the correct value in the register.
    Fix:     Bootcode is changed to program correct expansion ROM size
             setting in NVRAM configuration into register.

  3. Changed core voltage to 1.2v
  
    Problem: The ASIC default 1.2v voltage was not 1.2v
    Fix:     Adjusted the 1.2v voltage to 1.2v

Version 3.08
    1. Fixed PXE with no link lock problem

Version 3.07
    1. Changed the default Dual Mac Mode to port swap.
    2. Fixed configuration bug.
    3. Use hardware autonegotiation
    4. Default Dual Mac mode to Port Swapping mode

Version 3.06
    1. Fixed CPU hang problem (disabled PowerDissipated/PowerConsumed cfg.)
    2. Supports Shared Memory data structure version 1
    3. Removed phase 2 image loading failure LED blink feature (to save space)
    4. Added Alt. Clock control. (slow clock when in VAUX only. Speed up
       with full power)
    5. Fixed Wol bug

Version 3.05
  1. Support A2 revision
  2. Changed phy type always to be serdes
  
    Problem: 
      User could change phy type in NVRAM configuration to copper and 
      cause the bootcode to misbehave
             
    Cause:   
      Originally, the bootcode was shared between copper and Serdes 
      verion; therefore, we needed a configuration field to indicate if 
      this is copper or serdes. Today, we separated the bootcode image 
      already, we don't need to use this configuration any more.
              
    Fix:
      Instead of reading phy type from configuration, it now will always 
      force this field to be serdes type. 

Version 3.04
    1. Removed SST Flash support.
    2. Added 2nd phase signature.
    3. Added delay to kick off PCI reset workaround to cover long PCI reset 
       assertion case.
    4. Lowering power consumption in first stage loader instead 2nd.
    5. Support Turbo Teaming Revision
     . Propagate PXE enable bit to share memory
    7. Changed default device id from 0x1648 to 0x16a8

Version 3.03:
    1. Support WoL
    2. Add PCI Reset Workaround
    3. Filled the remaining 15 MAC address array with default address
    4. Support 5704sA2
    5. Support PowerSaving
    6. Support FiberWoLCapable Config.
    7. Support portSwap Config.
    8. Support BothPort100MbpsCapable Config.

Version 3.02:
    1. Fixed State Reg. 2nd stage boodcode override bug
    2. Added workaround for ATMEL flash corruption problem
    3. Fixed driver/bootcode race condition on MII register read problem
    4. Program all MacAddr Registers with the MacAddress in NVRAM

Version 3.01:
    1. Fixed PXE speed bug
    2. Removed CIOB GPIO0 & GPIO2 access
    3. Added PCIX State Reg. RETRY_SAME_DMA	workaround

Version 3.0:	
    Fixed Primary/Secondary Mac Address bug 

Version 2.0:	
    Initial Version