1. sbc_455.zip Driver
2. RELNOTE.TXT File Contents

RELNOTE.TXT Driver File Contents (sbc_455.zip)

Chips and Technologies, Inc.
OC65548 VGA Compatible BIOS
Release Notes



Revision:   Version 1.1.0
Release Date:  June 26, 1996
============================

1.  Fixed a problem where the screen was going out of sync in
    extended mode 24h.

2.  Added the VESA VBE/DDC Read and Write Function hook to allow
    a system with a unique hardware DDC design to use most of the
    video BIOS's DDC code.  This is done by calling the system
    BIOS with sub-functions that read and write the DDC data
    lines, DDC clock lines, and initialize and restore the DDC
    state.

3.  Added a popup function (AX=5F14h, BL=5h, CX=X-Pos, DX=Y-Pos)
    to set the X and Y positions in the OC65548 VL BIOS.

4.  Added popup support for 800x600 and 1024x768 DSTN panels in
    the OC65548-VL BIOS.

5.  Added full popup support for F65548 PCI chipset.

6.  Enabled NTSC support in the 32K BIOS.

7.  Enabled the monitor detect code in the 32K BIOS.

8.  Modified the BMS files for the 32K BIOS.

Note:     Reserve 44KB for the video BIOS in the next generation
          of CHIPS graphics controllers.

Revision:   Version 1.0.4
Release Date:  November 14, 1995
================================

1.  Modified the BIOS to enable the write buffer in all modes.

2.  Modified the BIOS to clear the screen before displaying the
    signon message.


Revision:   Version 1.0.2
Release Date:  October 26, 1995
===============================

1.  Modified the BIOS to fix the boot up problem on TFT panels 5,
    6, 7, and 8 by programming XR51[2]=0 in the Panel Control
    table.

2.  Modified the following BIOS parameters on all 640x480 panels:
    RegisterNew ValueOld Value
     XR64      0Bh       0CH
     XR67      0Ch       0Bh

3.  Modified XR54[1]=0 for all 640x480 TFT panels to prevent
    Display Enable from toggling within the Vsync period.

4.  Disabled the FLM delay for all the TFT panels (XR2F[7]=1).

5.  Modified the BIOS to disable PC Video Interface for Panel #6
    (XR06[4]=0).

6.  Disabled the XRAM and write buffer in 1024x768x256 at 70 and
    75 Hz (CRT only mode) and 800x600x32k/64k modes.

7.  Changed both Hsync and Vsync polarity to positive (+) for
    800x600 and 1024x768 panels (XR55[76]=00).


Revision:   Version 1.0.1
Release Date:  September 21, 1995
=================================

1.  Modified the BIOS to eliminate a delay when switching
    displays.

2.  Fixed a problem  where the system would hang during the
    initial boot process.



Revision:   Version 1.0.0
Release Date:  July 11, 1995
============================

1.  Modified the BIOS so the OEM can use the BMP to set the
    correct frequency for all the panel types.

2.  Fixed a clock jitter problem with the high color modes.

3.  Fixed a problem with INT 15h system BIOS DDC hook.

4.  Fixed a problem with the optimal compensation where function
    5F5Ch caused the system to reboot.